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Searched defs:VOffset (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.cpp723 unsigned VOffset = 0; in getMachineOpValue() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp3199 Register VOffset = MI.getOperand(4 + OpOffset).getReg(); in selectBufferLoadLds() local
3322 Register VOffset; in selectGlobalLoadLds() local
4435 if (Register VOffset = matchZeroExtendFromS32(*MRI, PtrBaseOffset)) { in selectGlobalSAddr() local
4459 Register VOffset = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in selectGlobalSAddr() local
H A DAMDGPULegalizerInfo.cpp5838 Register VOffset = MI.getOperand(3 + OpOffset).getReg(); in legalizeBufferStore() local
5892 Register VIndex, Register VOffset, Register SOffset, in buildBufferLoad()
5949 Register VOffset = MI.getOperand(3 + OpOffset).getReg(); in legalizeBufferLoad() local
6184 Register VOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferAtomic() local
H A DSIRegisterInfo.cpp1388 int64_t VOffset) { in buildSpillLoadStore()
H A DAMDGPUISelDAGToDAG.cpp1765 SDValue &VOffset, in SelectGlobalSAddr()
H A DAMDGPURegisterBankInfo.cpp1363 Register VOffset; in applyMappingSBufferLoad() local
H A DSIISelLowering.cpp9714 SDValue VOffset = Op.getOperand(5 + OpOffset); in LowerINTRINSIC_VOID() local
9816 SDValue VOffset; in LowerINTRINSIC_VOID() local
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp41461 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4; in combineTargetShuffle() local