1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _VMM_DEV_H_ 30 #define _VMM_DEV_H_ 31 32 #include <sys/domainset.h> 33 34 #include <machine/vmm.h> 35 #include <machine/vmm_snapshot.h> 36 37 struct vm_memmap { 38 vm_paddr_t gpa; 39 int segid; /* memory segment */ 40 vm_ooffset_t segoff; /* offset into memory segment */ 41 size_t len; /* mmap length */ 42 int prot; /* RWX */ 43 int flags; 44 }; 45 #define VM_MEMMAP_F_WIRED 0x01 46 #define VM_MEMMAP_F_IOMMU 0x02 47 48 struct vm_munmap { 49 vm_paddr_t gpa; 50 size_t len; 51 }; 52 53 #define VM_MEMSEG_NAME(m) ((m)->name[0] != '\0' ? (m)->name : NULL) 54 struct vm_memseg { 55 int segid; 56 size_t len; 57 char name[VM_MAX_SUFFIXLEN + 1]; 58 domainset_t *ds_mask; 59 size_t ds_mask_size; 60 int ds_policy; 61 }; 62 63 struct vm_register { 64 int cpuid; 65 int regnum; /* enum vm_reg_name */ 66 uint64_t regval; 67 }; 68 69 struct vm_seg_desc { /* data or code segment */ 70 int cpuid; 71 int regnum; /* enum vm_reg_name */ 72 struct seg_desc desc; 73 }; 74 75 struct vm_register_set { 76 int cpuid; 77 unsigned int count; 78 const int *regnums; /* enum vm_reg_name */ 79 uint64_t *regvals; 80 }; 81 82 struct vm_run { 83 int cpuid; 84 cpuset_t *cpuset; /* CPU set storage */ 85 size_t cpusetsize; 86 struct vm_exit *vm_exit; 87 }; 88 89 struct vm_exception { 90 int cpuid; 91 int vector; 92 uint32_t error_code; 93 int error_code_valid; 94 int restart_instruction; 95 }; 96 97 struct vm_lapic_msi { 98 uint64_t msg; 99 uint64_t addr; 100 }; 101 102 struct vm_lapic_irq { 103 int cpuid; 104 int vector; 105 }; 106 107 struct vm_ioapic_irq { 108 int irq; 109 }; 110 111 struct vm_isa_irq { 112 int atpic_irq; 113 int ioapic_irq; 114 }; 115 116 struct vm_isa_irq_trigger { 117 int atpic_irq; 118 enum vm_intr_trigger trigger; 119 }; 120 121 struct vm_capability { 122 int cpuid; 123 enum vm_cap_type captype; 124 int capval; 125 int allcpus; 126 }; 127 128 struct vm_pptdev { 129 int bus; 130 int slot; 131 int func; 132 }; 133 134 struct vm_pptdev_mmio { 135 int bus; 136 int slot; 137 int func; 138 vm_paddr_t gpa; 139 vm_paddr_t hpa; 140 size_t len; 141 }; 142 143 struct vm_pptdev_msi { 144 int vcpu; /* unused */ 145 int bus; 146 int slot; 147 int func; 148 int numvec; /* 0 means disabled */ 149 uint64_t msg; 150 uint64_t addr; 151 }; 152 153 struct vm_pptdev_msix { 154 int vcpu; /* unused */ 155 int bus; 156 int slot; 157 int func; 158 int idx; 159 uint64_t msg; 160 uint32_t vector_control; 161 uint64_t addr; 162 }; 163 164 struct vm_nmi { 165 int cpuid; 166 }; 167 168 #define MAX_VM_STATS 64 169 struct vm_stats { 170 int cpuid; /* in */ 171 int index; /* in */ 172 int num_entries; /* out */ 173 struct timeval tv; 174 uint64_t statbuf[MAX_VM_STATS]; 175 }; 176 177 struct vm_stat_desc { 178 int index; /* in */ 179 char desc[128]; /* out */ 180 }; 181 182 struct vm_x2apic { 183 int cpuid; 184 enum x2apic_state state; 185 }; 186 187 struct vm_gpa_pte { 188 uint64_t gpa; /* in */ 189 uint64_t pte[4]; /* out */ 190 int ptenum; 191 }; 192 193 struct vm_hpet_cap { 194 uint32_t capabilities; /* lower 32 bits of HPET capabilities */ 195 }; 196 197 struct vm_suspend { 198 enum vm_suspend_how how; 199 }; 200 201 struct vm_gla2gpa { 202 int vcpuid; /* inputs */ 203 int prot; /* PROT_READ or PROT_WRITE */ 204 uint64_t gla; 205 struct vm_guest_paging paging; 206 int fault; /* outputs */ 207 uint64_t gpa; 208 }; 209 210 struct vm_activate_cpu { 211 int vcpuid; 212 }; 213 214 struct vm_cpuset { 215 int which; 216 int cpusetsize; 217 cpuset_t *cpus; 218 }; 219 #define VM_ACTIVE_CPUS 0 220 #define VM_SUSPENDED_CPUS 1 221 #define VM_DEBUG_CPUS 2 222 223 struct vm_intinfo { 224 int vcpuid; 225 uint64_t info1; 226 uint64_t info2; 227 }; 228 229 struct vm_rtc_time { 230 time_t secs; 231 }; 232 233 struct vm_rtc_data { 234 int offset; 235 uint8_t value; 236 }; 237 238 struct vm_cpu_topology { 239 uint16_t sockets; 240 uint16_t cores; 241 uint16_t threads; 242 uint16_t maxcpus; 243 }; 244 245 struct vm_readwrite_kernemu_device { 246 int vcpuid; 247 unsigned access_width : 3; 248 unsigned _unused : 29; 249 uint64_t gpa; 250 uint64_t value; 251 }; 252 _Static_assert(sizeof(struct vm_readwrite_kernemu_device) == 24, "ABI"); 253 254 enum { 255 /* general routines */ 256 IOCNUM_ABIVERS = 0, 257 IOCNUM_RUN = 1, 258 IOCNUM_SET_CAPABILITY = 2, 259 IOCNUM_GET_CAPABILITY = 3, 260 IOCNUM_SUSPEND = 4, 261 IOCNUM_REINIT = 5, 262 263 /* memory apis */ 264 IOCNUM_MAP_MEMORY = 10, /* deprecated */ 265 IOCNUM_GET_MEMORY_SEG = 11, /* deprecated */ 266 IOCNUM_GET_GPA_PMAP = 12, 267 IOCNUM_GLA2GPA = 13, 268 IOCNUM_ALLOC_MEMSEG = 14, 269 IOCNUM_GET_MEMSEG = 15, 270 IOCNUM_MMAP_MEMSEG = 16, 271 IOCNUM_MMAP_GETNEXT = 17, 272 IOCNUM_GLA2GPA_NOFAULT = 18, 273 IOCNUM_MUNMAP_MEMSEG = 19, 274 275 /* register/state accessors */ 276 IOCNUM_SET_REGISTER = 20, 277 IOCNUM_GET_REGISTER = 21, 278 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22, 279 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23, 280 IOCNUM_SET_REGISTER_SET = 24, 281 IOCNUM_GET_REGISTER_SET = 25, 282 IOCNUM_GET_KERNEMU_DEV = 26, 283 IOCNUM_SET_KERNEMU_DEV = 27, 284 285 /* interrupt injection */ 286 IOCNUM_GET_INTINFO = 28, 287 IOCNUM_SET_INTINFO = 29, 288 IOCNUM_INJECT_EXCEPTION = 30, 289 IOCNUM_LAPIC_IRQ = 31, 290 IOCNUM_INJECT_NMI = 32, 291 IOCNUM_IOAPIC_ASSERT_IRQ = 33, 292 IOCNUM_IOAPIC_DEASSERT_IRQ = 34, 293 IOCNUM_IOAPIC_PULSE_IRQ = 35, 294 IOCNUM_LAPIC_MSI = 36, 295 IOCNUM_LAPIC_LOCAL_IRQ = 37, 296 IOCNUM_IOAPIC_PINCOUNT = 38, 297 IOCNUM_RESTART_INSTRUCTION = 39, 298 299 /* PCI pass-thru */ 300 IOCNUM_BIND_PPTDEV = 40, 301 IOCNUM_UNBIND_PPTDEV = 41, 302 IOCNUM_MAP_PPTDEV_MMIO = 42, 303 IOCNUM_PPTDEV_MSI = 43, 304 IOCNUM_PPTDEV_MSIX = 44, 305 IOCNUM_PPTDEV_DISABLE_MSIX = 45, 306 IOCNUM_UNMAP_PPTDEV_MMIO = 46, 307 308 /* statistics */ 309 IOCNUM_VM_STATS = 50, 310 IOCNUM_VM_STAT_DESC = 51, 311 312 /* kernel device state */ 313 IOCNUM_SET_X2APIC_STATE = 60, 314 IOCNUM_GET_X2APIC_STATE = 61, 315 IOCNUM_GET_HPET_CAPABILITIES = 62, 316 317 /* CPU Topology */ 318 IOCNUM_SET_TOPOLOGY = 63, 319 IOCNUM_GET_TOPOLOGY = 64, 320 321 /* legacy interrupt injection */ 322 IOCNUM_ISA_ASSERT_IRQ = 80, 323 IOCNUM_ISA_DEASSERT_IRQ = 81, 324 IOCNUM_ISA_PULSE_IRQ = 82, 325 IOCNUM_ISA_SET_IRQ_TRIGGER = 83, 326 327 /* vm_cpuset */ 328 IOCNUM_ACTIVATE_CPU = 90, 329 IOCNUM_GET_CPUSET = 91, 330 IOCNUM_SUSPEND_CPU = 92, 331 IOCNUM_RESUME_CPU = 93, 332 333 /* RTC */ 334 IOCNUM_RTC_READ = 100, 335 IOCNUM_RTC_WRITE = 101, 336 IOCNUM_RTC_SETTIME = 102, 337 IOCNUM_RTC_GETTIME = 103, 338 339 /* checkpoint */ 340 IOCNUM_SNAPSHOT_REQ = 113, 341 342 IOCNUM_RESTORE_TIME = 115 343 }; 344 345 #define VM_RUN \ 346 _IOW('v', IOCNUM_RUN, struct vm_run) 347 #define VM_SUSPEND \ 348 _IOW('v', IOCNUM_SUSPEND, struct vm_suspend) 349 #define VM_REINIT \ 350 _IO('v', IOCNUM_REINIT) 351 #define VM_ALLOC_MEMSEG \ 352 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg) 353 #define VM_GET_MEMSEG \ 354 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg) 355 #define VM_MMAP_MEMSEG \ 356 _IOW('v', IOCNUM_MMAP_MEMSEG, struct vm_memmap) 357 #define VM_MMAP_GETNEXT \ 358 _IOWR('v', IOCNUM_MMAP_GETNEXT, struct vm_memmap) 359 #define VM_MUNMAP_MEMSEG \ 360 _IOW('v', IOCNUM_MUNMAP_MEMSEG, struct vm_munmap) 361 #define VM_SET_REGISTER \ 362 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register) 363 #define VM_GET_REGISTER \ 364 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register) 365 #define VM_SET_SEGMENT_DESCRIPTOR \ 366 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 367 #define VM_GET_SEGMENT_DESCRIPTOR \ 368 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 369 #define VM_SET_REGISTER_SET \ 370 _IOW('v', IOCNUM_SET_REGISTER_SET, struct vm_register_set) 371 #define VM_GET_REGISTER_SET \ 372 _IOWR('v', IOCNUM_GET_REGISTER_SET, struct vm_register_set) 373 #define VM_SET_KERNEMU_DEV \ 374 _IOW('v', IOCNUM_SET_KERNEMU_DEV, \ 375 struct vm_readwrite_kernemu_device) 376 #define VM_GET_KERNEMU_DEV \ 377 _IOWR('v', IOCNUM_GET_KERNEMU_DEV, \ 378 struct vm_readwrite_kernemu_device) 379 #define VM_INJECT_EXCEPTION \ 380 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception) 381 #define VM_LAPIC_IRQ \ 382 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq) 383 #define VM_LAPIC_LOCAL_IRQ \ 384 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq) 385 #define VM_LAPIC_MSI \ 386 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi) 387 #define VM_IOAPIC_ASSERT_IRQ \ 388 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq) 389 #define VM_IOAPIC_DEASSERT_IRQ \ 390 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq) 391 #define VM_IOAPIC_PULSE_IRQ \ 392 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq) 393 #define VM_IOAPIC_PINCOUNT \ 394 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int) 395 #define VM_ISA_ASSERT_IRQ \ 396 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq) 397 #define VM_ISA_DEASSERT_IRQ \ 398 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq) 399 #define VM_ISA_PULSE_IRQ \ 400 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq) 401 #define VM_ISA_SET_IRQ_TRIGGER \ 402 _IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger) 403 #define VM_SET_CAPABILITY \ 404 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability) 405 #define VM_GET_CAPABILITY \ 406 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability) 407 #define VM_BIND_PPTDEV \ 408 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev) 409 #define VM_UNBIND_PPTDEV \ 410 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev) 411 #define VM_MAP_PPTDEV_MMIO \ 412 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 413 #define VM_PPTDEV_MSI \ 414 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi) 415 #define VM_PPTDEV_MSIX \ 416 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix) 417 #define VM_PPTDEV_DISABLE_MSIX \ 418 _IOW('v', IOCNUM_PPTDEV_DISABLE_MSIX, struct vm_pptdev) 419 #define VM_UNMAP_PPTDEV_MMIO \ 420 _IOW('v', IOCNUM_UNMAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 421 #define VM_INJECT_NMI \ 422 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi) 423 #define VM_STATS \ 424 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats) 425 #define VM_STAT_DESC \ 426 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc) 427 #define VM_SET_X2APIC_STATE \ 428 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic) 429 #define VM_GET_X2APIC_STATE \ 430 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic) 431 #define VM_GET_HPET_CAPABILITIES \ 432 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap) 433 #define VM_SET_TOPOLOGY \ 434 _IOW('v', IOCNUM_SET_TOPOLOGY, struct vm_cpu_topology) 435 #define VM_GET_TOPOLOGY \ 436 _IOR('v', IOCNUM_GET_TOPOLOGY, struct vm_cpu_topology) 437 #define VM_GET_GPA_PMAP \ 438 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte) 439 #define VM_GLA2GPA \ 440 _IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa) 441 #define VM_GLA2GPA_NOFAULT \ 442 _IOWR('v', IOCNUM_GLA2GPA_NOFAULT, struct vm_gla2gpa) 443 #define VM_ACTIVATE_CPU \ 444 _IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu) 445 #define VM_GET_CPUS \ 446 _IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset) 447 #define VM_SUSPEND_CPU \ 448 _IOW('v', IOCNUM_SUSPEND_CPU, struct vm_activate_cpu) 449 #define VM_RESUME_CPU \ 450 _IOW('v', IOCNUM_RESUME_CPU, struct vm_activate_cpu) 451 #define VM_SET_INTINFO \ 452 _IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo) 453 #define VM_GET_INTINFO \ 454 _IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo) 455 #define VM_RTC_WRITE \ 456 _IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data) 457 #define VM_RTC_READ \ 458 _IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data) 459 #define VM_RTC_SETTIME \ 460 _IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time) 461 #define VM_RTC_GETTIME \ 462 _IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time) 463 #define VM_RESTART_INSTRUCTION \ 464 _IOW('v', IOCNUM_RESTART_INSTRUCTION, int) 465 #define VM_SNAPSHOT_REQ \ 466 _IOWR('v', IOCNUM_SNAPSHOT_REQ, struct vm_snapshot_meta) 467 #define VM_RESTORE_TIME \ 468 _IOWR('v', IOCNUM_RESTORE_TIME, int) 469 #endif 470