1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2015, 2016 ARM Ltd.
4 */
5 #ifndef __KVM_ARM_VGIC_NEW_H__
6 #define __KVM_ARM_VGIC_NEW_H__
7
8 #include <linux/irqchip/arm-gic-common.h>
9 #include <asm/kvm_mmu.h>
10
11 #define PRODUCT_ID_KVM 0x4b /* ASCII code K */
12 #define IMPLEMENTER_ARM 0x43b
13
14 #define VGIC_ADDR_UNDEF (-1)
15 #define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
16
17 #define INTERRUPT_ID_BITS_SPIS 10
18 #define INTERRUPT_ID_BITS_ITS 16
19 #define VGIC_LPI_MAX_INTID ((1 << INTERRUPT_ID_BITS_ITS) - 1)
20 #define VGIC_PRI_BITS 5
21
22 #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
23
24 #define VGIC_AFFINITY_0_SHIFT 0
25 #define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
26 #define VGIC_AFFINITY_1_SHIFT 8
27 #define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
28 #define VGIC_AFFINITY_2_SHIFT 16
29 #define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
30 #define VGIC_AFFINITY_3_SHIFT 24
31 #define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)
32
33 #define VGIC_AFFINITY_LEVEL(reg, level) \
34 ((((reg) & VGIC_AFFINITY_## level ##_MASK) \
35 >> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
36
37 /*
38 * The Userspace encodes the affinity differently from the MPIDR,
39 * Below macro converts vgic userspace format to MPIDR reg format.
40 */
41 #define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \
42 VGIC_AFFINITY_LEVEL(val, 1) | \
43 VGIC_AFFINITY_LEVEL(val, 2) | \
44 VGIC_AFFINITY_LEVEL(val, 3))
45
46 /*
47 * As per Documentation/virt/kvm/devices/arm-vgic-v3.rst,
48 * below macros are defined for CPUREG encoding.
49 */
50 #define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK 0x000000000000c000
51 #define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT 14
52 #define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK 0x0000000000003800
53 #define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT 11
54 #define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK 0x0000000000000780
55 #define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT 7
56 #define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK 0x0000000000000078
57 #define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT 3
58 #define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK 0x0000000000000007
59 #define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT 0
60
61 #define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK | \
62 KVM_REG_ARM_VGIC_SYSREG_OP1_MASK | \
63 KVM_REG_ARM_VGIC_SYSREG_CRN_MASK | \
64 KVM_REG_ARM_VGIC_SYSREG_CRM_MASK | \
65 KVM_REG_ARM_VGIC_SYSREG_OP2_MASK)
66
67 /*
68 * As per Documentation/virt/kvm/devices/arm-vgic-its.rst,
69 * below macros are defined for ITS table entry encoding.
70 */
71 #define KVM_ITS_CTE_VALID_SHIFT 63
72 #define KVM_ITS_CTE_VALID_MASK BIT_ULL(63)
73 #define KVM_ITS_CTE_RDBASE_SHIFT 16
74 #define KVM_ITS_CTE_ICID_MASK GENMASK_ULL(15, 0)
75 #define KVM_ITS_ITE_NEXT_SHIFT 48
76 #define KVM_ITS_ITE_PINTID_SHIFT 16
77 #define KVM_ITS_ITE_PINTID_MASK GENMASK_ULL(47, 16)
78 #define KVM_ITS_ITE_ICID_MASK GENMASK_ULL(15, 0)
79 #define KVM_ITS_DTE_VALID_SHIFT 63
80 #define KVM_ITS_DTE_VALID_MASK BIT_ULL(63)
81 #define KVM_ITS_DTE_NEXT_SHIFT 49
82 #define KVM_ITS_DTE_NEXT_MASK GENMASK_ULL(62, 49)
83 #define KVM_ITS_DTE_ITTADDR_SHIFT 5
84 #define KVM_ITS_DTE_ITTADDR_MASK GENMASK_ULL(48, 5)
85 #define KVM_ITS_DTE_SIZE_MASK GENMASK_ULL(4, 0)
86 #define KVM_ITS_L1E_VALID_MASK BIT_ULL(63)
87 /* we only support 64 kB translation table page size */
88 #define KVM_ITS_L1E_ADDR_MASK GENMASK_ULL(51, 16)
89
90 #define KVM_VGIC_V3_RDIST_INDEX_MASK GENMASK_ULL(11, 0)
91 #define KVM_VGIC_V3_RDIST_FLAGS_MASK GENMASK_ULL(15, 12)
92 #define KVM_VGIC_V3_RDIST_FLAGS_SHIFT 12
93 #define KVM_VGIC_V3_RDIST_BASE_MASK GENMASK_ULL(51, 16)
94 #define KVM_VGIC_V3_RDIST_COUNT_MASK GENMASK_ULL(63, 52)
95 #define KVM_VGIC_V3_RDIST_COUNT_SHIFT 52
96
97 #ifdef CONFIG_DEBUG_SPINLOCK
98 #define DEBUG_SPINLOCK_BUG_ON(p) BUG_ON(p)
99 #else
100 #define DEBUG_SPINLOCK_BUG_ON(p)
101 #endif
102
vgic_get_implementation_rev(struct kvm_vcpu * vcpu)103 static inline u32 vgic_get_implementation_rev(struct kvm_vcpu *vcpu)
104 {
105 return vcpu->kvm->arch.vgic.implementation_rev;
106 }
107
108 /* Requires the irq_lock to be held by the caller. */
irq_is_pending(struct vgic_irq * irq)109 static inline bool irq_is_pending(struct vgic_irq *irq)
110 {
111 if (irq->config == VGIC_CONFIG_EDGE)
112 return irq->pending_latch;
113 else
114 return irq->pending_latch || irq->line_level;
115 }
116
vgic_irq_is_mapped_level(struct vgic_irq * irq)117 static inline bool vgic_irq_is_mapped_level(struct vgic_irq *irq)
118 {
119 return irq->config == VGIC_CONFIG_LEVEL && irq->hw;
120 }
121
vgic_irq_get_lr_count(struct vgic_irq * irq)122 static inline int vgic_irq_get_lr_count(struct vgic_irq *irq)
123 {
124 /* Account for the active state as an interrupt */
125 if (vgic_irq_is_sgi(irq->intid) && irq->source)
126 return hweight8(irq->source) + irq->active;
127
128 return irq_is_pending(irq) || irq->active;
129 }
130
vgic_irq_is_multi_sgi(struct vgic_irq * irq)131 static inline bool vgic_irq_is_multi_sgi(struct vgic_irq *irq)
132 {
133 return vgic_irq_get_lr_count(irq) > 1;
134 }
135
vgic_write_guest_lock(struct kvm * kvm,gpa_t gpa,const void * data,unsigned long len)136 static inline int vgic_write_guest_lock(struct kvm *kvm, gpa_t gpa,
137 const void *data, unsigned long len)
138 {
139 struct vgic_dist *dist = &kvm->arch.vgic;
140 int ret;
141
142 dist->table_write_in_progress = true;
143 ret = kvm_write_guest_lock(kvm, gpa, data, len);
144 dist->table_write_in_progress = false;
145
146 return ret;
147 }
148
149 /*
150 * This struct provides an intermediate representation of the fields contained
151 * in the GICH_VMCR and ICH_VMCR registers, such that code exporting the GIC
152 * state to userspace can generate either GICv2 or GICv3 CPU interface
153 * registers regardless of the hardware backed GIC used.
154 */
155 struct vgic_vmcr {
156 u32 grpen0;
157 u32 grpen1;
158
159 u32 ackctl;
160 u32 fiqen;
161 u32 cbpr;
162 u32 eoim;
163
164 u32 abpr;
165 u32 bpr;
166 u32 pmr; /* Priority mask field in the GICC_PMR and
167 * ICC_PMR_EL1 priority field format */
168 };
169
170 struct vgic_reg_attr {
171 struct kvm_vcpu *vcpu;
172 gpa_t addr;
173 };
174
175 struct its_device {
176 struct list_head dev_list;
177
178 /* the head for the list of ITTEs */
179 struct list_head itt_head;
180 u32 num_eventid_bits;
181 gpa_t itt_addr;
182 u32 device_id;
183 };
184
185 #define COLLECTION_NOT_MAPPED ((u32)~0)
186
187 struct its_collection {
188 struct list_head coll_list;
189
190 u32 collection_id;
191 u32 target_addr;
192 };
193
194 #define its_is_collection_mapped(coll) ((coll) && \
195 ((coll)->target_addr != COLLECTION_NOT_MAPPED))
196
197 struct its_ite {
198 struct list_head ite_list;
199
200 struct vgic_irq *irq;
201 struct its_collection *collection;
202 u32 event_id;
203 };
204
205 int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
206 struct vgic_reg_attr *reg_attr);
207 int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
208 struct vgic_reg_attr *reg_attr);
209 const struct vgic_register_region *
210 vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
211 gpa_t addr, int len);
212 struct vgic_irq *vgic_get_irq(struct kvm *kvm, u32 intid);
213 struct vgic_irq *vgic_get_vcpu_irq(struct kvm_vcpu *vcpu, u32 intid);
214 void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq);
215 bool vgic_get_phys_line_level(struct vgic_irq *irq);
216 void vgic_irq_set_phys_pending(struct vgic_irq *irq, bool pending);
217 void vgic_irq_set_phys_active(struct vgic_irq *irq, bool active);
218 bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq,
219 unsigned long flags) __releases(&irq->irq_lock);
220 void vgic_kick_vcpus(struct kvm *kvm);
221 void vgic_irq_handle_resampling(struct vgic_irq *irq,
222 bool lr_deactivated, bool lr_pending);
223
224 int vgic_check_iorange(struct kvm *kvm, phys_addr_t ioaddr,
225 phys_addr_t addr, phys_addr_t alignment,
226 phys_addr_t size);
227
228 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
229 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
230 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
231 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
232 int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
233 int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
234 int offset, u32 *val);
235 int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
236 int offset, u32 *val);
237 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
238 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
239 void vgic_v2_enable(struct kvm_vcpu *vcpu);
240 int vgic_v2_probe(const struct gic_kvm_info *info);
241 int vgic_v2_map_resources(struct kvm *kvm);
242 int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
243 enum vgic_type);
244
245 void vgic_v2_init_lrs(void);
246 void vgic_v2_load(struct kvm_vcpu *vcpu);
247 void vgic_v2_put(struct kvm_vcpu *vcpu);
248
249 void vgic_v2_save_state(struct kvm_vcpu *vcpu);
250 void vgic_v2_restore_state(struct kvm_vcpu *vcpu);
251
vgic_try_get_irq_kref(struct vgic_irq * irq)252 static inline bool vgic_try_get_irq_kref(struct vgic_irq *irq)
253 {
254 if (!irq)
255 return false;
256
257 if (irq->intid < VGIC_MIN_LPI)
258 return true;
259
260 return kref_get_unless_zero(&irq->refcount);
261 }
262
vgic_get_irq_kref(struct vgic_irq * irq)263 static inline void vgic_get_irq_kref(struct vgic_irq *irq)
264 {
265 WARN_ON_ONCE(!vgic_try_get_irq_kref(irq));
266 }
267
268 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
269 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
270 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
271 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
272 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
273 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
274 void vgic_v3_enable(struct kvm_vcpu *vcpu);
275 int vgic_v3_probe(const struct gic_kvm_info *info);
276 int vgic_v3_map_resources(struct kvm *kvm);
277 int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq);
278 int vgic_v3_save_pending_tables(struct kvm *kvm);
279 int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count);
280 int vgic_register_redist_iodev(struct kvm_vcpu *vcpu);
281 void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu);
282 bool vgic_v3_check_base(struct kvm *kvm);
283
284 void vgic_v3_load(struct kvm_vcpu *vcpu);
285 void vgic_v3_put(struct kvm_vcpu *vcpu);
286
287 bool vgic_has_its(struct kvm *kvm);
288 int kvm_vgic_register_its_device(void);
289 void vgic_enable_lpis(struct kvm_vcpu *vcpu);
290 void vgic_flush_pending_lpis(struct kvm_vcpu *vcpu);
291 int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi);
292 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
293 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
294 int offset, u32 *val);
295 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
296 int offset, u32 *val);
297 int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu,
298 struct kvm_device_attr *attr, bool is_write);
299 int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr);
300 int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
301 u32 intid, u32 *val);
302 int kvm_register_vgic_device(unsigned long type);
303 void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
304 void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
305 int vgic_lazy_init(struct kvm *kvm);
306 int vgic_init(struct kvm *kvm);
307
308 void vgic_debug_init(struct kvm *kvm);
309 void vgic_debug_destroy(struct kvm *kvm);
310
vgic_v3_max_apr_idx(struct kvm_vcpu * vcpu)311 static inline int vgic_v3_max_apr_idx(struct kvm_vcpu *vcpu)
312 {
313 struct vgic_cpu *cpu_if = &vcpu->arch.vgic_cpu;
314
315 /*
316 * num_pri_bits are initialized with HW supported values.
317 * We can rely safely on num_pri_bits even if VM has not
318 * restored ICC_CTLR_EL1 before restoring APnR registers.
319 */
320 switch (cpu_if->num_pri_bits) {
321 case 7: return 3;
322 case 6: return 1;
323 default: return 0;
324 }
325 }
326
327 static inline bool
vgic_v3_redist_region_full(struct vgic_redist_region * region)328 vgic_v3_redist_region_full(struct vgic_redist_region *region)
329 {
330 if (!region->count)
331 return false;
332
333 return (region->free_index >= region->count);
334 }
335
336 struct vgic_redist_region *vgic_v3_rdist_free_slot(struct list_head *rdregs);
337
338 static inline size_t
vgic_v3_rd_region_size(struct kvm * kvm,struct vgic_redist_region * rdreg)339 vgic_v3_rd_region_size(struct kvm *kvm, struct vgic_redist_region *rdreg)
340 {
341 if (!rdreg->count)
342 return atomic_read(&kvm->online_vcpus) * KVM_VGIC_V3_REDIST_SIZE;
343 else
344 return rdreg->count * KVM_VGIC_V3_REDIST_SIZE;
345 }
346
347 struct vgic_redist_region *vgic_v3_rdist_region_from_index(struct kvm *kvm,
348 u32 index);
349 void vgic_v3_free_redist_region(struct kvm *kvm, struct vgic_redist_region *rdreg);
350
351 bool vgic_v3_rdist_overlap(struct kvm *kvm, gpa_t base, size_t size);
352
vgic_dist_overlap(struct kvm * kvm,gpa_t base,size_t size)353 static inline bool vgic_dist_overlap(struct kvm *kvm, gpa_t base, size_t size)
354 {
355 struct vgic_dist *d = &kvm->arch.vgic;
356
357 return (base + size > d->vgic_dist_base) &&
358 (base < d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE);
359 }
360
361 bool vgic_lpis_enabled(struct kvm_vcpu *vcpu);
362 int vgic_its_resolve_lpi(struct kvm *kvm, struct vgic_its *its,
363 u32 devid, u32 eventid, struct vgic_irq **irq);
364 struct vgic_its *vgic_msi_to_its(struct kvm *kvm, struct kvm_msi *msi);
365 int vgic_its_inject_cached_translation(struct kvm *kvm, struct kvm_msi *msi);
366 void vgic_its_invalidate_all_caches(struct kvm *kvm);
367
368 /* GICv4.1 MMIO interface */
369 int vgic_its_inv_lpi(struct kvm *kvm, struct vgic_irq *irq);
370 int vgic_its_invall(struct kvm_vcpu *vcpu);
371
372 bool vgic_supports_direct_msis(struct kvm *kvm);
373 int vgic_v4_init(struct kvm *kvm);
374 void vgic_v4_teardown(struct kvm *kvm);
375 void vgic_v4_configure_vsgis(struct kvm *kvm);
376 void vgic_v4_get_vlpi_state(struct vgic_irq *irq, bool *val);
377 int vgic_v4_request_vpe_irq(struct kvm_vcpu *vcpu, int irq);
378
379 void vcpu_set_ich_hcr(struct kvm_vcpu *vcpu);
380
kvm_has_gicv3(struct kvm * kvm)381 static inline bool kvm_has_gicv3(struct kvm *kvm)
382 {
383 return kvm_has_feat(kvm, ID_AA64PFR0_EL1, GIC, IMP);
384 }
385
386 void vgic_v3_sync_nested(struct kvm_vcpu *vcpu);
387 void vgic_v3_load_nested(struct kvm_vcpu *vcpu);
388 void vgic_v3_put_nested(struct kvm_vcpu *vcpu);
389 void vgic_v3_handle_nested_maint_irq(struct kvm_vcpu *vcpu);
390 void vgic_v3_nested_update_mi(struct kvm_vcpu *vcpu);
391
392 int vgic_its_debug_init(struct kvm_device *dev);
393 void vgic_its_debug_destroy(struct kvm_device *dev);
394
395 #endif
396