xref: /freebsd/sys/dev/vge/if_vgereg.h (revision 04440331b5700e124c42b570ae1dfd00ea9c26f7)
1 /*-
2  * SPDX-License-Identifier: BSD-4-Clause
3  *
4  * Copyright (c) 2004
5  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *	This product includes software developed by Bill Paul.
18  * 4. Neither the name of the author nor the names of any co-contributors
19  *    may be used to endorse or promote products derived from this software
20  *    without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32  * THE POSSIBILITY OF SUCH DAMAGE.
33  */
34 
35 /*
36  * Register definitions for the VIA VT6122 gigabit ethernet controller.
37  * Definitions for the built-in copper PHY can be found in vgphy.h.
38  *
39  * The VT612x controllers have 256 bytes of register space. The
40  * manual seems to imply that the registers should all be accessed
41  * using 32-bit I/O cycles, but some of them are less than 32 bits
42  * wide. Go figure.
43  */
44 
45 #ifndef _IF_VGEREG_H_
46 #define _IF_VGEREG_H_
47 
48 #define VIA_VENDORID		0x1106
49 #define VIA_DEVICEID_61XX	0x3119
50 
51 #define VGE_PAR0		0x00	/* physical address register */
52 #define VGE_PAR1		0x02
53 #define VGE_PAR2		0x04
54 #define VGE_RXCTL		0x06	/* RX control register */
55 #define VGE_TXCTL		0x07	/* TX control register */
56 #define VGE_CRS0		0x08	/* Global cmd register 0 (w to set) */
57 #define VGE_CRS1		0x09	/* Global cmd register 1 (w to set) */
58 #define VGE_CRS2		0x0A	/* Global cmd register 2 (w to set) */
59 #define VGE_CRS3		0x0B	/* Global cmd register 3 (w to set) */
60 #define VGE_CRC0		0x0C	/* Global cmd register 0 (w to clr) */
61 #define VGE_CRC1		0x0D	/* Global cmd register 1 (w to clr) */
62 #define VGE_CRC2		0x0E	/* Global cmd register 2 (w to clr) */
63 #define VGE_CRC3		0x0F	/* Global cmd register 3 (w to clr) */
64 #define VGE_MAR0		0x10	/* Mcast hash/CAM register 0 */
65 #define VGE_MAR1		0x14	/* Mcast hash/CAM register 1 */
66 #define VGE_CAM0		0x10
67 #define VGE_CAM1		0x11
68 #define VGE_CAM2		0x12
69 #define VGE_CAM3		0x13
70 #define VGE_CAM4		0x14
71 #define VGE_CAM5		0x15
72 #define VGE_CAM6		0x16
73 #define VGE_CAM7		0x17
74 #define VGE_TXDESC_HIADDR	0x18	/* Hi part of 64bit txdesc base addr */
75 #define VGE_DATABUF_HIADDR	0x1D	/* Hi part of 64bit data buffer addr */
76 #define VGE_INTCTL0		0x20	/* interrupt control register */
77 #define VGE_RXSUPPTHR		0x20
78 #define VGE_TXSUPPTHR		0x20
79 #define VGE_INTHOLDOFF		0x20
80 #define VGE_INTCTL1		0x21	/* interrupt control register */
81 #define VGE_TXHOSTERR		0x22	/* TX host error status */
82 #define VGE_RXHOSTERR		0x23	/* RX host error status */
83 #define VGE_ISR			0x24	/* Interrupt status register */
84 #define VGE_IMR			0x28	/* Interrupt mask register */
85 #define VGE_TXSTS_PORT		0x2C	/* Transmit status port (???) */
86 #define VGE_TXQCSRS		0x30	/* TX queue ctl/status set */
87 #define VGE_RXQCSRS		0x32	/* RX queue ctl/status set */
88 #define VGE_TXQCSRC		0x34	/* TX queue ctl/status clear */
89 #define VGE_RXQCSRC		0x36	/* RX queue ctl/status clear */
90 #define VGE_RXDESC_ADDR_LO	0x38	/* RX desc base addr (lo 32 bits) */
91 #define VGE_RXDESC_CONSIDX	0x3C	/* Current RX descriptor index */
92 #define VGE_TXQTIMER		0x3E	/* TX queue timer pend register */
93 #define VGE_RXQTIMER		0x3F	/* RX queue timer pend register */
94 #define VGE_TXDESC_ADDR_LO0	0x40	/* TX desc0 base addr (lo 32 bits) */
95 #define VGE_TXDESC_ADDR_LO1	0x44	/* TX desc1 base addr (lo 32 bits) */
96 #define VGE_TXDESC_ADDR_LO2	0x48	/* TX desc2 base addr (lo 32 bits) */
97 #define VGE_TXDESC_ADDR_LO3	0x4C	/* TX desc3 base addr (lo 32 bits) */
98 #define VGE_RXDESCNUM		0x50	/* Size of RX desc ring */
99 #define VGE_TXDESCNUM		0x52	/* Size of TX desc ring */
100 #define VGE_TXDESC_CONSIDX0	0x54	/* Current TX descriptor index */
101 #define VGE_TXDESC_CONSIDX1	0x56	/* Current TX descriptor index */
102 #define VGE_TXDESC_CONSIDX2	0x58	/* Current TX descriptor index */
103 #define VGE_TXDESC_CONSIDX3	0x5A	/* Current TX descriptor index */
104 #define VGE_TX_PAUSE_TIMER	0x5C	/* TX pause frame timer */
105 #define VGE_RXDESC_RESIDUECNT	0x5E	/* RX descriptor residue count */
106 #define VGE_FIFOTEST0		0x60	/* FIFO test register */
107 #define VGE_FIFOTEST1		0x64	/* FIFO test register */
108 #define VGE_CAMADDR		0x68	/* CAM address register */
109 #define VGE_CAMCTL		0x69	/* CAM control register */
110 #define VGE_GFTEST		0x6A
111 #define VGE_FTSCMD		0x6B
112 #define VGE_MIICFG		0x6C	/* MII port config register */
113 #define VGE_MIISTS		0x6D	/* MII port status register */
114 #define VGE_PHYSTS0		0x6E	/* PHY status register */
115 #define VGE_PHYSTS1		0x6F	/* PHY status register */
116 #define VGE_MIICMD		0x70	/* MII command register */
117 #define VGE_MIIADDR		0x71	/* MII address register */
118 #define VGE_MIIDATA		0x72	/* MII data register */
119 #define VGE_SSTIMER		0x74	/* single-shot timer */
120 #define VGE_PTIMER		0x76	/* periodic timer */
121 #define VGE_CHIPCFG0		0x78	/* chip config A */
122 #define VGE_CHIPCFG1		0x79	/* chip config B */
123 #define VGE_CHIPCFG2		0x7A	/* chip config C */
124 #define VGE_CHIPCFG3		0x7B	/* chip config D */
125 #define VGE_DMACFG0		0x7C	/* DMA config 0 */
126 #define VGE_DMACFG1		0x7D	/* DMA config 1 */
127 #define VGE_RXCFG		0x7E	/* MAC RX config */
128 #define VGE_TXCFG		0x7F	/* MAC TX config */
129 #define VGE_PWRMGMT		0x82	/* power management shadow register */
130 #define VGE_PWRSTAT		0x83	/* power state shadow register */
131 #define VGE_MIBCSR		0x84	/* MIB control/status register */
132 #define VGE_SWEEDATA		0x85	/* EEPROM software loaded data */
133 #define VGE_MIBDATA		0x88	/* MIB data register */
134 #define VGE_EEWRDAT		0x8C	/* EEPROM embedded write */
135 #define VGE_EECSUM		0x92	/* EEPROM checksum */
136 #define VGE_EECSR		0x93	/* EEPROM control/status */
137 #define VGE_EERDDAT		0x94	/* EEPROM embedded read */
138 #define VGE_EEADDR		0x96	/* EEPROM address */
139 #define VGE_EECMD		0x97	/* EEPROM embedded command */
140 #define VGE_CHIPSTRAP		0x99	/* Chip jumper strapping status */
141 #define VGE_MEDIASTRAP		0x9B	/* Media jumper strapping */
142 #define VGE_DIAGSTS		0x9C	/* Chip diagnostic status */
143 #define VGE_DBGCTL		0x9E	/* Chip debug control */
144 #define VGE_DIAGCTL		0x9F	/* Chip diagnostic control */
145 #define VGE_WOLCR0S		0xA0	/* WOL0 event set */
146 #define VGE_WOLCR1S		0xA1	/* WOL1 event set */
147 #define VGE_PWRCFGS		0xA2	/* Power management config set */
148 #define VGE_WOLCFGS		0xA3	/* WOL config set */
149 #define VGE_WOLCR0C		0xA4	/* WOL0 event clear */
150 #define VGE_WOLCR1C		0xA5	/* WOL1 event clear */
151 #define VGE_PWRCFGC		0xA6	/* Power management config clear */
152 #define VGE_WOLCFGC		0xA7	/* WOL config clear */
153 #define VGE_WOLSR0S		0xA8	/* WOL status set */
154 #define VGE_WOLSR1S		0xA9	/* WOL status set */
155 #define VGE_WOLSR0C		0xAC	/* WOL status clear */
156 #define VGE_WOLSR1C		0xAD	/* WOL status clear */
157 #define VGE_WAKEPAT_CRC0	0xB0
158 #define VGE_WAKEPAT_CRC1	0xB2
159 #define VGE_WAKEPAT_CRC2	0xB4
160 #define VGE_WAKEPAT_CRC3	0xB6
161 #define VGE_WAKEPAT_CRC4	0xB8
162 #define VGE_WAKEPAT_CRC5	0xBA
163 #define VGE_WAKEPAT_CRC6	0xBC
164 #define VGE_WAKEPAT_CRC7	0xBE
165 #define VGE_WAKEPAT_MSK0_0	0xC0
166 #define VGE_WAKEPAT_MSK0_1	0xC4
167 #define VGE_WAKEPAT_MSK0_2	0xC8
168 #define VGE_WAKEPAT_MSK0_3	0xCC
169 #define VGE_WAKEPAT_MSK1_0	0xD0
170 #define VGE_WAKEPAT_MSK1_1	0xD4
171 #define VGE_WAKEPAT_MSK1_2	0xD8
172 #define VGE_WAKEPAT_MSK1_3	0xDC
173 #define VGE_WAKEPAT_MSK2_0	0xE0
174 #define VGE_WAKEPAT_MSK2_1	0xE4
175 #define VGE_WAKEPAT_MSK2_2	0xE8
176 #define VGE_WAKEPAT_MSK2_3	0xEC
177 #define VGE_WAKEPAT_MSK3_0	0xF0
178 #define VGE_WAKEPAT_MSK3_1	0xF4
179 #define VGE_WAKEPAT_MSK3_2	0xF8
180 #define VGE_WAKEPAT_MSK3_3	0xFC
181 
182 /* Receive control register */
183 
184 #define VGE_RXCTL_RX_BADFRAMES		0x01 /* accept CRC error frames */
185 #define VGE_RXCTL_RX_RUNT		0x02 /* accept runts */
186 #define VGE_RXCTL_RX_MCAST		0x04 /* accept multicasts */
187 #define VGE_RXCTL_RX_BCAST		0x08 /* accept broadcasts */
188 #define VGE_RXCTL_RX_PROMISC		0x10 /* promisc mode */
189 #define VGE_RXCTL_RX_GIANT		0x20 /* accept VLAN tagged frames */
190 #define VGE_RXCTL_RX_UCAST		0x40 /* use perfect filtering */
191 #define VGE_RXCTL_RX_SYMERR		0x80 /* accept symbol err packet */
192 
193 /* Transmit control register */
194 
195 #define VGE_TXCTL_LOOPCTL		0x03 /* loopback control */
196 #define VGE_TXCTL_COLLCTL		0x0C /* collision retry control */
197 
198 #define VGE_TXLOOPCTL_OFF		0x00
199 #define VGE_TXLOOPCTL_MAC_INTERNAL	0x01
200 #define VGE_TXLOOPCTL_EXTERNAL		0x02
201 
202 #define VGE_TXCOLLS_NORMAL		0x00 /* one set of 16 retries */
203 #define VGE_TXCOLLS_32			0x04 /* two sets of 16 retries */
204 #define VGE_TXCOLLS_48			0x08 /* three sets of 16 retries */
205 #define VGE_TXCOLLS_INFINITE		0x0C /* retry forever */
206 
207 /* Global command register 0 */
208 
209 #define VGE_CR0_START			0x01 /* start NIC */
210 #define VGE_CR0_STOP			0x02 /* stop NIC */
211 #define VGE_CR0_RX_ENABLE		0x04 /* turn on RX engine */
212 #define VGE_CR0_TX_ENABLE		0x08 /* turn on TX engine */
213 
214 /* Global command register 1 */
215 
216 #define VGE_CR1_NOUCAST			0x01 /* disable unicast reception */
217 #define VGE_CR1_NOPOLL			0x08 /* disable RX/TX desc polling */
218 #define VGE_CR1_TIMER0_ENABLE		0x20 /* enable single shot timer */
219 #define VGE_CR1_TIMER1_ENABLE		0x40 /* enable periodic timer */
220 #define VGE_CR1_SOFTRESET		0x80 /* software reset */
221 
222 /* Global command register 2 */
223 
224 #define VGE_CR2_TXPAUSE_THRESH_LO	0x03 /* TX pause frame lo threshold */
225 #define VGE_CR2_TXPAUSE_THRESH_HI	0x0C /* TX pause frame hi threshold */
226 #define VGE_CR2_HDX_FLOWCTL_ENABLE	0x10 /* half duplex flow control */
227 #define VGE_CR2_FDX_RXFLOWCTL_ENABLE	0x20 /* full duplex RX flow control */
228 #define VGE_CR2_FDX_TXFLOWCTL_ENABLE	0x40 /* full duplex TX flow control */
229 #define VGE_CR2_XON_ENABLE		0x80 /* 802.3x XON/XOFF flow control */
230 
231 /* Global command register 3 */
232 
233 #define VGE_CR3_INT_SWPEND		0x01 /* disable multi-level int bits */
234 #define VGE_CR3_INT_GMSK		0x02 /* mask off all interrupts */
235 #define VGE_CR3_INT_HOLDOFF		0x04 /* enable int hold off timer */
236 #define VGE_CR3_DIAG			0x10 /* diagnostic enabled */
237 #define VGE_CR3_PHYRST			0x20 /* assert PHYRSTZ */
238 #define VGE_CR3_STOP_FORCE		0x40 /* force NIC to stopped state */
239 
240 /* Interrupt control register */
241 
242 #define VGE_INTCTL_SC_RELOAD		0x01 /* reload hold timer */
243 #define VGE_INTCTL_HC_RELOAD		0x02 /* enable hold timer reload */
244 #define VGE_INTCTL_STATUS		0x04 /* interrupt pending status */
245 #define VGE_INTCTL_MASK			0x18 /* multilayer int mask */
246 #define VGE_INTCTL_RXINTSUP_DISABLE	0x20 /* disable RX int supression */
247 #define VGE_INTCTL_TXINTSUP_DISABLE	0x40 /* disable TX int supression */
248 #define VGE_INTCTL_SOFTINT		0x80 /* request soft interrupt */
249 
250 #define VGE_INTMASK_LAYER0		0x00
251 #define VGE_INTMASK_LAYER1		0x08
252 #define VGE_INTMASK_ALL			0x10
253 #define VGE_INTMASK_ALL2		0x18
254 
255 /* Transmit host error status register */
256 
257 #define VGE_TXHOSTERR_TDSTRUCT		0x01 /* bad TX desc structure */
258 #define VGE_TXHOSTERR_TDFETCH_BUSERR	0x02 /* bus error on desc fetch */
259 #define VGE_TXHOSTERR_TDWBACK_BUSERR	0x04 /* bus error on desc writeback */
260 #define VGE_TXHOSTERR_FIFOERR		0x08 /* TX FIFO DMA bus error */
261 
262 /* Receive host error status register */
263 
264 #define VGE_RXHOSTERR_RDSTRUCT		0x01 /* bad RX desc structure */
265 #define VGE_RXHOSTERR_RDFETCH_BUSERR	0x02 /* bus error on desc fetch */
266 #define VGE_RXHOSTERR_RDWBACK_BUSERR	0x04 /* bus error on desc writeback */
267 #define VGE_RXHOSTERR_FIFOERR		0x08 /* RX FIFO DMA bus error */
268 
269 /* Interrupt status register */
270 
271 #define VGE_ISR_RXOK_HIPRIO	0x00000001 /* hi prio RX int */
272 #define VGE_ISR_TXOK_HIPRIO	0x00000002 /* hi prio TX int */
273 #define VGE_ISR_RXOK		0x00000004 /* normal RX done */
274 #define VGE_ISR_TXOK		0x00000008 /* combo results for next 4 bits */
275 #define VGE_ISR_TXOK0		0x00000010 /* TX complete on queue 0 */
276 #define VGE_ISR_TXOK1		0x00000020 /* TX complete on queue 1 */
277 #define VGE_ISR_TXOK2		0x00000040 /* TX complete on queue 2 */
278 #define VGE_ISR_TXOK3		0x00000080 /* TX complete on queue 3 */
279 #define VGE_ISR_RXCNTOFLOW	0x00000400 /* RX packet count overflow */
280 #define VGE_ISR_RXPAUSE		0x00000800 /* pause frame RX'ed */
281 #define VGE_ISR_RXOFLOW		0x00001000 /* RX FIFO overflow */
282 #define VGE_ISR_RXNODESC	0x00002000 /* ran out of RX descriptors */
283 #define VGE_ISR_RXNODESC_WARN	0x00004000 /* running out of RX descs */
284 #define VGE_ISR_LINKSTS		0x00008000 /* link status change */
285 #define VGE_ISR_TIMER0		0x00010000 /* one shot timer expired */
286 #define VGE_ISR_TIMER1		0x00020000 /* periodic timer expired */
287 #define VGE_ISR_PWR		0x00040000 /* wake up power event */
288 #define VGE_ISR_PHYINT		0x00080000 /* PHY interrupt */
289 #define VGE_ISR_STOPPED		0x00100000 /* software shutdown complete */
290 #define VGE_ISR_MIBOFLOW	0x00200000 /* MIB counter overflow warning */
291 #define VGE_ISR_SOFTINT		0x00400000 /* software interrupt */
292 #define VGE_ISR_HOLDOFF_RELOAD	0x00800000 /* reload hold timer */
293 #define VGE_ISR_RXDMA_STALL	0x01000000 /* RX DMA stall */
294 #define VGE_ISR_TXDMA_STALL	0x02000000 /* TX DMA STALL */
295 #define VGE_ISR_ISRC0		0x10000000 /* interrupt source indication */
296 #define VGE_ISR_ISRC1		0x20000000 /* interrupt source indication */
297 #define VGE_ISR_ISRC2		0x40000000 /* interrupt source indication */
298 #define VGE_ISR_ISRC3		0x80000000 /* interrupt source indication */
299 
300 #define VGE_INTRS	(VGE_ISR_TXOK0|VGE_ISR_RXOK|VGE_ISR_STOPPED|	\
301 			 VGE_ISR_RXOFLOW|VGE_ISR_PHYINT|		\
302 			 VGE_ISR_LINKSTS|VGE_ISR_RXNODESC|		\
303 			 VGE_ISR_RXDMA_STALL|VGE_ISR_TXDMA_STALL)
304 
305 #define VGE_INTRS_POLLING	(VGE_ISR_PHYINT|VGE_ISR_LINKSTS)
306 
307 /* Interrupt mask register */
308 
309 #define VGE_IMR_RXOK_HIPRIO	0x00000001 /* hi prio RX int */
310 #define VGE_IMR_TXOK_HIPRIO	0x00000002 /* hi prio TX int */
311 #define VGE_IMR_RXOK		0x00000004 /* normal RX done */
312 #define VGE_IMR_TXOK		0x00000008 /* combo results for next 4 bits */
313 #define VGE_IMR_TXOK0		0x00000010 /* TX complete on queue 0 */
314 #define VGE_IMR_TXOK1		0x00000020 /* TX complete on queue 1 */
315 #define VGE_IMR_TXOK2		0x00000040 /* TX complete on queue 2 */
316 #define VGE_IMR_TXOK3		0x00000080 /* TX complete on queue 3 */
317 #define VGE_IMR_RXCNTOFLOW	0x00000400 /* RX packet count overflow */
318 #define VGE_IMR_RXPAUSE		0x00000800 /* pause frame RX'ed */
319 #define VGE_IMR_RXOFLOW		0x00001000 /* RX FIFO overflow */
320 #define VGE_IMR_RXNODESC	0x00002000 /* ran out of RX descriptors */
321 #define VGE_IMR_RXNODESC_WARN	0x00004000 /* running out of RX descs */
322 #define VGE_IMR_LINKSTS		0x00008000 /* link status change */
323 #define VGE_IMR_TIMER0		0x00010000 /* one shot timer expired */
324 #define VGE_IMR_TIMER1		0x00020000 /* periodic timer expired */
325 #define VGE_IMR_PWR		0x00040000 /* wake up power event */
326 #define VGE_IMR_PHYINT		0x00080000 /* PHY interrupt */
327 #define VGE_IMR_STOPPED		0x00100000 /* software shutdown complete */
328 #define VGE_IMR_MIBOFLOW	0x00200000 /* MIB counter overflow warning */
329 #define VGE_IMR_SOFTINT		0x00400000 /* software interrupt */
330 #define VGE_IMR_HOLDOFF_RELOAD	0x00800000 /* reload hold timer */
331 #define VGE_IMR_RXDMA_STALL	0x01000000 /* RX DMA stall */
332 #define VGE_IMR_TXDMA_STALL	0x02000000 /* TX DMA STALL */
333 #define VGE_IMR_ISRC0		0x10000000 /* interrupt source indication */
334 #define VGE_IMR_ISRC1		0x20000000 /* interrupt source indication */
335 #define VGE_IMR_ISRC2		0x40000000 /* interrupt source indication */
336 #define VGE_IMR_ISRC3		0x80000000 /* interrupt source indication */
337 
338 /* TX descriptor queue control/status register */
339 
340 #define VGE_TXQCSR_RUN0		0x0001	/* Enable TX queue 0 */
341 #define VGE_TXQCSR_ACT0		0x0002	/* queue 0 active indicator */
342 #define VGE_TXQCSR_WAK0		0x0004	/* Wake up (poll) queue 0 */
343 #define VGE_TXQCSR_DEAD0	0x0008	/* queue 0 dead indicator */
344 #define VGE_TXQCSR_RUN1		0x0010	/* Enable TX queue 1 */
345 #define VGE_TXQCSR_ACT1		0x0020	/* queue 1 active indicator */
346 #define VGE_TXQCSR_WAK1		0x0040	/* Wake up (poll) queue 1 */
347 #define VGE_TXQCSR_DEAD1	0x0080	/* queue 1 dead indicator */
348 #define VGE_TXQCSR_RUN2		0x0100	/* Enable TX queue 2 */
349 #define VGE_TXQCSR_ACT2		0x0200	/* queue 2 active indicator */
350 #define VGE_TXQCSR_WAK2		0x0400	/* Wake up (poll) queue 2 */
351 #define VGE_TXQCSR_DEAD2	0x0800	/* queue 2 dead indicator */
352 #define VGE_TXQCSR_RUN3		0x1000	/* Enable TX queue 3 */
353 #define VGE_TXQCSR_ACT3		0x2000	/* queue 3 active indicator */
354 #define VGE_TXQCSR_WAK3		0x4000	/* Wake up (poll) queue 3 */
355 #define VGE_TXQCSR_DEAD3	0x8000	/* queue 3 dead indicator */
356 
357 /* RX descriptor queue control/status register */
358 
359 #define VGE_RXQCSR_RUN		0x0001	/* Enable RX queue */
360 #define VGE_RXQCSR_ACT		0x0002	/* queue active indicator */
361 #define VGE_RXQCSR_WAK		0x0004	/* Wake up (poll) queue */
362 #define VGE_RXQCSR_DEAD		0x0008	/* queue dead indicator */
363 
364 /* RX/TX queue empty interrupt delay timer register */
365 
366 #define VGE_QTIMER_PENDCNT	0x3F
367 #define VGE_QTIMER_RESOLUTION	0xC0
368 
369 #define VGE_QTIMER_RES_1US	0x00
370 #define VGE_QTIMER_RES_4US	0x40
371 #define VGE_QTIMER_RES_16US	0x80
372 #define VGE_QTIMER_RES_64US	0xC0
373 
374 /* CAM address register */
375 
376 #define VGE_CAMADDR_ADDR	0x3F	/* CAM address to program */
377 #define VGE_CAMADDR_AVSEL	0x40	/* 0 = address cam, 1 = VLAN cam */
378 #define VGE_CAMADDR_ENABLE	0x80	/* enable CAM read/write */
379 
380 #define VGE_CAM_MAXADDRS	64
381 
382 /*
383  * CAM command register
384  * Note that the page select bits in this register affect three
385  * different things:
386  * - The behavior of the MAR0/MAR1 registers at offset 0x10 (the
387  *   page select bits control whether the MAR0/MAR1 registers affect
388  *   the multicast hash filter or the CAM table)
389  * - The behavior of the interrupt holdoff timer register at offset
390  *   0x20 (the page select bits allow you to set the interrupt
391  *   holdoff timer, the TX interrupt supression count or the
392  *   RX interrupt supression count)
393  * - The behavior the WOL pattern programming registers at offset
394  *   0xC0 (controls which pattern is set)
395  */
396 
397 #define VGE_CAMCTL_WRITE	0x04	/* CAM write command */
398 #define VGE_CAMCTL_READ		0x08	/* CAM read command */
399 #define VGE_CAMCTL_INTPKT_SIZ	0x10	/* select interesting pkt CAM size */
400 #define VGE_CAMCTL_INTPKT_ENB	0x20	/* enable interesting packet mode */
401 #define VGE_CAMCTL_PAGESEL	0xC0	/* page select */
402 
403 #define VGE_PAGESEL_MAR		0x00
404 #define VGE_PAGESEL_CAMMASK	0x40
405 #define VGE_PAGESEL_CAMDATA	0x80
406 
407 #define VGE_PAGESEL_INTHLDOFF	0x00
408 #define VGE_PAGESEL_TXSUPPTHR	0x40
409 #define VGE_PAGESEL_RXSUPPTHR	0x80
410 
411 #define VGE_PAGESEL_WOLPAT0	0x00
412 #define VGE_PAGESEL_WOLPAT1	0x40
413 
414 /* MII port config register */
415 
416 #define VGE_MIICFG_PHYADDR	0x1F	/* PHY address (internal PHY is 1) */
417 #define VGE_MIICFG_MDCSPEED	0x20	/* MDC accelerate x 4 */
418 #define VGE_MIICFG_POLLINT	0xC0	/* polling interval */
419 
420 #define VGE_MIIPOLLINT_1024	0x00
421 #define VGE_MIIPOLLINT_512	0x40
422 #define VGE_MIIPOLLINT_128	0x80
423 #define VGE_MIIPOLLINT_64	0xC0
424 
425 /* MII port status register */
426 
427 #define VGE_MIISTS_IIDL		0x80	/* not at sofrware/timer poll cycle */
428 
429 /* PHY status register */
430 
431 #define VGE_PHYSTS_TXFLOWCAP	0x01	/* resolved TX flow control cap */
432 #define VGE_PHYSTS_RXFLOWCAP	0x02	/* resolved RX flow control cap */
433 #define VGE_PHYSTS_SPEED10	0x04	/* PHY in 10Mbps mode */
434 #define VGE_PHYSTS_SPEED1000	0x08	/* PHY in giga mode */
435 #define VGE_PHYSTS_FDX		0x10	/* PHY in full duplex mode */
436 #define VGE_PHYSTS_LINK		0x40	/* link status */
437 #define VGE_PHYSTS_RESETSTS	0x80	/* reset status */
438 
439 /* MII management command register */
440 
441 #define VGE_MIICMD_MDC		0x01	/* clock pin */
442 #define VGE_MIICMD_MDI		0x02	/* data in pin */
443 #define VGE_MIICMD_MDO		0x04	/* data out pin */
444 #define VGE_MIICMD_MOUT		0x08	/* data out pin enable */
445 #define VGE_MIICMD_MDP		0x10	/* enable direct programming mode */
446 #define VGE_MIICMD_WCMD		0x20	/* embedded mode write */
447 #define VGE_MIICMD_RCMD		0x40	/* embedded mode read */
448 #define VGE_MIICMD_MAUTO	0x80	/* enable autopolling */
449 
450 /* MII address register */
451 
452 #define VGE_MIIADDR_SWMPL	0x80	/* initiate priority resolution */
453 
454 /* Chip config register A */
455 
456 #define VGE_CHIPCFG0_PACPI	0x01	/* pre-ACPI wakeup function */
457 #define VGE_CHIPCFG0_ABSHDN	0x02	/* abnormal shutdown function */
458 #define VGE_CHIPCFG0_GPIO1PD	0x04	/* GPIO pin enable */
459 #define VGE_CHIPCFG0_SKIPTAG	0x08	/* omit 802.1p tag from CRC calc */
460 #define VGE_CHIPCFG0_PHLED	0x30	/* phy LED select */
461 
462 /* Chip config register B */
463 /* Note: some of these bits are not documented in the manual! */
464 
465 #define VGE_CHIPCFG1_BAKOPT	0x01
466 #define VGE_CHIPCFG1_MBA	0x02
467 #define VGE_CHIPCFG1_CAP	0x04
468 #define VGE_CHIPCFG1_CRANDOM	0x08
469 #define VGE_CHIPCFG1_OFSET	0x10
470 #define VGE_CHIPCFG1_SLOTTIME	0x20	/* slot time 512/500 in giga mode */
471 #define VGE_CHIPCFG1_MIIOPT	0x40
472 #define VGE_CHIPCFG1_GTCKOPT	0x80
473 
474 /* Chip config register C */
475 
476 #define VGE_CHIPCFG2_EELOAD	0x80	/* enable EEPROM programming */
477 
478 /* Chip config register D */
479 
480 #define VGE_CHIPCFG3_64BIT_DAC	0x20	/* enable 64bit via DAC */
481 #define VGE_CHIPCFG3_IODISABLE	0x80	/* disable I/O access mode */
482 
483 /* DMA config register 0 */
484 
485 #define VGE_DMACFG0_BURSTLEN	0x07	/* RX/TX DMA burst (in dwords) */
486 
487 #define VGE_DMABURST_8		0x00
488 #define VGE_DMABURST_16		0x01
489 #define VGE_DMABURST_32		0x02
490 #define VGE_DMABURST_64		0x03
491 #define VGE_DMABURST_128	0x04
492 #define VGE_DMABURST_256	0x05
493 #define VGE_DMABURST_STRFWD	0x07
494 
495 /* DMA config register 1 */
496 
497 #define VGE_DMACFG1_LATENB	0x01	/* Latency timer enable */
498 #define VGE_DMACFG1_MWWAIT	0x02	/* insert wait on master write */
499 #define VGE_DMACFG1_MRWAIT	0x04	/* insert wait on master read */
500 #define VGE_DMACFG1_MRM		0x08	/* use memory read multiple */
501 #define VGE_DMACFG1_PERR_DIS	0x10	/* disable parity error checking */
502 #define VGE_DMACFG1_XMRL	0x20	/* disable memory read line support */
503 
504 /* RX MAC config register */
505 
506 #define VGE_RXCFG_VLANFILT	0x01	/* filter VLAN ID mismatches */
507 #define VGE_RXCFG_VTAGOPT	0x06	/* VLAN tag handling */
508 #define VGE_RXCFG_FIFO_LOWAT	0x08	/* RX FIFO low watermark (7QW/15QW) */
509 #define VGE_RXCFG_FIFO_THR	0x30	/* RX FIFO threshold */
510 #define VGE_RXCFG_ARB_PRIO	0x80	/* arbitration priority */
511 
512 #define VGE_VTAG_OPT0		0x00	/* TX: no tag insertion
513 					   RX: rx all, no tag extraction */
514 
515 #define VGE_VTAG_OPT1		0x02	/* TX: no tag insertion
516 					   RX: rx only tagged pkts, no
517 					       extraction */
518 
519 #define VGE_VTAG_OPT2		0x04	/* TX: perform tag insertion,
520 					   RX: rx all, extract tags */
521 
522 #define VGE_VTAG_OPT3		0x06	/* TX: perform tag insertion,
523 					   RX: rx only tagged pkts,
524 					       with extraction */
525 
526 #define VGE_RXFIFOTHR_128BYTES	0x00
527 #define VGE_RXFIFOTHR_512BYTES	0x10
528 #define VGE_RXFIFOTHR_1024BYTES	0x20
529 #define VGE_RXFIFOTHR_STRNFWD	0x30
530 
531 /* TX MAC config register */
532 
533 #define VGE_TXCFG_SNAPOPT	0x01	/* 1 == insert VLAN tag at
534 					   13th byte
535 					   0 == insert VLANM tag after
536 					   SNAP header (21st byte) */
537 #define VGE_TXCFG_NONBLK	0x02	/* priority TX/non-blocking mode */
538 #define VGE_TXCFG_NONBLK_THR	0x0C	/* non-blocking threshold */
539 #define VGE_TXCFG_ARB_PRIO	0x80	/* arbitration priority */
540 
541 #define VGE_TXBLOCK_64PKTS	0x00
542 #define VGE_TXBLOCK_32PKTS	0x04
543 #define VGE_TXBLOCK_128PKTS	0x08
544 #define VGE_TXBLOCK_8PKTS	0x0C
545 
546 /* MIB control/status register */
547 #define	VGE_MIBCSR_CLR		0x01
548 #define	VGE_MIBCSR_RINI		0x02
549 #define	VGE_MIBCSR_FLUSH	0x04
550 #define	VGE_MIBCSR_FREEZE	0x08
551 #define	VGE_MIBCSR_HI_80	0x00
552 #define	VGE_MIBCSR_HI_C0	0x10
553 #define	VGE_MIBCSR_BISTGO	0x40
554 #define	VGE_MIBCSR_BISTOK	0x80
555 
556 /* MIB data index. */
557 #define	VGE_MIB_RX_FRAMES		0
558 #define	VGE_MIB_RX_GOOD_FRAMES		1
559 #define	VGE_MIB_TX_GOOD_FRAMES		2
560 #define	VGE_MIB_RX_FIFO_OVERRUNS	3
561 #define	VGE_MIB_RX_RUNTS		4
562 #define	VGE_MIB_RX_RUNTS_ERRS		5
563 #define	VGE_MIB_RX_PKTS_64		6
564 #define	VGE_MIB_TX_PKTS_64		7
565 #define	VGE_MIB_RX_PKTS_65_127		8
566 #define	VGE_MIB_TX_PKTS_65_127		9
567 #define	VGE_MIB_RX_PKTS_128_255		10
568 #define	VGE_MIB_TX_PKTS_128_255		11
569 #define	VGE_MIB_RX_PKTS_256_511		12
570 #define	VGE_MIB_TX_PKTS_256_511		13
571 #define	VGE_MIB_RX_PKTS_512_1023	14
572 #define	VGE_MIB_TX_PKTS_512_1023	15
573 #define	VGE_MIB_RX_PKTS_1024_1518	16
574 #define	VGE_MIB_TX_PKTS_1024_1518	17
575 #define	VGE_MIB_TX_COLLS		18
576 #define	VGE_MIB_RX_CRCERRS		19
577 #define	VGE_MIB_RX_JUMBOS		20
578 #define	VGE_MIB_TX_JUMBOS		21
579 #define	VGE_MIB_RX_PAUSE		22
580 #define	VGE_MIB_TX_PAUSE		23
581 #define	VGE_MIB_RX_ALIGNERRS		24
582 #define	VGE_MIB_RX_PKTS_1519_MAX	25
583 #define	VGE_MIB_RX_PKTS_1519_MAX_ERRS	26
584 #define	VGE_MIB_TX_SQEERRS		27
585 #define	VGE_MIB_RX_NOBUFS		28
586 #define	VGE_MIB_RX_SYMERRS		29
587 #define	VGE_MIB_RX_LENERRS		30
588 #define	VGE_MIB_TX_LATECOLLS		31
589 
590 #define	VGE_MIB_CNT		(VGE_MIB_TX_LATECOLLS - VGE_MIB_RX_FRAMES + 1)
591 #define	VGE_MIB_DATA_MASK	0x00FFFFFF
592 #define	VGE_MIB_DATA_IDX(x)	((x) >> 24)
593 
594 /* Sticky bit shadow register */
595 
596 #define	VGE_STICKHW_DS0		0x01
597 #define	VGE_STICKHW_DS1		0x02
598 #define	VGE_STICKHW_WOL_ENB	0x04
599 #define	VGE_STICKHW_WOL_STS	0x08
600 #define	VGE_STICKHW_SWPTAG	0x10
601 
602 /* WOL pattern control */
603 #define	VGE_WOLCR0_PATTERN0	0x01
604 #define	VGE_WOLCR0_PATTERN1	0x02
605 #define	VGE_WOLCR0_PATTERN2	0x04
606 #define	VGE_WOLCR0_PATTERN3	0x08
607 #define	VGE_WOLCR0_PATTERN4	0x10
608 #define	VGE_WOLCR0_PATTERN5	0x20
609 #define	VGE_WOLCR0_PATTERN6	0x40
610 #define	VGE_WOLCR0_PATTERN7	0x80
611 #define	VGE_WOLCR0_PATTERN_ALL	0xFF
612 
613 /* WOL event control */
614 #define	VGE_WOLCR1_UCAST	0x01
615 #define	VGE_WOLCR1_MAGIC	0x02
616 #define	VGE_WOLCR1_LINKON	0x04
617 #define	VGE_WOLCR1_LINKOFF	0x08
618 
619 /* Poweer management config */
620 #define VGE_PWRCFG_LEGACY_WOLEN	0x01
621 #define VGE_PWRCFG_WOL_PULSE	0x20
622 #define VGE_PWRCFG_WOL_BUTTON	0x00
623 
624 /* WOL config register */
625 #define	VGE_WOLCFG_PHYINT_ENB	0x01
626 #define	VGE_WOLCFG_SAB		0x10
627 #define	VGE_WOLCFG_SAM		0x20
628 #define	VGE_WOLCFG_PMEOVR	0x80
629 
630 /* EEPROM control/status register */
631 
632 #define VGE_EECSR_EDO		0x01	/* data out pin */
633 #define VGE_EECSR_EDI		0x02	/* data in pin */
634 #define VGE_EECSR_ECK		0x04	/* clock pin */
635 #define VGE_EECSR_ECS		0x08	/* chip select pin */
636 #define VGE_EECSR_DPM		0x10	/* direct program mode enable */
637 #define VGE_EECSR_RELOAD	0x20	/* trigger reload from EEPROM */
638 #define VGE_EECSR_EMBP		0x40	/* embedded program mode enable */
639 
640 /* EEPROM embedded command register */
641 
642 #define VGE_EECMD_ERD		0x01	/* EEPROM read command */
643 #define VGE_EECMD_EWR		0x02	/* EEPROM write command */
644 #define VGE_EECMD_EWEN		0x04	/* EEPROM write enable */
645 #define VGE_EECMD_EWDIS		0x08	/* EEPROM write disable */
646 #define VGE_EECMD_EDONE		0x80	/* read/write done */
647 
648 /* Chip operation and diagnostic control register */
649 
650 #define VGE_DIAGCTL_PHYINT_ENB	0x01	/* Enable PHY interrupts */
651 #define VGE_DIAGCTL_TIMER0_RES	0x02	/* timer0 uSec resolution */
652 #define VGE_DIAGCTL_TIMER1_RES	0x04	/* timer1 uSec resolution */
653 #define VGE_DIAGCTL_LPSEL_DIS	0x08	/* disable LPSEL field */
654 #define VGE_DIAGCTL_MACFORCE	0x10	/* MAC side force mode */
655 #define VGE_DIAGCTL_FCRSVD	0x20	/* reserved for future fiber use */
656 #define VGE_DIAGCTL_FDXFORCE	0x40	/* force full duplex mode */
657 #define VGE_DIAGCTL_GMII	0x80	/* force GMII mode, otherwise MII */
658 
659 /* Location of station address in EEPROM */
660 #define VGE_EE_EADDR		0
661 
662 /* DMA descriptor structures */
663 
664 /*
665  * Each TX DMA descriptor has a control and status word, and 7
666  * fragment address/length words. If a transmitted packet spans
667  * more than 7 fragments, it has to be coalesced.
668  */
669 
670 #define VGE_TX_FRAGS	7
671 
672 struct vge_tx_frag {
673 	uint32_t		vge_addrlo;
674 	uint32_t		vge_addrhi;
675 };
676 
677 /*
678  * The high bit in the buflen field of fragment #0 has special meaning.
679  * Normally, the chip requires the driver to issue a TX poll command
680  * for every packet that gets put in the TX DMA queue. Sometimes though,
681  * the driver might want to queue up several packets at once and just
682  * issue one transmit command to have all of them processed. In order
683  * to obtain this behavior, the special 'queue' bit must be set.
684  */
685 
686 #define VGE_TXDESC_Q		0x80000000
687 
688 struct vge_tx_desc {
689 	uint32_t		vge_sts;
690 	uint32_t		vge_ctl;
691 	struct vge_tx_frag	vge_frag[VGE_TX_FRAGS];
692 };
693 
694 #define VGE_TDSTS_COLLCNT	0x0000000F	/* TX collision count */
695 #define VGE_TDSTS_COLL		0x00000010	/* collision seen */
696 #define VGE_TDSTS_OWINCOLL	0x00000020	/* out of window collision */
697 #define VGE_TDSTS_OWT		0x00000040	/* jumbo frame tx abort */
698 #define VGE_TDSTS_EXCESSCOLL	0x00000080	/* TX aborted, excess colls */
699 #define VGE_TDSTS_HBEATFAIL	0x00000100	/* heartbeat detect failed */
700 #define VGE_TDSTS_CARRLOSS	0x00000200	/* carrier sense lost */
701 #define VGE_TDSTS_SHUTDOWN	0x00000400	/* shutdown during TX */
702 #define VGE_TDSTS_LINKFAIL	0x00001000	/* link fail during TX */
703 #define VGE_TDSTS_GMII		0x00002000	/* GMII transmission */
704 #define VGE_TDSTS_FDX		0x00004000	/* full duplex transmit */
705 #define VGE_TDSTS_TXERR		0x00008000	/* error occurred */
706 #define VGE_TDSTS_SEGSIZE	0x3FFF0000	/* TCP large send size */
707 #define VGE_TDSTS_OWN		0x80000000	/* own bit */
708 
709 #define VGE_TDCTL_VLANID	0x00000FFF	/* VLAN ID */
710 #define VGE_TDCTL_CFI		0x00001000	/* VLAN CFI bit */
711 #define VGE_TDCTL_PRIO		0x0000E000	/* VLAN prio bits */
712 #define VGE_TDCTL_NOCRC		0x00010000	/* disable CRC generation */
713 #define VGE_TDCTL_JUMBO		0x00020000	/* jumbo frame */
714 #define VGE_TDCTL_TCPCSUM	0x00040000	/* do TCP hw checksum */
715 #define VGE_TDCTL_UDPCSUM	0x00080000	/* do UDP hw checksum */
716 #define VGE_TDCTL_IPCSUM	0x00100000	/* do IP hw checksum */
717 #define VGE_TDCTL_VTAG		0x00200000	/* insert VLAN tag */
718 #define VGE_TDCTL_PRIO_INT	0x00400000	/* priority int request */
719 #define VGE_TDCTL_TIC		0x00800000	/* transfer int request */
720 #define VGE_TDCTL_TCPLSCTL	0x03000000	/* TCP large send ctl */
721 #define VGE_TDCTL_FRAGCNT	0xF0000000	/* number of frags used */
722 
723 #define VGE_TD_LS_MOF		0x00000000	/* middle of large send */
724 #define VGE_TD_LS_SOF		0x01000000	/* start of large send */
725 #define VGE_TD_LS_EOF		0x02000000	/* end of large send */
726 #define VGE_TD_LS_NORM		0x03000000	/* normal frame */
727 
728 /* Receive DMA descriptors have a single fragment pointer. */
729 
730 struct vge_rx_desc {
731 	uint32_t	vge_sts;
732 	uint32_t	vge_ctl;
733 	uint32_t	vge_addrlo;
734 	uint32_t	vge_addrhi;
735 };
736 
737 /*
738  * Like the TX descriptor, the high bit in the buflen field in the
739  * RX descriptor has special meaning. This bit controls whether or
740  * not interrupts are generated for this descriptor.
741  */
742 
743 #define VGE_RXDESC_I		0x80000000
744 
745 #define VGE_RDSTS_VIDM		0x00000001	/* VLAN tag filter miss */
746 #define VGE_RDSTS_CRCERR	0x00000002	/* bad CRC error */
747 #define VGE_RDSTS_FAERR		0x00000004	/* frame alignment error */
748 #define VGE_RDSTS_CSUMERR	0x00000008	/* bad TCP/IP checksum */
749 #define VGE_RDSTS_RLERR		0x00000010	/* RX length error */
750 #define VGE_RDSTS_SYMERR	0x00000020	/* PCS symbol error */
751 #define VGE_RDSTS_SNTAG		0x00000040	/* RX'ed tagged SNAP pkt */
752 #define VGE_RDSTS_DETAG		0x00000080	/* VLAN tag extracted */
753 #define VGE_RDSTS_BOUNDARY	0x00000300	/* frame boundary bits */
754 #define VGE_RDSTS_VTAG		0x00000400	/* VLAN tag indicator */
755 #define VGE_RDSTS_UCAST		0x00000800	/* unicast frame */
756 #define VGE_RDSTS_BCAST		0x00001000	/* broadcast frame */
757 #define VGE_RDSTS_MCAST		0x00002000	/* multicast frame */
758 #define VGE_RDSTS_PFT		0x00004000	/* perfect filter hit */
759 #define VGE_RDSTS_RXOK		0x00008000	/* frame is good. */
760 #define VGE_RDSTS_BUFSIZ	0x3FFF0000	/* received frame len */
761 #define VGE_RDSTS_SHUTDOWN	0x40000000	/* shutdown during RX */
762 #define VGE_RDSTS_OWN		0x80000000	/* own bit. */
763 
764 #define VGE_RXPKT_ONEFRAG	0x00000000	/* only one fragment */
765 #define VGE_RXPKT_EOF		0x00000100	/* last frag in frame */
766 #define VGE_RXPKT_SOF		0x00000200	/* first frag in frame */
767 #define VGE_RXPKT_MOF		0x00000300	/* intermediate frag */
768 
769 #define VGE_RDCTL_VLANID	0x0000FFFF	/* VLAN ID info */
770 #define VGE_RDCTL_UDPPKT	0x00010000	/* UDP packet received */
771 #define VGE_RDCTL_TCPPKT	0x00020000	/* TCP packet received */
772 #define VGE_RDCTL_IPPKT		0x00040000	/* IP packet received */
773 #define VGE_RDCTL_UDPZERO	0x00080000	/* pkt with UDP CSUM of 0 */
774 #define VGE_RDCTL_FRAG		0x00100000	/* received IP frag */
775 #define VGE_RDCTL_PROTOCSUMOK	0x00200000	/* TCP/UDP checksum ok */
776 #define VGE_RDCTL_IPCSUMOK	0x00400000	/* IP checksum ok */
777 #define VGE_RDCTL_FILTIDX	0x3C000000	/* interesting filter idx */
778 
779 #endif /* _IF_VGEREG_H_ */
780