1 /******************************************************************************* 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3 * 4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided 5 *that the following conditions are met: 6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7 *following disclaimer. 8 *2. Redistributions in binary form must reproduce the above copyright notice, 9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided 10 *with the distribution. 11 * 12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20 * 21 * 22 ********************************************************************************/ 23 #ifndef __SMDEFS_H__ 24 #define __SMDEFS_H__ 25 26 #include <dev/pms/RefTisa/tisa/sassata/common/ossa.h> 27 28 /* the index for memory requirement, must be continious */ 29 #define SM_ROOT_MEM_INDEX 0 /**< the index of dm root memory */ 30 #define SM_DEVICE_MEM_INDEX 1 /**< the index of Device descriptors memory */ 31 #define SM_IO_MEM_INDEX 2 /**< the index of IO command descriptors memory */ 32 33 34 #define SM_MAX_DEV 256 35 #define SM_MAX_IO 1024 36 37 #define SM_USECS_PER_TICK 1000000 /**< defines the heart beat of the LL layer 10ms */ 38 39 enum sm_locks_e 40 { 41 SM_TIMER_LOCK = 0, 42 SM_DEVICE_LOCK, 43 SM_INTERNAL_IO_LOCK, 44 SM_EXTERNAL_IO_LOCK, 45 SM_NCQ_TAG_LOCK, 46 SM_TBD_LOCK, 47 SM_MAX_LOCKS 48 }; 49 50 /* ATA device type */ 51 #define SATA_ATA_DEVICE 0x01 /**< ATA ATA device type */ 52 #define SATA_ATAPI_DEVICE 0x02 /**< ATA ATAPI device type */ 53 #define SATA_PM_DEVICE 0x03 /**< ATA PM device type */ 54 #define SATA_SEMB_DEVICE 0x04 /**< ATA SEMB device type */ 55 #define SATA_SEMB_WO_SEP_DEVICE 0x05 /**< ATA SEMB without SEP device type */ 56 #define UNKNOWN_DEVICE 0xFF 57 58 /* 59 * FIS type 60 */ 61 #define PIO_SETUP_DEV_TO_HOST_FIS 0x5F 62 #define REG_DEV_TO_HOST_FIS 0x34 63 #define SET_DEV_BITS_FIS 0xA1 64 65 /* 66 * ATA Command code 67 */ 68 #define SAT_READ_FPDMA_QUEUED 0x60 69 #define SAT_READ_DMA_EXT 0x25 70 #define SAT_READ_DMA 0xC8 71 #define SAT_WRITE_FPDMA_QUEUED 0x61 72 #define SAT_WRITE_DMA_EXT 0x35 73 #define SAT_WRITE_DMA_FUA_EXT 0x3D 74 #define SAT_WRITE_DMA 0xCA 75 #define SAT_CHECK_POWER_MODE 0xE5 76 #define SAT_READ_LOG_EXT 0x2F 77 #define SAT_READ_VERIFY_SECTORS 0x40 78 #define SAT_READ_VERIFY_SECTORS_EXT 0x42 79 #define SAT_SMART 0xB0 80 #define SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE 0xD4 81 #define SAT_SMART_RETURN_STATUS 0xDA 82 #define SAT_SMART_READ_LOG 0xD5 83 #define SAT_SMART_ENABLE_OPERATIONS 0xD8 84 #define SAT_SMART_DISABLE_OPERATIONS 0xD9 85 #define SAT_FLUSH_CACHE 0xE7 86 #define SAT_FLUSH_CACHE_EXT 0xEA 87 #define SAT_STANDBY 0xE2 88 #define SAT_MEDIA_EJECT 0xED 89 #define SAT_WRITE_SECTORS 0x30 90 #define SAT_WRITE_SECTORS_EXT 0x34 91 #define SAT_READ_SECTORS 0x20 92 #define SAT_READ_SECTORS_EXT 0x24 93 #define SAT_GET_MEDIA_STATUS 0xDA 94 #define SAT_SET_FEATURES 0xEF 95 #define SAT_IDENTIFY_DEVICE 0xEC 96 #define SAT_READ_BUFFER 0xE4 97 #define SAT_WRITE_BUFFER 0xE8 98 99 /* 100 * ATAPI Command code 101 */ 102 #define SAT_IDENTIFY_PACKET_DEVICE 0xA1 103 #define SAT_PACKET 0xA0 104 #define SAT_DEVICE_RESET 0x08 105 #define SAT_EXECUTE_DEVICE_DIAGNOSTIC 0x90 106 107 108 /* 109 * ATA Status Register Mask 110 */ 111 #define ERR_ATA_STATUS_MASK 0x01 /* Error/check bit */ 112 #define DRQ_ATA_STATUS_MASK 0x08 /* Data Request bit */ 113 #define DF_ATA_STATUS_MASK 0x20 /* Device Fault bit */ 114 #define DRDY_ATA_STATUS_MASK 0x40 /* Device Ready bit */ 115 #define BSY_ATA_STATUS_MASK 0x80 /* Busy bit */ 116 117 /* 118 * ATA Error Register Mask 119 */ 120 #define NM_ATA_ERROR_MASK 0x02 /* No media present bit */ 121 #define ABRT_ATA_ERROR_MASK 0x04 /* Command aborted bit */ 122 #define MCR_ATA_ERROR_MASK 0x08 /* Media change request bit */ 123 #define IDNF_ATA_ERROR_MASK 0x10 /* Address not found bit */ 124 #define MC_ATA_ERROR_MASK 0x20 /* Media has changed bit */ 125 #define UNC_ATA_ERROR_MASK 0x40 /* Uncorrectable data error bit */ 126 #define ICRC_ATA_ERROR_MASK 0x80 /* Interface CRC error bit */ 127 128 129 130 131 /* 132 * transfer length and LBA limit 2^28 See identify device data word 61:60 133 * ATA spec p125 134 * 7 zeros 135 */ 136 #define SAT_TR_LBA_LIMIT 0x10000000 137 138 /* 139 * transfer length and LBA limit 2^48 See identify device data word 61:60 140 * ATA spec p125 141 * 12 zeros 142 */ 143 #define SAT_EXT_TR_LBA_LIMIT 0x1000000000000 144 145 146 /* 147 * ATA command type. This is for setting LBA, Sector Count 148 */ 149 #define SAT_NON_EXT_TYPE 0 150 #define SAT_EXT_TYPE 1 151 #define SAT_FP_TYPE 2 152 153 154 /* 155 * Report LUNs response data. 156 */ 157 typedef struct smScsiReportLun_s 158 { 159 bit8 len[4]; 160 bit32 reserved; 161 tiLUN_t lunList[1]; 162 } smScsiReportLun_t; 163 164 /* Inquiry vendor string */ 165 #define AG_SAT_VENDOR_ID_STRING "ATA " 166 167 /* 168 * Simple form of SATA Identify Device Data, similar definition is defined by 169 * LL Layer as agsaSATAIdentifyData_t. 170 */ 171 typedef struct satSimpleSATAIdentifyData_s 172 { 173 bit16 word[256]; 174 } satSimpleSATAIdentifyData_t; 175 176 177 /* 178 * READ LOG EXT page 10h 179 */ 180 typedef struct satReadLogExtPage10h_s 181 { 182 bit8 byte[512]; 183 } satReadLogExtPage10h_t; 184 185 /* 186 * READ LOG EXT Extended Self-test log 187 * ATA Table27 p196 188 */ 189 typedef struct satReadLogExtSelfTest_s 190 { 191 bit8 byte[512]; 192 } satReadLogExtSelfTest_t; 193 194 /* 195 * SMART READ LOG Self-test log 196 * ATA Table60 p296 197 */ 198 typedef struct satSmartReadLogSelfTest_s 199 { 200 bit8 byte[512]; 201 } satSmartReadLogSelfTest_t; 202 203 204 /* 205 * Flag definition for satIntFlag field in smSatInternalIo_t. 206 */ 207 208 /* Original NCQ I/O already completed, so at the completion of READ LOG EXT 209 * page 10h, ignore the TAG tranaltion to get the failed I/O 210 */ 211 #define AG_SAT_INT_IO_FLAG_ORG_IO_COMPLETED 0x00000001 212 213 #define INQUIRY_SUPPORTED_VPD_PAGE 0x00 214 #define INQUIRY_UNIT_SERIAL_NUMBER_VPD_PAGE 0x80 215 #define INQUIRY_DEVICE_IDENTIFICATION_VPD_PAGE 0x83 216 #define INQUIRY_ATA_INFORMATION_VPD_PAGE 0x89 217 #define INQUIRY_BLOCK_DEVICE_CHARACTERISTICS_VPD_PAGE 0xB1 218 219 #define MODESENSE_CONTROL_PAGE 0x0A 220 #define MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE 0x01 221 #define MODESENSE_CACHING 0x08 222 #define MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE 0x1C 223 #define MODESENSE_RETURN_ALL_PAGES 0x3F 224 #define MODESENSE_VENDOR_SPECIFIC_PAGE 0x00 225 226 #define MODESELECT_CONTROL_PAGE 0x0A 227 #define MODESELECT_READ_WRITE_ERROR_RECOVERY_PAGE 0x01 228 #define MODESELECT_CACHING 0x08 229 #define MODESELECT_INFORMATION_EXCEPTION_CONTROL_PAGE 0x1C 230 #define MODESELECT_RETURN_ALL_PAGES 0x3F 231 #define MODESELECT_VENDOR_SPECIFIC_PAGE 0x00 232 233 #define LOGSENSE_SUPPORTED_LOG_PAGES 0x00 234 #define LOGSENSE_SELFTEST_RESULTS_PAGE 0x10 235 #define LOGSENSE_INFORMATION_EXCEPTIONS_PAGE 0x2F 236 237 238 /* 239 * Bit mask definition 240 */ 241 #define SCSI_EVPD_MASK 0x01 242 #define SCSI_IMMED_MASK 0x01 243 #define SCSI_NACA_MASK 0x04 244 #define SCSI_LINK_MASK 0x01 245 #define SCSI_PF_MASK 0x10 246 #define SCSI_DEVOFFL_MASK 0x02 247 #define SCSI_UNITOFFL_MASK 0x01 248 #define SCSI_START_MASK 0x01 249 #define SCSI_LOEJ_MASK 0x02 250 #define SCSI_NM_MASK 0x02 251 #define SCSI_FLUSH_CACHE_IMMED_MASK 0x02 252 #define SCSI_FUA_NV_MASK 0x02 253 #define SCSI_VERIFY_BYTCHK_MASK 0x02 254 #define SCSI_FORMAT_UNIT_IMMED_MASK 0x02 255 #define SCSI_FORMAT_UNIT_FOV_MASK 0x80 256 #define SCSI_FORMAT_UNIT_DCRT_MASK 0x20 257 #define SCSI_FORMAT_UNIT_IP_MASK 0x08 258 #define SCSI_WRITE_SAME_LBDATA_MASK 0x02 259 #define SCSI_WRITE_SAME_PBDATA_MASK 0x04 260 #define SCSI_SYNC_CACHE_IMMED_MASK 0x02 261 #define SCSI_WRITE_N_VERIFY_BYTCHK_MASK 0x02 262 #define SCSI_SEND_DIAGNOSTIC_SELFTEST_MASK 0x04 263 #define SCSI_FORMAT_UNIT_DEFECT_LIST_FORMAT_MASK 0x07 264 #define SCSI_FORMAT_UNIT_FMTDATA_MASK 0x10 265 #define SCSI_FORMAT_UNIT_DCRT_MASK 0x20 266 #define SCSI_FORMAT_UNIT_CMPLIST_MASK 0x08 267 #define SCSI_FORMAT_UNIT_LONGLIST_MASK 0x20 268 #define SCSI_READ10_FUA_MASK 0x08 269 #define SCSI_READ12_FUA_MASK 0x08 270 #define SCSI_READ16_FUA_MASK 0x08 271 #define SCSI_WRITE10_FUA_MASK 0x08 272 #define SCSI_WRITE12_FUA_MASK 0x08 273 #define SCSI_WRITE16_FUA_MASK 0x08 274 #define SCSI_READ_CAPACITY10_PMI_MASK 0x01 275 #define SCSI_READ_CAPACITY16_PMI_MASK 0x01 276 #define SCSI_MODE_SENSE6_PC_MASK 0xC0 277 #define SCSI_MODE_SENSE6_PAGE_CODE_MASK 0x3F 278 #define SCSI_MODE_SENSE10_PC_MASK 0xC0 279 #define SCSI_MODE_SENSE10_LLBAA_MASK 0x10 280 #define SCSI_MODE_SENSE10_PAGE_CODE_MASK 0x3F 281 #define SCSI_SEND_DIAGNOSTIC_TEST_CODE_MASK 0xE0 282 #define SCSI_LOG_SENSE_PAGE_CODE_MASK 0x3F 283 #define SCSI_MODE_SELECT6_PF_MASK 0x10 284 #define SCSI_MODE_SELECT6_AWRE_MASK 0x80 285 #define SCSI_MODE_SELECT6_RC_MASK 0x10 286 #define SCSI_MODE_SELECT6_EER_MASK 0x08 287 #define SCSI_MODE_SELECT6_PER_MASK 0x04 288 #define SCSI_MODE_SELECT6_DTE_MASK 0x02 289 #define SCSI_MODE_SELECT6_DCR_MASK 0x01 290 #define SCSI_MODE_SELECT6_WCE_MASK 0x04 291 #define SCSI_MODE_SELECT6_DRA_MASK 0x20 292 #define SCSI_MODE_SELECT6_PERF_MASK 0x80 293 #define SCSI_MODE_SELECT6_TEST_MASK 0x04 294 #define SCSI_MODE_SELECT6_DEXCPT_MASK 0x08 295 #define SCSI_MODE_SELECT10_PF_MASK 0x10 296 #define SCSI_MODE_SELECT10_LONGLBA_MASK 0x01 297 #define SCSI_MODE_SELECT10_AWRE_MASK 0x80 298 #define SCSI_MODE_SELECT10_RC_MASK 0x10 299 #define SCSI_MODE_SELECT10_EER_MASK 0x08 300 #define SCSI_MODE_SELECT10_PER_MASK 0x04 301 #define SCSI_MODE_SELECT10_DTE_MASK 0x02 302 #define SCSI_MODE_SELECT10_DCR_MASK 0x01 303 #define SCSI_MODE_SELECT10_WCE_MASK 0x04 304 #define SCSI_MODE_SELECT10_DRA_MASK 0x20 305 #define SCSI_MODE_SELECT10_PERF_MASK 0x80 306 #define SCSI_MODE_SELECT10_TEST_MASK 0x04 307 #define SCSI_MODE_SELECT10_DEXCPT_MASK 0x08 308 #define SCSI_WRITE_N_VERIFY10_FUA_MASK 0x08 309 #define SCSI_REQUEST_SENSE_DESC_MASK 0x01 310 #define SCSI_READ_BUFFER_MODE_MASK 0x1F 311 312 #define ATA_REMOVABLE_MEDIA_DEVICE_MASK 0x80 313 #define SCSI_REASSIGN_BLOCKS_LONGLIST_MASK 0x01 314 #define SCSI_REASSIGN_BLOCKS_LONGLBA_MASK 0x02 315 316 317 #define SENSE_DATA_LENGTH 0x12 /* 18 */ 318 #define SELFTEST_RESULTS_LOG_PAGE_LENGTH 404 319 #define INFORMATION_EXCEPTIONS_LOG_PAGE_LENGTH 11 320 #define ZERO_MEDIA_SERIAL_NUMBER_LENGTH 8 321 322 #define LOG_SENSE_0 0 323 #define LOG_SENSE_1 1 324 #define LOG_SENSE_2 2 325 326 #define READ_BUFFER_DATA_MODE 0x02 327 #define READ_BUFFER_DESCRIPTOR_MODE 0x03 328 #define READ_BUFFER_DESCRIPTOR_MODE_DATA_LEN 0x04 329 330 #define WRITE_BUFFER_DATA_MODE 0x02 331 #define WRITE_BUFFER_DL_MICROCODE_SAVE_MODE 0x05 332 333 /* bit mask */ 334 #define BIT0_MASK 0x01 335 #define BIT1_MASK 0x02 336 #define BIT2_MASK 0x04 337 #define BIT3_MASK 0x08 338 #define BIT4_MASK 0x10 339 #define BIT5_MASK 0x20 340 #define BIT6_MASK 0x40 341 #define BIT7_MASK 0x80 342 343 #define MODE_SENSE6_RETURN_ALL_PAGES_LEN 68 344 #define MODE_SENSE6_CONTROL_PAGE_LEN 24 345 #define MODE_SENSE6_READ_WRITE_ERROR_RECOVERY_PAGE_LEN 24 346 #define MODE_SENSE6_CACHING_LEN 32 347 #define MODE_SENSE6_INFORMATION_EXCEPTION_CONTROL_PAGE_LEN 24 348 349 350 #define MODE_SENSE10_RETURN_ALL_PAGES_LEN 68 + 4 351 #define MODE_SENSE10_CONTROL_PAGE_LEN 24 + 4 352 #define MODE_SENSE10_READ_WRITE_ERROR_RECOVERY_PAGE_LEN 24 + 4 353 #define MODE_SENSE10_CACHING_LEN 32 + 4 354 #define MODE_SENSE10_INFORMATION_EXCEPTION_CONTROL_PAGE_LEN 24 + 4 355 356 #define MODE_SENSE10_RETURN_ALL_PAGES_LLBAA_LEN 68 + 4 + 8 357 #define MODE_SENSE10_CONTROL_PAGE_LLBAA_LEN 24 + 4 + 8 358 #define MODE_SENSE10_READ_WRITE_ERROR_RECOVERY_PAGE_LLBAA_LEN 24 + 4 + 8 359 #define MODE_SENSE10_CACHING_LLBAA_LEN 32 + 4 + 8 360 #define MODE_SENSE10_INFORMATION_EXCEPTION_CONTROL_PAGE_LLBAA_LEN 24 + 4 + 8 361 362 /***************************************************************************** 363 ** SCSI SENSE KEY VALUES 364 *****************************************************************************/ 365 366 #define SCSI_SNSKEY_NO_SENSE 0x00 367 #define SCSI_SNSKEY_RECOVERED_ERROR 0x01 368 #define SCSI_SNSKEY_NOT_READY 0x02 369 #define SCSI_SNSKEY_MEDIUM_ERROR 0x03 370 #define SCSI_SNSKEY_HARDWARE_ERROR 0x04 371 #define SCSI_SNSKEY_ILLEGAL_REQUEST 0x05 372 #define SCSI_SNSKEY_UNIT_ATTENTION 0x06 373 #define SCSI_SNSKEY_DATA_PROTECT 0x07 374 #define SCSI_SNSKEY_ABORTED_COMMAND 0x0B 375 #define SCSI_SNSKEY_MISCOMPARE 0x0E 376 377 /***************************************************************************** 378 ** SCSI Additional Sense Codes and Qualifiers combo two-bytes 379 *****************************************************************************/ 380 381 #define SCSI_SNSCODE_NO_ADDITIONAL_INFO 0x0000 382 #define SCSI_SNSCODE_LUN_CRC_ERROR_DETECTED 0x0803 383 #define SCSI_SNSCODE_INVALID_COMMAND 0x2000 384 #define SCSI_SNSCODE_LOGICAL_BLOCK_OUT 0x2100 385 #define SCSI_SNSCODE_INVALID_FIELD_IN_CDB 0x2400 386 #define SCSI_SNSCODE_LOGICAL_NOT_SUPPORTED 0x2500 387 #define SCSI_SNSCODE_POWERON_RESET 0x2900 388 #define SCSI_SNSCODE_EVERLAPPED_CMDS 0x4e00 389 #define SCSI_SNSCODE_INTERNAL_TARGET_FAILURE 0x4400 390 #define SCSI_SNSCODE_MEDIUM_NOT_PRESENT 0x3a00 391 #define SCSI_SNSCODE_UNRECOVERED_READ_ERROR 0x1100 392 #define SCSI_SNSCODE_RECORD_NOT_FOUND 0x1401 393 #define SCSI_SNSCODE_NOT_READY_TO_READY_CHANGE 0x2800 394 #define SCSI_SNSCODE_OPERATOR_MEDIUM_REMOVAL_REQUEST 0x5a01 395 #define SCSI_SNSCODE_INFORMATION_UNIT_CRC_ERROR 0x4703 396 #define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_FORMAT_IN_PROGRESS 0x0404 397 #define SCSI_SNSCODE_HARDWARE_IMPENDING_FAILURE 0x5d10 398 #define SCSI_SNSCODE_LOW_POWER_CONDITION_ON 0x5e00 399 #define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_INIT_REQUIRED 0x0402 400 #define SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST 0x2600 401 #define SCSI_SNSCODE_ATA_DEVICE_FAILED_SET_FEATURES 0x4471 402 #define SCSI_SNSCODE_ATA_DEVICE_FEATURE_NOT_ENABLED 0x670B 403 #define SCSI_SNSCODE_LOGICAL_UNIT_FAILED_SELF_TEST 0x3E03 404 #define SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR 0x2C00 405 #define SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x2100 406 #define SCSI_SNSCODE_LOGICAL_UNIT_FAILURE 0x3E01 407 #define SCSI_SNSCODE_MEDIA_LOAD_OR_EJECT_FAILED 0x5300 408 #define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED 0x0402 409 #define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE 0x0400 410 #define SCSI_SNSCODE_LOGICAL_UNIT_DOES_NOT_RESPOND_TO_SELECTION 0x0500 411 #define SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN 0x4000 412 #define SCSI_SNSCODE_COMMANDS_CLEARED_BY_ANOTHER_INITIATOR 0x2F00 413 #define SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED 0x0C02 414 #define SCSI_SNSCODE_ATA_PASS_THROUGH_INFORMATION_AVAILABLE 0x001D 415 416 /***************************************************************************** 417 ** SCSI Additional Sense Codes and Qualifiers saparate bytes 418 *****************************************************************************/ 419 420 #define SCSI_ASC_NOTREADY_INIT_CMD_REQ 0x04 421 #define SCSI_ASCQ_NOTREADY_INIT_CMD_REQ 0x02 422 423 424 /***************************************************************************** 425 ** Inquiry command fields and response sizes 426 *****************************************************************************/ 427 #define SCSIOP_INQUIRY_CMDDT 0x02 428 #define SCSIOP_INQUIRY_EVPD 0x01 429 #define STANDARD_INQUIRY_SIZE 36 430 #define SATA_PAGE83_INQUIRY_WWN_SIZE 16 /* SAT, revision8, Table81, p78, 12 + 4 */ 431 #define SATA_PAGE83_INQUIRY_NO_WWN_SIZE 76 /* SAT, revision8, Table81, p78, 72 + 4 */ 432 #define SATA_PAGE89_INQUIRY_SIZE 572 /* SAT, revision8, Table87, p84 */ 433 #define SATA_PAGE0_INQUIRY_SIZE 9 /* SPC-4, 7.6.9 Table331, p345 */ 434 #define SATA_PAGE80_INQUIRY_SIZE 24 /* SAT, revision8, Table79, p77 */ 435 #define SATA_PAGEB1_INQUIRY_SIZE 64 /* SBC-3, revision31, Table193, p273 */ 436 437 /***************************************************************************** 438 ** SCSI Operation Codes (first byte in CDB) 439 *****************************************************************************/ 440 441 442 #define SCSIOPC_TEST_UNIT_READY 0x00 443 #define SCSIOPC_INQUIRY 0x12 444 #define SCSIOPC_MODE_SENSE_6 0x1A 445 #define SCSIOPC_MODE_SENSE_10 0x5A 446 #define SCSIOPC_MODE_SELECT_6 0x15 447 #define SCSIOPC_START_STOP_UNIT 0x1B 448 #define SCSIOPC_READ_CAPACITY_10 0x25 449 #define SCSIOPC_READ_CAPACITY_16 0x9E 450 #define SCSIOPC_READ_6 0x08 451 #define SCSIOPC_READ_10 0x28 452 #define SCSIOPC_READ_12 0xA8 453 #define SCSIOPC_READ_16 0x88 454 #define SCSIOPC_WRITE_6 0x0A 455 #define SCSIOPC_WRITE_10 0x2A 456 #define SCSIOPC_WRITE_12 0xAA 457 #define SCSIOPC_WRITE_16 0x8A 458 #define SCSIOPC_WRITE_VERIFY 0x2E 459 #define SCSIOPC_VERIFY_10 0x2F 460 #define SCSIOPC_VERIFY_12 0xAF 461 #define SCSIOPC_VERIFY_16 0x8F 462 #define SCSIOPC_REQUEST_SENSE 0x03 463 #define SCSIOPC_REPORT_LUN 0xA0 464 #define SCSIOPC_FORMAT_UNIT 0x04 465 #define SCSIOPC_SEND_DIAGNOSTIC 0x1D 466 #define SCSIOPC_WRITE_SAME_10 0x41 467 #define SCSIOPC_WRITE_SAME_16 0x93 468 #define SCSIOPC_READ_BUFFER 0x3C 469 #define SCSIOPC_WRITE_BUFFER 0x3B 470 471 #define SCSIOPC_LOG_SENSE 0x4D 472 #define SCSIOPC_LOG_SELECT 0x4C 473 #define SCSIOPC_MODE_SELECT_6 0x15 474 #define SCSIOPC_MODE_SELECT_10 0x55 475 #define SCSIOPC_SYNCHRONIZE_CACHE_10 0x35 476 #define SCSIOPC_SYNCHRONIZE_CACHE_16 0x91 477 #define SCSIOPC_WRITE_AND_VERIFY_10 0x2E 478 #define SCSIOPC_WRITE_AND_VERIFY_12 0xAE 479 #define SCSIOPC_WRITE_AND_VERIFY_16 0x8E 480 #define SCSIOPC_READ_MEDIA_SERIAL_NUMBER 0xAB 481 #define SCSIOPC_REASSIGN_BLOCKS 0x07 482 483 #define SCSIOPC_GET_CONFIG 0x46 484 #define SCSIOPC_GET_EVENT_STATUS_NOTIFICATION 0x4a 485 #define SCSIOPC_REPORT_KEY 0xA4 486 #define SCSIOPC_SEND_KEY 0xA3 487 #define SCSIOPC_READ_DVD_STRUCTURE 0xAD 488 #define SCSIOPC_TOC 0x43 489 #define SCSIOPC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E 490 #define SCSIOPC_READ_VERIFY 0x42 491 #define SCSIOPC_ATA_PASS_THROUGH12 0xA1 492 #define SCSIOPC_ATA_PASS_THROUGH16 0x85 493 494 495 /*! \def MIN(a,b) 496 * \brief MIN macro 497 * 498 * use to find MIN of two values 499 */ 500 #ifndef MIN 501 #define MIN(a,b) ((a) < (b) ? (a) : (b)) 502 #endif 503 504 /*! \def MAX(a,b) 505 * \brief MAX macro 506 * 507 * use to find MAX of two values 508 */ 509 #ifndef MAX 510 #define MAX(a,b) ((a) < (b) ? (b) : (a)) 511 #endif 512 513 /* for debugging print */ 514 #if defined(SM_DEBUG) 515 516 /* 517 * for debugging purposes. 518 */ 519 extern bit32 gSMDebugLevel; 520 521 #define SM_DBG0(format) tdsmLogDebugString(gSMDebugLevel, 0, format) 522 #define SM_DBG1(format) tdsmLogDebugString(gSMDebugLevel, 1, format) 523 #define SM_DBG2(format) tdsmLogDebugString(gSMDebugLevel, 2, format) 524 #define SM_DBG3(format) tdsmLogDebugString(gSMDebugLevel, 3, format) 525 #define SM_DBG4(format) tdsmLogDebugString(gSMDebugLevel, 4, format) 526 #define SM_DBG5(format) tdsmLogDebugString(gSMDebugLevel, 5, format) 527 #define SM_DBG6(format) tdsmLogDebugString(gSMDebugLevel, 6, format) 528 529 #else 530 531 #define SM_DBG0(format) 532 #define SM_DBG1(format) 533 #define SM_DBG2(format) 534 #define SM_DBG3(format) 535 #define SM_DBG4(format) 536 #define SM_DBG5(format) 537 #define SM_DBG6(format) 538 539 #endif /* SM_DEBUG */ 540 541 //#define SM_ASSERT OS_ASSERT 542 //#define tdsmLogDebugString TIDEBUG_MSG 543 544 /* 545 * SAT specific structure per SATA drive 546 */ 547 #define SAT_NONNCQ_MAX 1 548 #define SAT_NCQ_MAX 32 549 #define SAT_MAX_INT_IO 16 550 #define SAT_APAPI_CMDQ_MAX 2 551 552 /* Device state */ 553 #define SAT_DEV_STATE_NORMAL 0 /* Normal */ 554 #define SAT_DEV_STATE_IN_RECOVERY 1 /* SAT in recovery mode */ 555 #define SAT_DEV_STATE_FORMAT_IN_PROGRESS 2 /* Format unit in progress */ 556 #define SAT_DEV_STATE_SMART_THRESHOLD 3 /* SMART Threshold Exceeded Condition*/ 557 #define SAT_DEV_STATE_LOW_POWER 4 /* Low Power State*/ 558 559 #ifndef agNULL 560 #define agNULL ((void *)0) 561 #endif 562 563 #define SM_SET_ESGL_EXTEND(val) \ 564 ((val) = (val) | 0x80000000) 565 566 #define SM_CLEAR_ESGL_EXTEND(val) \ 567 ((val) = (val) & 0x7FFFFFFF) 568 569 #ifndef OPEN_RETRY_RETRIES 570 #define OPEN_RETRY_RETRIES 10 571 #endif 572 573 /********************************************************************* 574 * CPU buffer access macro * 575 * * 576 */ 577 578 #define OSSA_OFFSET_OF(STRUCT_TYPE, FEILD) \ 579 (bitptr)&(((STRUCT_TYPE *)0)->FEILD) 580 581 582 #if defined(SA_CPU_LITTLE_ENDIAN) 583 584 #define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 585 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16); 586 587 #define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 588 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32); 589 590 #define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 591 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) 592 593 #define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 594 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) 595 596 #define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 597 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \ 598 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)(((bit16)VALUE16)&0xFF); 599 600 #define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 601 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \ 602 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \ 603 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \ 604 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)(((bit32)VALUE32)&0xFF); 605 606 #define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 607 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 608 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); 609 610 #define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 611 (*(bit8 *)(((bit8 *)ADDR32)+3)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 612 (*(bit8 *)(((bit8 *)ADDR32)+2)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \ 613 (*(bit8 *)(((bit8 *)ADDR32)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \ 614 (*(bit8 *)(((bit8 *)ADDR32))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))); 615 616 #define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \ 617 si_memcpy(DEST_ADDR, SRC_ADDR, LEN); 618 619 620 #elif defined(SA_CPU_BIG_ENDIAN) 621 622 #define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 623 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \ 624 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit16)VALUE16)&0xFF); 625 626 #define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 627 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \ 628 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \ 629 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \ 630 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit32)VALUE32)&0xFF); 631 632 #define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 633 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 634 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); 635 636 #define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 637 (*((bit8 *)(((bit8 *)ADDR32)+3))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 638 (*((bit8 *)(((bit8 *)ADDR32)+2))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \ 639 (*((bit8 *)(((bit8 *)ADDR32)+1))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \ 640 (*((bit8 *)(((bit8 *)ADDR32)))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))); 641 642 #define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 643 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16); 644 645 #define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 646 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32); 647 648 #define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 649 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); 650 651 #define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 652 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); 653 654 #define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \ 655 si_memcpy(DEST_ADDR, SRC_ADDR, LEN); 656 657 #else 658 659 #error (Host CPU endianess undefined!!) 660 661 #endif 662 663 664 #if defined(SA_CPU_LITTLE_ENDIAN) 665 666 #ifndef LEBIT16_TO_BIT16 667 #define LEBIT16_TO_BIT16(_x) (_x) 668 #endif 669 670 #ifndef BIT16_TO_LEBIT16 671 #define BIT16_TO_LEBIT16(_x) (_x) 672 #endif 673 674 #ifndef BIT16_TO_BEBIT16 675 #define BIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 676 #endif 677 678 #ifndef BEBIT16_TO_BIT16 679 #define BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) 680 #endif 681 682 #ifndef LEBIT32_TO_BIT32 683 #define LEBIT32_TO_BIT32(_x) (_x) 684 #endif 685 686 #ifndef BIT32_TO_LEBIT32 687 #define BIT32_TO_LEBIT32(_x) (_x) 688 #endif 689 690 691 #ifndef BEBIT32_TO_BIT32 692 #define BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) 693 #endif 694 695 #ifndef BIT32_TO_BEBIT32 696 #define BIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 697 #endif 698 699 #elif defined(SA_CPU_BIG_ENDIAN) 700 701 #ifndef LEBIT16_TO_BIT16 702 #define LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) 703 #endif 704 705 #ifndef BIT16_TO_LEBIT16 706 #define BIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 707 #endif 708 709 #ifndef BIT16_TO_BEBIT16 710 #define BIT16_TO_BEBIT16(_x) (_x) 711 #endif 712 713 #ifndef BEBIT16_TO_BIT16 714 #define BEBIT16_TO_BIT16(_x) (_x) 715 #endif 716 717 #ifndef LEBIT32_TO_BIT32 718 #define LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) 719 #endif 720 721 #ifndef BIT32_TO_LEBIT32 722 #define BIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 723 #endif 724 725 #ifndef BEBIT32_TO_BIT32 726 #define BEBIT32_TO_BIT32(_x) (_x) 727 #endif 728 729 #ifndef BIT32_TO_BEBIT32 730 #define BIT32_TO_BEBIT32(_x) (_x) 731 #endif 732 733 #else 734 735 #error No definition of SA_CPU_BIG_ENDIAN or SA_CPU_LITTLE_ENDIAN 736 737 #endif 738 739 740 /* 741 * Task Management task used in tiINITaskManagement() 742 * 743 * 1 SM_ABORT TASK - aborts the task identified by the Referenced Task Tag field. 744 * 2 SM_ABORT TASK SET - aborts all Tasks issued by this initiator on the Logical Unit 745 * 3 SM_CLEAR ACA - clears the Auto Contingent Allegiance condition. 746 * 4 SM_CLEAR TASK SET - Aborts all Tasks (from all initiators) for the Logical Unit. 747 * 5 SM_LOGICAL UNIT RESET 748 * 6 SM_TARGET WARM RESET - iSCSI only 749 * 7 SM_TARGET_COLD_RESET - iSCSI only 750 * 8 SM_TASK_REASSIGN - iSCSI only 751 * 9 SM_QUERY_TASK - SAS only 752 */ 753 754 #define SM_ABORT_TASK 1 755 #define SM_ABORT_TASK_SET 2 756 #define SM_CLEAR_ACA 3 757 #define SM_CLEAR_TASK_SET 4 758 #define SM_LOGICAL_UNIT_RESET 5 759 #define SM_TARGET_WARM_RESET 6 /* iSCSI only */ 760 #define SM_TARGET_COLD_RESET 7 /* iSCSI only */ 761 #define SM_TASK_REASSIGN 8 /* iSCSI only */ 762 #define SM_QUERY_TASK 9 /* SAS only */ 763 764 /* SMP PHY CONTROL OPERATION */ 765 #define SMP_PHY_CONTROL_NOP 0x00 766 #define SMP_PHY_CONTROL_LINK_RESET 0x01 767 #define SMP_PHY_CONTROL_HARD_RESET 0x02 768 #define SMP_PHY_CONTROL_DISABLE 0x03 769 #define SMP_PHY_CONTROL_CLEAR_ERROR_LOG 0x05 770 #define SMP_PHY_CONTROL_CLEAR_AFFILIATION 0x06 771 #define SMP_PHY_CONTROL_XMIT_SATA_PS_SIGNAL 0x07 772 773 /**************************************************************** 774 * Phy Control request 775 ****************************************************************/ 776 typedef struct smpReqPhyControl_s 777 { 778 bit8 reserved1[4]; 779 bit8 reserved2; 780 bit8 phyIdentifier; 781 bit8 phyOperation; 782 bit8 updatePartialPathwayTOValue; 783 /* b7-1 : reserved */ 784 /* b0 : update partial pathway timeout value */ 785 bit8 reserved3[20]; 786 bit8 programmedMinPhysicalLinkRate; 787 /* b7-4 : programmed Minimum Physical Link Rate*/ 788 /* b3-0 : reserved */ 789 bit8 programmedMaxPhysicalLinkRate; 790 /* b7-4 : programmed Maximum Physical Link Rate*/ 791 /* b3-0 : reserved */ 792 bit8 reserved4[2]; 793 bit8 partialPathwayTOValue; 794 /* b7-4 : reserved */ 795 /* b3-0 : partial Pathway TO Value */ 796 bit8 reserved5[3]; 797 } smpReqPhyControl_t; 798 799 800 typedef struct smSMPFrameHeader_s 801 { 802 bit8 smpFrameType; /* The first byte of SMP frame represents the SMP FRAME TYPE */ 803 bit8 smpFunction; /* The second byte of the SMP frame represents the SMP FUNCTION */ 804 bit8 smpFunctionResult; /* The third byte of SMP frame represents FUNCTION RESULT of the SMP response. */ 805 bit8 smpReserved; /* reserved */ 806 } smSMPFrameHeader_t; 807 808 /* SMP direct payload size limit: IOMB direct payload size = 48 */ 809 #define SMP_DIRECT_PAYLOAD_LIMIT 44 810 811 #define SMP_REQUEST 0x40 812 #define SMP_RESPONSE 0x41 813 814 #define SMP_PHY_CONTROL 0x91 815 816 /* SMP function results */ 817 #define SMP_FUNCTION_ACCEPTED 0x00 818 819 /* bit8 array[4] -> bit32 */ 820 #define SM_GET_SAS_ADDRESSLO(sasAddressLo) \ 821 DMA_BEBIT32_TO_BIT32(*(bit32 *)sasAddressLo) 822 823 #define SM_GET_SAS_ADDRESSHI(sasAddressHi) \ 824 DMA_BEBIT32_TO_BIT32(*(bit32 *)sasAddressHi) 825 826 /* SATA sector size 512 bytes = 0x200 bytes */ 827 #define SATA_SECTOR_SIZE 0x200 828 /* TL limit in sector */ 829 /* for SAT_READ/WRITE_DMA and SAT_READ/WRITE_SECTORS ATA command */ 830 #define NON_BIT48_ADDRESS_TL_LIMIT 0x100 831 /* for SAT_READ/WRITE_DMA_EXT and SAT_READ/WRITE_SECTORS_EXT and SAT_READ/WRITE_FPDMA_QUEUEDATA command */ 832 #define BIT48_ADDRESS_TL_LIMIT 0xFFFF 833 834 #define VEN_DEV_SPC 0x800111f8 835 #define VEN_DEV_SPCv 0x800811f8 836 #define VEN_DEV_SPCve 0x800911f8 837 #define VEN_DEV_SPCvplus 0x801811f8 838 #define VEN_DEV_SPCveplus 0x801911f8 839 840 #define SMIsSPC(agr) (VEN_DEV_SPC == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPC */ 841 #define SMIsSPCv(agr) (VEN_DEV_SPCv == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCv */ 842 #define SMIsSPCve(agr) (VEN_DEV_SPCve == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCve */ 843 #define SMIsSPCvplus(agr) (VEN_DEV_SPCvplus == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCv+ */ 844 #define SMIsSPCveplus(agr) (VEN_DEV_SPCveplus == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCve+ */ 845 846 #define DEFAULT_KEY_BUFFER_SIZE 64 847 848 849 #endif /* __SMDEFS_H__ */ 850 851