1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Copyright (C) 2019 IBM Corp. */
3 #include <linux/bitops.h>
4 #include <linux/init.h>
5 #include <linux/io.h>
6 #include <linux/kernel.h>
7 #include <linux/mfd/syscon.h>
8 #include <linux/mutex.h>
9 #include <linux/of.h>
10 #include <linux/platform_device.h>
11 #include <linux/pinctrl/pinctrl.h>
12 #include <linux/pinctrl/pinmux.h>
13 #include <linux/string.h>
14 #include <linux/types.h>
15
16 #include "../core.h"
17 #include "../pinctrl-utils.h"
18 #include "pinctrl-aspeed.h"
19
20 #define SCU400 0x400 /* Multi-function Pin Control #1 */
21 #define SCU404 0x404 /* Multi-function Pin Control #2 */
22 #define SCU40C 0x40C /* Multi-function Pin Control #3 */
23 #define SCU410 0x410 /* Multi-function Pin Control #4 */
24 #define SCU414 0x414 /* Multi-function Pin Control #5 */
25 #define SCU418 0x418 /* Multi-function Pin Control #6 */
26 #define SCU41C 0x41C /* Multi-function Pin Control #7 */
27 #define SCU430 0x430 /* Multi-function Pin Control #8 */
28 #define SCU434 0x434 /* Multi-function Pin Control #9 */
29 #define SCU438 0x438 /* Multi-function Pin Control #10 */
30 #define SCU440 0x440 /* USB Multi-function Pin Control #12 */
31 #define SCU450 0x450 /* Multi-function Pin Control #14 */
32 #define SCU454 0x454 /* Multi-function Pin Control #15 */
33 #define SCU458 0x458 /* Multi-function Pin Control #16 */
34 #define SCU4B0 0x4B0 /* Multi-function Pin Control #17 */
35 #define SCU4B4 0x4B4 /* Multi-function Pin Control #18 */
36 #define SCU4B8 0x4B8 /* Multi-function Pin Control #19 */
37 #define SCU4BC 0x4BC /* Multi-function Pin Control #20 */
38 #define SCU4D4 0x4D4 /* Multi-function Pin Control #22 */
39 #define SCU4D8 0x4D8 /* Multi-function Pin Control #23 */
40 #define SCU500 0x500 /* Hardware Strap 1 */
41 #define SCU510 0x510 /* Hardware Strap 2 */
42 #define SCU610 0x610 /* Disable GPIO Internal Pull-Down #0 */
43 #define SCU614 0x614 /* Disable GPIO Internal Pull-Down #1 */
44 #define SCU618 0x618 /* Disable GPIO Internal Pull-Down #2 */
45 #define SCU61C 0x61c /* Disable GPIO Internal Pull-Down #3 */
46 #define SCU630 0x630 /* Disable GPIO Internal Pull-Down #4 */
47 #define SCU634 0x634 /* Disable GPIO Internal Pull-Down #5 */
48 #define SCU638 0x638 /* Disable GPIO Internal Pull-Down #6 */
49 #define SCU690 0x690 /* Multi-function Pin Control #24 */
50 #define SCU694 0x694 /* Multi-function Pin Control #25 */
51 #define SCU69C 0x69C /* Multi-function Pin Control #27 */
52 #define SCU6D0 0x6D0 /* Multi-function Pin Control #29 */
53 #define SCUC20 0xC20 /* PCIE configuration Setting Control */
54
55 #define ASPEED_G6_NR_PINS 256
56
57 #define M24 0
58 SIG_EXPR_LIST_DECL_SESG(M24, MDC3, MDIO3, SIG_DESC_SET(SCU410, 0));
59 SIG_EXPR_LIST_DECL_SESG(M24, SCL11, I2C11, SIG_DESC_SET(SCU4B0, 0));
60 PIN_DECL_2(M24, GPIOA0, MDC3, SCL11);
61
62 #define M25 1
63 SIG_EXPR_LIST_DECL_SESG(M25, MDIO3, MDIO3, SIG_DESC_SET(SCU410, 1));
64 SIG_EXPR_LIST_DECL_SESG(M25, SDA11, I2C11, SIG_DESC_SET(SCU4B0, 1));
65 PIN_DECL_2(M25, GPIOA1, MDIO3, SDA11);
66
67 FUNC_GROUP_DECL(MDIO3, M24, M25);
68 FUNC_GROUP_DECL(I2C11, M24, M25);
69
70 #define L26 2
71 SIG_EXPR_LIST_DECL_SESG(L26, MDC4, MDIO4, SIG_DESC_SET(SCU410, 2));
72 SIG_EXPR_LIST_DECL_SESG(L26, SCL12, I2C12, SIG_DESC_SET(SCU4B0, 2));
73 PIN_DECL_2(L26, GPIOA2, MDC4, SCL12);
74
75 #define K24 3
76 SIG_EXPR_LIST_DECL_SESG(K24, MDIO4, MDIO4, SIG_DESC_SET(SCU410, 3));
77 SIG_EXPR_LIST_DECL_SESG(K24, SDA12, I2C12, SIG_DESC_SET(SCU4B0, 3));
78 PIN_DECL_2(K24, GPIOA3, MDIO4, SDA12);
79
80 FUNC_GROUP_DECL(MDIO4, L26, K24);
81 FUNC_GROUP_DECL(I2C12, L26, K24);
82
83 #define K26 4
84 SIG_EXPR_LIST_DECL_SESG(K26, MACLINK1, MACLINK1, SIG_DESC_SET(SCU410, 4));
85 SIG_EXPR_LIST_DECL_SESG(K26, SCL13, I2C13, SIG_DESC_SET(SCU4B0, 4));
86 SIG_EXPR_LIST_DECL_SESG(K26, SGPS2CK, SGPS2, SIG_DESC_SET(SCU690, 4));
87 SIG_EXPR_LIST_DECL_SESG(K26, SGPM2CLK, SGPM2, SIG_DESC_SET(SCU6D0, 4));
88 PIN_DECL_4(K26, GPIOA4, MACLINK1, SCL13, SGPS2CK, SGPM2CLK);
89 FUNC_GROUP_DECL(MACLINK1, K26);
90
91 #define L24 5
92 SIG_EXPR_LIST_DECL_SESG(L24, MACLINK2, MACLINK2, SIG_DESC_SET(SCU410, 5));
93 SIG_EXPR_LIST_DECL_SESG(L24, SDA13, I2C13, SIG_DESC_SET(SCU4B0, 5));
94 SIG_EXPR_LIST_DECL_SESG(L24, SGPS2LD, SGPS2, SIG_DESC_SET(SCU690, 5));
95 SIG_EXPR_LIST_DECL_SESG(L24, SGPM2LD, SGPM2, SIG_DESC_SET(SCU6D0, 5));
96 PIN_DECL_4(L24, GPIOA5, MACLINK2, SDA13, SGPS2LD, SGPM2LD);
97 FUNC_GROUP_DECL(MACLINK2, L24);
98
99 FUNC_GROUP_DECL(I2C13, K26, L24);
100
101 #define L23 6
102 SIG_EXPR_LIST_DECL_SESG(L23, MACLINK3, MACLINK3, SIG_DESC_SET(SCU410, 6));
103 SIG_EXPR_LIST_DECL_SESG(L23, SCL14, I2C14, SIG_DESC_SET(SCU4B0, 6));
104 SIG_EXPR_LIST_DECL_SESG(L23, SGPS2O, SGPS2, SIG_DESC_SET(SCU690, 6));
105 SIG_EXPR_LIST_DECL_SESG(L23, SGPM2O, SGPM2, SIG_DESC_SET(SCU6D0, 6));
106 PIN_DECL_4(L23, GPIOA6, MACLINK3, SCL14, SGPS2O, SGPM2O);
107 FUNC_GROUP_DECL(MACLINK3, L23);
108
109 #define K25 7
110 SIG_EXPR_LIST_DECL_SESG(K25, MACLINK4, MACLINK4, SIG_DESC_SET(SCU410, 7));
111 SIG_EXPR_LIST_DECL_SESG(K25, SDA14, I2C14, SIG_DESC_SET(SCU4B0, 7));
112 SIG_EXPR_LIST_DECL_SESG(K25, SGPS2I, SGPS2, SIG_DESC_SET(SCU690, 7));
113 SIG_EXPR_LIST_DECL_SESG(K25, SGPM2I, SGPM2, SIG_DESC_SET(SCU6D0, 7));
114 PIN_DECL_4(K25, GPIOA7, MACLINK4, SDA14, SGPS2I, SGPM2I);
115 FUNC_GROUP_DECL(MACLINK4, K25);
116
117 FUNC_GROUP_DECL(I2C14, L23, K25);
118 FUNC_GROUP_DECL(SGPM2, K26, L24, L23, K25);
119 FUNC_GROUP_DECL(SGPS2, K26, L24, L23, K25);
120
121 #define J26 8
122 SIG_EXPR_LIST_DECL_SESG(J26, SALT1, SALT1, SIG_DESC_SET(SCU410, 8));
123 SIG_EXPR_LIST_DECL_SESG(J26, LHAD0, LPCHC, SIG_DESC_SET(SCU4B0, 8));
124 PIN_DECL_2(J26, GPIOB0, SALT1, LHAD0);
125 FUNC_GROUP_DECL(SALT1, J26);
126
127 #define K23 9
128 SIG_EXPR_LIST_DECL_SESG(K23, SALT2, SALT2, SIG_DESC_SET(SCU410, 9));
129 SIG_EXPR_LIST_DECL_SESG(K23, LHAD1, LPCHC, SIG_DESC_SET(SCU4B0, 9));
130 PIN_DECL_2(K23, GPIOB1, SALT2, LHAD1);
131 FUNC_GROUP_DECL(SALT2, K23);
132
133 #define H26 10
134 SIG_EXPR_LIST_DECL_SESG(H26, SALT3, SALT3, SIG_DESC_SET(SCU410, 10));
135 SIG_EXPR_LIST_DECL_SESG(H26, LHAD2, LPCHC, SIG_DESC_SET(SCU4B0, 10));
136 PIN_DECL_2(H26, GPIOB2, SALT3, LHAD2);
137 FUNC_GROUP_DECL(SALT3, H26);
138
139 #define J25 11
140 SIG_EXPR_LIST_DECL_SESG(J25, SALT4, SALT4, SIG_DESC_SET(SCU410, 11));
141 SIG_EXPR_LIST_DECL_SESG(J25, LHAD3, LPCHC, SIG_DESC_SET(SCU4B0, 11));
142 PIN_DECL_2(J25, GPIOB3, SALT4, LHAD3);
143 FUNC_GROUP_DECL(SALT4, J25);
144
145 #define J23 12
146 SIG_EXPR_LIST_DECL_SESG(J23, MDC2, MDIO2, SIG_DESC_SET(SCU410, 12));
147 SIG_EXPR_LIST_DECL_SESG(J23, LHCLK, LPCHC, SIG_DESC_SET(SCU4B0, 12));
148 PIN_DECL_2(J23, GPIOB4, MDC2, LHCLK);
149
150 #define G26 13
151 SIG_EXPR_LIST_DECL_SESG(G26, MDIO2, MDIO2, SIG_DESC_SET(SCU410, 13));
152 SIG_EXPR_LIST_DECL_SESG(G26, LHFRAME, LPCHC, SIG_DESC_SET(SCU4B0, 13));
153 PIN_DECL_2(G26, GPIOB5, MDIO2, LHFRAME);
154
155 FUNC_GROUP_DECL(MDIO2, J23, G26);
156
157 #define H25 14
158 SIG_EXPR_LIST_DECL_SESG(H25, TXD4, TXD4, SIG_DESC_SET(SCU410, 14));
159 SIG_EXPR_LIST_DECL_SESG(H25, LHSIRQ, LHSIRQ, SIG_DESC_SET(SCU4B0, 14));
160 PIN_DECL_2(H25, GPIOB6, TXD4, LHSIRQ);
161 FUNC_GROUP_DECL(TXD4, H25);
162 FUNC_GROUP_DECL(LHSIRQ, H25);
163
164 #define J24 15
165 SIG_EXPR_LIST_DECL_SESG(J24, RXD4, RXD4, SIG_DESC_SET(SCU410, 15));
166 SIG_EXPR_LIST_DECL_SESG(J24, LHRST, LPCHC, SIG_DESC_SET(SCU4B0, 15));
167 PIN_DECL_2(J24, GPIOB7, RXD4, LHRST);
168 FUNC_GROUP_DECL(RXD4, J24);
169
170 FUNC_GROUP_DECL(LPCHC, J26, K23, H26, J25, J23, G26, H25, J24);
171
172 #define H24 16
173 SIG_EXPR_LIST_DECL_SESG(H24, RGMII3TXCK, RGMII3, SIG_DESC_SET(SCU410, 16),
174 SIG_DESC_SET(SCU510, 0));
175 SIG_EXPR_LIST_DECL_SESG(H24, RMII3RCLKO, RMII3, SIG_DESC_SET(SCU410, 16),
176 SIG_DESC_CLEAR(SCU510, 0));
177 PIN_DECL_2(H24, GPIOC0, RGMII3TXCK, RMII3RCLKO);
178
179 #define J22 17
180 SIG_EXPR_LIST_DECL_SESG(J22, RGMII3TXCTL, RGMII3, SIG_DESC_SET(SCU410, 17),
181 SIG_DESC_SET(SCU510, 0));
182 SIG_EXPR_LIST_DECL_SESG(J22, RMII3TXEN, RMII3, SIG_DESC_SET(SCU410, 17),
183 SIG_DESC_CLEAR(SCU510, 0));
184 PIN_DECL_2(J22, GPIOC1, RGMII3TXCTL, RMII3TXEN);
185
186 #define H22 18
187 SIG_EXPR_LIST_DECL_SESG(H22, RGMII3TXD0, RGMII3, SIG_DESC_SET(SCU410, 18),
188 SIG_DESC_SET(SCU510, 0));
189 SIG_EXPR_LIST_DECL_SESG(H22, RMII3TXD0, RMII3, SIG_DESC_SET(SCU410, 18),
190 SIG_DESC_CLEAR(SCU510, 0));
191 PIN_DECL_2(H22, GPIOC2, RGMII3TXD0, RMII3TXD0);
192
193 #define H23 19
194 SIG_EXPR_LIST_DECL_SESG(H23, RGMII3TXD1, RGMII3, SIG_DESC_SET(SCU410, 19),
195 SIG_DESC_SET(SCU510, 0));
196 SIG_EXPR_LIST_DECL_SESG(H23, RMII3TXD1, RMII3, SIG_DESC_SET(SCU410, 19),
197 SIG_DESC_CLEAR(SCU510, 0));
198 PIN_DECL_2(H23, GPIOC3, RGMII3TXD1, RMII3TXD1);
199
200 #define G22 20
201 SIG_EXPR_LIST_DECL_SESG(G22, RGMII3TXD2, RGMII3, SIG_DESC_SET(SCU410, 20),
202 SIG_DESC_SET(SCU510, 0));
203 PIN_DECL_1(G22, GPIOC4, RGMII3TXD2);
204
205 #define F22 21
206 SIG_EXPR_LIST_DECL_SESG(F22, RGMII3TXD3, RGMII3, SIG_DESC_SET(SCU410, 21),
207 SIG_DESC_SET(SCU510, 0));
208 PIN_DECL_1(F22, GPIOC5, RGMII3TXD3);
209
210 #define G23 22
211 SIG_EXPR_LIST_DECL_SESG(G23, RGMII3RXCK, RGMII3, SIG_DESC_SET(SCU410, 22),
212 SIG_DESC_SET(SCU510, 0));
213 SIG_EXPR_LIST_DECL_SESG(G23, RMII3RCLKI, RMII3, SIG_DESC_SET(SCU410, 22),
214 SIG_DESC_CLEAR(SCU510, 0));
215 PIN_DECL_2(G23, GPIOC6, RGMII3RXCK, RMII3RCLKI);
216
217 #define G24 23
218 SIG_EXPR_LIST_DECL_SESG(G24, RGMII3RXCTL, RGMII3, SIG_DESC_SET(SCU410, 23),
219 SIG_DESC_SET(SCU510, 0));
220 PIN_DECL_1(G24, GPIOC7, RGMII3RXCTL);
221
222 #define F23 24
223 SIG_EXPR_LIST_DECL_SESG(F23, RGMII3RXD0, RGMII3, SIG_DESC_SET(SCU410, 24),
224 SIG_DESC_SET(SCU510, 0));
225 SIG_EXPR_LIST_DECL_SESG(F23, RMII3RXD0, RMII3, SIG_DESC_SET(SCU410, 24),
226 SIG_DESC_CLEAR(SCU510, 0));
227 PIN_DECL_2(F23, GPIOD0, RGMII3RXD0, RMII3RXD0);
228
229 #define F26 25
230 SIG_EXPR_LIST_DECL_SESG(F26, RGMII3RXD1, RGMII3, SIG_DESC_SET(SCU410, 25),
231 SIG_DESC_SET(SCU510, 0));
232 SIG_EXPR_LIST_DECL_SESG(F26, RMII3RXD1, RMII3, SIG_DESC_SET(SCU410, 25),
233 SIG_DESC_CLEAR(SCU510, 0));
234 PIN_DECL_2(F26, GPIOD1, RGMII3RXD1, RMII3RXD1);
235
236 #define F25 26
237 SIG_EXPR_LIST_DECL_SESG(F25, RGMII3RXD2, RGMII3, SIG_DESC_SET(SCU410, 26),
238 SIG_DESC_SET(SCU510, 0));
239 SIG_EXPR_LIST_DECL_SESG(F25, RMII3CRSDV, RMII3, SIG_DESC_SET(SCU410, 26),
240 SIG_DESC_CLEAR(SCU510, 0));
241 PIN_DECL_2(F25, GPIOD2, RGMII3RXD2, RMII3CRSDV);
242
243 #define E26 27
244 SIG_EXPR_LIST_DECL_SESG(E26, RGMII3RXD3, RGMII3, SIG_DESC_SET(SCU410, 27),
245 SIG_DESC_SET(SCU510, 0));
246 SIG_EXPR_LIST_DECL_SESG(E26, RMII3RXER, RMII3, SIG_DESC_SET(SCU410, 27),
247 SIG_DESC_CLEAR(SCU510, 0));
248 PIN_DECL_2(E26, GPIOD3, RGMII3RXD3, RMII3RXER);
249
250 FUNC_GROUP_DECL(RGMII3, H24, J22, H22, H23, G22, F22, G23, G24, F23, F26, F25,
251 E26);
252 GROUP_DECL(RMII3, H24, J22, H22, H23, G23, F23, F26, F25, E26);
253 GROUP_DECL(NCSI3, J22, H22, H23, G23, F23, F26, F25, E26);
254 FUNC_DECL_2(RMII3, RMII3, NCSI3);
255
256 #define F24 28
257 SIG_EXPR_LIST_DECL_SESG(F24, NCTS3, NCTS3, SIG_DESC_SET(SCU410, 28));
258 SIG_EXPR_LIST_DECL_SESG(F24, RGMII4TXCK, RGMII4, SIG_DESC_SET(SCU4B0, 28),
259 SIG_DESC_SET(SCU510, 1));
260 SIG_EXPR_LIST_DECL_SESG(F24, RMII4RCLKO, RMII4, SIG_DESC_SET(SCU4B0, 28),
261 SIG_DESC_CLEAR(SCU510, 1));
262 PIN_DECL_3(F24, GPIOD4, NCTS3, RGMII4TXCK, RMII4RCLKO);
263 FUNC_GROUP_DECL(NCTS3, F24);
264
265 #define E23 29
266 SIG_EXPR_LIST_DECL_SESG(E23, NDCD3, NDCD3, SIG_DESC_SET(SCU410, 29));
267 SIG_EXPR_LIST_DECL_SESG(E23, RGMII4TXCTL, RGMII4, SIG_DESC_SET(SCU4B0, 29),
268 SIG_DESC_SET(SCU510, 1));
269 SIG_EXPR_LIST_DECL_SESG(E23, RMII4TXEN, RMII4, SIG_DESC_SET(SCU4B0, 29),
270 SIG_DESC_CLEAR(SCU510, 1));
271 PIN_DECL_3(E23, GPIOD5, NDCD3, RGMII4TXCTL, RMII4TXEN);
272 FUNC_GROUP_DECL(NDCD3, E23);
273
274 #define E24 30
275 SIG_EXPR_LIST_DECL_SESG(E24, NDSR3, NDSR3, SIG_DESC_SET(SCU410, 30));
276 SIG_EXPR_LIST_DECL_SESG(E24, RGMII4TXD0, RGMII4, SIG_DESC_SET(SCU4B0, 30),
277 SIG_DESC_SET(SCU510, 1));
278 SIG_EXPR_LIST_DECL_SESG(E24, RMII4TXD0, RMII4, SIG_DESC_SET(SCU4B0, 30),
279 SIG_DESC_CLEAR(SCU510, 1));
280 PIN_DECL_3(E24, GPIOD6, NDSR3, RGMII4TXD0, RMII4TXD0);
281 FUNC_GROUP_DECL(NDSR3, E24);
282
283 #define E25 31
284 SIG_EXPR_LIST_DECL_SESG(E25, NRI3, NRI3, SIG_DESC_SET(SCU410, 31));
285 SIG_EXPR_LIST_DECL_SESG(E25, RGMII4TXD1, RGMII4, SIG_DESC_SET(SCU4B0, 31),
286 SIG_DESC_SET(SCU510, 1));
287 SIG_EXPR_LIST_DECL_SESG(E25, RMII4TXD1, RMII4, SIG_DESC_SET(SCU4B0, 31),
288 SIG_DESC_CLEAR(SCU510, 1));
289 PIN_DECL_3(E25, GPIOD7, NRI3, RGMII4TXD1, RMII4TXD1);
290 FUNC_GROUP_DECL(NRI3, E25);
291
292 #define D26 32
293 SIG_EXPR_LIST_DECL_SESG(D26, NDTR3, NDTR3, SIG_DESC_SET(SCU414, 0));
294 SIG_EXPR_LIST_DECL_SESG(D26, RGMII4TXD2, RGMII4, SIG_DESC_SET(SCU4B4, 0),
295 SIG_DESC_SET(SCU510, 1));
296 PIN_DECL_2(D26, GPIOE0, NDTR3, RGMII4TXD2);
297 FUNC_GROUP_DECL(NDTR3, D26);
298
299 #define D24 33
300 SIG_EXPR_LIST_DECL_SESG(D24, NRTS3, NRTS3, SIG_DESC_SET(SCU414, 1));
301 SIG_EXPR_LIST_DECL_SESG(D24, RGMII4TXD3, RGMII4, SIG_DESC_SET(SCU4B4, 1),
302 SIG_DESC_SET(SCU510, 1));
303 PIN_DECL_2(D24, GPIOE1, NRTS3, RGMII4TXD3);
304 FUNC_GROUP_DECL(NRTS3, D24);
305
306 #define C25 34
307 SIG_EXPR_LIST_DECL_SESG(C25, NCTS4, NCTS4, SIG_DESC_SET(SCU414, 2));
308 SIG_EXPR_LIST_DECL_SESG(C25, RGMII4RXCK, RGMII4, SIG_DESC_SET(SCU4B4, 2),
309 SIG_DESC_SET(SCU510, 1));
310 SIG_EXPR_LIST_DECL_SESG(C25, RMII4RCLKI, RMII4, SIG_DESC_SET(SCU4B4, 2),
311 SIG_DESC_CLEAR(SCU510, 1));
312 PIN_DECL_3(C25, GPIOE2, NCTS4, RGMII4RXCK, RMII4RCLKI);
313 FUNC_GROUP_DECL(NCTS4, C25);
314
315 #define C26 35
316 SIG_EXPR_LIST_DECL_SESG(C26, NDCD4, NDCD4, SIG_DESC_SET(SCU414, 3));
317 SIG_EXPR_LIST_DECL_SESG(C26, RGMII4RXCTL, RGMII4, SIG_DESC_SET(SCU4B4, 3),
318 SIG_DESC_SET(SCU510, 1));
319 PIN_DECL_2(C26, GPIOE3, NDCD4, RGMII4RXCTL);
320 FUNC_GROUP_DECL(NDCD4, C26);
321
322 #define C24 36
323 SIG_EXPR_LIST_DECL_SESG(C24, NDSR4, NDSR4, SIG_DESC_SET(SCU414, 4));
324 SIG_EXPR_LIST_DECL_SESG(C24, RGMII4RXD0, RGMII4, SIG_DESC_SET(SCU4B4, 4),
325 SIG_DESC_SET(SCU510, 1));
326 SIG_EXPR_LIST_DECL_SESG(C24, RMII4RXD0, RMII4, SIG_DESC_SET(SCU4B4, 4),
327 SIG_DESC_CLEAR(SCU510, 1));
328 PIN_DECL_3(C24, GPIOE4, NDSR4, RGMII4RXD0, RMII4RXD0);
329 FUNC_GROUP_DECL(NDSR4, C24);
330
331 #define B26 37
332 SIG_EXPR_LIST_DECL_SESG(B26, NRI4, NRI4, SIG_DESC_SET(SCU414, 5));
333 SIG_EXPR_LIST_DECL_SESG(B26, RGMII4RXD1, RGMII4, SIG_DESC_SET(SCU4B4, 5),
334 SIG_DESC_SET(SCU510, 1));
335 SIG_EXPR_LIST_DECL_SESG(B26, RMII4RXD1, RMII4, SIG_DESC_SET(SCU4B4, 5),
336 SIG_DESC_CLEAR(SCU510, 1));
337 PIN_DECL_3(B26, GPIOE5, NRI4, RGMII4RXD1, RMII4RXD1);
338 FUNC_GROUP_DECL(NRI4, B26);
339
340 #define B25 38
341 SIG_EXPR_LIST_DECL_SESG(B25, NDTR4, NDTR4, SIG_DESC_SET(SCU414, 6));
342 SIG_EXPR_LIST_DECL_SESG(B25, RGMII4RXD2, RGMII4, SIG_DESC_SET(SCU4B4, 6),
343 SIG_DESC_SET(SCU510, 1));
344 SIG_EXPR_LIST_DECL_SESG(B25, RMII4CRSDV, RMII4, SIG_DESC_SET(SCU4B4, 6),
345 SIG_DESC_CLEAR(SCU510, 1));
346 PIN_DECL_3(B25, GPIOE6, NDTR4, RGMII4RXD2, RMII4CRSDV);
347 FUNC_GROUP_DECL(NDTR4, B25);
348
349 #define B24 39
350 SIG_EXPR_LIST_DECL_SESG(B24, NRTS4, NRTS4, SIG_DESC_SET(SCU414, 7));
351 SIG_EXPR_LIST_DECL_SESG(B24, RGMII4RXD3, RGMII4, SIG_DESC_SET(SCU4B4, 7),
352 SIG_DESC_SET(SCU510, 1));
353 SIG_EXPR_LIST_DECL_SESG(B24, RMII4RXER, RMII4, SIG_DESC_SET(SCU4B4, 7),
354 SIG_DESC_CLEAR(SCU510, 1));
355 PIN_DECL_3(B24, GPIOE7, NRTS4, RGMII4RXD3, RMII4RXER);
356 FUNC_GROUP_DECL(NRTS4, B24);
357
358 FUNC_GROUP_DECL(RGMII4, F24, E23, E24, E25, D26, D24, C25, C26, C24, B26, B25,
359 B24);
360 GROUP_DECL(RMII4, F24, E23, E24, E25, C25, C24, B26, B25, B24);
361 GROUP_DECL(NCSI4, E23, E24, E25, C25, C24, B26, B25, B24);
362 FUNC_DECL_2(RMII4, RMII4, NCSI4);
363
364 #define D22 40
365 SIG_EXPR_LIST_DECL_SESG(D22, SD1CLK, SD1, SIG_DESC_SET(SCU414, 8));
366 SIG_EXPR_LIST_DECL_SEMG(D22, PWM8, PWM8G0, PWM8, SIG_DESC_SET(SCU4B4, 8));
367 PIN_DECL_2(D22, GPIOF0, SD1CLK, PWM8);
368 GROUP_DECL(PWM8G0, D22);
369
370 #define E22 41
371 SIG_EXPR_LIST_DECL_SESG(E22, SD1CMD, SD1, SIG_DESC_SET(SCU414, 9));
372 SIG_EXPR_LIST_DECL_SEMG(E22, PWM9, PWM9G0, PWM9, SIG_DESC_SET(SCU4B4, 9));
373 PIN_DECL_2(E22, GPIOF1, SD1CMD, PWM9);
374 GROUP_DECL(PWM9G0, E22);
375
376 #define D23 42
377 SIG_EXPR_LIST_DECL_SESG(D23, SD1DAT0, SD1, SIG_DESC_SET(SCU414, 10));
378 SIG_EXPR_LIST_DECL_SEMG(D23, PWM10, PWM10G0, PWM10, SIG_DESC_SET(SCU4B4, 10));
379 PIN_DECL_2(D23, GPIOF2, SD1DAT0, PWM10);
380 GROUP_DECL(PWM10G0, D23);
381
382 #define C23 43
383 SIG_EXPR_LIST_DECL_SESG(C23, SD1DAT1, SD1, SIG_DESC_SET(SCU414, 11));
384 SIG_EXPR_LIST_DECL_SEMG(C23, PWM11, PWM11G0, PWM11, SIG_DESC_SET(SCU4B4, 11));
385 PIN_DECL_2(C23, GPIOF3, SD1DAT1, PWM11);
386 GROUP_DECL(PWM11G0, C23);
387
388 #define C22 44
389 SIG_EXPR_LIST_DECL_SESG(C22, SD1DAT2, SD1, SIG_DESC_SET(SCU414, 12));
390 SIG_EXPR_LIST_DECL_SEMG(C22, PWM12, PWM12G0, PWM12, SIG_DESC_SET(SCU4B4, 12));
391 PIN_DECL_2(C22, GPIOF4, SD1DAT2, PWM12);
392 GROUP_DECL(PWM12G0, C22);
393
394 #define A25 45
395 SIG_EXPR_LIST_DECL_SESG(A25, SD1DAT3, SD1, SIG_DESC_SET(SCU414, 13));
396 SIG_EXPR_LIST_DECL_SEMG(A25, PWM13, PWM13G0, PWM13, SIG_DESC_SET(SCU4B4, 13));
397 PIN_DECL_2(A25, GPIOF5, SD1DAT3, PWM13);
398 GROUP_DECL(PWM13G0, A25);
399
400 #define A24 46
401 SIG_EXPR_LIST_DECL_SESG(A24, SD1CD, SD1, SIG_DESC_SET(SCU414, 14));
402 SIG_EXPR_LIST_DECL_SEMG(A24, PWM14, PWM14G0, PWM14, SIG_DESC_SET(SCU4B4, 14));
403 PIN_DECL_2(A24, GPIOF6, SD1CD, PWM14);
404 GROUP_DECL(PWM14G0, A24);
405
406 #define A23 47
407 SIG_EXPR_LIST_DECL_SESG(A23, SD1WP, SD1, SIG_DESC_SET(SCU414, 15));
408 SIG_EXPR_LIST_DECL_SEMG(A23, PWM15, PWM15G0, PWM15, SIG_DESC_SET(SCU4B4, 15));
409 PIN_DECL_2(A23, GPIOF7, SD1WP, PWM15);
410 GROUP_DECL(PWM15G0, A23);
411
412 FUNC_GROUP_DECL(SD1, D22, E22, D23, C23, C22, A25, A24, A23);
413
414 #define E21 48
415 SIG_EXPR_LIST_DECL_SESG(E21, TXD6, UART6, SIG_DESC_SET(SCU414, 16));
416 SIG_EXPR_LIST_DECL_SESG(E21, SD2CLK, SD2, SIG_DESC_SET(SCU4B4, 16),
417 SIG_DESC_SET(SCU450, 1));
418 SIG_EXPR_LIST_DECL_SEMG(E21, SALT9, SALT9G0, SALT9, SIG_DESC_SET(SCU694, 16));
419 PIN_DECL_3(E21, GPIOG0, TXD6, SD2CLK, SALT9);
420 GROUP_DECL(SALT9G0, E21);
421
422 #define B22 49
423 SIG_EXPR_LIST_DECL_SESG(B22, RXD6, UART6, SIG_DESC_SET(SCU414, 17));
424 SIG_EXPR_LIST_DECL_SESG(B22, SD2CMD, SD2, SIG_DESC_SET(SCU4B4, 17),
425 SIG_DESC_SET(SCU450, 1));
426 SIG_EXPR_LIST_DECL_SEMG(B22, SALT10, SALT10G0, SALT10,
427 SIG_DESC_SET(SCU694, 17));
428 PIN_DECL_3(B22, GPIOG1, RXD6, SD2CMD, SALT10);
429 GROUP_DECL(SALT10G0, B22);
430
431 FUNC_GROUP_DECL(UART6, E21, B22);
432
433 #define C21 50
434 SIG_EXPR_LIST_DECL_SESG(C21, TXD7, UART7, SIG_DESC_SET(SCU414, 18));
435 SIG_EXPR_LIST_DECL_SESG(C21, SD2DAT0, SD2, SIG_DESC_SET(SCU4B4, 18),
436 SIG_DESC_SET(SCU450, 1));
437 SIG_EXPR_LIST_DECL_SEMG(C21, SALT11, SALT11G0, SALT11,
438 SIG_DESC_SET(SCU694, 18));
439 PIN_DECL_3(C21, GPIOG2, TXD7, SD2DAT0, SALT11);
440 GROUP_DECL(SALT11G0, C21);
441
442 #define A22 51
443 SIG_EXPR_LIST_DECL_SESG(A22, RXD7, UART7, SIG_DESC_SET(SCU414, 19));
444 SIG_EXPR_LIST_DECL_SESG(A22, SD2DAT1, SD2, SIG_DESC_SET(SCU4B4, 19),
445 SIG_DESC_SET(SCU450, 1));
446 SIG_EXPR_LIST_DECL_SEMG(A22, SALT12, SALT12G0, SALT12,
447 SIG_DESC_SET(SCU694, 19));
448 PIN_DECL_3(A22, GPIOG3, RXD7, SD2DAT1, SALT12);
449 GROUP_DECL(SALT12G0, A22);
450
451 FUNC_GROUP_DECL(UART7, C21, A22);
452
453 #define A21 52
454 SIG_EXPR_LIST_DECL_SESG(A21, TXD8, UART8, SIG_DESC_SET(SCU414, 20));
455 SIG_EXPR_LIST_DECL_SESG(A21, SD2DAT2, SD2, SIG_DESC_SET(SCU4B4, 20),
456 SIG_DESC_SET(SCU450, 1));
457 SIG_EXPR_LIST_DECL_SEMG(A21, SALT13, SALT13G0, SALT13,
458 SIG_DESC_SET(SCU694, 20));
459 PIN_DECL_3(A21, GPIOG4, TXD8, SD2DAT2, SALT13);
460 GROUP_DECL(SALT13G0, A21);
461
462 #define E20 53
463 SIG_EXPR_LIST_DECL_SESG(E20, RXD8, UART8, SIG_DESC_SET(SCU414, 21));
464 SIG_EXPR_LIST_DECL_SESG(E20, SD2DAT3, SD2, SIG_DESC_SET(SCU4B4, 21),
465 SIG_DESC_SET(SCU450, 1));
466 SIG_EXPR_LIST_DECL_SEMG(E20, SALT14, SALT14G0, SALT14,
467 SIG_DESC_SET(SCU694, 21));
468 PIN_DECL_3(E20, GPIOG5, RXD8, SD2DAT3, SALT14);
469 GROUP_DECL(SALT14G0, E20);
470
471 FUNC_GROUP_DECL(UART8, A21, E20);
472
473 #define D21 54
474 SIG_EXPR_LIST_DECL_SESG(D21, TXD9, UART9, SIG_DESC_SET(SCU414, 22));
475 SIG_EXPR_LIST_DECL_SESG(D21, SD2CD, SD2, SIG_DESC_SET(SCU4B4, 22),
476 SIG_DESC_SET(SCU450, 1));
477 SIG_EXPR_LIST_DECL_SEMG(D21, SALT15, SALT15G0, SALT15,
478 SIG_DESC_SET(SCU694, 22));
479 PIN_DECL_3(D21, GPIOG6, TXD9, SD2CD, SALT15);
480 GROUP_DECL(SALT15G0, D21);
481
482 #define B21 55
483 SIG_EXPR_LIST_DECL_SESG(B21, RXD9, UART9, SIG_DESC_SET(SCU414, 23));
484 SIG_EXPR_LIST_DECL_SESG(B21, SD2WP, SD2, SIG_DESC_SET(SCU4B4, 23),
485 SIG_DESC_SET(SCU450, 1));
486 SIG_EXPR_LIST_DECL_SEMG(B21, SALT16, SALT16G0, SALT16,
487 SIG_DESC_SET(SCU694, 23));
488 PIN_DECL_3(B21, GPIOG7, RXD9, SD2WP, SALT16);
489 GROUP_DECL(SALT16G0, B21);
490
491 FUNC_GROUP_DECL(UART9, D21, B21);
492
493 FUNC_GROUP_DECL(SD2, E21, B22, C21, A22, A21, E20, D21, B21);
494
495 #define A18 56
496 SIG_EXPR_LIST_DECL_SESG(A18, SGPM1CLK, SGPM1, SIG_DESC_SET(SCU414, 24));
497 PIN_DECL_1(A18, GPIOH0, SGPM1CLK);
498
499 #define B18 57
500 SIG_EXPR_LIST_DECL_SESG(B18, SGPM1LD, SGPM1, SIG_DESC_SET(SCU414, 25));
501 PIN_DECL_1(B18, GPIOH1, SGPM1LD);
502
503 #define C18 58
504 SIG_EXPR_LIST_DECL_SESG(C18, SGPM1O, SGPM1, SIG_DESC_SET(SCU414, 26));
505 PIN_DECL_1(C18, GPIOH2, SGPM1O);
506
507 #define A17 59
508 SIG_EXPR_LIST_DECL_SESG(A17, SGPM1I, SGPM1, SIG_DESC_SET(SCU414, 27));
509 PIN_DECL_1(A17, GPIOH3, SGPM1I);
510
511 FUNC_GROUP_DECL(SGPM1, A18, B18, C18, A17);
512
513 #define D18 60
514 SIG_EXPR_LIST_DECL_SESG(D18, SGPS1CK, SGPS1, SIG_DESC_SET(SCU414, 28));
515 SIG_EXPR_LIST_DECL_SESG(D18, SCL15, I2C15, SIG_DESC_SET(SCU4B4, 28));
516 PIN_DECL_2(D18, GPIOH4, SGPS1CK, SCL15);
517
518 #define B17 61
519 SIG_EXPR_LIST_DECL_SESG(B17, SGPS1LD, SGPS1, SIG_DESC_SET(SCU414, 29));
520 SIG_EXPR_LIST_DECL_SESG(B17, SDA15, I2C15, SIG_DESC_SET(SCU4B4, 29));
521 PIN_DECL_2(B17, GPIOH5, SGPS1LD, SDA15);
522
523 FUNC_GROUP_DECL(I2C15, D18, B17);
524
525 #define C17 62
526 SIG_EXPR_LIST_DECL_SESG(C17, SGPS1O, SGPS1, SIG_DESC_SET(SCU414, 30));
527 SIG_EXPR_LIST_DECL_SESG(C17, SCL16, I2C16, SIG_DESC_SET(SCU4B4, 30));
528 PIN_DECL_2(C17, GPIOH6, SGPS1O, SCL16);
529
530 #define E18 63
531 SIG_EXPR_LIST_DECL_SESG(E18, SGPS1I, SGPS1, SIG_DESC_SET(SCU414, 31));
532 SIG_EXPR_LIST_DECL_SESG(E18, SDA16, I2C16, SIG_DESC_SET(SCU4B4, 31));
533 PIN_DECL_2(E18, GPIOH7, SGPS1I, SDA16);
534
535 FUNC_GROUP_DECL(I2C16, C17, E18);
536 FUNC_GROUP_DECL(SGPS1, D18, B17, C17, E18);
537
538 #define D17 64
539 SIG_EXPR_LIST_DECL_SESG(D17, MTRSTN, JTAGM, SIG_DESC_SET(SCU418, 0));
540 SIG_EXPR_LIST_DECL_SEMG(D17, TXD12, UART12G0, UART12, SIG_DESC_SET(SCU4B8, 0));
541 PIN_DECL_2(D17, GPIOI0, MTRSTN, TXD12);
542
543 #define A16 65
544 SIG_EXPR_LIST_DECL_SESG(A16, MTDI, JTAGM, SIG_DESC_SET(SCU418, 1));
545 SIG_EXPR_LIST_DECL_SEMG(A16, RXD12, UART12G0, UART12, SIG_DESC_SET(SCU4B8, 1));
546 PIN_DECL_2(A16, GPIOI1, MTDI, RXD12);
547
548 GROUP_DECL(UART12G0, D17, A16);
549
550 #define E17 66
551 SIG_EXPR_LIST_DECL_SESG(E17, MTCK, JTAGM, SIG_DESC_SET(SCU418, 2));
552 SIG_EXPR_LIST_DECL_SEMG(E17, TXD13, UART13G0, UART13, SIG_DESC_SET(SCU4B8, 2));
553 PIN_DECL_2(E17, GPIOI2, MTCK, TXD13);
554
555 #define D16 67
556 SIG_EXPR_LIST_DECL_SESG(D16, MTMS, JTAGM, SIG_DESC_SET(SCU418, 3));
557 SIG_EXPR_LIST_DECL_SEMG(D16, RXD13, UART13G0, UART13, SIG_DESC_SET(SCU4B8, 3));
558 PIN_DECL_2(D16, GPIOI3, MTMS, RXD13);
559
560 GROUP_DECL(UART13G0, E17, D16);
561
562 #define C16 68
563 SIG_EXPR_LIST_DECL_SESG(C16, MTDO, JTAGM, SIG_DESC_SET(SCU418, 4));
564 PIN_DECL_1(C16, GPIOI4, MTDO);
565
566 FUNC_GROUP_DECL(JTAGM, D17, A16, E17, D16, C16);
567
568 #define E16 69
569 SIG_EXPR_LIST_DECL_SESG(E16, SIOPBO, SIOPBO, SIG_DESC_SET(SCU418, 5));
570 PIN_DECL_1(E16, GPIOI5, SIOPBO);
571 FUNC_GROUP_DECL(SIOPBO, E16);
572
573 #define B16 70
574 SIG_EXPR_LIST_DECL_SESG(B16, SIOPBI, SIOPBI, SIG_DESC_SET(SCU418, 6));
575 PIN_DECL_1(B16, GPIOI6, SIOPBI);
576 FUNC_GROUP_DECL(SIOPBI, B16);
577
578 #define A15 71
579 SIG_EXPR_LIST_DECL_SESG(A15, BMCINT, BMCINT, SIG_DESC_SET(SCU418, 7));
580 SIG_EXPR_LIST_DECL_SESG(A15, SIOSCI, SIOSCI, SIG_DESC_SET(SCU4B8, 7));
581 PIN_DECL_2(A15, GPIOI7, BMCINT, SIOSCI);
582 FUNC_GROUP_DECL(BMCINT, A15);
583 FUNC_GROUP_DECL(SIOSCI, A15);
584
585 #define B20 72
586 SIG_EXPR_LIST_DECL_SEMG(B20, I3C3SCL, HVI3C3, I3C3, SIG_DESC_SET(SCU418, 8));
587 SIG_EXPR_LIST_DECL_SESG(B20, SCL1, I2C1, SIG_DESC_SET(SCU4B8, 8));
588 PIN_DECL_2(B20, GPIOJ0, I3C3SCL, SCL1);
589
590 #define A20 73
591 SIG_EXPR_LIST_DECL_SEMG(A20, I3C3SDA, HVI3C3, I3C3, SIG_DESC_SET(SCU418, 9));
592 SIG_EXPR_LIST_DECL_SESG(A20, SDA1, I2C1, SIG_DESC_SET(SCU4B8, 9));
593 PIN_DECL_2(A20, GPIOJ1, I3C3SDA, SDA1);
594
595 GROUP_DECL(HVI3C3, B20, A20);
596 FUNC_GROUP_DECL(I2C1, B20, A20);
597
598 #define E19 74
599 SIG_EXPR_LIST_DECL_SEMG(E19, I3C4SCL, HVI3C4, I3C4, SIG_DESC_SET(SCU418, 10));
600 SIG_EXPR_LIST_DECL_SESG(E19, SCL2, I2C2, SIG_DESC_SET(SCU4B8, 10));
601 PIN_DECL_2(E19, GPIOJ2, I3C4SCL, SCL2);
602
603 #define D20 75
604 SIG_EXPR_LIST_DECL_SEMG(D20, I3C4SDA, HVI3C4, I3C4, SIG_DESC_SET(SCU418, 11));
605 SIG_EXPR_LIST_DECL_SESG(D20, SDA2, I2C2, SIG_DESC_SET(SCU4B8, 11));
606 PIN_DECL_2(D20, GPIOJ3, I3C4SDA, SDA2);
607
608 GROUP_DECL(HVI3C4, E19, D20);
609 FUNC_GROUP_DECL(I2C2, E19, D20);
610
611 #define C19 76
612 SIG_EXPR_LIST_DECL_SESG(C19, I3C5SCL, I3C5, SIG_DESC_SET(SCU418, 12));
613 SIG_EXPR_LIST_DECL_SESG(C19, SCL3, I2C3, SIG_DESC_SET(SCU4B8, 12));
614 PIN_DECL_2(C19, GPIOJ4, I3C5SCL, SCL3);
615
616 #define A19 77
617 SIG_EXPR_LIST_DECL_SESG(A19, I3C5SDA, I3C5, SIG_DESC_SET(SCU418, 13));
618 SIG_EXPR_LIST_DECL_SESG(A19, SDA3, I2C3, SIG_DESC_SET(SCU4B8, 13));
619 PIN_DECL_2(A19, GPIOJ5, I3C5SDA, SDA3);
620
621 FUNC_GROUP_DECL(I3C5, C19, A19);
622 FUNC_GROUP_DECL(I2C3, C19, A19);
623
624 #define C20 78
625 SIG_EXPR_LIST_DECL_SESG(C20, I3C6SCL, I3C6, SIG_DESC_SET(SCU418, 14));
626 SIG_EXPR_LIST_DECL_SESG(C20, SCL4, I2C4, SIG_DESC_SET(SCU4B8, 14));
627 PIN_DECL_2(C20, GPIOJ6, I3C6SCL, SCL4);
628
629 #define D19 79
630 SIG_EXPR_LIST_DECL_SESG(D19, I3C6SDA, I3C6, SIG_DESC_SET(SCU418, 15));
631 SIG_EXPR_LIST_DECL_SESG(D19, SDA4, I2C4, SIG_DESC_SET(SCU4B8, 15));
632 PIN_DECL_2(D19, GPIOJ7, I3C6SDA, SDA4);
633
634 FUNC_GROUP_DECL(I3C6, C20, D19);
635 FUNC_GROUP_DECL(I2C4, C20, D19);
636
637 #define A11 80
638 SIG_EXPR_LIST_DECL_SESG(A11, SCL5, I2C5, SIG_DESC_SET(SCU418, 16));
639 PIN_DECL_1(A11, GPIOK0, SCL5);
640
641 #define C11 81
642 SIG_EXPR_LIST_DECL_SESG(C11, SDA5, I2C5, SIG_DESC_SET(SCU418, 17));
643 PIN_DECL_1(C11, GPIOK1, SDA5);
644
645 FUNC_GROUP_DECL(I2C5, A11, C11);
646
647 #define D12 82
648 SIG_EXPR_LIST_DECL_SESG(D12, SCL6, I2C6, SIG_DESC_SET(SCU418, 18));
649 PIN_DECL_1(D12, GPIOK2, SCL6);
650
651 #define E13 83
652 SIG_EXPR_LIST_DECL_SESG(E13, SDA6, I2C6, SIG_DESC_SET(SCU418, 19));
653 PIN_DECL_1(E13, GPIOK3, SDA6);
654
655 FUNC_GROUP_DECL(I2C6, D12, E13);
656
657 #define D11 84
658 SIG_EXPR_LIST_DECL_SESG(D11, SCL7, I2C7, SIG_DESC_SET(SCU418, 20));
659 PIN_DECL_1(D11, GPIOK4, SCL7);
660
661 #define E11 85
662 SIG_EXPR_LIST_DECL_SESG(E11, SDA7, I2C7, SIG_DESC_SET(SCU418, 21));
663 PIN_DECL_1(E11, GPIOK5, SDA7);
664
665 FUNC_GROUP_DECL(I2C7, D11, E11);
666
667 #define F13 86
668 SIG_EXPR_LIST_DECL_SESG(F13, SCL8, I2C8, SIG_DESC_SET(SCU418, 22));
669 PIN_DECL_1(F13, GPIOK6, SCL8);
670
671 #define E12 87
672 SIG_EXPR_LIST_DECL_SESG(E12, SDA8, I2C8, SIG_DESC_SET(SCU418, 23));
673 PIN_DECL_1(E12, GPIOK7, SDA8);
674
675 FUNC_GROUP_DECL(I2C8, F13, E12);
676
677 #define D15 88
678 SIG_EXPR_LIST_DECL_SESG(D15, SCL9, I2C9, SIG_DESC_SET(SCU418, 24));
679 PIN_DECL_1(D15, GPIOL0, SCL9);
680
681 #define A14 89
682 SIG_EXPR_LIST_DECL_SESG(A14, SDA9, I2C9, SIG_DESC_SET(SCU418, 25));
683 PIN_DECL_1(A14, GPIOL1, SDA9);
684
685 FUNC_GROUP_DECL(I2C9, D15, A14);
686
687 #define E15 90
688 SIG_EXPR_LIST_DECL_SESG(E15, SCL10, I2C10, SIG_DESC_SET(SCU418, 26));
689 PIN_DECL_1(E15, GPIOL2, SCL10);
690
691 #define A13 91
692 SIG_EXPR_LIST_DECL_SESG(A13, SDA10, I2C10, SIG_DESC_SET(SCU418, 27));
693 PIN_DECL_1(A13, GPIOL3, SDA10);
694
695 FUNC_GROUP_DECL(I2C10, E15, A13);
696
697 #define C15 92
698 SSSF_PIN_DECL(C15, GPIOL4, TXD3, SIG_DESC_SET(SCU418, 28));
699
700 #define F15 93
701 SSSF_PIN_DECL(F15, GPIOL5, RXD3, SIG_DESC_SET(SCU418, 29));
702
703 #define B14 94
704 SSSF_PIN_DECL(B14, GPIOL6, VGAHS, SIG_DESC_SET(SCU418, 30));
705
706 #define C14 95
707 SSSF_PIN_DECL(C14, GPIOL7, VGAVS, SIG_DESC_SET(SCU418, 31));
708
709 #define D14 96
710 SSSF_PIN_DECL(D14, GPIOM0, NCTS1, SIG_DESC_SET(SCU41C, 0));
711
712 #define B13 97
713 SSSF_PIN_DECL(B13, GPIOM1, NDCD1, SIG_DESC_SET(SCU41C, 1));
714
715 #define A12 98
716 SSSF_PIN_DECL(A12, GPIOM2, NDSR1, SIG_DESC_SET(SCU41C, 2));
717
718 #define E14 99
719 SSSF_PIN_DECL(E14, GPIOM3, NRI1, SIG_DESC_SET(SCU41C, 3));
720
721 #define B12 100
722 SSSF_PIN_DECL(B12, GPIOM4, NDTR1, SIG_DESC_SET(SCU41C, 4));
723
724 #define C12 101
725 SSSF_PIN_DECL(C12, GPIOM5, NRTS1, SIG_DESC_SET(SCU41C, 5));
726
727 #define C13 102
728 SSSF_PIN_DECL(C13, GPIOM6, TXD1, SIG_DESC_SET(SCU41C, 6));
729
730 #define D13 103
731 SSSF_PIN_DECL(D13, GPIOM7, RXD1, SIG_DESC_SET(SCU41C, 7));
732
733 #define P25 104
734 SSSF_PIN_DECL(P25, GPION0, NCTS2, SIG_DESC_SET(SCU41C, 8));
735
736 #define N23 105
737 SSSF_PIN_DECL(N23, GPION1, NDCD2, SIG_DESC_SET(SCU41C, 9));
738
739 #define N25 106
740 SSSF_PIN_DECL(N25, GPION2, NDSR2, SIG_DESC_SET(SCU41C, 10));
741
742 #define N24 107
743 SSSF_PIN_DECL(N24, GPION3, NRI2, SIG_DESC_SET(SCU41C, 11));
744
745 #define P26 108
746 SSSF_PIN_DECL(P26, GPION4, NDTR2, SIG_DESC_SET(SCU41C, 12));
747
748 #define M23 109
749 SSSF_PIN_DECL(M23, GPION5, NRTS2, SIG_DESC_SET(SCU41C, 13));
750
751 #define N26 110
752 SSSF_PIN_DECL(N26, GPION6, TXD2, SIG_DESC_SET(SCU41C, 14));
753
754 #define M26 111
755 SSSF_PIN_DECL(M26, GPION7, RXD2, SIG_DESC_SET(SCU41C, 15));
756
757 #define AD26 112
758 SSSF_PIN_DECL(AD26, GPIOO0, PWM0, SIG_DESC_SET(SCU41C, 16));
759
760 #define AD22 113
761 SSSF_PIN_DECL(AD22, GPIOO1, PWM1, SIG_DESC_SET(SCU41C, 17));
762
763 #define AD23 114
764 SSSF_PIN_DECL(AD23, GPIOO2, PWM2, SIG_DESC_SET(SCU41C, 18));
765
766 #define AD24 115
767 SSSF_PIN_DECL(AD24, GPIOO3, PWM3, SIG_DESC_SET(SCU41C, 19));
768
769 #define AD25 116
770 SSSF_PIN_DECL(AD25, GPIOO4, PWM4, SIG_DESC_SET(SCU41C, 20));
771
772 #define AC22 117
773 SSSF_PIN_DECL(AC22, GPIOO5, PWM5, SIG_DESC_SET(SCU41C, 21));
774
775 #define AC24 118
776 SSSF_PIN_DECL(AC24, GPIOO6, PWM6, SIG_DESC_SET(SCU41C, 22));
777
778 #define AC23 119
779 SSSF_PIN_DECL(AC23, GPIOO7, PWM7, SIG_DESC_SET(SCU41C, 23));
780
781 #define AB22 120
782 SIG_EXPR_LIST_DECL_SEMG(AB22, PWM8, PWM8G1, PWM8, SIG_DESC_SET(SCU41C, 24));
783 SIG_EXPR_LIST_DECL_SESG(AB22, THRUIN0, THRU0, SIG_DESC_SET(SCU4BC, 24));
784 PIN_DECL_2(AB22, GPIOP0, PWM8, THRUIN0);
785 GROUP_DECL(PWM8G1, AB22);
786 FUNC_DECL_2(PWM8, PWM8G0, PWM8G1);
787
788 #define W24 121
789 SIG_EXPR_LIST_DECL_SEMG(W24, PWM9, PWM9G1, PWM9, SIG_DESC_SET(SCU41C, 25));
790 SIG_EXPR_LIST_DECL_SESG(W24, THRUOUT0, THRU0, SIG_DESC_SET(SCU4BC, 25));
791 PIN_DECL_2(W24, GPIOP1, PWM9, THRUOUT0);
792
793 FUNC_GROUP_DECL(THRU0, AB22, W24);
794
795 GROUP_DECL(PWM9G1, W24);
796 FUNC_DECL_2(PWM9, PWM9G0, PWM9G1);
797
798 #define AA23 122
799 SIG_EXPR_LIST_DECL_SEMG(AA23, PWM10, PWM10G1, PWM10, SIG_DESC_SET(SCU41C, 26));
800 SIG_EXPR_LIST_DECL_SESG(AA23, THRUIN1, THRU1, SIG_DESC_SET(SCU4BC, 26));
801 PIN_DECL_2(AA23, GPIOP2, PWM10, THRUIN1);
802 GROUP_DECL(PWM10G1, AA23);
803 FUNC_DECL_2(PWM10, PWM10G0, PWM10G1);
804
805 #define AA24 123
806 SIG_EXPR_LIST_DECL_SEMG(AA24, PWM11, PWM11G1, PWM11, SIG_DESC_SET(SCU41C, 27));
807 SIG_EXPR_LIST_DECL_SESG(AA24, THRUOUT1, THRU1, SIG_DESC_SET(SCU4BC, 27));
808 PIN_DECL_2(AA24, GPIOP3, PWM11, THRUOUT1);
809 GROUP_DECL(PWM11G1, AA24);
810 FUNC_DECL_2(PWM11, PWM11G0, PWM11G1);
811
812 FUNC_GROUP_DECL(THRU1, AA23, AA24);
813
814 #define W23 124
815 SIG_EXPR_LIST_DECL_SEMG(W23, PWM12, PWM12G1, PWM12, SIG_DESC_SET(SCU41C, 28));
816 SIG_EXPR_LIST_DECL_SESG(W23, THRUIN2, THRU2, SIG_DESC_SET(SCU4BC, 28));
817 PIN_DECL_2(W23, GPIOP4, PWM12, THRUIN2);
818 GROUP_DECL(PWM12G1, W23);
819 FUNC_DECL_2(PWM12, PWM12G0, PWM12G1);
820
821 #define AB23 125
822 SIG_EXPR_LIST_DECL_SEMG(AB23, PWM13, PWM13G1, PWM13, SIG_DESC_SET(SCU41C, 29));
823 SIG_EXPR_LIST_DECL_SESG(AB23, THRUOUT2, THRU2, SIG_DESC_SET(SCU4BC, 29));
824 PIN_DECL_2(AB23, GPIOP5, PWM13, THRUOUT2);
825 GROUP_DECL(PWM13G1, AB23);
826 FUNC_DECL_2(PWM13, PWM13G0, PWM13G1);
827
828 FUNC_GROUP_DECL(THRU2, W23, AB23);
829
830 #define AB24 126
831 SIG_EXPR_LIST_DECL_SEMG(AB24, PWM14, PWM14G1, PWM14, SIG_DESC_SET(SCU41C, 30));
832 SIG_EXPR_LIST_DECL_SESG(AB24, THRUIN3, THRU3, SIG_DESC_SET(SCU4BC, 30));
833 PIN_DECL_2(AB24, GPIOP6, PWM14, THRUIN3);
834 GROUP_DECL(PWM14G1, AB24);
835 FUNC_DECL_2(PWM14, PWM14G0, PWM14G1);
836
837 #define Y23 127
838 SIG_EXPR_LIST_DECL_SEMG(Y23, PWM15, PWM15G1, PWM15, SIG_DESC_SET(SCU41C, 31));
839 SIG_EXPR_LIST_DECL_SESG(Y23, THRUOUT3, THRU3, SIG_DESC_SET(SCU4BC, 31));
840 SIG_EXPR_LIST_DECL_SESG(Y23, HEARTBEAT, HEARTBEAT, SIG_DESC_SET(SCU69C, 31));
841 PIN_DECL_3(Y23, GPIOP7, PWM15, THRUOUT3, HEARTBEAT);
842 GROUP_DECL(PWM15G1, Y23);
843 FUNC_DECL_2(PWM15, PWM15G0, PWM15G1);
844
845 FUNC_GROUP_DECL(THRU3, AB24, Y23);
846 FUNC_GROUP_DECL(HEARTBEAT, Y23);
847
848 #define AA25 128
849 SSSF_PIN_DECL(AA25, GPIOQ0, TACH0, SIG_DESC_SET(SCU430, 0));
850
851 #define AB25 129
852 SSSF_PIN_DECL(AB25, GPIOQ1, TACH1, SIG_DESC_SET(SCU430, 1));
853
854 #define Y24 130
855 SSSF_PIN_DECL(Y24, GPIOQ2, TACH2, SIG_DESC_SET(SCU430, 2));
856
857 #define AB26 131
858 SSSF_PIN_DECL(AB26, GPIOQ3, TACH3, SIG_DESC_SET(SCU430, 3));
859
860 #define Y26 132
861 SSSF_PIN_DECL(Y26, GPIOQ4, TACH4, SIG_DESC_SET(SCU430, 4));
862
863 #define AC26 133
864 SSSF_PIN_DECL(AC26, GPIOQ5, TACH5, SIG_DESC_SET(SCU430, 5));
865
866 #define Y25 134
867 SSSF_PIN_DECL(Y25, GPIOQ6, TACH6, SIG_DESC_SET(SCU430, 6));
868
869 #define AA26 135
870 SSSF_PIN_DECL(AA26, GPIOQ7, TACH7, SIG_DESC_SET(SCU430, 7));
871
872 #define V25 136
873 SSSF_PIN_DECL(V25, GPIOR0, TACH8, SIG_DESC_SET(SCU430, 8));
874
875 #define U24 137
876 SSSF_PIN_DECL(U24, GPIOR1, TACH9, SIG_DESC_SET(SCU430, 9));
877
878 #define V24 138
879 SSSF_PIN_DECL(V24, GPIOR2, TACH10, SIG_DESC_SET(SCU430, 10));
880
881 #define V26 139
882 SSSF_PIN_DECL(V26, GPIOR3, TACH11, SIG_DESC_SET(SCU430, 11));
883
884 #define U25 140
885 SSSF_PIN_DECL(U25, GPIOR4, TACH12, SIG_DESC_SET(SCU430, 12));
886
887 #define T23 141
888 SSSF_PIN_DECL(T23, GPIOR5, TACH13, SIG_DESC_SET(SCU430, 13));
889
890 #define W26 142
891 SSSF_PIN_DECL(W26, GPIOR6, TACH14, SIG_DESC_SET(SCU430, 14));
892
893 #define U26 143
894 SSSF_PIN_DECL(U26, GPIOR7, TACH15, SIG_DESC_SET(SCU430, 15));
895
896 #define R23 144
897 SIG_EXPR_LIST_DECL_SESG(R23, MDC1, MDIO1, SIG_DESC_SET(SCU430, 16));
898 PIN_DECL_1(R23, GPIOS0, MDC1);
899
900 #define T25 145
901 SIG_EXPR_LIST_DECL_SESG(T25, MDIO1, MDIO1, SIG_DESC_SET(SCU430, 17));
902 PIN_DECL_1(T25, GPIOS1, MDIO1);
903
904 FUNC_GROUP_DECL(MDIO1, R23, T25);
905
906 #define T26 146
907 SSSF_PIN_DECL(T26, GPIOS2, PEWAKE, SIG_DESC_SET(SCU430, 18));
908
909 #define R24 147
910 SSSF_PIN_DECL(R24, GPIOS3, OSCCLK, SIG_DESC_SET(SCU430, 19));
911
912 #define R26 148
913 SIG_EXPR_LIST_DECL_SESG(R26, TXD10, UART10, SIG_DESC_SET(SCU430, 20));
914 PIN_DECL_1(R26, GPIOS4, TXD10);
915
916 #define P24 149
917 SIG_EXPR_LIST_DECL_SESG(P24, RXD10, UART10, SIG_DESC_SET(SCU430, 21));
918 PIN_DECL_1(P24, GPIOS5, RXD10);
919
920 FUNC_GROUP_DECL(UART10, R26, P24);
921
922 #define P23 150
923 SIG_EXPR_LIST_DECL_SESG(P23, TXD11, UART11, SIG_DESC_SET(SCU430, 22));
924 PIN_DECL_1(P23, GPIOS6, TXD11);
925
926 #define T24 151
927 SIG_EXPR_LIST_DECL_SESG(T24, RXD11, UART11, SIG_DESC_SET(SCU430, 23));
928 PIN_DECL_1(T24, GPIOS7, RXD11);
929
930 FUNC_GROUP_DECL(UART11, P23, T24);
931
932 #define AD20 152
933 SIG_EXPR_LIST_DECL_SESG(AD20, GPIT0, GPIT0, SIG_DESC_SET(SCU430, 24));
934 SIG_EXPR_LIST_DECL_SESG(AD20, ADC0, ADC0);
935 PIN_DECL_(AD20, SIG_EXPR_LIST_PTR(AD20, GPIT0), SIG_EXPR_LIST_PTR(AD20, ADC0));
936 FUNC_GROUP_DECL(GPIT0, AD20);
937 FUNC_GROUP_DECL(ADC0, AD20);
938
939 #define AC18 153
940 SIG_EXPR_LIST_DECL_SESG(AC18, GPIT1, GPIT1, SIG_DESC_SET(SCU430, 25));
941 SIG_EXPR_LIST_DECL_SESG(AC18, ADC1, ADC1);
942 PIN_DECL_(AC18, SIG_EXPR_LIST_PTR(AC18, GPIT1), SIG_EXPR_LIST_PTR(AC18, ADC1));
943 FUNC_GROUP_DECL(GPIT1, AC18);
944 FUNC_GROUP_DECL(ADC1, AC18);
945
946 #define AE19 154
947 SIG_EXPR_LIST_DECL_SESG(AE19, GPIT2, GPIT2, SIG_DESC_SET(SCU430, 26));
948 SIG_EXPR_LIST_DECL_SESG(AE19, ADC2, ADC2);
949 PIN_DECL_(AE19, SIG_EXPR_LIST_PTR(AE19, GPIT2), SIG_EXPR_LIST_PTR(AE19, ADC2));
950 FUNC_GROUP_DECL(GPIT2, AE19);
951 FUNC_GROUP_DECL(ADC2, AE19);
952
953 #define AD19 155
954 SIG_EXPR_LIST_DECL_SESG(AD19, GPIT3, GPIT3, SIG_DESC_SET(SCU430, 27));
955 SIG_EXPR_LIST_DECL_SESG(AD19, ADC3, ADC3);
956 PIN_DECL_(AD19, SIG_EXPR_LIST_PTR(AD19, GPIT3), SIG_EXPR_LIST_PTR(AD19, ADC3));
957 FUNC_GROUP_DECL(GPIT3, AD19);
958 FUNC_GROUP_DECL(ADC3, AD19);
959
960 #define AC19 156
961 SIG_EXPR_LIST_DECL_SESG(AC19, GPIT4, GPIT4, SIG_DESC_SET(SCU430, 28));
962 SIG_EXPR_LIST_DECL_SESG(AC19, ADC4, ADC4);
963 PIN_DECL_(AC19, SIG_EXPR_LIST_PTR(AC19, GPIT4), SIG_EXPR_LIST_PTR(AC19, ADC4));
964 FUNC_GROUP_DECL(GPIT4, AC19);
965 FUNC_GROUP_DECL(ADC4, AC19);
966
967 #define AB19 157
968 SIG_EXPR_LIST_DECL_SESG(AB19, GPIT5, GPIT5, SIG_DESC_SET(SCU430, 29));
969 SIG_EXPR_LIST_DECL_SESG(AB19, ADC5, ADC5);
970 PIN_DECL_(AB19, SIG_EXPR_LIST_PTR(AB19, GPIT5), SIG_EXPR_LIST_PTR(AB19, ADC5));
971 FUNC_GROUP_DECL(GPIT5, AB19);
972 FUNC_GROUP_DECL(ADC5, AB19);
973
974 #define AB18 158
975 SIG_EXPR_LIST_DECL_SESG(AB18, GPIT6, GPIT6, SIG_DESC_SET(SCU430, 30));
976 SIG_EXPR_LIST_DECL_SESG(AB18, ADC6, ADC6);
977 PIN_DECL_(AB18, SIG_EXPR_LIST_PTR(AB18, GPIT6), SIG_EXPR_LIST_PTR(AB18, ADC6));
978 FUNC_GROUP_DECL(GPIT6, AB18);
979 FUNC_GROUP_DECL(ADC6, AB18);
980
981 #define AE18 159
982 SIG_EXPR_LIST_DECL_SESG(AE18, GPIT7, GPIT7, SIG_DESC_SET(SCU430, 31));
983 SIG_EXPR_LIST_DECL_SESG(AE18, ADC7, ADC7);
984 PIN_DECL_(AE18, SIG_EXPR_LIST_PTR(AE18, GPIT7), SIG_EXPR_LIST_PTR(AE18, ADC7));
985 FUNC_GROUP_DECL(GPIT7, AE18);
986 FUNC_GROUP_DECL(ADC7, AE18);
987
988 #define AB16 160
989 SIG_EXPR_LIST_DECL_SEMG(AB16, SALT9, SALT9G1, SALT9, SIG_DESC_SET(SCU434, 0),
990 SIG_DESC_CLEAR(SCU694, 16));
991 SIG_EXPR_LIST_DECL_SESG(AB16, GPIU0, GPIU0, SIG_DESC_SET(SCU434, 0),
992 SIG_DESC_SET(SCU694, 16));
993 SIG_EXPR_LIST_DECL_SESG(AB16, ADC8, ADC8);
994 PIN_DECL_(AB16, SIG_EXPR_LIST_PTR(AB16, SALT9), SIG_EXPR_LIST_PTR(AB16, GPIU0),
995 SIG_EXPR_LIST_PTR(AB16, ADC8));
996 GROUP_DECL(SALT9G1, AB16);
997 FUNC_DECL_2(SALT9, SALT9G0, SALT9G1);
998 FUNC_GROUP_DECL(GPIU0, AB16);
999 FUNC_GROUP_DECL(ADC8, AB16);
1000
1001 #define AA17 161
1002 SIG_EXPR_LIST_DECL_SEMG(AA17, SALT10, SALT10G1, SALT10, SIG_DESC_SET(SCU434, 1),
1003 SIG_DESC_CLEAR(SCU694, 17));
1004 SIG_EXPR_LIST_DECL_SESG(AA17, GPIU1, GPIU1, SIG_DESC_SET(SCU434, 1),
1005 SIG_DESC_SET(SCU694, 17));
1006 SIG_EXPR_LIST_DECL_SESG(AA17, ADC9, ADC9);
1007 PIN_DECL_(AA17, SIG_EXPR_LIST_PTR(AA17, SALT10), SIG_EXPR_LIST_PTR(AA17, GPIU1),
1008 SIG_EXPR_LIST_PTR(AA17, ADC9));
1009 GROUP_DECL(SALT10G1, AA17);
1010 FUNC_DECL_2(SALT10, SALT10G0, SALT10G1);
1011 FUNC_GROUP_DECL(GPIU1, AA17);
1012 FUNC_GROUP_DECL(ADC9, AA17);
1013
1014 #define AB17 162
1015 SIG_EXPR_LIST_DECL_SEMG(AB17, SALT11, SALT11G1, SALT11, SIG_DESC_SET(SCU434, 2),
1016 SIG_DESC_CLEAR(SCU694, 18));
1017 SIG_EXPR_LIST_DECL_SESG(AB17, GPIU2, GPIU2, SIG_DESC_SET(SCU434, 2),
1018 SIG_DESC_SET(SCU694, 18));
1019 SIG_EXPR_LIST_DECL_SESG(AB17, ADC10, ADC10);
1020 PIN_DECL_(AB17, SIG_EXPR_LIST_PTR(AB17, SALT11), SIG_EXPR_LIST_PTR(AB17, GPIU2),
1021 SIG_EXPR_LIST_PTR(AB17, ADC10));
1022 GROUP_DECL(SALT11G1, AB17);
1023 FUNC_DECL_2(SALT11, SALT11G0, SALT11G1);
1024 FUNC_GROUP_DECL(GPIU2, AB17);
1025 FUNC_GROUP_DECL(ADC10, AB17);
1026
1027 #define AE16 163
1028 SIG_EXPR_LIST_DECL_SEMG(AE16, SALT12, SALT12G1, SALT12, SIG_DESC_SET(SCU434, 3),
1029 SIG_DESC_CLEAR(SCU694, 19));
1030 SIG_EXPR_LIST_DECL_SESG(AE16, GPIU3, GPIU3, SIG_DESC_SET(SCU434, 3),
1031 SIG_DESC_SET(SCU694, 19));
1032 SIG_EXPR_LIST_DECL_SESG(AE16, ADC11, ADC11);
1033 PIN_DECL_(AE16, SIG_EXPR_LIST_PTR(AE16, SALT12), SIG_EXPR_LIST_PTR(AE16, GPIU3),
1034 SIG_EXPR_LIST_PTR(AE16, ADC11));
1035 GROUP_DECL(SALT12G1, AE16);
1036 FUNC_DECL_2(SALT12, SALT12G0, SALT12G1);
1037 FUNC_GROUP_DECL(GPIU3, AE16);
1038 FUNC_GROUP_DECL(ADC11, AE16);
1039
1040 #define AC16 164
1041 SIG_EXPR_LIST_DECL_SEMG(AC16, SALT13, SALT13G1, SALT13, SIG_DESC_SET(SCU434, 4),
1042 SIG_DESC_CLEAR(SCU694, 20));
1043 SIG_EXPR_LIST_DECL_SESG(AC16, GPIU4, GPIU4, SIG_DESC_SET(SCU434, 4),
1044 SIG_DESC_SET(SCU694, 20));
1045 SIG_EXPR_LIST_DECL_SESG(AC16, ADC12, ADC12);
1046 PIN_DECL_(AC16, SIG_EXPR_LIST_PTR(AC16, SALT13), SIG_EXPR_LIST_PTR(AC16, GPIU4),
1047 SIG_EXPR_LIST_PTR(AC16, ADC12));
1048 GROUP_DECL(SALT13G1, AC16);
1049 FUNC_DECL_2(SALT13, SALT13G0, SALT13G1);
1050 FUNC_GROUP_DECL(GPIU4, AC16);
1051 FUNC_GROUP_DECL(ADC12, AC16);
1052
1053 #define AA16 165
1054 SIG_EXPR_LIST_DECL_SEMG(AA16, SALT14, SALT14G1, SALT14, SIG_DESC_SET(SCU434, 5),
1055 SIG_DESC_CLEAR(SCU694, 21));
1056 SIG_EXPR_LIST_DECL_SESG(AA16, GPIU5, GPIU5, SIG_DESC_SET(SCU434, 5),
1057 SIG_DESC_SET(SCU694, 21));
1058 SIG_EXPR_LIST_DECL_SESG(AA16, ADC13, ADC13);
1059 PIN_DECL_(AA16, SIG_EXPR_LIST_PTR(AA16, SALT14), SIG_EXPR_LIST_PTR(AA16, GPIU5),
1060 SIG_EXPR_LIST_PTR(AA16, ADC13));
1061 GROUP_DECL(SALT14G1, AA16);
1062 FUNC_DECL_2(SALT14, SALT14G0, SALT14G1);
1063 FUNC_GROUP_DECL(GPIU5, AA16);
1064 FUNC_GROUP_DECL(ADC13, AA16);
1065
1066 #define AD16 166
1067 SIG_EXPR_LIST_DECL_SEMG(AD16, SALT15, SALT15G1, SALT15, SIG_DESC_SET(SCU434, 6),
1068 SIG_DESC_CLEAR(SCU694, 22));
1069 SIG_EXPR_LIST_DECL_SESG(AD16, GPIU6, GPIU6, SIG_DESC_SET(SCU434, 6),
1070 SIG_DESC_SET(SCU694, 22));
1071 SIG_EXPR_LIST_DECL_SESG(AD16, ADC14, ADC14);
1072 PIN_DECL_(AD16, SIG_EXPR_LIST_PTR(AD16, SALT15), SIG_EXPR_LIST_PTR(AD16, GPIU6),
1073 SIG_EXPR_LIST_PTR(AD16, ADC14));
1074 GROUP_DECL(SALT15G1, AD16);
1075 FUNC_DECL_2(SALT15, SALT15G0, SALT15G1);
1076 FUNC_GROUP_DECL(GPIU6, AD16);
1077 FUNC_GROUP_DECL(ADC14, AD16);
1078
1079 #define AC17 167
1080 SIG_EXPR_LIST_DECL_SEMG(AC17, SALT16, SALT16G1, SALT16, SIG_DESC_SET(SCU434, 7),
1081 SIG_DESC_CLEAR(SCU694, 23));
1082 SIG_EXPR_LIST_DECL_SESG(AC17, GPIU7, GPIU7, SIG_DESC_SET(SCU434, 7),
1083 SIG_DESC_SET(SCU694, 23));
1084 SIG_EXPR_LIST_DECL_SESG(AC17, ADC15, ADC15);
1085 PIN_DECL_(AC17, SIG_EXPR_LIST_PTR(AC17, SALT16), SIG_EXPR_LIST_PTR(AC17, GPIU7),
1086 SIG_EXPR_LIST_PTR(AC17, ADC15));
1087 GROUP_DECL(SALT16G1, AC17);
1088 FUNC_DECL_2(SALT16, SALT16G0, SALT16G1);
1089 FUNC_GROUP_DECL(GPIU7, AC17);
1090 FUNC_GROUP_DECL(ADC15, AC17);
1091
1092 #define AB15 168
1093 SSSF_PIN_DECL(AB15, GPIOV0, SIOS3, SIG_DESC_SET(SCU434, 8));
1094
1095 #define AF14 169
1096 SSSF_PIN_DECL(AF14, GPIOV1, SIOS5, SIG_DESC_SET(SCU434, 9));
1097
1098 #define AD14 170
1099 SSSF_PIN_DECL(AD14, GPIOV2, SIOPWREQ, SIG_DESC_SET(SCU434, 10));
1100
1101 #define AC15 171
1102 SSSF_PIN_DECL(AC15, GPIOV3, SIOONCTRL, SIG_DESC_SET(SCU434, 11));
1103
1104 #define AE15 172
1105 SSSF_PIN_DECL(AE15, GPIOV4, SIOPWRGD, SIG_DESC_SET(SCU434, 12));
1106
1107 #define AE14 173
1108 SIG_EXPR_LIST_DECL_SESG(AE14, LPCPD, LPCPD, SIG_DESC_SET(SCU434, 13));
1109 SIG_EXPR_LIST_DECL_SESG(AE14, LHPD, LHPD, SIG_DESC_SET(SCU4D4, 13));
1110 PIN_DECL_2(AE14, GPIOV5, LPCPD, LHPD);
1111 FUNC_GROUP_DECL(LPCPD, AE14);
1112 FUNC_GROUP_DECL(LHPD, AE14);
1113
1114 #define AD15 174
1115 SSSF_PIN_DECL(AD15, GPIOV6, LPCPME, SIG_DESC_SET(SCU434, 14));
1116
1117 #define AF15 175
1118 SSSF_PIN_DECL(AF15, GPIOV7, LPCSMI, SIG_DESC_SET(SCU434, 15));
1119
1120 #define AB7 176
1121 SIG_EXPR_LIST_DECL_SESG(AB7, LAD0, LPC, SIG_DESC_SET(SCU434, 16),
1122 SIG_DESC_SET(SCU510, 6));
1123 SIG_EXPR_LIST_DECL_SESG(AB7, ESPID0, ESPI, SIG_DESC_SET(SCU434, 16));
1124 PIN_DECL_2(AB7, GPIOW0, LAD0, ESPID0);
1125
1126 #define AB8 177
1127 SIG_EXPR_LIST_DECL_SESG(AB8, LAD1, LPC, SIG_DESC_SET(SCU434, 17),
1128 SIG_DESC_SET(SCU510, 6));
1129 SIG_EXPR_LIST_DECL_SESG(AB8, ESPID1, ESPI, SIG_DESC_SET(SCU434, 17));
1130 PIN_DECL_2(AB8, GPIOW1, LAD1, ESPID1);
1131
1132 #define AC8 178
1133 SIG_EXPR_LIST_DECL_SESG(AC8, LAD2, LPC, SIG_DESC_SET(SCU434, 18),
1134 SIG_DESC_SET(SCU510, 6));
1135 SIG_EXPR_LIST_DECL_SESG(AC8, ESPID2, ESPI, SIG_DESC_SET(SCU434, 18));
1136 PIN_DECL_2(AC8, GPIOW2, LAD2, ESPID2);
1137
1138 #define AC7 179
1139 SIG_EXPR_LIST_DECL_SESG(AC7, LAD3, LPC, SIG_DESC_SET(SCU434, 19),
1140 SIG_DESC_SET(SCU510, 6));
1141 SIG_EXPR_LIST_DECL_SESG(AC7, ESPID3, ESPI, SIG_DESC_SET(SCU434, 19));
1142 PIN_DECL_2(AC7, GPIOW3, LAD3, ESPID3);
1143
1144 #define AE7 180
1145 SIG_EXPR_LIST_DECL_SESG(AE7, LCLK, LPC, SIG_DESC_SET(SCU434, 20),
1146 SIG_DESC_SET(SCU510, 6));
1147 SIG_EXPR_LIST_DECL_SESG(AE7, ESPICK, ESPI, SIG_DESC_SET(SCU434, 20));
1148 PIN_DECL_2(AE7, GPIOW4, LCLK, ESPICK);
1149
1150 #define AF7 181
1151 SIG_EXPR_LIST_DECL_SESG(AF7, LFRAME, LPC, SIG_DESC_SET(SCU434, 21),
1152 SIG_DESC_SET(SCU510, 6));
1153 SIG_EXPR_LIST_DECL_SESG(AF7, ESPICS, ESPI, SIG_DESC_SET(SCU434, 21));
1154 PIN_DECL_2(AF7, GPIOW5, LFRAME, ESPICS);
1155
1156 #define AD7 182
1157 SIG_EXPR_LIST_DECL_SESG(AD7, LSIRQ, LSIRQ, SIG_DESC_SET(SCU434, 22),
1158 SIG_DESC_SET(SCU510, 6));
1159 SIG_EXPR_LIST_DECL_SESG(AD7, ESPIALT, ESPIALT, SIG_DESC_SET(SCU434, 22));
1160 PIN_DECL_2(AD7, GPIOW6, LSIRQ, ESPIALT);
1161 FUNC_GROUP_DECL(LSIRQ, AD7);
1162 FUNC_GROUP_DECL(ESPIALT, AD7);
1163
1164 #define AD8 183
1165 SIG_EXPR_LIST_DECL_SESG(AD8, LPCRST, LPC, SIG_DESC_SET(SCU434, 23),
1166 SIG_DESC_SET(SCU510, 6));
1167 SIG_EXPR_LIST_DECL_SESG(AD8, ESPIRST, ESPI, SIG_DESC_SET(SCU434, 23));
1168 PIN_DECL_2(AD8, GPIOW7, LPCRST, ESPIRST);
1169
1170 FUNC_GROUP_DECL(LPC, AB7, AB8, AC8, AC7, AE7, AF7, AD8);
1171 FUNC_GROUP_DECL(ESPI, AB7, AB8, AC8, AC7, AE7, AF7, AD8);
1172
1173 #define AE8 184
1174 SIG_EXPR_LIST_DECL_SEMG(AE8, SPI2CS0, SPI2, SPI2, SIG_DESC_SET(SCU434, 24));
1175 PIN_DECL_1(AE8, GPIOX0, SPI2CS0);
1176
1177 #define AA9 185
1178 SSSF_PIN_DECL(AA9, GPIOX1, SPI2CS1, SIG_DESC_SET(SCU434, 25));
1179
1180 #define AC9 186
1181 SSSF_PIN_DECL(AC9, GPIOX2, SPI2CS2, SIG_DESC_SET(SCU434, 26));
1182
1183 #define AF8 187
1184 SIG_EXPR_LIST_DECL_SEMG(AF8, SPI2CK, SPI2, SPI2, SIG_DESC_SET(SCU434, 27));
1185 PIN_DECL_1(AF8, GPIOX3, SPI2CK);
1186
1187 #define AB9 188
1188 SIG_EXPR_LIST_DECL_SEMG(AB9, SPI2MOSI, SPI2, SPI2, SIG_DESC_SET(SCU434, 28));
1189 PIN_DECL_1(AB9, GPIOX4, SPI2MOSI);
1190
1191 #define AD9 189
1192 SIG_EXPR_LIST_DECL_SEMG(AD9, SPI2MISO, SPI2, SPI2, SIG_DESC_SET(SCU434, 29));
1193 PIN_DECL_1(AD9, GPIOX5, SPI2MISO);
1194
1195 GROUP_DECL(SPI2, AE8, AF8, AB9, AD9);
1196
1197 #define AF9 190
1198 SIG_EXPR_LIST_DECL_SEMG(AF9, SPI2DQ2, QSPI2, SPI2, SIG_DESC_SET(SCU434, 30));
1199 SIG_EXPR_LIST_DECL_SEMG(AF9, TXD12, UART12G1, UART12, SIG_DESC_SET(SCU4D4, 30));
1200 PIN_DECL_2(AF9, GPIOX6, SPI2DQ2, TXD12);
1201
1202 #define AB10 191
1203 SIG_EXPR_LIST_DECL_SEMG(AB10, SPI2DQ3, QSPI2, SPI2, SIG_DESC_SET(SCU434, 31));
1204 SIG_EXPR_LIST_DECL_SEMG(AB10, RXD12, UART12G1, UART12,
1205 SIG_DESC_SET(SCU4D4, 31));
1206 PIN_DECL_2(AB10, GPIOX7, SPI2DQ3, RXD12);
1207
1208 GROUP_DECL(QSPI2, AE8, AF8, AB9, AD9, AF9, AB10);
1209 FUNC_DECL_2(SPI2, SPI2, QSPI2);
1210
1211 GROUP_DECL(UART12G1, AF9, AB10);
1212 FUNC_DECL_2(UART12, UART12G0, UART12G1);
1213
1214 #define AF11 192
1215 SIG_EXPR_LIST_DECL_SESG(AF11, SALT5, SALT5, SIG_DESC_SET(SCU438, 0));
1216 SIG_EXPR_LIST_DECL_SESG(AF11, WDTRST1, WDTRST1, SIG_DESC_SET(SCU4D8, 0));
1217 PIN_DECL_2(AF11, GPIOY0, SALT5, WDTRST1);
1218 FUNC_GROUP_DECL(SALT5, AF11);
1219 FUNC_GROUP_DECL(WDTRST1, AF11);
1220
1221 #define AD12 193
1222 SIG_EXPR_LIST_DECL_SESG(AD12, SALT6, SALT6, SIG_DESC_SET(SCU438, 1));
1223 SIG_EXPR_LIST_DECL_SESG(AD12, WDTRST2, WDTRST2, SIG_DESC_SET(SCU4D8, 1));
1224 PIN_DECL_2(AD12, GPIOY1, SALT6, WDTRST2);
1225 FUNC_GROUP_DECL(SALT6, AD12);
1226 FUNC_GROUP_DECL(WDTRST2, AD12);
1227
1228 #define AE11 194
1229 SIG_EXPR_LIST_DECL_SESG(AE11, SALT7, SALT7, SIG_DESC_SET(SCU438, 2));
1230 SIG_EXPR_LIST_DECL_SESG(AE11, WDTRST3, WDTRST3, SIG_DESC_SET(SCU4D8, 2));
1231 PIN_DECL_2(AE11, GPIOY2, SALT7, WDTRST3);
1232 FUNC_GROUP_DECL(SALT7, AE11);
1233 FUNC_GROUP_DECL(WDTRST3, AE11);
1234
1235 #define AA12 195
1236 SIG_EXPR_LIST_DECL_SESG(AA12, SALT8, SALT8, SIG_DESC_SET(SCU438, 3));
1237 SIG_EXPR_LIST_DECL_SESG(AA12, WDTRST4, WDTRST4, SIG_DESC_SET(SCU4D8, 3));
1238 PIN_DECL_2(AA12, GPIOY3, SALT8, WDTRST4);
1239 FUNC_GROUP_DECL(SALT8, AA12);
1240 FUNC_GROUP_DECL(WDTRST4, AA12);
1241
1242 #define AE12 196
1243 SIG_EXPR_LIST_DECL_SESG(AE12, FWSPIQ2, FWQSPI, SIG_DESC_SET(SCU438, 4));
1244 SIG_EXPR_LIST_DECL_SESG(AE12, GPIOY4, GPIOY4);
1245 PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, FWSPIQ2),
1246 SIG_EXPR_LIST_PTR(AE12, GPIOY4));
1247
1248 #define AF12 197
1249 SIG_EXPR_LIST_DECL_SESG(AF12, FWSPIQ3, FWQSPI, SIG_DESC_SET(SCU438, 5));
1250 SIG_EXPR_LIST_DECL_SESG(AF12, GPIOY5, GPIOY5);
1251 PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, FWSPIQ3),
1252 SIG_EXPR_LIST_PTR(AF12, GPIOY5));
1253 FUNC_GROUP_DECL(FWQSPI, AE12, AF12);
1254
1255 #define AC12 198
1256 SSSF_PIN_DECL(AC12, GPIOY6, FWSPIABR, SIG_DESC_SET(SCU438, 6));
1257
1258 #define AB12 199
1259 SSSF_PIN_DECL(AB12, GPIOY7, FWSPIWP, SIG_DESC_SET(SCU438, 7));
1260
1261 #define AC10 200
1262 SSSF_PIN_DECL(AC10, GPIOZ0, SPI1CS1, SIG_DESC_SET(SCU438, 8));
1263
1264 #define AD10 201
1265 SSSF_PIN_DECL(AD10, GPIOZ1, SPI1ABR, SIG_DESC_SET(SCU438, 9));
1266
1267 #define AE10 202
1268 SSSF_PIN_DECL(AE10, GPIOZ2, SPI1WP, SIG_DESC_SET(SCU438, 10));
1269
1270 #define AB11 203
1271 SIG_EXPR_LIST_DECL_SEMG(AB11, SPI1CK, SPI1, SPI1, SIG_DESC_SET(SCU438, 11));
1272 PIN_DECL_1(AB11, GPIOZ3, SPI1CK);
1273
1274 #define AC11 204
1275 SIG_EXPR_LIST_DECL_SEMG(AC11, SPI1MOSI, SPI1, SPI1, SIG_DESC_SET(SCU438, 12));
1276 PIN_DECL_1(AC11, GPIOZ4, SPI1MOSI);
1277
1278 #define AA11 205
1279 SIG_EXPR_LIST_DECL_SEMG(AA11, SPI1MISO, SPI1, SPI1, SIG_DESC_SET(SCU438, 13));
1280 PIN_DECL_1(AA11, GPIOZ5, SPI1MISO);
1281
1282 GROUP_DECL(SPI1, AB11, AC11, AA11);
1283
1284 #define AD11 206
1285 SIG_EXPR_LIST_DECL_SEMG(AD11, SPI1DQ2, QSPI1, SPI1, SIG_DESC_SET(SCU438, 14));
1286 SIG_EXPR_LIST_DECL_SEMG(AD11, TXD13, UART13G1, UART13,
1287 SIG_DESC_CLEAR(SCU4B8, 2), SIG_DESC_SET(SCU4D8, 14));
1288 PIN_DECL_2(AD11, GPIOZ6, SPI1DQ2, TXD13);
1289
1290 #define AF10 207
1291 SIG_EXPR_LIST_DECL_SEMG(AF10, SPI1DQ3, QSPI1, SPI1, SIG_DESC_SET(SCU438, 15));
1292 SIG_EXPR_LIST_DECL_SEMG(AF10, RXD13, UART13G1, UART13,
1293 SIG_DESC_CLEAR(SCU4B8, 3), SIG_DESC_SET(SCU4D8, 15));
1294 PIN_DECL_2(AF10, GPIOZ7, SPI1DQ3, RXD13);
1295
1296 GROUP_DECL(QSPI1, AB11, AC11, AA11, AD11, AF10);
1297 FUNC_DECL_2(SPI1, SPI1, QSPI1);
1298
1299 GROUP_DECL(UART13G1, AD11, AF10);
1300 FUNC_DECL_2(UART13, UART13G0, UART13G1);
1301
1302 #define C6 208
1303 SIG_EXPR_LIST_DECL_SESG(C6, RGMII1TXCK, RGMII1, SIG_DESC_SET(SCU400, 0),
1304 SIG_DESC_SET(SCU500, 6));
1305 SIG_EXPR_LIST_DECL_SESG(C6, RMII1RCLKO, RMII1, SIG_DESC_SET(SCU400, 0),
1306 SIG_DESC_CLEAR(SCU500, 6));
1307 PIN_DECL_2(C6, GPIO18A0, RGMII1TXCK, RMII1RCLKO);
1308
1309 #define D6 209
1310 SIG_EXPR_LIST_DECL_SESG(D6, RGMII1TXCTL, RGMII1, SIG_DESC_SET(SCU400, 1),
1311 SIG_DESC_SET(SCU500, 6));
1312 SIG_EXPR_LIST_DECL_SESG(D6, RMII1TXEN, RMII1, SIG_DESC_SET(SCU400, 1),
1313 SIG_DESC_CLEAR(SCU500, 6));
1314 PIN_DECL_2(D6, GPIO18A1, RGMII1TXCTL, RMII1TXEN);
1315
1316 #define D5 210
1317 SIG_EXPR_LIST_DECL_SESG(D5, RGMII1TXD0, RGMII1, SIG_DESC_SET(SCU400, 2),
1318 SIG_DESC_SET(SCU500, 6));
1319 SIG_EXPR_LIST_DECL_SESG(D5, RMII1TXD0, RMII1, SIG_DESC_SET(SCU400, 2),
1320 SIG_DESC_CLEAR(SCU500, 6));
1321 PIN_DECL_2(D5, GPIO18A2, RGMII1TXD0, RMII1TXD0);
1322
1323 #define A3 211
1324 SIG_EXPR_LIST_DECL_SESG(A3, RGMII1TXD1, RGMII1, SIG_DESC_SET(SCU400, 3),
1325 SIG_DESC_SET(SCU500, 6));
1326 SIG_EXPR_LIST_DECL_SESG(A3, RMII1TXD1, RMII1, SIG_DESC_SET(SCU400, 3),
1327 SIG_DESC_CLEAR(SCU500, 6));
1328 PIN_DECL_2(A3, GPIO18A3, RGMII1TXD1, RMII1TXD1);
1329
1330 #define C5 212
1331 SIG_EXPR_LIST_DECL_SESG(C5, RGMII1TXD2, RGMII1, SIG_DESC_SET(SCU400, 4),
1332 SIG_DESC_SET(SCU500, 6));
1333 PIN_DECL_1(C5, GPIO18A4, RGMII1TXD2);
1334
1335 #define E6 213
1336 SIG_EXPR_LIST_DECL_SESG(E6, RGMII1TXD3, RGMII1, SIG_DESC_SET(SCU400, 5),
1337 SIG_DESC_SET(SCU500, 6));
1338 PIN_DECL_1(E6, GPIO18A5, RGMII1TXD3);
1339
1340 #define B3 214
1341 SIG_EXPR_LIST_DECL_SESG(B3, RGMII1RXCK, RGMII1, SIG_DESC_SET(SCU400, 6),
1342 SIG_DESC_SET(SCU500, 6));
1343 SIG_EXPR_LIST_DECL_SESG(B3, RMII1RCLKI, RMII1, SIG_DESC_SET(SCU400, 6),
1344 SIG_DESC_CLEAR(SCU500, 6));
1345 PIN_DECL_2(B3, GPIO18A6, RGMII1RXCK, RMII1RCLKI);
1346
1347 #define A2 215
1348 SIG_EXPR_LIST_DECL_SESG(A2, RGMII1RXCTL, RGMII1, SIG_DESC_SET(SCU400, 7),
1349 SIG_DESC_SET(SCU500, 6));
1350 PIN_DECL_1(A2, GPIO18A7, RGMII1RXCTL);
1351
1352 #define B2 216
1353 SIG_EXPR_LIST_DECL_SESG(B2, RGMII1RXD0, RGMII1, SIG_DESC_SET(SCU400, 8),
1354 SIG_DESC_SET(SCU500, 6));
1355 SIG_EXPR_LIST_DECL_SESG(B2, RMII1RXD0, RMII1, SIG_DESC_SET(SCU400, 8),
1356 SIG_DESC_CLEAR(SCU500, 6));
1357 PIN_DECL_2(B2, GPIO18B0, RGMII1RXD0, RMII1RXD0);
1358
1359 #define B1 217
1360 SIG_EXPR_LIST_DECL_SESG(B1, RGMII1RXD1, RGMII1, SIG_DESC_SET(SCU400, 9),
1361 SIG_DESC_SET(SCU500, 6));
1362 SIG_EXPR_LIST_DECL_SESG(B1, RMII1RXD1, RMII1, SIG_DESC_SET(SCU400, 9),
1363 SIG_DESC_CLEAR(SCU500, 6));
1364 PIN_DECL_2(B1, GPIO18B1, RGMII1RXD1, RMII1RXD1);
1365
1366 #define C4 218
1367 SIG_EXPR_LIST_DECL_SESG(C4, RGMII1RXD2, RGMII1, SIG_DESC_SET(SCU400, 10),
1368 SIG_DESC_SET(SCU500, 6));
1369 SIG_EXPR_LIST_DECL_SESG(C4, RMII1CRSDV, RMII1, SIG_DESC_SET(SCU400, 10),
1370 SIG_DESC_CLEAR(SCU500, 6));
1371 PIN_DECL_2(C4, GPIO18B2, RGMII1RXD2, RMII1CRSDV);
1372
1373 #define E5 219
1374 SIG_EXPR_LIST_DECL_SESG(E5, RGMII1RXD3, RGMII1, SIG_DESC_SET(SCU400, 11),
1375 SIG_DESC_SET(SCU500, 6));
1376 SIG_EXPR_LIST_DECL_SESG(E5, RMII1RXER, RMII1, SIG_DESC_SET(SCU400, 11),
1377 SIG_DESC_CLEAR(SCU500, 6));
1378 PIN_DECL_2(E5, GPIO18B3, RGMII1RXD3, RMII1RXER);
1379
1380 FUNC_GROUP_DECL(RGMII1, C6, D6, D5, A3, C5, E6, B3, A2, B2, B1, C4, E5);
1381 FUNC_GROUP_DECL(RMII1, C6, D6, D5, A3, B3, B2, B1, C4, E5);
1382
1383 #define D4 220
1384 SIG_EXPR_LIST_DECL_SESG(D4, RGMII2TXCK, RGMII2, SIG_DESC_SET(SCU400, 12),
1385 SIG_DESC_SET(SCU500, 7));
1386 SIG_EXPR_LIST_DECL_SESG(D4, RMII2RCLKO, RMII2, SIG_DESC_SET(SCU400, 12),
1387 SIG_DESC_CLEAR(SCU500, 7));
1388 PIN_DECL_2(D4, GPIO18B4, RGMII2TXCK, RMII2RCLKO);
1389
1390 #define C2 221
1391 SIG_EXPR_LIST_DECL_SESG(C2, RGMII2TXCTL, RGMII2, SIG_DESC_SET(SCU400, 13),
1392 SIG_DESC_SET(SCU500, 7));
1393 SIG_EXPR_LIST_DECL_SESG(C2, RMII2TXEN, RMII2, SIG_DESC_SET(SCU400, 13),
1394 SIG_DESC_CLEAR(SCU500, 7));
1395 PIN_DECL_2(C2, GPIO18B5, RGMII2TXCTL, RMII2TXEN);
1396
1397 #define C1 222
1398 SIG_EXPR_LIST_DECL_SESG(C1, RGMII2TXD0, RGMII2, SIG_DESC_SET(SCU400, 14),
1399 SIG_DESC_SET(SCU500, 7));
1400 SIG_EXPR_LIST_DECL_SESG(C1, RMII2TXD0, RMII2, SIG_DESC_SET(SCU400, 14),
1401 SIG_DESC_CLEAR(SCU500, 7));
1402 PIN_DECL_2(C1, GPIO18B6, RGMII2TXD0, RMII2TXD0);
1403
1404 #define D3 223
1405 SIG_EXPR_LIST_DECL_SESG(D3, RGMII2TXD1, RGMII2, SIG_DESC_SET(SCU400, 15),
1406 SIG_DESC_SET(SCU500, 7));
1407 SIG_EXPR_LIST_DECL_SESG(D3, RMII2TXD1, RMII2, SIG_DESC_SET(SCU400, 15),
1408 SIG_DESC_CLEAR(SCU500, 7));
1409 PIN_DECL_2(D3, GPIO18B7, RGMII2TXD1, RMII2TXD1);
1410
1411 #define E4 224
1412 SIG_EXPR_LIST_DECL_SESG(E4, RGMII2TXD2, RGMII2, SIG_DESC_SET(SCU400, 16),
1413 SIG_DESC_SET(SCU500, 7));
1414 PIN_DECL_1(E4, GPIO18C0, RGMII2TXD2);
1415
1416 #define F5 225
1417 SIG_EXPR_LIST_DECL_SESG(F5, RGMII2TXD3, RGMII2, SIG_DESC_SET(SCU400, 17),
1418 SIG_DESC_SET(SCU500, 7));
1419 PIN_DECL_1(F5, GPIO18C1, RGMII2TXD3);
1420
1421 #define D2 226
1422 SIG_EXPR_LIST_DECL_SESG(D2, RGMII2RXCK, RGMII2, SIG_DESC_SET(SCU400, 18),
1423 SIG_DESC_SET(SCU500, 7));
1424 SIG_EXPR_LIST_DECL_SESG(D2, RMII2RCLKI, RMII2, SIG_DESC_SET(SCU400, 18),
1425 SIG_DESC_CLEAR(SCU500, 7));
1426 PIN_DECL_2(D2, GPIO18C2, RGMII2RXCK, RMII2RCLKI);
1427
1428 #define E3 227
1429 SIG_EXPR_LIST_DECL_SESG(E3, RGMII2RXCTL, RGMII2, SIG_DESC_SET(SCU400, 19),
1430 SIG_DESC_SET(SCU500, 7));
1431 PIN_DECL_1(E3, GPIO18C3, RGMII2RXCTL);
1432
1433 #define D1 228
1434 SIG_EXPR_LIST_DECL_SESG(D1, RGMII2RXD0, RGMII2, SIG_DESC_SET(SCU400, 20),
1435 SIG_DESC_SET(SCU500, 7));
1436 SIG_EXPR_LIST_DECL_SESG(D1, RMII2RXD0, RMII2, SIG_DESC_SET(SCU400, 20),
1437 SIG_DESC_CLEAR(SCU500, 7));
1438 PIN_DECL_2(D1, GPIO18C4, RGMII2RXD0, RMII2RXD0);
1439
1440 #define F4 229
1441 SIG_EXPR_LIST_DECL_SESG(F4, RGMII2RXD1, RGMII2, SIG_DESC_SET(SCU400, 21),
1442 SIG_DESC_SET(SCU500, 7));
1443 SIG_EXPR_LIST_DECL_SESG(F4, RMII2RXD1, RMII2, SIG_DESC_SET(SCU400, 21),
1444 SIG_DESC_CLEAR(SCU500, 7));
1445 PIN_DECL_2(F4, GPIO18C5, RGMII2RXD1, RMII2RXD1);
1446
1447 #define E2 230
1448 SIG_EXPR_LIST_DECL_SESG(E2, RGMII2RXD2, RGMII2, SIG_DESC_SET(SCU400, 22),
1449 SIG_DESC_SET(SCU500, 7));
1450 SIG_EXPR_LIST_DECL_SESG(E2, RMII2CRSDV, RMII2, SIG_DESC_SET(SCU400, 22),
1451 SIG_DESC_CLEAR(SCU500, 7));
1452 PIN_DECL_2(E2, GPIO18C6, RGMII2RXD2, RMII2CRSDV);
1453
1454 #define E1 231
1455 SIG_EXPR_LIST_DECL_SESG(E1, RGMII2RXD3, RGMII2, SIG_DESC_SET(SCU400, 23),
1456 SIG_DESC_SET(SCU500, 7));
1457 SIG_EXPR_LIST_DECL_SESG(E1, RMII2RXER, RMII2, SIG_DESC_SET(SCU400, 23),
1458 SIG_DESC_CLEAR(SCU500, 7));
1459 PIN_DECL_2(E1, GPIO18C7, RGMII2RXD3, RMII2RXER);
1460
1461 FUNC_GROUP_DECL(RGMII2, D4, C2, C1, D3, E4, F5, D2, E3, D1, F4, E2, E1);
1462 FUNC_GROUP_DECL(RMII2, D4, C2, C1, D3, D2, D1, F4, E2, E1);
1463
1464 #define AB4 232
1465 SIG_EXPR_LIST_DECL_SEMG(AB4, EMMCCLK, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 24));
1466 PIN_DECL_1(AB4, GPIO18D0, EMMCCLK);
1467
1468 #define AA4 233
1469 SIG_EXPR_LIST_DECL_SEMG(AA4, EMMCCMD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 25));
1470 PIN_DECL_1(AA4, GPIO18D1, EMMCCMD);
1471
1472 #define AC4 234
1473 SIG_EXPR_LIST_DECL_SEMG(AC4, EMMCDAT0, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 26));
1474 PIN_DECL_1(AC4, GPIO18D2, EMMCDAT0);
1475
1476 #define AA5 235
1477 SIG_EXPR_LIST_DECL_SEMG(AA5, EMMCDAT1, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 27));
1478 PIN_DECL_1(AA5, GPIO18D3, EMMCDAT1);
1479
1480 #define Y5 236
1481 SIG_EXPR_LIST_DECL_SEMG(Y5, EMMCDAT2, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 28));
1482 PIN_DECL_1(Y5, GPIO18D4, EMMCDAT2);
1483
1484 #define AB5 237
1485 SIG_EXPR_LIST_DECL_SEMG(AB5, EMMCDAT3, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 29));
1486 PIN_DECL_1(AB5, GPIO18D5, EMMCDAT3);
1487
1488 #define AB6 238
1489 SIG_EXPR_LIST_DECL_SEMG(AB6, EMMCCD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 30));
1490 PIN_DECL_1(AB6, GPIO18D6, EMMCCD);
1491
1492 #define AC5 239
1493 SIG_EXPR_LIST_DECL_SEMG(AC5, EMMCWP, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 31));
1494 PIN_DECL_1(AC5, GPIO18D7, EMMCWP);
1495
1496 GROUP_DECL(EMMCG1, AB4, AA4, AC4, AB6, AC5);
1497 GROUP_DECL(EMMCG4, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5);
1498
1499 #define Y1 240
1500 SIG_EXPR_LIST_DECL_SEMG(Y1, FWSPIDCS, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3));
1501 SIG_EXPR_LIST_DECL_SESG(Y1, VBCS, VB, SIG_DESC_SET(SCU500, 5));
1502 SIG_EXPR_LIST_DECL_SEMG(Y1, EMMCDAT4, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 0));
1503 PIN_DECL_3(Y1, GPIO18E0, FWSPIDCS, VBCS, EMMCDAT4);
1504
1505 #define Y2 241
1506 SIG_EXPR_LIST_DECL_SEMG(Y2, FWSPIDCK, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3));
1507 SIG_EXPR_LIST_DECL_SESG(Y2, VBCK, VB, SIG_DESC_SET(SCU500, 5));
1508 SIG_EXPR_LIST_DECL_SEMG(Y2, EMMCDAT5, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 1));
1509 PIN_DECL_3(Y2, GPIO18E1, FWSPIDCK, VBCK, EMMCDAT5);
1510
1511 #define Y3 242
1512 SIG_EXPR_LIST_DECL_SEMG(Y3, FWSPIDMOSI, FWSPID, FWSPID,
1513 SIG_DESC_SET(SCU500, 3));
1514 SIG_EXPR_LIST_DECL_SESG(Y3, VBMOSI, VB, SIG_DESC_SET(SCU500, 5));
1515 SIG_EXPR_LIST_DECL_SEMG(Y3, EMMCDAT6, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 2));
1516 PIN_DECL_3(Y3, GPIO18E2, FWSPIDMOSI, VBMOSI, EMMCDAT6);
1517
1518 #define Y4 243
1519 SIG_EXPR_LIST_DECL_SEMG(Y4, FWSPIDMISO, FWSPID, FWSPID,
1520 SIG_DESC_SET(SCU500, 3));
1521 SIG_EXPR_LIST_DECL_SESG(Y4, VBMISO, VB, SIG_DESC_SET(SCU500, 5));
1522 SIG_EXPR_LIST_DECL_SEMG(Y4, EMMCDAT7, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 3));
1523 PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, EMMCDAT7);
1524
1525 GROUP_DECL(FWSPID, Y1, Y2, Y3, Y4);
1526 GROUP_DECL(EMMCG8, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5, Y1, Y2, Y3, Y4);
1527 FUNC_DECL_1(FWSPID, FWSPID);
1528 FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4);
1529 FUNC_DECL_3(EMMC, EMMCG1, EMMCG4, EMMCG8);
1530 /*
1531 * FIXME: Confirm bits and priorities are the right way around for the
1532 * following 4 pins
1533 */
1534 #define AF25 244
1535 SIG_EXPR_LIST_DECL_SEMG(AF25, I3C3SCL, I3C3, I3C3, SIG_DESC_SET(SCU438, 20));
1536 SIG_EXPR_LIST_DECL_SESG(AF25, FSI1CLK, FSI1, SIG_DESC_SET(SCU4D8, 20));
1537 PIN_DECL_(AF25, SIG_EXPR_LIST_PTR(AF25, I3C3SCL),
1538 SIG_EXPR_LIST_PTR(AF25, FSI1CLK));
1539
1540 #define AE26 245
1541 SIG_EXPR_LIST_DECL_SEMG(AE26, I3C3SDA, I3C3, I3C3, SIG_DESC_SET(SCU438, 21));
1542 SIG_EXPR_LIST_DECL_SESG(AE26, FSI1DATA, FSI1, SIG_DESC_SET(SCU4D8, 21));
1543 PIN_DECL_(AE26, SIG_EXPR_LIST_PTR(AE26, I3C3SDA),
1544 SIG_EXPR_LIST_PTR(AE26, FSI1DATA));
1545
1546 GROUP_DECL(I3C3, AF25, AE26);
1547 FUNC_DECL_2(I3C3, HVI3C3, I3C3);
1548 FUNC_GROUP_DECL(FSI1, AF25, AE26);
1549
1550 #define AE25 246
1551 SIG_EXPR_LIST_DECL_SEMG(AE25, I3C4SCL, I3C4, I3C4, SIG_DESC_SET(SCU438, 22));
1552 SIG_EXPR_LIST_DECL_SESG(AE25, FSI2CLK, FSI2, SIG_DESC_SET(SCU4D8, 22));
1553 PIN_DECL_(AE25, SIG_EXPR_LIST_PTR(AE25, I3C4SCL),
1554 SIG_EXPR_LIST_PTR(AE25, FSI2CLK));
1555
1556 #define AF24 247
1557 SIG_EXPR_LIST_DECL_SEMG(AF24, I3C4SDA, I3C4, I3C4, SIG_DESC_SET(SCU438, 23));
1558 SIG_EXPR_LIST_DECL_SESG(AF24, FSI2DATA, FSI2, SIG_DESC_SET(SCU4D8, 23));
1559 PIN_DECL_(AF24, SIG_EXPR_LIST_PTR(AF24, I3C4SDA),
1560 SIG_EXPR_LIST_PTR(AF24, FSI2DATA));
1561
1562 GROUP_DECL(I3C4, AE25, AF24);
1563 FUNC_DECL_2(I3C4, HVI3C4, I3C4);
1564 FUNC_GROUP_DECL(FSI2, AE25, AF24);
1565
1566 #define AF23 248
1567 SIG_EXPR_LIST_DECL_SESG(AF23, I3C1SCL, I3C1, SIG_DESC_SET(SCU438, 16));
1568 PIN_DECL_(AF23, SIG_EXPR_LIST_PTR(AF23, I3C1SCL));
1569
1570 #define AE24 249
1571 SIG_EXPR_LIST_DECL_SESG(AE24, I3C1SDA, I3C1, SIG_DESC_SET(SCU438, 17));
1572 PIN_DECL_(AE24, SIG_EXPR_LIST_PTR(AE24, I3C1SDA));
1573
1574 FUNC_GROUP_DECL(I3C1, AF23, AE24);
1575
1576 #define AF22 250
1577 SIG_EXPR_LIST_DECL_SESG(AF22, I3C2SCL, I3C2, SIG_DESC_SET(SCU438, 18));
1578 PIN_DECL_(AF22, SIG_EXPR_LIST_PTR(AF22, I3C2SCL));
1579
1580 #define AE22 251
1581 SIG_EXPR_LIST_DECL_SESG(AE22, I3C2SDA, I3C2, SIG_DESC_SET(SCU438, 19));
1582 PIN_DECL_(AE22, SIG_EXPR_LIST_PTR(AE22, I3C2SDA));
1583
1584 FUNC_GROUP_DECL(I3C2, AF22, AE22);
1585
1586 #define USB2ADP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 0, 0 }
1587 #define USB2AD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 1, 0 }
1588 #define USB2AH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 2, 0 }
1589 #define USB2AHP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 3, 0 }
1590 #define USB11BHID_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 0, 0 }
1591 #define USB2BD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 1, 0 }
1592 #define USB2BH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 2, 0 }
1593
1594 #define A4 252
1595 SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADPDP, USBA, USB2ADP, USB2ADP_DESC,
1596 SIG_DESC_SET(SCUC20, 16));
1597 SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADDP, USBA, USB2AD, USB2AD_DESC);
1598 SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHDP, USBA, USB2AH, USB2AH_DESC);
1599 SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHPDP, USBA, USB2AHP, USB2AHP_DESC,
1600 SIG_DESC_SET(SCUC20, 16));
1601 PIN_DECL_(A4, SIG_EXPR_LIST_PTR(A4, USB2ADPDP), SIG_EXPR_LIST_PTR(A4, USB2ADDP),
1602 SIG_EXPR_LIST_PTR(A4, USB2AHDP), SIG_EXPR_LIST_PTR(A4, USB2AHPDP));
1603
1604 #define B4 253
1605 SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADPDN, USBA, USB2ADP, USB2ADP_DESC);
1606 SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADDN, USBA, USB2AD, USB2AD_DESC);
1607 SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHDN, USBA, USB2AH, USB2AH_DESC);
1608 SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHPDN, USBA, USB2AHP, USB2AHP_DESC);
1609 PIN_DECL_(B4, SIG_EXPR_LIST_PTR(B4, USB2ADPDN), SIG_EXPR_LIST_PTR(B4, USB2ADDN),
1610 SIG_EXPR_LIST_PTR(B4, USB2AHDN), SIG_EXPR_LIST_PTR(B4, USB2AHPDN));
1611
1612 GROUP_DECL(USBA, A4, B4);
1613
1614 FUNC_DECL_1(USB2ADP, USBA);
1615 FUNC_DECL_1(USB2AD, USBA);
1616 FUNC_DECL_1(USB2AH, USBA);
1617 FUNC_DECL_1(USB2AHP, USBA);
1618
1619 #define A6 254
1620 SIG_EXPR_LIST_DECL_SEMG(A6, USB11BDP, USBB, USB11BHID, USB11BHID_DESC);
1621 SIG_EXPR_LIST_DECL_SEMG(A6, USB2BDDP, USBB, USB2BD, USB2BD_DESC);
1622 SIG_EXPR_LIST_DECL_SEMG(A6, USB2BHDP, USBB, USB2BH, USB2BH_DESC);
1623 PIN_DECL_(A6, SIG_EXPR_LIST_PTR(A6, USB11BDP), SIG_EXPR_LIST_PTR(A6, USB2BDDP),
1624 SIG_EXPR_LIST_PTR(A6, USB2BHDP));
1625
1626 #define B6 255
1627 SIG_EXPR_LIST_DECL_SEMG(B6, USB11BDN, USBB, USB11BHID, USB11BHID_DESC);
1628 SIG_EXPR_LIST_DECL_SEMG(B6, USB2BDDN, USBB, USB2BD, USB2BD_DESC);
1629 SIG_EXPR_LIST_DECL_SEMG(B6, USB2BHDN, USBB, USB2BH, USB2BH_DESC);
1630 PIN_DECL_(B6, SIG_EXPR_LIST_PTR(B6, USB11BDN), SIG_EXPR_LIST_PTR(B6, USB2BDDN),
1631 SIG_EXPR_LIST_PTR(B6, USB2BHDN));
1632
1633 GROUP_DECL(USBB, A6, B6);
1634
1635 FUNC_DECL_1(USB11BHID, USBB);
1636 FUNC_DECL_1(USB2BD, USBB);
1637 FUNC_DECL_1(USB2BH, USBB);
1638
1639 /* Pins, groups and functions are sort(1):ed alphabetically for sanity */
1640
1641 static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
1642 ASPEED_PINCTRL_PIN(A11),
1643 ASPEED_PINCTRL_PIN(A12),
1644 ASPEED_PINCTRL_PIN(A13),
1645 ASPEED_PINCTRL_PIN(A14),
1646 ASPEED_PINCTRL_PIN(A15),
1647 ASPEED_PINCTRL_PIN(A16),
1648 ASPEED_PINCTRL_PIN(A17),
1649 ASPEED_PINCTRL_PIN(A18),
1650 ASPEED_PINCTRL_PIN(A19),
1651 ASPEED_PINCTRL_PIN(A2),
1652 ASPEED_PINCTRL_PIN(A20),
1653 ASPEED_PINCTRL_PIN(A21),
1654 ASPEED_PINCTRL_PIN(A22),
1655 ASPEED_PINCTRL_PIN(A23),
1656 ASPEED_PINCTRL_PIN(A24),
1657 ASPEED_PINCTRL_PIN(A25),
1658 ASPEED_PINCTRL_PIN(A3),
1659 ASPEED_PINCTRL_PIN(A4),
1660 ASPEED_PINCTRL_PIN(A6),
1661 ASPEED_PINCTRL_PIN(AA11),
1662 ASPEED_PINCTRL_PIN(AA12),
1663 ASPEED_PINCTRL_PIN(AA16),
1664 ASPEED_PINCTRL_PIN(AA17),
1665 ASPEED_PINCTRL_PIN(AA23),
1666 ASPEED_PINCTRL_PIN(AA24),
1667 ASPEED_PINCTRL_PIN(AA25),
1668 ASPEED_PINCTRL_PIN(AA26),
1669 ASPEED_PINCTRL_PIN(AA4),
1670 ASPEED_PINCTRL_PIN(AA5),
1671 ASPEED_PINCTRL_PIN(AA9),
1672 ASPEED_PINCTRL_PIN(AB10),
1673 ASPEED_PINCTRL_PIN(AB11),
1674 ASPEED_PINCTRL_PIN(AB12),
1675 ASPEED_PINCTRL_PIN(AB15),
1676 ASPEED_PINCTRL_PIN(AB16),
1677 ASPEED_PINCTRL_PIN(AB17),
1678 ASPEED_PINCTRL_PIN(AB18),
1679 ASPEED_PINCTRL_PIN(AB19),
1680 ASPEED_PINCTRL_PIN(AB22),
1681 ASPEED_PINCTRL_PIN(AB23),
1682 ASPEED_PINCTRL_PIN(AB24),
1683 ASPEED_PINCTRL_PIN(AB25),
1684 ASPEED_PINCTRL_PIN(AB26),
1685 ASPEED_PINCTRL_PIN(AB4),
1686 ASPEED_PINCTRL_PIN(AB5),
1687 ASPEED_PINCTRL_PIN(AB6),
1688 ASPEED_PINCTRL_PIN(AB7),
1689 ASPEED_PINCTRL_PIN(AB8),
1690 ASPEED_PINCTRL_PIN(AB9),
1691 ASPEED_PINCTRL_PIN(AC10),
1692 ASPEED_PINCTRL_PIN(AC11),
1693 ASPEED_PINCTRL_PIN(AC12),
1694 ASPEED_PINCTRL_PIN(AC15),
1695 ASPEED_PINCTRL_PIN(AC16),
1696 ASPEED_PINCTRL_PIN(AC17),
1697 ASPEED_PINCTRL_PIN(AC18),
1698 ASPEED_PINCTRL_PIN(AC19),
1699 ASPEED_PINCTRL_PIN(AC22),
1700 ASPEED_PINCTRL_PIN(AC23),
1701 ASPEED_PINCTRL_PIN(AC24),
1702 ASPEED_PINCTRL_PIN(AC26),
1703 ASPEED_PINCTRL_PIN(AC4),
1704 ASPEED_PINCTRL_PIN(AC5),
1705 ASPEED_PINCTRL_PIN(AC7),
1706 ASPEED_PINCTRL_PIN(AC8),
1707 ASPEED_PINCTRL_PIN(AC9),
1708 ASPEED_PINCTRL_PIN(AD10),
1709 ASPEED_PINCTRL_PIN(AD11),
1710 ASPEED_PINCTRL_PIN(AD12),
1711 ASPEED_PINCTRL_PIN(AD14),
1712 ASPEED_PINCTRL_PIN(AD15),
1713 ASPEED_PINCTRL_PIN(AD16),
1714 ASPEED_PINCTRL_PIN(AD19),
1715 ASPEED_PINCTRL_PIN(AD20),
1716 ASPEED_PINCTRL_PIN(AD22),
1717 ASPEED_PINCTRL_PIN(AD23),
1718 ASPEED_PINCTRL_PIN(AD24),
1719 ASPEED_PINCTRL_PIN(AD25),
1720 ASPEED_PINCTRL_PIN(AD26),
1721 ASPEED_PINCTRL_PIN(AD7),
1722 ASPEED_PINCTRL_PIN(AD8),
1723 ASPEED_PINCTRL_PIN(AD9),
1724 ASPEED_PINCTRL_PIN(AE10),
1725 ASPEED_PINCTRL_PIN(AE11),
1726 ASPEED_PINCTRL_PIN(AE12),
1727 ASPEED_PINCTRL_PIN(AE14),
1728 ASPEED_PINCTRL_PIN(AE15),
1729 ASPEED_PINCTRL_PIN(AE16),
1730 ASPEED_PINCTRL_PIN(AE18),
1731 ASPEED_PINCTRL_PIN(AE19),
1732 ASPEED_PINCTRL_PIN(AE22),
1733 ASPEED_PINCTRL_PIN(AE24),
1734 ASPEED_PINCTRL_PIN(AE25),
1735 ASPEED_PINCTRL_PIN(AE26),
1736 ASPEED_PINCTRL_PIN(AE7),
1737 ASPEED_PINCTRL_PIN(AE8),
1738 ASPEED_PINCTRL_PIN(AF10),
1739 ASPEED_PINCTRL_PIN(AF11),
1740 ASPEED_PINCTRL_PIN(AF12),
1741 ASPEED_PINCTRL_PIN(AF14),
1742 ASPEED_PINCTRL_PIN(AF15),
1743 ASPEED_PINCTRL_PIN(AF22),
1744 ASPEED_PINCTRL_PIN(AF23),
1745 ASPEED_PINCTRL_PIN(AF24),
1746 ASPEED_PINCTRL_PIN(AF25),
1747 ASPEED_PINCTRL_PIN(AF7),
1748 ASPEED_PINCTRL_PIN(AF8),
1749 ASPEED_PINCTRL_PIN(AF9),
1750 ASPEED_PINCTRL_PIN(B1),
1751 ASPEED_PINCTRL_PIN(B12),
1752 ASPEED_PINCTRL_PIN(B13),
1753 ASPEED_PINCTRL_PIN(B14),
1754 ASPEED_PINCTRL_PIN(B16),
1755 ASPEED_PINCTRL_PIN(B17),
1756 ASPEED_PINCTRL_PIN(B18),
1757 ASPEED_PINCTRL_PIN(B2),
1758 ASPEED_PINCTRL_PIN(B20),
1759 ASPEED_PINCTRL_PIN(B21),
1760 ASPEED_PINCTRL_PIN(B22),
1761 ASPEED_PINCTRL_PIN(B24),
1762 ASPEED_PINCTRL_PIN(B25),
1763 ASPEED_PINCTRL_PIN(B26),
1764 ASPEED_PINCTRL_PIN(B3),
1765 ASPEED_PINCTRL_PIN(B4),
1766 ASPEED_PINCTRL_PIN(B6),
1767 ASPEED_PINCTRL_PIN(C1),
1768 ASPEED_PINCTRL_PIN(C11),
1769 ASPEED_PINCTRL_PIN(C12),
1770 ASPEED_PINCTRL_PIN(C13),
1771 ASPEED_PINCTRL_PIN(C14),
1772 ASPEED_PINCTRL_PIN(C15),
1773 ASPEED_PINCTRL_PIN(C16),
1774 ASPEED_PINCTRL_PIN(C17),
1775 ASPEED_PINCTRL_PIN(C18),
1776 ASPEED_PINCTRL_PIN(C19),
1777 ASPEED_PINCTRL_PIN(C2),
1778 ASPEED_PINCTRL_PIN(C20),
1779 ASPEED_PINCTRL_PIN(C21),
1780 ASPEED_PINCTRL_PIN(C22),
1781 ASPEED_PINCTRL_PIN(C23),
1782 ASPEED_PINCTRL_PIN(C24),
1783 ASPEED_PINCTRL_PIN(C25),
1784 ASPEED_PINCTRL_PIN(C26),
1785 ASPEED_PINCTRL_PIN(C4),
1786 ASPEED_PINCTRL_PIN(C5),
1787 ASPEED_PINCTRL_PIN(C6),
1788 ASPEED_PINCTRL_PIN(D1),
1789 ASPEED_PINCTRL_PIN(D11),
1790 ASPEED_PINCTRL_PIN(D12),
1791 ASPEED_PINCTRL_PIN(D13),
1792 ASPEED_PINCTRL_PIN(D14),
1793 ASPEED_PINCTRL_PIN(D15),
1794 ASPEED_PINCTRL_PIN(D16),
1795 ASPEED_PINCTRL_PIN(D17),
1796 ASPEED_PINCTRL_PIN(D18),
1797 ASPEED_PINCTRL_PIN(D19),
1798 ASPEED_PINCTRL_PIN(D2),
1799 ASPEED_PINCTRL_PIN(D20),
1800 ASPEED_PINCTRL_PIN(D21),
1801 ASPEED_PINCTRL_PIN(D22),
1802 ASPEED_PINCTRL_PIN(D23),
1803 ASPEED_PINCTRL_PIN(D24),
1804 ASPEED_PINCTRL_PIN(D26),
1805 ASPEED_PINCTRL_PIN(D3),
1806 ASPEED_PINCTRL_PIN(D4),
1807 ASPEED_PINCTRL_PIN(D5),
1808 ASPEED_PINCTRL_PIN(D6),
1809 ASPEED_PINCTRL_PIN(E1),
1810 ASPEED_PINCTRL_PIN(E11),
1811 ASPEED_PINCTRL_PIN(E12),
1812 ASPEED_PINCTRL_PIN(E13),
1813 ASPEED_PINCTRL_PIN(E14),
1814 ASPEED_PINCTRL_PIN(E15),
1815 ASPEED_PINCTRL_PIN(E16),
1816 ASPEED_PINCTRL_PIN(E17),
1817 ASPEED_PINCTRL_PIN(E18),
1818 ASPEED_PINCTRL_PIN(E19),
1819 ASPEED_PINCTRL_PIN(E2),
1820 ASPEED_PINCTRL_PIN(E20),
1821 ASPEED_PINCTRL_PIN(E21),
1822 ASPEED_PINCTRL_PIN(E22),
1823 ASPEED_PINCTRL_PIN(E23),
1824 ASPEED_PINCTRL_PIN(E24),
1825 ASPEED_PINCTRL_PIN(E25),
1826 ASPEED_PINCTRL_PIN(E26),
1827 ASPEED_PINCTRL_PIN(E3),
1828 ASPEED_PINCTRL_PIN(E4),
1829 ASPEED_PINCTRL_PIN(E5),
1830 ASPEED_PINCTRL_PIN(E6),
1831 ASPEED_PINCTRL_PIN(F13),
1832 ASPEED_PINCTRL_PIN(F15),
1833 ASPEED_PINCTRL_PIN(F22),
1834 ASPEED_PINCTRL_PIN(F23),
1835 ASPEED_PINCTRL_PIN(F24),
1836 ASPEED_PINCTRL_PIN(F25),
1837 ASPEED_PINCTRL_PIN(F26),
1838 ASPEED_PINCTRL_PIN(F4),
1839 ASPEED_PINCTRL_PIN(F5),
1840 ASPEED_PINCTRL_PIN(G22),
1841 ASPEED_PINCTRL_PIN(G23),
1842 ASPEED_PINCTRL_PIN(G24),
1843 ASPEED_PINCTRL_PIN(G26),
1844 ASPEED_PINCTRL_PIN(H22),
1845 ASPEED_PINCTRL_PIN(H23),
1846 ASPEED_PINCTRL_PIN(H24),
1847 ASPEED_PINCTRL_PIN(H25),
1848 ASPEED_PINCTRL_PIN(H26),
1849 ASPEED_PINCTRL_PIN(J22),
1850 ASPEED_PINCTRL_PIN(J23),
1851 ASPEED_PINCTRL_PIN(J24),
1852 ASPEED_PINCTRL_PIN(J25),
1853 ASPEED_PINCTRL_PIN(J26),
1854 ASPEED_PINCTRL_PIN(K23),
1855 ASPEED_PINCTRL_PIN(K24),
1856 ASPEED_PINCTRL_PIN(K25),
1857 ASPEED_PINCTRL_PIN(K26),
1858 ASPEED_PINCTRL_PIN(L23),
1859 ASPEED_PINCTRL_PIN(L24),
1860 ASPEED_PINCTRL_PIN(L26),
1861 ASPEED_PINCTRL_PIN(M23),
1862 ASPEED_PINCTRL_PIN(M24),
1863 ASPEED_PINCTRL_PIN(M25),
1864 ASPEED_PINCTRL_PIN(M26),
1865 ASPEED_PINCTRL_PIN(N23),
1866 ASPEED_PINCTRL_PIN(N24),
1867 ASPEED_PINCTRL_PIN(N25),
1868 ASPEED_PINCTRL_PIN(N26),
1869 ASPEED_PINCTRL_PIN(P23),
1870 ASPEED_PINCTRL_PIN(P24),
1871 ASPEED_PINCTRL_PIN(P25),
1872 ASPEED_PINCTRL_PIN(P26),
1873 ASPEED_PINCTRL_PIN(R23),
1874 ASPEED_PINCTRL_PIN(R24),
1875 ASPEED_PINCTRL_PIN(R26),
1876 ASPEED_PINCTRL_PIN(T23),
1877 ASPEED_PINCTRL_PIN(T24),
1878 ASPEED_PINCTRL_PIN(T25),
1879 ASPEED_PINCTRL_PIN(T26),
1880 ASPEED_PINCTRL_PIN(U24),
1881 ASPEED_PINCTRL_PIN(U25),
1882 ASPEED_PINCTRL_PIN(U26),
1883 ASPEED_PINCTRL_PIN(V24),
1884 ASPEED_PINCTRL_PIN(V25),
1885 ASPEED_PINCTRL_PIN(V26),
1886 ASPEED_PINCTRL_PIN(W23),
1887 ASPEED_PINCTRL_PIN(W24),
1888 ASPEED_PINCTRL_PIN(W26),
1889 ASPEED_PINCTRL_PIN(Y1),
1890 ASPEED_PINCTRL_PIN(Y2),
1891 ASPEED_PINCTRL_PIN(Y23),
1892 ASPEED_PINCTRL_PIN(Y24),
1893 ASPEED_PINCTRL_PIN(Y25),
1894 ASPEED_PINCTRL_PIN(Y26),
1895 ASPEED_PINCTRL_PIN(Y3),
1896 ASPEED_PINCTRL_PIN(Y4),
1897 ASPEED_PINCTRL_PIN(Y5),
1898 };
1899
1900 static const struct aspeed_pin_group aspeed_g6_groups[] = {
1901 ASPEED_PINCTRL_GROUP(ADC0),
1902 ASPEED_PINCTRL_GROUP(ADC1),
1903 ASPEED_PINCTRL_GROUP(ADC10),
1904 ASPEED_PINCTRL_GROUP(ADC11),
1905 ASPEED_PINCTRL_GROUP(ADC12),
1906 ASPEED_PINCTRL_GROUP(ADC13),
1907 ASPEED_PINCTRL_GROUP(ADC14),
1908 ASPEED_PINCTRL_GROUP(ADC15),
1909 ASPEED_PINCTRL_GROUP(ADC2),
1910 ASPEED_PINCTRL_GROUP(ADC3),
1911 ASPEED_PINCTRL_GROUP(ADC4),
1912 ASPEED_PINCTRL_GROUP(ADC5),
1913 ASPEED_PINCTRL_GROUP(ADC6),
1914 ASPEED_PINCTRL_GROUP(ADC7),
1915 ASPEED_PINCTRL_GROUP(ADC8),
1916 ASPEED_PINCTRL_GROUP(ADC9),
1917 ASPEED_PINCTRL_GROUP(BMCINT),
1918 ASPEED_PINCTRL_GROUP(ESPI),
1919 ASPEED_PINCTRL_GROUP(ESPIALT),
1920 ASPEED_PINCTRL_GROUP(FSI1),
1921 ASPEED_PINCTRL_GROUP(FSI2),
1922 ASPEED_PINCTRL_GROUP(FWSPIABR),
1923 ASPEED_PINCTRL_GROUP(FWSPID),
1924 ASPEED_PINCTRL_GROUP(FWQSPI),
1925 ASPEED_PINCTRL_GROUP(FWSPIWP),
1926 ASPEED_PINCTRL_GROUP(GPIT0),
1927 ASPEED_PINCTRL_GROUP(GPIT1),
1928 ASPEED_PINCTRL_GROUP(GPIT2),
1929 ASPEED_PINCTRL_GROUP(GPIT3),
1930 ASPEED_PINCTRL_GROUP(GPIT4),
1931 ASPEED_PINCTRL_GROUP(GPIT5),
1932 ASPEED_PINCTRL_GROUP(GPIT6),
1933 ASPEED_PINCTRL_GROUP(GPIT7),
1934 ASPEED_PINCTRL_GROUP(GPIU0),
1935 ASPEED_PINCTRL_GROUP(GPIU1),
1936 ASPEED_PINCTRL_GROUP(GPIU2),
1937 ASPEED_PINCTRL_GROUP(GPIU3),
1938 ASPEED_PINCTRL_GROUP(GPIU4),
1939 ASPEED_PINCTRL_GROUP(GPIU5),
1940 ASPEED_PINCTRL_GROUP(GPIU6),
1941 ASPEED_PINCTRL_GROUP(GPIU7),
1942 ASPEED_PINCTRL_GROUP(HEARTBEAT),
1943 ASPEED_PINCTRL_GROUP(HVI3C3),
1944 ASPEED_PINCTRL_GROUP(HVI3C4),
1945 ASPEED_PINCTRL_GROUP(I2C1),
1946 ASPEED_PINCTRL_GROUP(I2C10),
1947 ASPEED_PINCTRL_GROUP(I2C11),
1948 ASPEED_PINCTRL_GROUP(I2C12),
1949 ASPEED_PINCTRL_GROUP(I2C13),
1950 ASPEED_PINCTRL_GROUP(I2C14),
1951 ASPEED_PINCTRL_GROUP(I2C15),
1952 ASPEED_PINCTRL_GROUP(I2C16),
1953 ASPEED_PINCTRL_GROUP(I2C2),
1954 ASPEED_PINCTRL_GROUP(I2C3),
1955 ASPEED_PINCTRL_GROUP(I2C4),
1956 ASPEED_PINCTRL_GROUP(I2C5),
1957 ASPEED_PINCTRL_GROUP(I2C6),
1958 ASPEED_PINCTRL_GROUP(I2C7),
1959 ASPEED_PINCTRL_GROUP(I2C8),
1960 ASPEED_PINCTRL_GROUP(I2C9),
1961 ASPEED_PINCTRL_GROUP(I3C1),
1962 ASPEED_PINCTRL_GROUP(I3C2),
1963 ASPEED_PINCTRL_GROUP(I3C3),
1964 ASPEED_PINCTRL_GROUP(I3C4),
1965 ASPEED_PINCTRL_GROUP(I3C5),
1966 ASPEED_PINCTRL_GROUP(I3C6),
1967 ASPEED_PINCTRL_GROUP(JTAGM),
1968 ASPEED_PINCTRL_GROUP(LHPD),
1969 ASPEED_PINCTRL_GROUP(LHSIRQ),
1970 ASPEED_PINCTRL_GROUP(LPC),
1971 ASPEED_PINCTRL_GROUP(LPCHC),
1972 ASPEED_PINCTRL_GROUP(LPCPD),
1973 ASPEED_PINCTRL_GROUP(LPCPME),
1974 ASPEED_PINCTRL_GROUP(LPCSMI),
1975 ASPEED_PINCTRL_GROUP(LSIRQ),
1976 ASPEED_PINCTRL_GROUP(MACLINK1),
1977 ASPEED_PINCTRL_GROUP(MACLINK2),
1978 ASPEED_PINCTRL_GROUP(MACLINK3),
1979 ASPEED_PINCTRL_GROUP(MACLINK4),
1980 ASPEED_PINCTRL_GROUP(MDIO1),
1981 ASPEED_PINCTRL_GROUP(MDIO2),
1982 ASPEED_PINCTRL_GROUP(MDIO3),
1983 ASPEED_PINCTRL_GROUP(MDIO4),
1984 ASPEED_PINCTRL_GROUP(NCSI3),
1985 ASPEED_PINCTRL_GROUP(NCSI4),
1986 ASPEED_PINCTRL_GROUP(NCTS1),
1987 ASPEED_PINCTRL_GROUP(NCTS2),
1988 ASPEED_PINCTRL_GROUP(NCTS3),
1989 ASPEED_PINCTRL_GROUP(NCTS4),
1990 ASPEED_PINCTRL_GROUP(NDCD1),
1991 ASPEED_PINCTRL_GROUP(NDCD2),
1992 ASPEED_PINCTRL_GROUP(NDCD3),
1993 ASPEED_PINCTRL_GROUP(NDCD4),
1994 ASPEED_PINCTRL_GROUP(NDSR1),
1995 ASPEED_PINCTRL_GROUP(NDSR2),
1996 ASPEED_PINCTRL_GROUP(NDSR3),
1997 ASPEED_PINCTRL_GROUP(NDSR4),
1998 ASPEED_PINCTRL_GROUP(NDTR1),
1999 ASPEED_PINCTRL_GROUP(NDTR2),
2000 ASPEED_PINCTRL_GROUP(NDTR3),
2001 ASPEED_PINCTRL_GROUP(NDTR4),
2002 ASPEED_PINCTRL_GROUP(NRI1),
2003 ASPEED_PINCTRL_GROUP(NRI2),
2004 ASPEED_PINCTRL_GROUP(NRI3),
2005 ASPEED_PINCTRL_GROUP(NRI4),
2006 ASPEED_PINCTRL_GROUP(NRTS1),
2007 ASPEED_PINCTRL_GROUP(NRTS2),
2008 ASPEED_PINCTRL_GROUP(NRTS3),
2009 ASPEED_PINCTRL_GROUP(NRTS4),
2010 ASPEED_PINCTRL_GROUP(OSCCLK),
2011 ASPEED_PINCTRL_GROUP(PEWAKE),
2012 ASPEED_PINCTRL_GROUP(PWM0),
2013 ASPEED_PINCTRL_GROUP(PWM1),
2014 ASPEED_PINCTRL_GROUP(PWM10G0),
2015 ASPEED_PINCTRL_GROUP(PWM10G1),
2016 ASPEED_PINCTRL_GROUP(PWM11G0),
2017 ASPEED_PINCTRL_GROUP(PWM11G1),
2018 ASPEED_PINCTRL_GROUP(PWM12G0),
2019 ASPEED_PINCTRL_GROUP(PWM12G1),
2020 ASPEED_PINCTRL_GROUP(PWM13G0),
2021 ASPEED_PINCTRL_GROUP(PWM13G1),
2022 ASPEED_PINCTRL_GROUP(PWM14G0),
2023 ASPEED_PINCTRL_GROUP(PWM14G1),
2024 ASPEED_PINCTRL_GROUP(PWM15G0),
2025 ASPEED_PINCTRL_GROUP(PWM15G1),
2026 ASPEED_PINCTRL_GROUP(PWM2),
2027 ASPEED_PINCTRL_GROUP(PWM3),
2028 ASPEED_PINCTRL_GROUP(PWM4),
2029 ASPEED_PINCTRL_GROUP(PWM5),
2030 ASPEED_PINCTRL_GROUP(PWM6),
2031 ASPEED_PINCTRL_GROUP(PWM7),
2032 ASPEED_PINCTRL_GROUP(PWM8G0),
2033 ASPEED_PINCTRL_GROUP(PWM8G1),
2034 ASPEED_PINCTRL_GROUP(PWM9G0),
2035 ASPEED_PINCTRL_GROUP(PWM9G1),
2036 ASPEED_PINCTRL_GROUP(QSPI1),
2037 ASPEED_PINCTRL_GROUP(QSPI2),
2038 ASPEED_PINCTRL_GROUP(RGMII1),
2039 ASPEED_PINCTRL_GROUP(RGMII2),
2040 ASPEED_PINCTRL_GROUP(RGMII3),
2041 ASPEED_PINCTRL_GROUP(RGMII4),
2042 ASPEED_PINCTRL_GROUP(RMII1),
2043 ASPEED_PINCTRL_GROUP(RMII2),
2044 ASPEED_PINCTRL_GROUP(RMII3),
2045 ASPEED_PINCTRL_GROUP(RMII4),
2046 ASPEED_PINCTRL_GROUP(RXD1),
2047 ASPEED_PINCTRL_GROUP(RXD2),
2048 ASPEED_PINCTRL_GROUP(RXD3),
2049 ASPEED_PINCTRL_GROUP(RXD4),
2050 ASPEED_PINCTRL_GROUP(SALT1),
2051 ASPEED_PINCTRL_GROUP(SALT10G0),
2052 ASPEED_PINCTRL_GROUP(SALT10G1),
2053 ASPEED_PINCTRL_GROUP(SALT11G0),
2054 ASPEED_PINCTRL_GROUP(SALT11G1),
2055 ASPEED_PINCTRL_GROUP(SALT12G0),
2056 ASPEED_PINCTRL_GROUP(SALT12G1),
2057 ASPEED_PINCTRL_GROUP(SALT13G0),
2058 ASPEED_PINCTRL_GROUP(SALT13G1),
2059 ASPEED_PINCTRL_GROUP(SALT14G0),
2060 ASPEED_PINCTRL_GROUP(SALT14G1),
2061 ASPEED_PINCTRL_GROUP(SALT15G0),
2062 ASPEED_PINCTRL_GROUP(SALT15G1),
2063 ASPEED_PINCTRL_GROUP(SALT16G0),
2064 ASPEED_PINCTRL_GROUP(SALT16G1),
2065 ASPEED_PINCTRL_GROUP(SALT2),
2066 ASPEED_PINCTRL_GROUP(SALT3),
2067 ASPEED_PINCTRL_GROUP(SALT4),
2068 ASPEED_PINCTRL_GROUP(SALT5),
2069 ASPEED_PINCTRL_GROUP(SALT6),
2070 ASPEED_PINCTRL_GROUP(SALT7),
2071 ASPEED_PINCTRL_GROUP(SALT8),
2072 ASPEED_PINCTRL_GROUP(SALT9G0),
2073 ASPEED_PINCTRL_GROUP(SALT9G1),
2074 ASPEED_PINCTRL_GROUP(SD1),
2075 ASPEED_PINCTRL_GROUP(SD2),
2076 ASPEED_PINCTRL_GROUP(EMMCG1),
2077 ASPEED_PINCTRL_GROUP(EMMCG4),
2078 ASPEED_PINCTRL_GROUP(EMMCG8),
2079 ASPEED_PINCTRL_GROUP(SGPM1),
2080 ASPEED_PINCTRL_GROUP(SGPM2),
2081 ASPEED_PINCTRL_GROUP(SGPS1),
2082 ASPEED_PINCTRL_GROUP(SGPS2),
2083 ASPEED_PINCTRL_GROUP(SIOONCTRL),
2084 ASPEED_PINCTRL_GROUP(SIOPBI),
2085 ASPEED_PINCTRL_GROUP(SIOPBO),
2086 ASPEED_PINCTRL_GROUP(SIOPWREQ),
2087 ASPEED_PINCTRL_GROUP(SIOPWRGD),
2088 ASPEED_PINCTRL_GROUP(SIOS3),
2089 ASPEED_PINCTRL_GROUP(SIOS5),
2090 ASPEED_PINCTRL_GROUP(SIOSCI),
2091 ASPEED_PINCTRL_GROUP(SPI1),
2092 ASPEED_PINCTRL_GROUP(SPI1ABR),
2093 ASPEED_PINCTRL_GROUP(SPI1CS1),
2094 ASPEED_PINCTRL_GROUP(SPI1WP),
2095 ASPEED_PINCTRL_GROUP(SPI2),
2096 ASPEED_PINCTRL_GROUP(SPI2CS1),
2097 ASPEED_PINCTRL_GROUP(SPI2CS2),
2098 ASPEED_PINCTRL_GROUP(TACH0),
2099 ASPEED_PINCTRL_GROUP(TACH1),
2100 ASPEED_PINCTRL_GROUP(TACH10),
2101 ASPEED_PINCTRL_GROUP(TACH11),
2102 ASPEED_PINCTRL_GROUP(TACH12),
2103 ASPEED_PINCTRL_GROUP(TACH13),
2104 ASPEED_PINCTRL_GROUP(TACH14),
2105 ASPEED_PINCTRL_GROUP(TACH15),
2106 ASPEED_PINCTRL_GROUP(TACH2),
2107 ASPEED_PINCTRL_GROUP(TACH3),
2108 ASPEED_PINCTRL_GROUP(TACH4),
2109 ASPEED_PINCTRL_GROUP(TACH5),
2110 ASPEED_PINCTRL_GROUP(TACH6),
2111 ASPEED_PINCTRL_GROUP(TACH7),
2112 ASPEED_PINCTRL_GROUP(TACH8),
2113 ASPEED_PINCTRL_GROUP(TACH9),
2114 ASPEED_PINCTRL_GROUP(THRU0),
2115 ASPEED_PINCTRL_GROUP(THRU1),
2116 ASPEED_PINCTRL_GROUP(THRU2),
2117 ASPEED_PINCTRL_GROUP(THRU3),
2118 ASPEED_PINCTRL_GROUP(TXD1),
2119 ASPEED_PINCTRL_GROUP(TXD2),
2120 ASPEED_PINCTRL_GROUP(TXD3),
2121 ASPEED_PINCTRL_GROUP(TXD4),
2122 ASPEED_PINCTRL_GROUP(UART10),
2123 ASPEED_PINCTRL_GROUP(UART11),
2124 ASPEED_PINCTRL_GROUP(UART12G0),
2125 ASPEED_PINCTRL_GROUP(UART12G1),
2126 ASPEED_PINCTRL_GROUP(UART13G0),
2127 ASPEED_PINCTRL_GROUP(UART13G1),
2128 ASPEED_PINCTRL_GROUP(UART6),
2129 ASPEED_PINCTRL_GROUP(UART7),
2130 ASPEED_PINCTRL_GROUP(UART8),
2131 ASPEED_PINCTRL_GROUP(UART9),
2132 ASPEED_PINCTRL_GROUP(USBA),
2133 ASPEED_PINCTRL_GROUP(USBB),
2134 ASPEED_PINCTRL_GROUP(VB),
2135 ASPEED_PINCTRL_GROUP(VGAHS),
2136 ASPEED_PINCTRL_GROUP(VGAVS),
2137 ASPEED_PINCTRL_GROUP(WDTRST1),
2138 ASPEED_PINCTRL_GROUP(WDTRST2),
2139 ASPEED_PINCTRL_GROUP(WDTRST3),
2140 ASPEED_PINCTRL_GROUP(WDTRST4),
2141 };
2142
2143 static const struct aspeed_pin_function aspeed_g6_functions[] = {
2144 ASPEED_PINCTRL_FUNC(ADC0),
2145 ASPEED_PINCTRL_FUNC(ADC1),
2146 ASPEED_PINCTRL_FUNC(ADC10),
2147 ASPEED_PINCTRL_FUNC(ADC11),
2148 ASPEED_PINCTRL_FUNC(ADC12),
2149 ASPEED_PINCTRL_FUNC(ADC13),
2150 ASPEED_PINCTRL_FUNC(ADC14),
2151 ASPEED_PINCTRL_FUNC(ADC15),
2152 ASPEED_PINCTRL_FUNC(ADC2),
2153 ASPEED_PINCTRL_FUNC(ADC3),
2154 ASPEED_PINCTRL_FUNC(ADC4),
2155 ASPEED_PINCTRL_FUNC(ADC5),
2156 ASPEED_PINCTRL_FUNC(ADC6),
2157 ASPEED_PINCTRL_FUNC(ADC7),
2158 ASPEED_PINCTRL_FUNC(ADC8),
2159 ASPEED_PINCTRL_FUNC(ADC9),
2160 ASPEED_PINCTRL_FUNC(BMCINT),
2161 ASPEED_PINCTRL_FUNC(EMMC),
2162 ASPEED_PINCTRL_FUNC(ESPI),
2163 ASPEED_PINCTRL_FUNC(ESPIALT),
2164 ASPEED_PINCTRL_FUNC(FSI1),
2165 ASPEED_PINCTRL_FUNC(FSI2),
2166 ASPEED_PINCTRL_FUNC(FWSPIABR),
2167 ASPEED_PINCTRL_FUNC(FWSPID),
2168 ASPEED_PINCTRL_FUNC(FWQSPI),
2169 ASPEED_PINCTRL_FUNC(FWSPIWP),
2170 ASPEED_PINCTRL_FUNC(GPIT0),
2171 ASPEED_PINCTRL_FUNC(GPIT1),
2172 ASPEED_PINCTRL_FUNC(GPIT2),
2173 ASPEED_PINCTRL_FUNC(GPIT3),
2174 ASPEED_PINCTRL_FUNC(GPIT4),
2175 ASPEED_PINCTRL_FUNC(GPIT5),
2176 ASPEED_PINCTRL_FUNC(GPIT6),
2177 ASPEED_PINCTRL_FUNC(GPIT7),
2178 ASPEED_PINCTRL_FUNC(GPIU0),
2179 ASPEED_PINCTRL_FUNC(GPIU1),
2180 ASPEED_PINCTRL_FUNC(GPIU2),
2181 ASPEED_PINCTRL_FUNC(GPIU3),
2182 ASPEED_PINCTRL_FUNC(GPIU4),
2183 ASPEED_PINCTRL_FUNC(GPIU5),
2184 ASPEED_PINCTRL_FUNC(GPIU6),
2185 ASPEED_PINCTRL_FUNC(GPIU7),
2186 ASPEED_PINCTRL_FUNC(HEARTBEAT),
2187 ASPEED_PINCTRL_FUNC(I2C1),
2188 ASPEED_PINCTRL_FUNC(I2C10),
2189 ASPEED_PINCTRL_FUNC(I2C11),
2190 ASPEED_PINCTRL_FUNC(I2C12),
2191 ASPEED_PINCTRL_FUNC(I2C13),
2192 ASPEED_PINCTRL_FUNC(I2C14),
2193 ASPEED_PINCTRL_FUNC(I2C15),
2194 ASPEED_PINCTRL_FUNC(I2C16),
2195 ASPEED_PINCTRL_FUNC(I2C2),
2196 ASPEED_PINCTRL_FUNC(I2C3),
2197 ASPEED_PINCTRL_FUNC(I2C4),
2198 ASPEED_PINCTRL_FUNC(I2C5),
2199 ASPEED_PINCTRL_FUNC(I2C6),
2200 ASPEED_PINCTRL_FUNC(I2C7),
2201 ASPEED_PINCTRL_FUNC(I2C8),
2202 ASPEED_PINCTRL_FUNC(I2C9),
2203 ASPEED_PINCTRL_FUNC(I3C1),
2204 ASPEED_PINCTRL_FUNC(I3C2),
2205 ASPEED_PINCTRL_FUNC(I3C3),
2206 ASPEED_PINCTRL_FUNC(I3C4),
2207 ASPEED_PINCTRL_FUNC(I3C5),
2208 ASPEED_PINCTRL_FUNC(I3C6),
2209 ASPEED_PINCTRL_FUNC(JTAGM),
2210 ASPEED_PINCTRL_FUNC(LHPD),
2211 ASPEED_PINCTRL_FUNC(LHSIRQ),
2212 ASPEED_PINCTRL_FUNC(LPC),
2213 ASPEED_PINCTRL_FUNC(LPCHC),
2214 ASPEED_PINCTRL_FUNC(LPCPD),
2215 ASPEED_PINCTRL_FUNC(LPCPME),
2216 ASPEED_PINCTRL_FUNC(LPCSMI),
2217 ASPEED_PINCTRL_FUNC(LSIRQ),
2218 ASPEED_PINCTRL_FUNC(MACLINK1),
2219 ASPEED_PINCTRL_FUNC(MACLINK2),
2220 ASPEED_PINCTRL_FUNC(MACLINK3),
2221 ASPEED_PINCTRL_FUNC(MACLINK4),
2222 ASPEED_PINCTRL_FUNC(MDIO1),
2223 ASPEED_PINCTRL_FUNC(MDIO2),
2224 ASPEED_PINCTRL_FUNC(MDIO3),
2225 ASPEED_PINCTRL_FUNC(MDIO4),
2226 ASPEED_PINCTRL_FUNC(NCTS1),
2227 ASPEED_PINCTRL_FUNC(NCTS2),
2228 ASPEED_PINCTRL_FUNC(NCTS3),
2229 ASPEED_PINCTRL_FUNC(NCTS4),
2230 ASPEED_PINCTRL_FUNC(NDCD1),
2231 ASPEED_PINCTRL_FUNC(NDCD2),
2232 ASPEED_PINCTRL_FUNC(NDCD3),
2233 ASPEED_PINCTRL_FUNC(NDCD4),
2234 ASPEED_PINCTRL_FUNC(NDSR1),
2235 ASPEED_PINCTRL_FUNC(NDSR2),
2236 ASPEED_PINCTRL_FUNC(NDSR3),
2237 ASPEED_PINCTRL_FUNC(NDSR4),
2238 ASPEED_PINCTRL_FUNC(NDTR1),
2239 ASPEED_PINCTRL_FUNC(NDTR2),
2240 ASPEED_PINCTRL_FUNC(NDTR3),
2241 ASPEED_PINCTRL_FUNC(NDTR4),
2242 ASPEED_PINCTRL_FUNC(NRI1),
2243 ASPEED_PINCTRL_FUNC(NRI2),
2244 ASPEED_PINCTRL_FUNC(NRI3),
2245 ASPEED_PINCTRL_FUNC(NRI4),
2246 ASPEED_PINCTRL_FUNC(NRTS1),
2247 ASPEED_PINCTRL_FUNC(NRTS2),
2248 ASPEED_PINCTRL_FUNC(NRTS3),
2249 ASPEED_PINCTRL_FUNC(NRTS4),
2250 ASPEED_PINCTRL_FUNC(OSCCLK),
2251 ASPEED_PINCTRL_FUNC(PEWAKE),
2252 ASPEED_PINCTRL_FUNC(PWM0),
2253 ASPEED_PINCTRL_FUNC(PWM1),
2254 ASPEED_PINCTRL_FUNC(PWM10),
2255 ASPEED_PINCTRL_FUNC(PWM11),
2256 ASPEED_PINCTRL_FUNC(PWM12),
2257 ASPEED_PINCTRL_FUNC(PWM13),
2258 ASPEED_PINCTRL_FUNC(PWM14),
2259 ASPEED_PINCTRL_FUNC(PWM15),
2260 ASPEED_PINCTRL_FUNC(PWM2),
2261 ASPEED_PINCTRL_FUNC(PWM3),
2262 ASPEED_PINCTRL_FUNC(PWM4),
2263 ASPEED_PINCTRL_FUNC(PWM5),
2264 ASPEED_PINCTRL_FUNC(PWM6),
2265 ASPEED_PINCTRL_FUNC(PWM7),
2266 ASPEED_PINCTRL_FUNC(PWM8),
2267 ASPEED_PINCTRL_FUNC(PWM9),
2268 ASPEED_PINCTRL_FUNC(RGMII1),
2269 ASPEED_PINCTRL_FUNC(RGMII2),
2270 ASPEED_PINCTRL_FUNC(RGMII3),
2271 ASPEED_PINCTRL_FUNC(RGMII4),
2272 ASPEED_PINCTRL_FUNC(RMII1),
2273 ASPEED_PINCTRL_FUNC(RMII2),
2274 ASPEED_PINCTRL_FUNC(RMII3),
2275 ASPEED_PINCTRL_FUNC(RMII4),
2276 ASPEED_PINCTRL_FUNC(RXD1),
2277 ASPEED_PINCTRL_FUNC(RXD2),
2278 ASPEED_PINCTRL_FUNC(RXD3),
2279 ASPEED_PINCTRL_FUNC(RXD4),
2280 ASPEED_PINCTRL_FUNC(SALT1),
2281 ASPEED_PINCTRL_FUNC(SALT10),
2282 ASPEED_PINCTRL_FUNC(SALT11),
2283 ASPEED_PINCTRL_FUNC(SALT12),
2284 ASPEED_PINCTRL_FUNC(SALT13),
2285 ASPEED_PINCTRL_FUNC(SALT14),
2286 ASPEED_PINCTRL_FUNC(SALT15),
2287 ASPEED_PINCTRL_FUNC(SALT16),
2288 ASPEED_PINCTRL_FUNC(SALT2),
2289 ASPEED_PINCTRL_FUNC(SALT3),
2290 ASPEED_PINCTRL_FUNC(SALT4),
2291 ASPEED_PINCTRL_FUNC(SALT5),
2292 ASPEED_PINCTRL_FUNC(SALT6),
2293 ASPEED_PINCTRL_FUNC(SALT7),
2294 ASPEED_PINCTRL_FUNC(SALT8),
2295 ASPEED_PINCTRL_FUNC(SALT9),
2296 ASPEED_PINCTRL_FUNC(SD1),
2297 ASPEED_PINCTRL_FUNC(SD2),
2298 ASPEED_PINCTRL_FUNC(SGPM1),
2299 ASPEED_PINCTRL_FUNC(SGPM2),
2300 ASPEED_PINCTRL_FUNC(SGPS1),
2301 ASPEED_PINCTRL_FUNC(SGPS2),
2302 ASPEED_PINCTRL_FUNC(SIOONCTRL),
2303 ASPEED_PINCTRL_FUNC(SIOPBI),
2304 ASPEED_PINCTRL_FUNC(SIOPBO),
2305 ASPEED_PINCTRL_FUNC(SIOPWREQ),
2306 ASPEED_PINCTRL_FUNC(SIOPWRGD),
2307 ASPEED_PINCTRL_FUNC(SIOS3),
2308 ASPEED_PINCTRL_FUNC(SIOS5),
2309 ASPEED_PINCTRL_FUNC(SIOSCI),
2310 ASPEED_PINCTRL_FUNC(SPI1),
2311 ASPEED_PINCTRL_FUNC(SPI1ABR),
2312 ASPEED_PINCTRL_FUNC(SPI1CS1),
2313 ASPEED_PINCTRL_FUNC(SPI1WP),
2314 ASPEED_PINCTRL_FUNC(SPI2),
2315 ASPEED_PINCTRL_FUNC(SPI2CS1),
2316 ASPEED_PINCTRL_FUNC(SPI2CS2),
2317 ASPEED_PINCTRL_FUNC(TACH0),
2318 ASPEED_PINCTRL_FUNC(TACH1),
2319 ASPEED_PINCTRL_FUNC(TACH10),
2320 ASPEED_PINCTRL_FUNC(TACH11),
2321 ASPEED_PINCTRL_FUNC(TACH12),
2322 ASPEED_PINCTRL_FUNC(TACH13),
2323 ASPEED_PINCTRL_FUNC(TACH14),
2324 ASPEED_PINCTRL_FUNC(TACH15),
2325 ASPEED_PINCTRL_FUNC(TACH2),
2326 ASPEED_PINCTRL_FUNC(TACH3),
2327 ASPEED_PINCTRL_FUNC(TACH4),
2328 ASPEED_PINCTRL_FUNC(TACH5),
2329 ASPEED_PINCTRL_FUNC(TACH6),
2330 ASPEED_PINCTRL_FUNC(TACH7),
2331 ASPEED_PINCTRL_FUNC(TACH8),
2332 ASPEED_PINCTRL_FUNC(TACH9),
2333 ASPEED_PINCTRL_FUNC(THRU0),
2334 ASPEED_PINCTRL_FUNC(THRU1),
2335 ASPEED_PINCTRL_FUNC(THRU2),
2336 ASPEED_PINCTRL_FUNC(THRU3),
2337 ASPEED_PINCTRL_FUNC(TXD1),
2338 ASPEED_PINCTRL_FUNC(TXD2),
2339 ASPEED_PINCTRL_FUNC(TXD3),
2340 ASPEED_PINCTRL_FUNC(TXD4),
2341 ASPEED_PINCTRL_FUNC(UART10),
2342 ASPEED_PINCTRL_FUNC(UART11),
2343 ASPEED_PINCTRL_FUNC(UART12),
2344 ASPEED_PINCTRL_FUNC(UART13),
2345 ASPEED_PINCTRL_FUNC(UART6),
2346 ASPEED_PINCTRL_FUNC(UART7),
2347 ASPEED_PINCTRL_FUNC(UART8),
2348 ASPEED_PINCTRL_FUNC(UART9),
2349 ASPEED_PINCTRL_FUNC(USB11BHID),
2350 ASPEED_PINCTRL_FUNC(USB2AD),
2351 ASPEED_PINCTRL_FUNC(USB2ADP),
2352 ASPEED_PINCTRL_FUNC(USB2AH),
2353 ASPEED_PINCTRL_FUNC(USB2AHP),
2354 ASPEED_PINCTRL_FUNC(USB2BD),
2355 ASPEED_PINCTRL_FUNC(USB2BH),
2356 ASPEED_PINCTRL_FUNC(VB),
2357 ASPEED_PINCTRL_FUNC(VGAHS),
2358 ASPEED_PINCTRL_FUNC(VGAVS),
2359 ASPEED_PINCTRL_FUNC(WDTRST1),
2360 ASPEED_PINCTRL_FUNC(WDTRST2),
2361 ASPEED_PINCTRL_FUNC(WDTRST3),
2362 ASPEED_PINCTRL_FUNC(WDTRST4),
2363 };
2364
2365 static struct aspeed_pin_config aspeed_g6_configs[] = {
2366 /* GPIOB7 */
2367 ASPEED_PULL_DOWN_PINCONF(J24, SCU610, 15),
2368 /* GPIOB6 */
2369 ASPEED_PULL_DOWN_PINCONF(H25, SCU610, 14),
2370 /* GPIOB5 */
2371 ASPEED_PULL_DOWN_PINCONF(G26, SCU610, 13),
2372 /* GPIOB4 */
2373 ASPEED_PULL_DOWN_PINCONF(J23, SCU610, 12),
2374 /* GPIOB3 */
2375 ASPEED_PULL_DOWN_PINCONF(J25, SCU610, 11),
2376 /* GPIOB2 */
2377 ASPEED_PULL_DOWN_PINCONF(H26, SCU610, 10),
2378 /* GPIOB1 */
2379 ASPEED_PULL_DOWN_PINCONF(K23, SCU610, 9),
2380 /* GPIOB0 */
2381 ASPEED_PULL_DOWN_PINCONF(J26, SCU610, 8),
2382
2383 /* GPIOH3 */
2384 ASPEED_PULL_DOWN_PINCONF(A17, SCU614, 27),
2385 /* GPIOH2 */
2386 ASPEED_PULL_DOWN_PINCONF(C18, SCU614, 26),
2387 /* GPIOH1 */
2388 ASPEED_PULL_DOWN_PINCONF(B18, SCU614, 25),
2389 /* GPIOH0 */
2390 ASPEED_PULL_DOWN_PINCONF(A18, SCU614, 24),
2391
2392 /* GPIOL7 */
2393 ASPEED_PULL_DOWN_PINCONF(C14, SCU618, 31),
2394 /* GPIOL6 */
2395 ASPEED_PULL_DOWN_PINCONF(B14, SCU618, 30),
2396 /* GPIOL5 */
2397 ASPEED_PULL_DOWN_PINCONF(F15, SCU618, 29),
2398 /* GPIOL4 */
2399 ASPEED_PULL_DOWN_PINCONF(C15, SCU618, 28),
2400
2401 /* GPIOJ7 */
2402 ASPEED_PULL_UP_PINCONF(D19, SCU618, 15),
2403 /* GPIOJ6 */
2404 ASPEED_PULL_UP_PINCONF(C20, SCU618, 14),
2405 /* GPIOJ5 */
2406 ASPEED_PULL_UP_PINCONF(A19, SCU618, 13),
2407 /* GPIOJ4 */
2408 ASPEED_PULL_UP_PINCONF(C19, SCU618, 12),
2409 /* GPIOJ3 */
2410 ASPEED_PULL_UP_PINCONF(D20, SCU618, 11),
2411 /* GPIOJ2 */
2412 ASPEED_PULL_UP_PINCONF(E19, SCU618, 10),
2413 /* GPIOJ1 */
2414 ASPEED_PULL_UP_PINCONF(A20, SCU618, 9),
2415 /* GPIOJ0 */
2416 ASPEED_PULL_UP_PINCONF(B20, SCU618, 8),
2417
2418 /* GPIOI7 */
2419 ASPEED_PULL_DOWN_PINCONF(A15, SCU618, 7),
2420 /* GPIOI6 */
2421 ASPEED_PULL_DOWN_PINCONF(B16, SCU618, 6),
2422 /* GPIOI5 */
2423 ASPEED_PULL_DOWN_PINCONF(E16, SCU618, 5),
2424 /* GPIOI4 */
2425 ASPEED_PULL_DOWN_PINCONF(C16, SCU618, 4),
2426 /* GPIOI3 */
2427 ASPEED_PULL_DOWN_PINCONF(D16, SCU618, 3),
2428 /* GPIOI2 */
2429 ASPEED_PULL_DOWN_PINCONF(E17, SCU618, 2),
2430 /* GPIOI1 */
2431 ASPEED_PULL_DOWN_PINCONF(A16, SCU618, 1),
2432 /* GPIOI0 */
2433 ASPEED_PULL_DOWN_PINCONF(D17, SCU618, 0),
2434
2435 /* GPIOP7 */
2436 ASPEED_PULL_DOWN_PINCONF(Y23, SCU61C, 31),
2437 /* GPIOP6 */
2438 ASPEED_PULL_DOWN_PINCONF(AB24, SCU61C, 30),
2439 /* GPIOP5 */
2440 ASPEED_PULL_DOWN_PINCONF(AB23, SCU61C, 29),
2441 /* GPIOP4 */
2442 ASPEED_PULL_DOWN_PINCONF(W23, SCU61C, 28),
2443 /* GPIOP3 */
2444 ASPEED_PULL_DOWN_PINCONF(AA24, SCU61C, 27),
2445 /* GPIOP2 */
2446 ASPEED_PULL_DOWN_PINCONF(AA23, SCU61C, 26),
2447 /* GPIOP1 */
2448 ASPEED_PULL_DOWN_PINCONF(W24, SCU61C, 25),
2449 /* GPIOP0 */
2450 ASPEED_PULL_DOWN_PINCONF(AB22, SCU61C, 24),
2451
2452 /* GPIOO7 */
2453 ASPEED_PULL_DOWN_PINCONF(AC23, SCU61C, 23),
2454 /* GPIOO6 */
2455 ASPEED_PULL_DOWN_PINCONF(AC24, SCU61C, 22),
2456 /* GPIOO5 */
2457 ASPEED_PULL_DOWN_PINCONF(AC22, SCU61C, 21),
2458 /* GPIOO4 */
2459 ASPEED_PULL_DOWN_PINCONF(AD25, SCU61C, 20),
2460 /* GPIOO3 */
2461 ASPEED_PULL_DOWN_PINCONF(AD24, SCU61C, 19),
2462 /* GPIOO2 */
2463 ASPEED_PULL_DOWN_PINCONF(AD23, SCU61C, 18),
2464 /* GPIOO1 */
2465 ASPEED_PULL_DOWN_PINCONF(AD22, SCU61C, 17),
2466 /* GPIOO0 */
2467 ASPEED_PULL_DOWN_PINCONF(AD26, SCU61C, 16),
2468
2469 /* GPION7 */
2470 ASPEED_PULL_DOWN_PINCONF(M26, SCU61C, 15),
2471 /* GPION6 */
2472 ASPEED_PULL_DOWN_PINCONF(N26, SCU61C, 14),
2473 /* GPION5 */
2474 ASPEED_PULL_DOWN_PINCONF(M23, SCU61C, 13),
2475 /* GPION4 */
2476 ASPEED_PULL_DOWN_PINCONF(P26, SCU61C, 12),
2477 /* GPION3 */
2478 ASPEED_PULL_DOWN_PINCONF(N24, SCU61C, 11),
2479 /* GPION2 */
2480 ASPEED_PULL_DOWN_PINCONF(N25, SCU61C, 10),
2481 /* GPION1 */
2482 ASPEED_PULL_DOWN_PINCONF(N23, SCU61C, 9),
2483 /* GPION0 */
2484 ASPEED_PULL_DOWN_PINCONF(P25, SCU61C, 8),
2485
2486 /* GPIOM7 */
2487 ASPEED_PULL_DOWN_PINCONF(D13, SCU61C, 7),
2488 /* GPIOM6 */
2489 ASPEED_PULL_DOWN_PINCONF(C13, SCU61C, 6),
2490 /* GPIOM5 */
2491 ASPEED_PULL_DOWN_PINCONF(C12, SCU61C, 5),
2492 /* GPIOM4 */
2493 ASPEED_PULL_DOWN_PINCONF(B12, SCU61C, 4),
2494 /* GPIOM3 */
2495 ASPEED_PULL_DOWN_PINCONF(E14, SCU61C, 3),
2496 /* GPIOM2 */
2497 ASPEED_PULL_DOWN_PINCONF(A12, SCU61C, 2),
2498 /* GPIOM1 */
2499 ASPEED_PULL_DOWN_PINCONF(B13, SCU61C, 1),
2500 /* GPIOM0 */
2501 ASPEED_PULL_DOWN_PINCONF(D14, SCU61C, 0),
2502
2503 /* GPIOS7 */
2504 ASPEED_PULL_DOWN_PINCONF(T24, SCU630, 23),
2505 /* GPIOS6 */
2506 ASPEED_PULL_DOWN_PINCONF(P23, SCU630, 22),
2507 /* GPIOS5 */
2508 ASPEED_PULL_DOWN_PINCONF(P24, SCU630, 21),
2509 /* GPIOS4 */
2510 ASPEED_PULL_DOWN_PINCONF(R26, SCU630, 20),
2511 /* GPIOS3*/
2512 ASPEED_PULL_DOWN_PINCONF(R24, SCU630, 19),
2513 /* GPIOS2 */
2514 ASPEED_PULL_DOWN_PINCONF(T26, SCU630, 18),
2515 /* GPIOS1 */
2516 ASPEED_PULL_DOWN_PINCONF(T25, SCU630, 17),
2517 /* GPIOS0 */
2518 ASPEED_PULL_DOWN_PINCONF(R23, SCU630, 16),
2519
2520 /* GPIOR7 */
2521 ASPEED_PULL_DOWN_PINCONF(U26, SCU630, 15),
2522 /* GPIOR6 */
2523 ASPEED_PULL_DOWN_PINCONF(W26, SCU630, 14),
2524 /* GPIOR5 */
2525 ASPEED_PULL_DOWN_PINCONF(T23, SCU630, 13),
2526 /* GPIOR4 */
2527 ASPEED_PULL_DOWN_PINCONF(U25, SCU630, 12),
2528 /* GPIOR3*/
2529 ASPEED_PULL_DOWN_PINCONF(V26, SCU630, 11),
2530 /* GPIOR2 */
2531 ASPEED_PULL_DOWN_PINCONF(V24, SCU630, 10),
2532 /* GPIOR1 */
2533 ASPEED_PULL_DOWN_PINCONF(U24, SCU630, 9),
2534 /* GPIOR0 */
2535 ASPEED_PULL_DOWN_PINCONF(V25, SCU630, 8),
2536
2537 /* GPIOX7 */
2538 ASPEED_PULL_DOWN_PINCONF(AB10, SCU634, 31),
2539 /* GPIOX6 */
2540 ASPEED_PULL_DOWN_PINCONF(AF9, SCU634, 30),
2541 /* GPIOX5 */
2542 ASPEED_PULL_DOWN_PINCONF(AD9, SCU634, 29),
2543 /* GPIOX4 */
2544 ASPEED_PULL_DOWN_PINCONF(AB9, SCU634, 28),
2545 /* GPIOX3*/
2546 ASPEED_PULL_DOWN_PINCONF(AF8, SCU634, 27),
2547 /* GPIOX2 */
2548 ASPEED_PULL_DOWN_PINCONF(AC9, SCU634, 26),
2549 /* GPIOX1 */
2550 ASPEED_PULL_DOWN_PINCONF(AA9, SCU634, 25),
2551 /* GPIOX0 */
2552 ASPEED_PULL_DOWN_PINCONF(AE8, SCU634, 24),
2553
2554 /* GPIOV7 */
2555 ASPEED_PULL_DOWN_PINCONF(AF15, SCU634, 15),
2556 /* GPIOV6 */
2557 ASPEED_PULL_DOWN_PINCONF(AD15, SCU634, 14),
2558 /* GPIOV5 */
2559 ASPEED_PULL_DOWN_PINCONF(AE14, SCU634, 13),
2560 /* GPIOV4 */
2561 ASPEED_PULL_DOWN_PINCONF(AE15, SCU634, 12),
2562 /* GPIOV3*/
2563 ASPEED_PULL_DOWN_PINCONF(AC15, SCU634, 11),
2564 /* GPIOV2 */
2565 ASPEED_PULL_DOWN_PINCONF(AD14, SCU634, 10),
2566 /* GPIOV1 */
2567 ASPEED_PULL_DOWN_PINCONF(AF14, SCU634, 9),
2568 /* GPIOV0 */
2569 ASPEED_PULL_DOWN_PINCONF(AB15, SCU634, 8),
2570
2571 /* GPIOZ7 */
2572 ASPEED_PULL_DOWN_PINCONF(AF10, SCU638, 15),
2573 /* GPIOZ6 */
2574 ASPEED_PULL_DOWN_PINCONF(AD11, SCU638, 14),
2575 /* GPIOZ5 */
2576 ASPEED_PULL_DOWN_PINCONF(AA11, SCU638, 13),
2577 /* GPIOZ4 */
2578 ASPEED_PULL_DOWN_PINCONF(AC11, SCU638, 12),
2579 /* GPIOZ3*/
2580 ASPEED_PULL_DOWN_PINCONF(AB11, SCU638, 11),
2581
2582 /* GPIOZ1 */
2583 ASPEED_PULL_DOWN_PINCONF(AD10, SCU638, 9),
2584 /* GPIOZ0 */
2585 ASPEED_PULL_DOWN_PINCONF(AC10, SCU638, 8),
2586
2587 /* GPIOY6 */
2588 ASPEED_PULL_DOWN_PINCONF(AC12, SCU638, 6),
2589 /* GPIOY5 */
2590 ASPEED_PULL_DOWN_PINCONF(AF12, SCU638, 5),
2591 /* GPIOY4 */
2592 ASPEED_PULL_DOWN_PINCONF(AE12, SCU638, 4),
2593 /* GPIOY3 */
2594 ASPEED_PULL_DOWN_PINCONF(AA12, SCU638, 3),
2595 /* GPIOY2 */
2596 ASPEED_PULL_DOWN_PINCONF(AE11, SCU638, 2),
2597 /* GPIOY1 */
2598 ASPEED_PULL_DOWN_PINCONF(AD12, SCU638, 1),
2599 /* GPIOY0 */
2600 ASPEED_PULL_DOWN_PINCONF(AF11, SCU638, 0),
2601
2602 /* LAD3 */
2603 { PIN_CONFIG_DRIVE_STRENGTH, { AC7, AC7 }, SCU454, GENMASK(31, 30)},
2604 /* LAD2 */
2605 { PIN_CONFIG_DRIVE_STRENGTH, { AC8, AC8 }, SCU454, GENMASK(29, 28)},
2606 /* LAD1 */
2607 { PIN_CONFIG_DRIVE_STRENGTH, { AB8, AB8 }, SCU454, GENMASK(27, 26)},
2608 /* LAD0 */
2609 { PIN_CONFIG_DRIVE_STRENGTH, { AB7, AB7 }, SCU454, GENMASK(25, 24)},
2610
2611 /* MAC3 */
2612 { PIN_CONFIG_POWER_SOURCE, { H24, E26 }, SCU458, BIT_MASK(4)},
2613 { PIN_CONFIG_DRIVE_STRENGTH, { H24, E26 }, SCU458, GENMASK(1, 0)},
2614 /* MAC4 */
2615 { PIN_CONFIG_POWER_SOURCE, { F24, B24 }, SCU458, BIT_MASK(5)},
2616 { PIN_CONFIG_DRIVE_STRENGTH, { F24, B24 }, SCU458, GENMASK(3, 2)},
2617
2618 /* GPIO18E */
2619 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, Y4, SCU40C, 4),
2620 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y1, Y4, SCU40C, 4),
2621 /* GPIO18D */
2622 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AB4, AC5, SCU40C, 3),
2623 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, AB4, AC5, SCU40C, 3),
2624 /* GPIO18C */
2625 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E4, E1, SCU40C, 2),
2626 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E4, E1, SCU40C, 2),
2627 /* GPIO18B */
2628 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D3, SCU40C, 1),
2629 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B2, D3, SCU40C, 1),
2630 /* GPIO18A */
2631 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C6, A2, SCU40C, 0),
2632 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C6, A2, SCU40C, 0),
2633 };
2634
2635 /**
2636 * aspeed_g6_sig_expr_set() - Configure a pin's signal by applying an
2637 * expression's descriptor state for all descriptors in the expression.
2638 *
2639 * @ctx: The pinmux context
2640 * @expr: The expression associated with the function whose signal is to be
2641 * configured
2642 * @enable: true to enable an function's signal through a pin's signal
2643 * expression, false to disable the function's signal
2644 *
2645 * Return: 0 if the expression is configured as requested and a negative error
2646 * code otherwise
2647 */
aspeed_g6_sig_expr_set(struct aspeed_pinmux_data * ctx,const struct aspeed_sig_expr * expr,bool enable)2648 static int aspeed_g6_sig_expr_set(struct aspeed_pinmux_data *ctx,
2649 const struct aspeed_sig_expr *expr,
2650 bool enable)
2651 {
2652 int ret;
2653 int i;
2654
2655 for (i = 0; i < expr->ndescs; i++) {
2656 const struct aspeed_sig_desc *desc = &expr->descs[i];
2657 u32 pattern = enable ? desc->enable : desc->disable;
2658 u32 val = (pattern << __ffs(desc->mask));
2659 bool is_strap;
2660
2661 if (!ctx->maps[desc->ip])
2662 return -ENODEV;
2663
2664 WARN_ON(desc->ip != ASPEED_IP_SCU);
2665 is_strap = desc->reg == SCU500 || desc->reg == SCU510;
2666
2667 if (is_strap) {
2668 /*
2669 * The AST2600 has write protection mask registers for
2670 * the hardware strapping in SCU508 and SCU518. Assume
2671 * that if the platform doesn't want the strapping
2672 * values changed that it has set the write mask.
2673 *
2674 * The strapping registers implement write-1-clear
2675 * behaviour. SCU500 is paired with clear writes on
2676 * SCU504, likewise SCU510 is paired with SCU514.
2677 */
2678 u32 clear = ~val & desc->mask;
2679 u32 w1c = desc->reg + 4;
2680
2681 if (clear)
2682 ret = regmap_update_bits(ctx->maps[desc->ip],
2683 w1c, desc->mask,
2684 clear);
2685 }
2686
2687 ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg,
2688 desc->mask, val);
2689 if (ret)
2690 return ret;
2691 }
2692
2693 ret = aspeed_sig_expr_eval(ctx, expr, enable);
2694 if (ret < 0)
2695 return ret;
2696
2697 if (!ret)
2698 return -EPERM;
2699 return 0;
2700 }
2701
2702 static const struct aspeed_pin_config_map aspeed_g6_pin_config_map[] = {
2703 { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
2704 { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
2705 { PIN_CONFIG_BIAS_PULL_UP, 0, 1, BIT_MASK(0)},
2706 { PIN_CONFIG_BIAS_PULL_UP, -1, 0, BIT_MASK(0)},
2707 { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
2708 { PIN_CONFIG_DRIVE_STRENGTH, 4, 0, GENMASK(1, 0)},
2709 { PIN_CONFIG_DRIVE_STRENGTH, 8, 1, GENMASK(1, 0)},
2710 { PIN_CONFIG_DRIVE_STRENGTH, 12, 2, GENMASK(1, 0)},
2711 { PIN_CONFIG_DRIVE_STRENGTH, 16, 3, GENMASK(1, 0)},
2712 { PIN_CONFIG_POWER_SOURCE, 3300, 0, BIT_MASK(0)},
2713 { PIN_CONFIG_POWER_SOURCE, 1800, 1, BIT_MASK(0)},
2714 };
2715
2716 static const struct aspeed_pinmux_ops aspeed_g5_ops = {
2717 .set = aspeed_g6_sig_expr_set,
2718 };
2719
2720 static struct aspeed_pinctrl_data aspeed_g6_pinctrl_data = {
2721 .pins = aspeed_g6_pins,
2722 .npins = ARRAY_SIZE(aspeed_g6_pins),
2723 .pinmux = {
2724 .ops = &aspeed_g5_ops,
2725 .groups = aspeed_g6_groups,
2726 .ngroups = ARRAY_SIZE(aspeed_g6_groups),
2727 .functions = aspeed_g6_functions,
2728 .nfunctions = ARRAY_SIZE(aspeed_g6_functions),
2729 },
2730 .configs = aspeed_g6_configs,
2731 .nconfigs = ARRAY_SIZE(aspeed_g6_configs),
2732 .confmaps = aspeed_g6_pin_config_map,
2733 .nconfmaps = ARRAY_SIZE(aspeed_g6_pin_config_map),
2734 };
2735
2736 static const struct pinmux_ops aspeed_g6_pinmux_ops = {
2737 .get_functions_count = aspeed_pinmux_get_fn_count,
2738 .get_function_name = aspeed_pinmux_get_fn_name,
2739 .get_function_groups = aspeed_pinmux_get_fn_groups,
2740 .set_mux = aspeed_pinmux_set_mux,
2741 .gpio_request_enable = aspeed_gpio_request_enable,
2742 .strict = true,
2743 };
2744
2745 static const struct pinctrl_ops aspeed_g6_pinctrl_ops = {
2746 .get_groups_count = aspeed_pinctrl_get_groups_count,
2747 .get_group_name = aspeed_pinctrl_get_group_name,
2748 .get_group_pins = aspeed_pinctrl_get_group_pins,
2749 .pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
2750 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
2751 .dt_free_map = pinctrl_utils_free_map,
2752 };
2753
2754 static const struct pinconf_ops aspeed_g6_conf_ops = {
2755 .is_generic = true,
2756 .pin_config_get = aspeed_pin_config_get,
2757 .pin_config_set = aspeed_pin_config_set,
2758 .pin_config_group_get = aspeed_pin_config_group_get,
2759 .pin_config_group_set = aspeed_pin_config_group_set,
2760 };
2761
2762 static struct pinctrl_desc aspeed_g6_pinctrl_desc = {
2763 .name = "aspeed-g6-pinctrl",
2764 .pins = aspeed_g6_pins,
2765 .npins = ARRAY_SIZE(aspeed_g6_pins),
2766 .pctlops = &aspeed_g6_pinctrl_ops,
2767 .pmxops = &aspeed_g6_pinmux_ops,
2768 .confops = &aspeed_g6_conf_ops,
2769 };
2770
aspeed_g6_pinctrl_probe(struct platform_device * pdev)2771 static int aspeed_g6_pinctrl_probe(struct platform_device *pdev)
2772 {
2773 int i;
2774
2775 for (i = 0; i < ARRAY_SIZE(aspeed_g6_pins); i++)
2776 aspeed_g6_pins[i].number = i;
2777
2778 return aspeed_pinctrl_probe(pdev, &aspeed_g6_pinctrl_desc,
2779 &aspeed_g6_pinctrl_data);
2780 }
2781
2782 static const struct of_device_id aspeed_g6_pinctrl_of_match[] = {
2783 { .compatible = "aspeed,ast2600-pinctrl", },
2784 { },
2785 };
2786
2787 static struct platform_driver aspeed_g6_pinctrl_driver = {
2788 .probe = aspeed_g6_pinctrl_probe,
2789 .driver = {
2790 .name = "aspeed-g6-pinctrl",
2791 .of_match_table = aspeed_g6_pinctrl_of_match,
2792 },
2793 };
2794
aspeed_g6_pinctrl_init(void)2795 static int aspeed_g6_pinctrl_init(void)
2796 {
2797 return platform_driver_register(&aspeed_g6_pinctrl_driver);
2798 }
2799
2800 arch_initcall(aspeed_g6_pinctrl_init);
2801