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Searched defs:UVD_MPC_SET_MUXB0__VARB_4__SHIFT (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h620 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
H A Duvd_3_1_sh_mask.h502 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 macro
H A Duvd_4_2_sh_mask.h506 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 macro
H A Duvd_4_0_sh_mask.h519 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x00000018 macro
H A Duvd_5_0_sh_mask.h538 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 macro
H A Duvd_6_0_sh_mask.h540 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1127 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
H A Dvcn_2_5_sh_mask.h2868 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h2633 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h2860 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h3941 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
H A Dvcn_4_0_5_sh_mask.h4058 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h4191 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h4234 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro