1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007 Hans Petter Selasky <hselasky@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _USS820_DCI_H_ 30 #define _USS820_DCI_H_ 31 32 #define USS820_MAX_DEVICES (USB_MIN_DEVICES + 1) 33 34 #define USS820_EP_MAX 8 /* maximum number of endpoints */ 35 36 #define USS820_TXDAT 0x00 /* Transmit FIFO data */ 37 38 #define USS820_TXCNTL 0x01 /* Transmit FIFO byte count low */ 39 #define USS820_TXCNTL_MASK 0xFF 40 41 #define USS820_TXCNTH 0x02 /* Transmit FIFO byte count high */ 42 #define USS820_TXCNTH_MASK 0x03 43 #define USS820_TXCNTH_UNUSED 0xFC 44 45 #define USS820_TXCON 0x03 /* USB transmit FIFO control */ 46 #define USS820_TXCON_REVRP 0x01 47 #define USS820_TXCON_ADVRM 0x02 48 #define USS820_TXCON_ATM 0x04 /* Automatic Transmit Management */ 49 #define USS820_TXCON_TXISO 0x08 /* Transmit Isochronous Data */ 50 #define USS820_TXCON_UNUSED 0x10 51 #define USS820_TXCON_FFSZ_16_64 0x00 52 #define USS820_TXCON_FFSZ_64_256 0x20 53 #define USS820_TXCON_FFSZ_8_512 0x40 54 #define USS820_TXCON_FFSZ_32_1024 0x60 55 #define USS820_TXCON_FFSZ_MASK 0x60 56 #define USS820_TXCON_TXCLR 0x80 /* Transmit FIFO clear */ 57 58 #define USS820_TXFLG 0x04 /* Transmit FIFO flag (Read Only) */ 59 #define USS820_TXFLG_TXOVF 0x01 /* TX overrun */ 60 #define USS820_TXFLG_TXURF 0x02 /* TX underrun */ 61 #define USS820_TXFLG_TXFULL 0x04 /* TX full */ 62 #define USS820_TXFLG_TXEMP 0x08 /* TX empty */ 63 #define USS820_TXFLG_UNUSED 0x30 64 #define USS820_TXFLG_TXFIF0 0x40 65 #define USS820_TXFLG_TXFIF1 0x80 66 67 #define USS820_RXDAT 0x05 /* Receive FIFO data */ 68 69 #define USS820_RXCNTL 0x06 /* Receive FIFO byte count low */ 70 #define USS820_RXCNTL_MASK 0xFF 71 72 #define USS820_RXCNTH 0x07 /* Receive FIFO byte count high */ 73 #define USS820_RXCNTH_MASK 0x03 74 #define USS820_RXCNTH_UNUSED 0xFC 75 76 #define USS820_RXCON 0x08 /* Receive FIFO control */ 77 #define USS820_RXCON_REVWP 0x01 78 #define USS820_RXCON_ADVWM 0x02 79 #define USS820_RXCON_ARM 0x04 /* Auto Receive Management */ 80 #define USS820_RXCON_RXISO 0x08 /* Receive Isochronous Data */ 81 #define USS820_RXCON_RXFFRC 0x10 /* FIFO Read Complete */ 82 #define USS820_RXCON_FFSZ_16_64 0x00 83 #define USS820_RXCON_FFSZ_64_256 0x20 84 #define USS820_RXCON_FFSZ_8_512 0x40 85 #define USS820_RXCON_FFSZ_32_1024 0x60 86 #define USS820_RXCON_RXCLR 0x80 /* Receive FIFO clear */ 87 88 #define USS820_RXFLG 0x09 /* Receive FIFO flag (Read Only) */ 89 #define USS820_RXFLG_RXOVF 0x01 /* RX overflow */ 90 #define USS820_RXFLG_RXURF 0x02 /* RX underflow */ 91 #define USS820_RXFLG_RXFULL 0x04 /* RX full */ 92 #define USS820_RXFLG_RXEMP 0x08 /* RX empty */ 93 #define USS820_RXFLG_RXFLUSH 0x10 /* RX flush */ 94 #define USS820_RXFLG_UNUSED 0x20 95 #define USS820_RXFLG_RXFIF0 0x40 96 #define USS820_RXFLG_RXFIF1 0x80 97 98 #define USS820_EPINDEX 0x0a /* Endpoint index selection */ 99 #define USS820_EPINDEX_MASK 0x07 100 #define USS820_EPINDEX_UNUSED 0xF8 101 102 #define USS820_EPCON 0x0b /* Endpoint control */ 103 #define USS820_EPCON_TXEPEN 0x01 /* Transmit Endpoint Enable */ 104 #define USS820_EPCON_TXOE 0x02 /* Transmit Output Enable */ 105 #define USS820_EPCON_RXEPEN 0x04 /* Receive Endpoint Enable */ 106 #define USS820_EPCON_RXIE 0x08 /* Receive Input Enable */ 107 #define USS820_EPCON_RXSPM 0x10 /* Receive Single-Packet Mode */ 108 #define USS820_EPCON_CTLEP 0x20 /* Control Endpoint */ 109 #define USS820_EPCON_TXSTL 0x40 /* Stall Transmit Endpoint */ 110 #define USS820_EPCON_RXSTL 0x80 /* Stall Receive Endpoint */ 111 112 #define USS820_TXSTAT 0x0c /* Transmit status */ 113 #define USS820_TXSTAT_TXACK 0x01 /* Transmit Acknowledge */ 114 #define USS820_TXSTAT_TXERR 0x02 /* Transmit Error */ 115 #define USS820_TXSTAT_TXVOID 0x04 /* Transmit Void */ 116 #define USS820_TXSTAT_TXSOVW 0x08 /* Transmit Data Sequence Overwrite 117 * Bit */ 118 #define USS820_TXSTAT_TXFLUSH 0x10 /* Transmit FIFO Packet Flushed */ 119 #define USS820_TXSTAT_TXNAKE 0x20 /* Transmit NAK Mode Enable */ 120 #define USS820_TXSTAT_TXDSAM 0x40 /* Transmit Data-Set-Available Mode */ 121 #define USS820_TXSTAT_TXSEQ 0x80 /* Transmitter Current Sequence Bit */ 122 123 #define USS820_RXSTAT 0x0d /* Receive status */ 124 #define USS820_RXSTAT_RXACK 0x01 /* Receive Acknowledge */ 125 #define USS820_RXSTAT_RXERR 0x02 /* Receive Error */ 126 #define USS820_RXSTAT_RXVOID 0x04 /* Receive Void */ 127 #define USS820_RXSTAT_RXSOVW 0x08 /* Receive Data Sequence Overwrite Bit */ 128 #define USS820_RXSTAT_EDOVW 0x10 /* End Overwrite Flag */ 129 #define USS820_RXSTAT_STOVW 0x20 /* Start Overwrite Flag */ 130 #define USS820_RXSTAT_RXSETUP 0x40 /* Received SETUP token */ 131 #define USS820_RXSTAT_RXSEQ 0x80 /* Receiver Endpoint Sequence Bit */ 132 133 #define USS820_SOFL 0x0e /* Start Of Frame counter low */ 134 #define USS820_SOFL_MASK 0xFF 135 136 #define USS820_SOFH 0x0f /* Start Of Frame counter high */ 137 #define USS820_SOFH_MASK 0x07 138 #define USS820_SOFH_SOFDIS 0x08 /* SOF Pin Output Disable */ 139 #define USS820_SOFH_FTLOCK 0x10 /* Frame Timer Lock */ 140 #define USS820_SOFH_SOFIE 0x20 /* SOF Interrupt Enable */ 141 #define USS820_SOFH_ASOF 0x40 /* Any Start of Frame */ 142 #define USS820_SOFH_SOFACK 0x80 /* SOF Token Received Without Error */ 143 144 #define USS820_FADDR 0x10 /* Function Address */ 145 #define USS820_FADDR_MASK 0x7F 146 #define USS820_FADDR_UNUSED 0x80 147 148 #define USS820_SCR 0x11 /* System Control */ 149 #define USS820_SCR_UNUSED 0x01 150 #define USS820_SCR_T_IRQ 0x02 /* Global Interrupt Enable */ 151 #define USS820_SCR_IRQLVL 0x04 /* Interrupt Mode */ 152 #define USS820_SCR_SRESET 0x08 /* Software reset */ 153 #define USS820_SCR_IE_RESET 0x10 /* Enable Reset Interrupt */ 154 #define USS820_SCR_IE_SUSP 0x20 /* Enable Suspend Interrupt */ 155 #define USS820_SCR_RWUPE 0x40 /* Enable Remote Wake-Up Feature */ 156 #define USS820_SCR_IRQPOL 0x80 /* IRQ polarity */ 157 158 #define USS820_SSR 0x12 /* System Status */ 159 #define USS820_SSR_RESET 0x01 /* Reset Condition Detected on USB 160 * cable */ 161 #define USS820_SSR_SUSPEND 0x02 /* Suspend Detected */ 162 #define USS820_SSR_RESUME 0x04 /* Resume Detected */ 163 #define USS820_SSR_SUSPDIS 0x08 /* Suspend Disable */ 164 #define USS820_SSR_SUSPPO 0x10 /* Suspend Power Off */ 165 #define USS820_SSR_UNUSED 0xE0 166 167 #define USS820_UNK0 0x13 /* Unknown */ 168 #define USS820_UNK0_UNUSED 0xFF 169 170 #define USS820_SBI 0x14 /* Serial bus interrupt low */ 171 #define USS820_SBI_FTXD0 0x01 /* Function Transmit Done, EP 0 */ 172 #define USS820_SBI_FRXD0 0x02 /* Function Receive Done, EP 0 */ 173 #define USS820_SBI_FTXD1 0x04 174 #define USS820_SBI_FRXD1 0x08 175 #define USS820_SBI_FTXD2 0x10 176 #define USS820_SBI_FRXD2 0x20 177 #define USS820_SBI_FTXD3 0x40 178 #define USS820_SBI_FRXD3 0x80 179 180 #define USS820_SBI1 0x15 /* Serial bus interrupt high */ 181 #define USS820_SBI1_FTXD4 0x01 182 #define USS820_SBI1_FRXD4 0x02 183 #define USS820_SBI1_FTXD5 0x04 184 #define USS820_SBI1_FRXD5 0x08 185 #define USS820_SBI1_FTXD6 0x10 186 #define USS820_SBI1_FRXD6 0x20 187 #define USS820_SBI1_FTXD7 0x40 188 #define USS820_SBI1_FRXD7 0x80 189 190 #define USS820_SBIE 0x16 /* Serial bus interrupt enable low */ 191 #define USS820_SBIE_FTXIE0 0x01 192 #define USS820_SBIE_FRXIE0 0x02 193 #define USS820_SBIE_FTXIE1 0x04 194 #define USS820_SBIE_FRXIE1 0x08 195 #define USS820_SBIE_FTXIE2 0x10 196 #define USS820_SBIE_FRXIE2 0x20 197 #define USS820_SBIE_FTXIE3 0x40 198 #define USS820_SBIE_FRXIE3 0x80 199 200 #define USS820_SBIE1 0x17 /* Serial bus interrupt enable high */ 201 #define USS820_SBIE1_FTXIE4 0x01 202 #define USS820_SBIE1_FRXIE4 0x02 203 #define USS820_SBIE1_FTXIE5 0x04 204 #define USS820_SBIE1_FRXIE5 0x08 205 #define USS820_SBIE1_FTXIE6 0x10 206 #define USS820_SBIE1_FRXIE6 0x20 207 #define USS820_SBIE1_FTXIE7 0x40 208 #define USS820_SBIE1_FRXIE7 0x80 209 210 #define USS820_REV 0x18 /* Hardware revision */ 211 #define USS820_REV_MIN 0x0F 212 #define USS820_REV_MAJ 0xF0 213 214 #define USS820_LOCK 0x19 /* Suspend power-off locking */ 215 #define USS820_LOCK_UNLOCKED 0x01 216 #define USS820_LOCK_UNUSED 0xFE 217 218 #define USS820_PEND 0x1a /* Pend hardware status update */ 219 #define USS820_PEND_PEND 0x01 220 #define USS820_PEND_UNUSED 0xFE 221 222 #define USS820_SCRATCH 0x1b /* Scratch firmware information */ 223 #define USS820_SCRATCH_MASK 0x7F 224 #define USS820_SCRATCH_IE_RESUME 0x80 /* Enable Resume Interrupt */ 225 226 #define USS820_MCSR 0x1c /* Miscellaneous control and status */ 227 #define USS820_MCSR_DPEN 0x01 /* DPLS Pull-Up Enable */ 228 #define USS820_MCSR_SUSPLOE 0x02 /* Suspend Lock Out Enable */ 229 #define USS820_MCSR_BDFEAT 0x04 /* Board Feature Enable */ 230 #define USS820_MCSR_FEAT 0x08 /* Feature Enable */ 231 #define USS820_MCSR_PKGID 0x10 /* Package Identification */ 232 #define USS820_MCSR_SUSPS 0x20 /* Suspend Status */ 233 #define USS820_MCSR_INIT 0x40 /* Device Initialized */ 234 #define USS820_MCSR_RWUPR 0x80 /* Remote Wakeup-Up Remember */ 235 236 #define USS820_DSAV 0x1d /* Data set available low (Read Only) */ 237 #define USS820_DSAV_TXAV0 0x01 238 #define USS820_DSAV_RXAV0 0x02 239 #define USS820_DSAV_TXAV1 0x04 240 #define USS820_DSAV_RXAV1 0x08 241 #define USS820_DSAV_TXAV2 0x10 242 #define USS820_DSAV_RXAV2 0x20 243 #define USS820_DSAV_TXAV3 0x40 244 #define USS820_DSAV_RXAV3 0x80 245 246 #define USS820_DSAV1 0x1e /* Data set available high */ 247 #define USS820_DSAV1_TXAV4 0x01 248 #define USS820_DSAV1_RXAV4 0x02 249 #define USS820_DSAV1_TXAV5 0x04 250 #define USS820_DSAV1_RXAV5 0x08 251 #define USS820_DSAV1_TXAV6 0x10 252 #define USS820_DSAV1_RXAV6 0x20 253 #define USS820_DSAV1_TXAV7 0x40 254 #define USS820_DSAV1_RXAV7 0x80 255 256 #define USS820_UNK1 0x1f /* Unknown */ 257 #define USS820_UNK1_UNKNOWN 0xFF 258 259 #ifndef USS820_REG_STRIDE 260 #define USS820_REG_STRIDE 1 261 #endif 262 263 #define USS820_READ_1(sc, reg) \ 264 bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (reg) * USS820_REG_STRIDE) 265 266 #define USS820_WRITE_1(sc, reg, data) \ 267 bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (reg) * USS820_REG_STRIDE, (data)) 268 269 struct uss820dci_td; 270 struct uss820dci_softc; 271 272 typedef uint8_t (uss820dci_cmd_t)(struct uss820dci_softc *, struct uss820dci_td *td); 273 274 struct uss820dci_td { 275 struct uss820dci_td *obj_next; 276 uss820dci_cmd_t *func; 277 struct usb_page_cache *pc; 278 uint32_t offset; 279 uint32_t remainder; 280 uint16_t max_packet_size; 281 uint8_t ep_index; 282 uint8_t error:1; 283 uint8_t alt_next:1; 284 uint8_t short_pkt:1; 285 uint8_t support_multi_buffer:1; 286 uint8_t did_stall:1; 287 uint8_t did_enable:1; 288 }; 289 290 struct uss820_std_temp { 291 uss820dci_cmd_t *func; 292 struct usb_page_cache *pc; 293 struct uss820dci_td *td; 294 struct uss820dci_td *td_next; 295 uint32_t len; 296 uint32_t offset; 297 uint16_t max_frame_size; 298 uint8_t short_pkt; 299 /* 300 * short_pkt = 0: transfer should be short terminated 301 * short_pkt = 1: transfer should not be short terminated 302 */ 303 uint8_t setup_alt_next; 304 uint8_t did_stall; 305 }; 306 307 struct uss820dci_config_desc { 308 struct usb_config_descriptor confd; 309 struct usb_interface_descriptor ifcd; 310 struct usb_endpoint_descriptor endpd; 311 } __packed; 312 313 union uss820_hub_temp { 314 uWord wValue; 315 struct usb_port_status ps; 316 }; 317 318 struct uss820_flags { 319 uint8_t change_connect:1; 320 uint8_t change_suspend:1; 321 uint8_t status_suspend:1; /* set if suspended */ 322 uint8_t status_vbus:1; /* set if present */ 323 uint8_t status_bus_reset:1; /* set if reset complete */ 324 uint8_t clocks_off:1; 325 uint8_t port_powered:1; 326 uint8_t port_enabled:1; 327 uint8_t d_pulled_up:1; 328 uint8_t mcsr_feat:1; 329 }; 330 331 struct uss820dci_softc { 332 struct usb_bus sc_bus; 333 union uss820_hub_temp sc_hub_temp; 334 335 struct usb_device *sc_devices[USS820_MAX_DEVICES]; 336 struct resource *sc_io_res; 337 struct resource *sc_irq_res; 338 void *sc_intr_hdl; 339 bus_size_t sc_io_size; 340 bus_space_tag_t sc_io_tag; 341 bus_space_handle_t sc_io_hdl; 342 343 uint32_t sc_xfer_complete; 344 345 uint8_t sc_rt_addr; /* root HUB address */ 346 uint8_t sc_dv_addr; /* device address */ 347 uint8_t sc_conf; /* root HUB config */ 348 349 uint8_t sc_hub_idata[1]; 350 351 struct uss820_flags sc_flags; 352 }; 353 354 /* prototypes */ 355 356 usb_error_t uss820dci_init(struct uss820dci_softc *sc); 357 void uss820dci_uninit(struct uss820dci_softc *sc); 358 driver_filter_t uss820dci_filter_interrupt; 359 driver_intr_t uss820dci_interrupt; 360 361 #endif /* _USS820_DCI_H_ */ 362