1
2 /*-
3 * Copyright (c) 2005, 2006
4 * Damien Bergamini <damien.bergamini@free.fr>
5 *
6 * Copyright (c) 2006, 2008
7 * Hans Petter Selasky <hselasky@FreeBSD.org>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 */
21
22 /*-
23 * Ralink Technology RT2500USB chipset driver
24 * http://www.ralinktech.com/
25 */
26
27 #include "opt_wlan.h"
28
29 #include <sys/param.h>
30 #include <sys/sockio.h>
31 #include <sys/sysctl.h>
32 #include <sys/lock.h>
33 #include <sys/mutex.h>
34 #include <sys/mbuf.h>
35 #include <sys/kernel.h>
36 #include <sys/socket.h>
37 #include <sys/systm.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/bus.h>
41 #include <sys/endian.h>
42 #include <sys/kdb.h>
43
44 #include <net/bpf.h>
45 #include <net/if.h>
46 #include <net/if_var.h>
47 #include <net/if_arp.h>
48 #include <net/ethernet.h>
49 #include <net/if_dl.h>
50 #include <net/if_media.h>
51 #include <net/if_types.h>
52
53 #ifdef INET
54 #include <netinet/in.h>
55 #include <netinet/in_systm.h>
56 #include <netinet/in_var.h>
57 #include <netinet/if_ether.h>
58 #include <netinet/ip.h>
59 #endif
60
61 #include <net80211/ieee80211_var.h>
62 #include <net80211/ieee80211_regdomain.h>
63 #include <net80211/ieee80211_radiotap.h>
64 #include <net80211/ieee80211_ratectl.h>
65
66 #include <dev/usb/usb.h>
67 #include <dev/usb/usbdi.h>
68 #include "usbdevs.h"
69
70 #define USB_DEBUG_VAR ural_debug
71 #include <dev/usb/usb_debug.h>
72
73 #include <dev/usb/wlan/if_uralreg.h>
74 #include <dev/usb/wlan/if_uralvar.h>
75
76 #ifdef USB_DEBUG
77 static int ural_debug = 0;
78
79 static SYSCTL_NODE(_hw_usb, OID_AUTO, ural, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
80 "USB ural");
81 SYSCTL_INT(_hw_usb_ural, OID_AUTO, debug, CTLFLAG_RWTUN, &ural_debug, 0,
82 "Debug level");
83 #endif
84
85 #define URAL_RSSI(rssi) \
86 ((rssi) > (RAL_NOISE_FLOOR + RAL_RSSI_CORR) ? \
87 ((rssi) - (RAL_NOISE_FLOOR + RAL_RSSI_CORR)) : 0)
88
89 /* various supported device vendors/products */
90 static const STRUCT_USB_HOST_ID ural_devs[] = {
91 #define URAL_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) }
92 URAL_DEV(ASUS, WL167G),
93 URAL_DEV(ASUS, RT2570),
94 URAL_DEV(BELKIN, F5D7050),
95 URAL_DEV(BELKIN, F5D7051),
96 URAL_DEV(CISCOLINKSYS, HU200TS),
97 URAL_DEV(CISCOLINKSYS, WUSB54G),
98 URAL_DEV(CISCOLINKSYS, WUSB54GP),
99 URAL_DEV(CONCEPTRONIC2, C54RU),
100 URAL_DEV(DLINK, DWLG122),
101 URAL_DEV(GIGABYTE, GN54G),
102 URAL_DEV(GIGABYTE, GNWBKG),
103 URAL_DEV(GUILLEMOT, HWGUSB254),
104 URAL_DEV(MELCO, KG54),
105 URAL_DEV(MELCO, KG54AI),
106 URAL_DEV(MELCO, KG54YB),
107 URAL_DEV(MELCO, NINWIFI),
108 URAL_DEV(MSI, RT2570),
109 URAL_DEV(MSI, RT2570_2),
110 URAL_DEV(MSI, RT2570_3),
111 URAL_DEV(NOVATECH, NV902),
112 URAL_DEV(RALINK, RT2570),
113 URAL_DEV(RALINK, RT2570_2),
114 URAL_DEV(RALINK, RT2570_3),
115 URAL_DEV(SIEMENS2, WL54G),
116 URAL_DEV(SMC, 2862WG),
117 URAL_DEV(SPHAIRON, UB801R),
118 URAL_DEV(SURECOM, RT2570),
119 URAL_DEV(VTECH, RT2570),
120 URAL_DEV(ZINWELL, RT2570),
121 #undef URAL_DEV
122 };
123
124 static usb_callback_t ural_bulk_read_callback;
125 static usb_callback_t ural_bulk_write_callback;
126
127 static usb_error_t ural_do_request(struct ural_softc *sc,
128 struct usb_device_request *req, void *data);
129 static struct ieee80211vap *ural_vap_create(struct ieee80211com *,
130 const char [IFNAMSIZ], int, enum ieee80211_opmode,
131 int, const uint8_t [IEEE80211_ADDR_LEN],
132 const uint8_t [IEEE80211_ADDR_LEN]);
133 static void ural_vap_delete(struct ieee80211vap *);
134 static void ural_tx_free(struct ural_tx_data *, int);
135 static void ural_setup_tx_list(struct ural_softc *);
136 static void ural_unsetup_tx_list(struct ural_softc *);
137 static int ural_newstate(struct ieee80211vap *,
138 enum ieee80211_state, int);
139 static void ural_setup_tx_desc(struct ural_softc *,
140 struct ural_tx_desc *, uint32_t, int, int);
141 static int ural_tx_bcn(struct ural_softc *, struct mbuf *,
142 struct ieee80211_node *);
143 static int ural_tx_mgt(struct ural_softc *, struct mbuf *,
144 struct ieee80211_node *);
145 static int ural_tx_data(struct ural_softc *, struct mbuf *,
146 struct ieee80211_node *);
147 static int ural_transmit(struct ieee80211com *, struct mbuf *);
148 static void ural_start(struct ural_softc *);
149 static void ural_parent(struct ieee80211com *);
150 static void ural_set_testmode(struct ural_softc *);
151 static void ural_eeprom_read(struct ural_softc *, uint16_t, void *,
152 int);
153 static uint16_t ural_read(struct ural_softc *, uint16_t);
154 static void ural_read_multi(struct ural_softc *, uint16_t, void *,
155 int);
156 static void ural_write(struct ural_softc *, uint16_t, uint16_t);
157 static void ural_write_multi(struct ural_softc *, uint16_t, void *,
158 int) __unused;
159 static void ural_bbp_write(struct ural_softc *, uint8_t, uint8_t);
160 static uint8_t ural_bbp_read(struct ural_softc *, uint8_t);
161 static void ural_rf_write(struct ural_softc *, uint8_t, uint32_t);
162 static void ural_scan_start(struct ieee80211com *);
163 static void ural_scan_end(struct ieee80211com *);
164 static void ural_getradiocaps(struct ieee80211com *, int, int *,
165 struct ieee80211_channel[]);
166 static void ural_set_channel(struct ieee80211com *);
167 static void ural_set_chan(struct ural_softc *,
168 struct ieee80211_channel *);
169 static void ural_disable_rf_tune(struct ural_softc *);
170 static void ural_enable_tsf_sync(struct ural_softc *);
171 static void ural_enable_tsf(struct ural_softc *);
172 static void ural_update_slot(struct ural_softc *);
173 static void ural_set_txpreamble(struct ural_softc *);
174 static void ural_set_basicrates(struct ural_softc *,
175 const struct ieee80211_channel *);
176 static void ural_set_bssid(struct ural_softc *, const uint8_t *);
177 static void ural_set_macaddr(struct ural_softc *, const uint8_t *);
178 static void ural_update_promisc(struct ieee80211com *);
179 static void ural_setpromisc(struct ural_softc *);
180 static const char *ural_get_rf(int);
181 static void ural_read_eeprom(struct ural_softc *);
182 static int ural_bbp_init(struct ural_softc *);
183 static void ural_set_txantenna(struct ural_softc *, int);
184 static void ural_set_rxantenna(struct ural_softc *, int);
185 static void ural_init(struct ural_softc *);
186 static void ural_stop(struct ural_softc *);
187 static int ural_raw_xmit(struct ieee80211_node *, struct mbuf *,
188 const struct ieee80211_bpf_params *);
189 static void ural_ratectl_start(struct ural_softc *,
190 struct ieee80211_node *);
191 static void ural_ratectl_timeout(void *);
192 static void ural_ratectl_task(void *, int);
193 static int ural_pause(struct ural_softc *sc, int timeout);
194
195 /*
196 * Default values for MAC registers; values taken from the reference driver.
197 */
198 static const struct {
199 uint16_t reg;
200 uint16_t val;
201 } ural_def_mac[] = {
202 { RAL_TXRX_CSR5, 0x8c8d },
203 { RAL_TXRX_CSR6, 0x8b8a },
204 { RAL_TXRX_CSR7, 0x8687 },
205 { RAL_TXRX_CSR8, 0x0085 },
206 { RAL_MAC_CSR13, 0x1111 },
207 { RAL_MAC_CSR14, 0x1e11 },
208 { RAL_TXRX_CSR21, 0xe78f },
209 { RAL_MAC_CSR9, 0xff1d },
210 { RAL_MAC_CSR11, 0x0002 },
211 { RAL_MAC_CSR22, 0x0053 },
212 { RAL_MAC_CSR15, 0x0000 },
213 { RAL_MAC_CSR8, RAL_FRAME_SIZE },
214 { RAL_TXRX_CSR19, 0x0000 },
215 { RAL_TXRX_CSR18, 0x005a },
216 { RAL_PHY_CSR2, 0x0000 },
217 { RAL_TXRX_CSR0, 0x1ec0 },
218 { RAL_PHY_CSR4, 0x000f }
219 };
220
221 /*
222 * Default values for BBP registers; values taken from the reference driver.
223 */
224 static const struct {
225 uint8_t reg;
226 uint8_t val;
227 } ural_def_bbp[] = {
228 { 3, 0x02 },
229 { 4, 0x19 },
230 { 14, 0x1c },
231 { 15, 0x30 },
232 { 16, 0xac },
233 { 17, 0x48 },
234 { 18, 0x18 },
235 { 19, 0xff },
236 { 20, 0x1e },
237 { 21, 0x08 },
238 { 22, 0x08 },
239 { 23, 0x08 },
240 { 24, 0x80 },
241 { 25, 0x50 },
242 { 26, 0x08 },
243 { 27, 0x23 },
244 { 30, 0x10 },
245 { 31, 0x2b },
246 { 32, 0xb9 },
247 { 34, 0x12 },
248 { 35, 0x50 },
249 { 39, 0xc4 },
250 { 40, 0x02 },
251 { 41, 0x60 },
252 { 53, 0x10 },
253 { 54, 0x18 },
254 { 56, 0x08 },
255 { 57, 0x10 },
256 { 58, 0x08 },
257 { 61, 0x60 },
258 { 62, 0x10 },
259 { 75, 0xff }
260 };
261
262 /*
263 * Default values for RF register R2 indexed by channel numbers.
264 */
265 static const uint32_t ural_rf2522_r2[] = {
266 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814,
267 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e
268 };
269
270 static const uint32_t ural_rf2523_r2[] = {
271 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d,
272 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346
273 };
274
275 static const uint32_t ural_rf2524_r2[] = {
276 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d,
277 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346
278 };
279
280 static const uint32_t ural_rf2525_r2[] = {
281 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d,
282 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346
283 };
284
285 static const uint32_t ural_rf2525_hi_r2[] = {
286 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345,
287 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e
288 };
289
290 static const uint32_t ural_rf2525e_r2[] = {
291 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463,
292 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b
293 };
294
295 static const uint32_t ural_rf2526_hi_r2[] = {
296 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d,
297 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241
298 };
299
300 static const uint32_t ural_rf2526_r2[] = {
301 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229,
302 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d
303 };
304
305 /*
306 * For dual-band RF, RF registers R1 and R4 also depend on channel number;
307 * values taken from the reference driver.
308 */
309 static const struct {
310 uint8_t chan;
311 uint32_t r1;
312 uint32_t r2;
313 uint32_t r4;
314 } ural_rf5222[] = {
315 { 1, 0x08808, 0x0044d, 0x00282 },
316 { 2, 0x08808, 0x0044e, 0x00282 },
317 { 3, 0x08808, 0x0044f, 0x00282 },
318 { 4, 0x08808, 0x00460, 0x00282 },
319 { 5, 0x08808, 0x00461, 0x00282 },
320 { 6, 0x08808, 0x00462, 0x00282 },
321 { 7, 0x08808, 0x00463, 0x00282 },
322 { 8, 0x08808, 0x00464, 0x00282 },
323 { 9, 0x08808, 0x00465, 0x00282 },
324 { 10, 0x08808, 0x00466, 0x00282 },
325 { 11, 0x08808, 0x00467, 0x00282 },
326 { 12, 0x08808, 0x00468, 0x00282 },
327 { 13, 0x08808, 0x00469, 0x00282 },
328 { 14, 0x08808, 0x0046b, 0x00286 },
329
330 { 36, 0x08804, 0x06225, 0x00287 },
331 { 40, 0x08804, 0x06226, 0x00287 },
332 { 44, 0x08804, 0x06227, 0x00287 },
333 { 48, 0x08804, 0x06228, 0x00287 },
334 { 52, 0x08804, 0x06229, 0x00287 },
335 { 56, 0x08804, 0x0622a, 0x00287 },
336 { 60, 0x08804, 0x0622b, 0x00287 },
337 { 64, 0x08804, 0x0622c, 0x00287 },
338
339 { 100, 0x08804, 0x02200, 0x00283 },
340 { 104, 0x08804, 0x02201, 0x00283 },
341 { 108, 0x08804, 0x02202, 0x00283 },
342 { 112, 0x08804, 0x02203, 0x00283 },
343 { 116, 0x08804, 0x02204, 0x00283 },
344 { 120, 0x08804, 0x02205, 0x00283 },
345 { 124, 0x08804, 0x02206, 0x00283 },
346 { 128, 0x08804, 0x02207, 0x00283 },
347 { 132, 0x08804, 0x02208, 0x00283 },
348 { 136, 0x08804, 0x02209, 0x00283 },
349 { 140, 0x08804, 0x0220a, 0x00283 },
350
351 { 149, 0x08808, 0x02429, 0x00281 },
352 { 153, 0x08808, 0x0242b, 0x00281 },
353 { 157, 0x08808, 0x0242d, 0x00281 },
354 { 161, 0x08808, 0x0242f, 0x00281 }
355 };
356
357 static const uint8_t ural_chan_5ghz[] =
358 { 36, 40, 44, 48, 52, 56, 60, 64,
359 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140,
360 149, 153, 157, 161 };
361
362 static const struct usb_config ural_config[URAL_N_TRANSFER] = {
363 [URAL_BULK_WR] = {
364 .type = UE_BULK,
365 .endpoint = UE_ADDR_ANY,
366 .direction = UE_DIR_OUT,
367 .bufsize = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE + 4),
368 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
369 .callback = ural_bulk_write_callback,
370 .timeout = 5000, /* ms */
371 },
372 [URAL_BULK_RD] = {
373 .type = UE_BULK,
374 .endpoint = UE_ADDR_ANY,
375 .direction = UE_DIR_IN,
376 .bufsize = (RAL_FRAME_SIZE + RAL_RX_DESC_SIZE),
377 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
378 .callback = ural_bulk_read_callback,
379 },
380 };
381
382 static device_probe_t ural_match;
383 static device_attach_t ural_attach;
384 static device_detach_t ural_detach;
385
386 static device_method_t ural_methods[] = {
387 /* Device interface */
388 DEVMETHOD(device_probe, ural_match),
389 DEVMETHOD(device_attach, ural_attach),
390 DEVMETHOD(device_detach, ural_detach),
391 DEVMETHOD_END
392 };
393
394 static driver_t ural_driver = {
395 .name = "ural",
396 .methods = ural_methods,
397 .size = sizeof(struct ural_softc),
398 };
399
400 DRIVER_MODULE(ural, uhub, ural_driver, NULL, NULL);
401 MODULE_DEPEND(ural, usb, 1, 1, 1);
402 MODULE_DEPEND(ural, wlan, 1, 1, 1);
403 MODULE_VERSION(ural, 1);
404 USB_PNP_HOST_INFO(ural_devs);
405
406 static int
ural_match(device_t self)407 ural_match(device_t self)
408 {
409 struct usb_attach_arg *uaa = device_get_ivars(self);
410
411 if (uaa->usb_mode != USB_MODE_HOST)
412 return (ENXIO);
413 if (uaa->info.bConfigIndex != 0)
414 return (ENXIO);
415 if (uaa->info.bIfaceIndex != RAL_IFACE_INDEX)
416 return (ENXIO);
417
418 return (usbd_lookup_id_by_uaa(ural_devs, sizeof(ural_devs), uaa));
419 }
420
421 static int
ural_attach(device_t self)422 ural_attach(device_t self)
423 {
424 struct usb_attach_arg *uaa = device_get_ivars(self);
425 struct ural_softc *sc = device_get_softc(self);
426 struct ieee80211com *ic = &sc->sc_ic;
427 uint8_t iface_index;
428 int error;
429
430 device_set_usb_desc(self);
431 sc->sc_udev = uaa->device;
432 sc->sc_dev = self;
433
434 mtx_init(&sc->sc_mtx, device_get_nameunit(self),
435 MTX_NETWORK_LOCK, MTX_DEF);
436 mbufq_init(&sc->sc_snd, ifqmaxlen);
437
438 iface_index = RAL_IFACE_INDEX;
439 error = usbd_transfer_setup(uaa->device,
440 &iface_index, sc->sc_xfer, ural_config,
441 URAL_N_TRANSFER, sc, &sc->sc_mtx);
442 if (error) {
443 device_printf(self, "could not allocate USB transfers, "
444 "err=%s\n", usbd_errstr(error));
445 goto detach;
446 }
447
448 RAL_LOCK(sc);
449 /* retrieve RT2570 rev. no */
450 sc->asic_rev = ural_read(sc, RAL_MAC_CSR0);
451
452 /* retrieve MAC address and various other things from EEPROM */
453 ural_read_eeprom(sc);
454 RAL_UNLOCK(sc);
455
456 device_printf(self, "MAC/BBP RT2570 (rev 0x%02x), RF %s\n",
457 sc->asic_rev, ural_get_rf(sc->rf_rev));
458
459 ic->ic_softc = sc;
460 ic->ic_name = device_get_nameunit(self);
461 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
462
463 /* set device capabilities */
464 ic->ic_caps =
465 IEEE80211_C_STA /* station mode supported */
466 | IEEE80211_C_IBSS /* IBSS mode supported */
467 | IEEE80211_C_MONITOR /* monitor mode supported */
468 | IEEE80211_C_HOSTAP /* HostAp mode supported */
469 | IEEE80211_C_TXPMGT /* tx power management */
470 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
471 | IEEE80211_C_SHSLOT /* short slot time supported */
472 | IEEE80211_C_BGSCAN /* bg scanning supported */
473 | IEEE80211_C_WPA /* 802.11i */
474 ;
475
476 ural_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans,
477 ic->ic_channels);
478
479 ieee80211_ifattach(ic);
480 ic->ic_update_promisc = ural_update_promisc;
481 ic->ic_raw_xmit = ural_raw_xmit;
482 ic->ic_scan_start = ural_scan_start;
483 ic->ic_scan_end = ural_scan_end;
484 ic->ic_getradiocaps = ural_getradiocaps;
485 ic->ic_set_channel = ural_set_channel;
486 ic->ic_parent = ural_parent;
487 ic->ic_transmit = ural_transmit;
488 ic->ic_vap_create = ural_vap_create;
489 ic->ic_vap_delete = ural_vap_delete;
490
491 ieee80211_radiotap_attach(ic,
492 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
493 RAL_TX_RADIOTAP_PRESENT,
494 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
495 RAL_RX_RADIOTAP_PRESENT);
496
497 if (bootverbose)
498 ieee80211_announce(ic);
499
500 return (0);
501
502 detach:
503 ural_detach(self);
504 return (ENXIO); /* failure */
505 }
506
507 static int
ural_detach(device_t self)508 ural_detach(device_t self)
509 {
510 struct ural_softc *sc = device_get_softc(self);
511 struct ieee80211com *ic = &sc->sc_ic;
512
513 /* prevent further ioctls */
514 RAL_LOCK(sc);
515 sc->sc_detached = 1;
516 RAL_UNLOCK(sc);
517
518 /* stop all USB transfers */
519 usbd_transfer_unsetup(sc->sc_xfer, URAL_N_TRANSFER);
520
521 /* free TX list, if any */
522 RAL_LOCK(sc);
523 ural_unsetup_tx_list(sc);
524 RAL_UNLOCK(sc);
525
526 if (ic->ic_softc == sc)
527 ieee80211_ifdetach(ic);
528 mbufq_drain(&sc->sc_snd);
529 mtx_destroy(&sc->sc_mtx);
530
531 return (0);
532 }
533
534 static usb_error_t
ural_do_request(struct ural_softc * sc,struct usb_device_request * req,void * data)535 ural_do_request(struct ural_softc *sc,
536 struct usb_device_request *req, void *data)
537 {
538 usb_error_t err;
539 int ntries = 10;
540
541 while (ntries--) {
542 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx,
543 req, data, 0, NULL, 250 /* ms */);
544 if (err == 0)
545 break;
546
547 DPRINTFN(1, "Control request failed, %s (retrying)\n",
548 usbd_errstr(err));
549 if (ural_pause(sc, hz / 100))
550 break;
551 }
552 return (err);
553 }
554
555 static struct ieee80211vap *
ural_vap_create(struct ieee80211com * ic,const char name[IFNAMSIZ],int unit,enum ieee80211_opmode opmode,int flags,const uint8_t bssid[IEEE80211_ADDR_LEN],const uint8_t mac[IEEE80211_ADDR_LEN])556 ural_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
557 enum ieee80211_opmode opmode, int flags,
558 const uint8_t bssid[IEEE80211_ADDR_LEN],
559 const uint8_t mac[IEEE80211_ADDR_LEN])
560 {
561 struct ural_softc *sc = ic->ic_softc;
562 struct ural_vap *uvp;
563 struct ieee80211vap *vap;
564
565 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
566 return NULL;
567 uvp = malloc(sizeof(struct ural_vap), M_80211_VAP, M_WAITOK | M_ZERO);
568 vap = &uvp->vap;
569 /* enable s/w bmiss handling for sta mode */
570
571 if (ieee80211_vap_setup(ic, vap, name, unit, opmode,
572 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) {
573 /* out of memory */
574 free(uvp, M_80211_VAP);
575 return (NULL);
576 }
577
578 /* override state transition machine */
579 uvp->newstate = vap->iv_newstate;
580 vap->iv_newstate = ural_newstate;
581
582 usb_callout_init_mtx(&uvp->ratectl_ch, &sc->sc_mtx, 0);
583 TASK_INIT(&uvp->ratectl_task, 0, ural_ratectl_task, uvp);
584 ieee80211_ratectl_init(vap);
585 ieee80211_ratectl_setinterval(vap, 1000 /* 1 sec */);
586
587 /* complete setup */
588 ieee80211_vap_attach(vap, ieee80211_media_change,
589 ieee80211_media_status, mac);
590 ic->ic_opmode = opmode;
591 return vap;
592 }
593
594 static void
ural_vap_delete(struct ieee80211vap * vap)595 ural_vap_delete(struct ieee80211vap *vap)
596 {
597 struct ural_vap *uvp = URAL_VAP(vap);
598 struct ieee80211com *ic = vap->iv_ic;
599
600 usb_callout_drain(&uvp->ratectl_ch);
601 ieee80211_draintask(ic, &uvp->ratectl_task);
602 ieee80211_ratectl_deinit(vap);
603 ieee80211_vap_detach(vap);
604 free(uvp, M_80211_VAP);
605 }
606
607 static void
ural_tx_free(struct ural_tx_data * data,int txerr)608 ural_tx_free(struct ural_tx_data *data, int txerr)
609 {
610 struct ural_softc *sc = data->sc;
611
612 if (data->m != NULL) {
613 ieee80211_tx_complete(data->ni, data->m, txerr);
614 data->m = NULL;
615 data->ni = NULL;
616 }
617 STAILQ_INSERT_TAIL(&sc->tx_free, data, next);
618 sc->tx_nfree++;
619 }
620
621 static void
ural_setup_tx_list(struct ural_softc * sc)622 ural_setup_tx_list(struct ural_softc *sc)
623 {
624 struct ural_tx_data *data;
625 int i;
626
627 sc->tx_nfree = 0;
628 STAILQ_INIT(&sc->tx_q);
629 STAILQ_INIT(&sc->tx_free);
630
631 for (i = 0; i < RAL_TX_LIST_COUNT; i++) {
632 data = &sc->tx_data[i];
633
634 data->sc = sc;
635 STAILQ_INSERT_TAIL(&sc->tx_free, data, next);
636 sc->tx_nfree++;
637 }
638 }
639
640 static void
ural_unsetup_tx_list(struct ural_softc * sc)641 ural_unsetup_tx_list(struct ural_softc *sc)
642 {
643 struct ural_tx_data *data;
644 int i;
645
646 /* make sure any subsequent use of the queues will fail */
647 sc->tx_nfree = 0;
648 STAILQ_INIT(&sc->tx_q);
649 STAILQ_INIT(&sc->tx_free);
650
651 /* free up all node references and mbufs */
652 for (i = 0; i < RAL_TX_LIST_COUNT; i++) {
653 data = &sc->tx_data[i];
654
655 if (data->m != NULL) {
656 m_freem(data->m);
657 data->m = NULL;
658 }
659 if (data->ni != NULL) {
660 ieee80211_free_node(data->ni);
661 data->ni = NULL;
662 }
663 }
664 }
665
666 static int
ural_newstate(struct ieee80211vap * vap,enum ieee80211_state nstate,int arg)667 ural_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
668 {
669 struct ural_vap *uvp = URAL_VAP(vap);
670 struct ieee80211com *ic = vap->iv_ic;
671 struct ural_softc *sc = ic->ic_softc;
672 const struct ieee80211_txparam *tp;
673 struct ieee80211_node *ni;
674 struct mbuf *m;
675
676 DPRINTF("%s -> %s\n",
677 ieee80211_state_name[vap->iv_state],
678 ieee80211_state_name[nstate]);
679
680 IEEE80211_UNLOCK(ic);
681 RAL_LOCK(sc);
682 usb_callout_stop(&uvp->ratectl_ch);
683
684 switch (nstate) {
685 case IEEE80211_S_INIT:
686 if (vap->iv_state == IEEE80211_S_RUN) {
687 /* abort TSF synchronization */
688 ural_write(sc, RAL_TXRX_CSR19, 0);
689
690 /* force tx led to stop blinking */
691 ural_write(sc, RAL_MAC_CSR20, 0);
692 }
693 break;
694
695 case IEEE80211_S_RUN:
696 ni = ieee80211_ref_node(vap->iv_bss);
697
698 if (vap->iv_opmode != IEEE80211_M_MONITOR) {
699 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC)
700 goto fail;
701
702 ural_update_slot(sc);
703 ural_set_txpreamble(sc);
704 ural_set_basicrates(sc, ic->ic_bsschan);
705 IEEE80211_ADDR_COPY(sc->sc_bssid, ni->ni_bssid);
706 ural_set_bssid(sc, sc->sc_bssid);
707 }
708
709 if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
710 vap->iv_opmode == IEEE80211_M_IBSS) {
711 m = ieee80211_beacon_alloc(ni);
712 if (m == NULL) {
713 device_printf(sc->sc_dev,
714 "could not allocate beacon\n");
715 goto fail;
716 }
717 ieee80211_ref_node(ni);
718 if (ural_tx_bcn(sc, m, ni) != 0) {
719 device_printf(sc->sc_dev,
720 "could not send beacon\n");
721 goto fail;
722 }
723 }
724
725 /* make tx led blink on tx (controlled by ASIC) */
726 ural_write(sc, RAL_MAC_CSR20, 1);
727
728 if (vap->iv_opmode != IEEE80211_M_MONITOR)
729 ural_enable_tsf_sync(sc);
730 else
731 ural_enable_tsf(sc);
732
733 /* enable automatic rate adaptation */
734 /* XXX should use ic_bsschan but not valid until after newstate call below */
735 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)];
736 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE)
737 ural_ratectl_start(sc, ni);
738 ieee80211_free_node(ni);
739 break;
740
741 default:
742 break;
743 }
744 RAL_UNLOCK(sc);
745 IEEE80211_LOCK(ic);
746 return (uvp->newstate(vap, nstate, arg));
747
748 fail:
749 RAL_UNLOCK(sc);
750 IEEE80211_LOCK(ic);
751 ieee80211_free_node(ni);
752 return (-1);
753 }
754
755 static void
ural_bulk_write_callback(struct usb_xfer * xfer,usb_error_t error)756 ural_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
757 {
758 struct ural_softc *sc = usbd_xfer_softc(xfer);
759 struct ieee80211vap *vap;
760 struct ural_tx_data *data;
761 struct mbuf *m;
762 struct usb_page_cache *pc;
763 int len;
764
765 usbd_xfer_status(xfer, &len, NULL, NULL, NULL);
766
767 switch (USB_GET_STATE(xfer)) {
768 case USB_ST_TRANSFERRED:
769 DPRINTFN(11, "transfer complete, %d bytes\n", len);
770
771 /* free resources */
772 data = usbd_xfer_get_priv(xfer);
773 ural_tx_free(data, 0);
774 usbd_xfer_set_priv(xfer, NULL);
775
776 /* FALLTHROUGH */
777 case USB_ST_SETUP:
778 tr_setup:
779 data = STAILQ_FIRST(&sc->tx_q);
780 if (data) {
781 STAILQ_REMOVE_HEAD(&sc->tx_q, next);
782 m = data->m;
783
784 if (m->m_pkthdr.len > (int)(RAL_FRAME_SIZE + RAL_TX_DESC_SIZE)) {
785 DPRINTFN(0, "data overflow, %u bytes\n",
786 m->m_pkthdr.len);
787 m->m_pkthdr.len = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE);
788 }
789 pc = usbd_xfer_get_frame(xfer, 0);
790 usbd_copy_in(pc, 0, &data->desc, RAL_TX_DESC_SIZE);
791 usbd_m_copy_in(pc, RAL_TX_DESC_SIZE, m, 0,
792 m->m_pkthdr.len);
793
794 vap = data->ni->ni_vap;
795 if (ieee80211_radiotap_active_vap(vap)) {
796 struct ural_tx_radiotap_header *tap = &sc->sc_txtap;
797
798 tap->wt_flags = 0;
799 tap->wt_rate = data->rate;
800 tap->wt_antenna = sc->tx_ant;
801
802 ieee80211_radiotap_tx(vap, m);
803 }
804
805 /* xfer length needs to be a multiple of two! */
806 len = (RAL_TX_DESC_SIZE + m->m_pkthdr.len + 1) & ~1;
807 if ((len % 64) == 0)
808 len += 2;
809
810 DPRINTFN(11, "sending frame len=%u xferlen=%u\n",
811 m->m_pkthdr.len, len);
812
813 usbd_xfer_set_frame_len(xfer, 0, len);
814 usbd_xfer_set_priv(xfer, data);
815
816 usbd_transfer_submit(xfer);
817 }
818 ural_start(sc);
819 break;
820
821 default: /* Error */
822 DPRINTFN(11, "transfer error, %s\n",
823 usbd_errstr(error));
824
825 data = usbd_xfer_get_priv(xfer);
826 if (data != NULL) {
827 ural_tx_free(data, error);
828 usbd_xfer_set_priv(xfer, NULL);
829 }
830
831 if (error == USB_ERR_STALLED) {
832 /* try to clear stall first */
833 usbd_xfer_set_stall(xfer);
834 goto tr_setup;
835 }
836 if (error == USB_ERR_TIMEOUT)
837 device_printf(sc->sc_dev, "device timeout\n");
838 break;
839 }
840 }
841
842 static void
ural_bulk_read_callback(struct usb_xfer * xfer,usb_error_t error)843 ural_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
844 {
845 struct ural_softc *sc = usbd_xfer_softc(xfer);
846 struct ieee80211com *ic = &sc->sc_ic;
847 struct ieee80211_node *ni;
848 struct mbuf *m = NULL;
849 struct usb_page_cache *pc;
850 uint32_t flags;
851 int8_t rssi = 0, nf = 0;
852 int len;
853
854 usbd_xfer_status(xfer, &len, NULL, NULL, NULL);
855
856 switch (USB_GET_STATE(xfer)) {
857 case USB_ST_TRANSFERRED:
858
859 DPRINTFN(15, "rx done, actlen=%d\n", len);
860
861 if (len < (int)(RAL_RX_DESC_SIZE + IEEE80211_MIN_LEN)) {
862 DPRINTF("%s: xfer too short %d\n",
863 device_get_nameunit(sc->sc_dev), len);
864 counter_u64_add(ic->ic_ierrors, 1);
865 goto tr_setup;
866 }
867
868 len -= RAL_RX_DESC_SIZE;
869 /* rx descriptor is located at the end */
870 pc = usbd_xfer_get_frame(xfer, 0);
871 usbd_copy_out(pc, len, &sc->sc_rx_desc, RAL_RX_DESC_SIZE);
872
873 rssi = URAL_RSSI(sc->sc_rx_desc.rssi);
874 nf = RAL_NOISE_FLOOR;
875 flags = le32toh(sc->sc_rx_desc.flags);
876 if (flags & (RAL_RX_PHY_ERROR | RAL_RX_CRC_ERROR)) {
877 /*
878 * This should not happen since we did not
879 * request to receive those frames when we
880 * filled RAL_TXRX_CSR2:
881 */
882 DPRINTFN(5, "PHY or CRC error\n");
883 counter_u64_add(ic->ic_ierrors, 1);
884 goto tr_setup;
885 }
886
887 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
888 if (m == NULL) {
889 DPRINTF("could not allocate mbuf\n");
890 counter_u64_add(ic->ic_ierrors, 1);
891 goto tr_setup;
892 }
893 usbd_copy_out(pc, 0, mtod(m, uint8_t *), len);
894
895 /* finalize mbuf */
896 m->m_pkthdr.len = m->m_len = (flags >> 16) & 0xfff;
897
898 if (ieee80211_radiotap_active(ic)) {
899 struct ural_rx_radiotap_header *tap = &sc->sc_rxtap;
900
901 /* XXX set once */
902 tap->wr_flags = 0;
903 tap->wr_rate = ieee80211_plcp2rate(sc->sc_rx_desc.rate,
904 (flags & RAL_RX_OFDM) ?
905 IEEE80211_T_OFDM : IEEE80211_T_CCK);
906 tap->wr_antenna = sc->rx_ant;
907 tap->wr_antsignal = nf + rssi;
908 tap->wr_antnoise = nf;
909 }
910 /* Strip trailing 802.11 MAC FCS. */
911 m_adj(m, -IEEE80211_CRC_LEN);
912
913 /* FALLTHROUGH */
914 case USB_ST_SETUP:
915 tr_setup:
916 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
917 usbd_transfer_submit(xfer);
918
919 /*
920 * At the end of a USB callback it is always safe to unlock
921 * the private mutex of a device! That is why we do the
922 * "ieee80211_input" here, and not some lines up!
923 */
924 RAL_UNLOCK(sc);
925 if (m) {
926 ni = ieee80211_find_rxnode(ic,
927 mtod(m, struct ieee80211_frame_min *));
928 if (ni != NULL) {
929 (void) ieee80211_input(ni, m, rssi, nf);
930 ieee80211_free_node(ni);
931 } else
932 (void) ieee80211_input_all(ic, m, rssi, nf);
933 }
934 RAL_LOCK(sc);
935 ural_start(sc);
936 return;
937
938 default: /* Error */
939 if (error != USB_ERR_CANCELLED) {
940 /* try to clear stall first */
941 usbd_xfer_set_stall(xfer);
942 goto tr_setup;
943 }
944 return;
945 }
946 }
947
948 static uint8_t
ural_plcp_signal(int rate)949 ural_plcp_signal(int rate)
950 {
951 switch (rate) {
952 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */
953 case 12: return 0xb;
954 case 18: return 0xf;
955 case 24: return 0xa;
956 case 36: return 0xe;
957 case 48: return 0x9;
958 case 72: return 0xd;
959 case 96: return 0x8;
960 case 108: return 0xc;
961
962 /* CCK rates (NB: not IEEE std, device-specific) */
963 case 2: return 0x0;
964 case 4: return 0x1;
965 case 11: return 0x2;
966 case 22: return 0x3;
967 }
968 return 0xff; /* XXX unsupported/unknown rate */
969 }
970
971 static void
ural_setup_tx_desc(struct ural_softc * sc,struct ural_tx_desc * desc,uint32_t flags,int len,int rate)972 ural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc,
973 uint32_t flags, int len, int rate)
974 {
975 struct ieee80211com *ic = &sc->sc_ic;
976 uint16_t plcp_length;
977 int remainder;
978
979 desc->flags = htole32(flags);
980 desc->flags |= htole32(RAL_TX_NEWSEQ);
981 desc->flags |= htole32(len << 16);
982
983 desc->wme = htole16(RAL_AIFSN(2) | RAL_LOGCWMIN(3) | RAL_LOGCWMAX(5));
984 desc->wme |= htole16(RAL_IVOFFSET(sizeof (struct ieee80211_frame)));
985
986 /* setup PLCP fields */
987 desc->plcp_signal = ural_plcp_signal(rate);
988 desc->plcp_service = 4;
989
990 len += IEEE80211_CRC_LEN;
991 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) {
992 desc->flags |= htole32(RAL_TX_OFDM);
993
994 plcp_length = len & 0xfff;
995 desc->plcp_length_hi = plcp_length >> 6;
996 desc->plcp_length_lo = plcp_length & 0x3f;
997 } else {
998 if (rate == 0)
999 rate = 2; /* avoid division by zero */
1000 plcp_length = howmany(16 * len, rate);
1001 if (rate == 22) {
1002 remainder = (16 * len) % 22;
1003 if (remainder != 0 && remainder < 7)
1004 desc->plcp_service |= RAL_PLCP_LENGEXT;
1005 }
1006 desc->plcp_length_hi = plcp_length >> 8;
1007 desc->plcp_length_lo = plcp_length & 0xff;
1008
1009 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1010 desc->plcp_signal |= 0x08;
1011 }
1012
1013 desc->iv = 0;
1014 desc->eiv = 0;
1015 }
1016
1017 #define RAL_TX_TIMEOUT 5000
1018
1019 static int
ural_tx_bcn(struct ural_softc * sc,struct mbuf * m0,struct ieee80211_node * ni)1020 ural_tx_bcn(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni)
1021 {
1022 struct ieee80211vap *vap = ni->ni_vap;
1023 struct ieee80211com *ic = ni->ni_ic;
1024 const struct ieee80211_txparam *tp;
1025 struct ural_tx_data *data;
1026
1027 if (sc->tx_nfree == 0) {
1028 m_freem(m0);
1029 ieee80211_free_node(ni);
1030 return (EIO);
1031 }
1032 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC) {
1033 m_freem(m0);
1034 ieee80211_free_node(ni);
1035 return (ENXIO);
1036 }
1037 data = STAILQ_FIRST(&sc->tx_free);
1038 STAILQ_REMOVE_HEAD(&sc->tx_free, next);
1039 sc->tx_nfree--;
1040 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_bsschan)];
1041
1042 data->m = m0;
1043 data->ni = ni;
1044 data->rate = tp->mgmtrate;
1045
1046 ural_setup_tx_desc(sc, &data->desc,
1047 RAL_TX_IFS_NEWBACKOFF | RAL_TX_TIMESTAMP, m0->m_pkthdr.len,
1048 tp->mgmtrate);
1049
1050 DPRINTFN(10, "sending beacon frame len=%u rate=%u\n",
1051 m0->m_pkthdr.len, tp->mgmtrate);
1052
1053 STAILQ_INSERT_TAIL(&sc->tx_q, data, next);
1054 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]);
1055
1056 return (0);
1057 }
1058
1059 static int
ural_tx_mgt(struct ural_softc * sc,struct mbuf * m0,struct ieee80211_node * ni)1060 ural_tx_mgt(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni)
1061 {
1062 const struct ieee80211_txparam *tp = ni->ni_txparms;
1063 struct ieee80211com *ic = ni->ni_ic;
1064 struct ural_tx_data *data;
1065 struct ieee80211_frame *wh;
1066 struct ieee80211_key *k;
1067 uint32_t flags;
1068 uint16_t dur;
1069
1070 RAL_LOCK_ASSERT(sc, MA_OWNED);
1071
1072 data = STAILQ_FIRST(&sc->tx_free);
1073 STAILQ_REMOVE_HEAD(&sc->tx_free, next);
1074 sc->tx_nfree--;
1075
1076 wh = mtod(m0, struct ieee80211_frame *);
1077 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1078 k = ieee80211_crypto_encap(ni, m0);
1079 if (k == NULL) {
1080 m_freem(m0);
1081 return ENOBUFS;
1082 }
1083 wh = mtod(m0, struct ieee80211_frame *);
1084 }
1085
1086 data->m = m0;
1087 data->ni = ni;
1088 data->rate = tp->mgmtrate;
1089
1090 flags = 0;
1091 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1092 flags |= RAL_TX_ACK;
1093
1094 dur = ieee80211_ack_duration(ic->ic_rt, tp->mgmtrate,
1095 ic->ic_flags & IEEE80211_F_SHPREAMBLE);
1096 USETW(wh->i_dur, dur);
1097
1098 /* tell hardware to add timestamp for probe responses */
1099 if (IEEE80211_IS_MGMT_PROBE_RESP(wh))
1100 flags |= RAL_TX_TIMESTAMP;
1101 }
1102
1103 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, tp->mgmtrate);
1104
1105 DPRINTFN(10, "sending mgt frame len=%u rate=%u\n",
1106 m0->m_pkthdr.len, tp->mgmtrate);
1107
1108 STAILQ_INSERT_TAIL(&sc->tx_q, data, next);
1109 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]);
1110
1111 return 0;
1112 }
1113
1114 static int
ural_sendprot(struct ural_softc * sc,const struct mbuf * m,struct ieee80211_node * ni,int prot,int rate)1115 ural_sendprot(struct ural_softc *sc,
1116 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate)
1117 {
1118 struct ieee80211com *ic = ni->ni_ic;
1119 struct ural_tx_data *data;
1120 struct mbuf *mprot;
1121 int protrate, flags;
1122
1123 mprot = ieee80211_alloc_prot(ni, m, rate, prot);
1124 if (mprot == NULL) {
1125 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1);
1126 device_printf(sc->sc_dev,
1127 "could not allocate mbuf for protection mode %d\n", prot);
1128 return ENOBUFS;
1129 }
1130
1131 protrate = ieee80211_ctl_rate(ic->ic_rt, rate);
1132 flags = RAL_TX_RETRY(7);
1133 if (prot == IEEE80211_PROT_RTSCTS)
1134 flags |= RAL_TX_ACK;
1135
1136 data = STAILQ_FIRST(&sc->tx_free);
1137 STAILQ_REMOVE_HEAD(&sc->tx_free, next);
1138 sc->tx_nfree--;
1139
1140 data->m = mprot;
1141 data->ni = ieee80211_ref_node(ni);
1142 data->rate = protrate;
1143 ural_setup_tx_desc(sc, &data->desc, flags, mprot->m_pkthdr.len, protrate);
1144
1145 STAILQ_INSERT_TAIL(&sc->tx_q, data, next);
1146 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]);
1147
1148 return 0;
1149 }
1150
1151 static int
ural_tx_raw(struct ural_softc * sc,struct mbuf * m0,struct ieee80211_node * ni,const struct ieee80211_bpf_params * params)1152 ural_tx_raw(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni,
1153 const struct ieee80211_bpf_params *params)
1154 {
1155 struct ieee80211com *ic = ni->ni_ic;
1156 struct ural_tx_data *data;
1157 uint32_t flags;
1158 int error;
1159 int rate;
1160
1161 RAL_LOCK_ASSERT(sc, MA_OWNED);
1162 KASSERT(params != NULL, ("no raw xmit params"));
1163
1164 rate = params->ibp_rate0;
1165 if (!ieee80211_isratevalid(ic->ic_rt, rate)) {
1166 m_freem(m0);
1167 return EINVAL;
1168 }
1169 flags = 0;
1170 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0)
1171 flags |= RAL_TX_ACK;
1172 if (params->ibp_flags & (IEEE80211_BPF_RTS|IEEE80211_BPF_CTS)) {
1173 error = ural_sendprot(sc, m0, ni,
1174 params->ibp_flags & IEEE80211_BPF_RTS ?
1175 IEEE80211_PROT_RTSCTS : IEEE80211_PROT_CTSONLY,
1176 rate);
1177 if (error || sc->tx_nfree == 0) {
1178 m_freem(m0);
1179 return ENOBUFS;
1180 }
1181 flags |= RAL_TX_IFS_SIFS;
1182 }
1183
1184 data = STAILQ_FIRST(&sc->tx_free);
1185 STAILQ_REMOVE_HEAD(&sc->tx_free, next);
1186 sc->tx_nfree--;
1187
1188 data->m = m0;
1189 data->ni = ni;
1190 data->rate = rate;
1191
1192 /* XXX need to setup descriptor ourself */
1193 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate);
1194
1195 DPRINTFN(10, "sending raw frame len=%u rate=%u\n",
1196 m0->m_pkthdr.len, rate);
1197
1198 STAILQ_INSERT_TAIL(&sc->tx_q, data, next);
1199 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]);
1200
1201 return 0;
1202 }
1203
1204 static int
ural_tx_data(struct ural_softc * sc,struct mbuf * m0,struct ieee80211_node * ni)1205 ural_tx_data(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni)
1206 {
1207 struct ieee80211vap *vap = ni->ni_vap;
1208 struct ieee80211com *ic = ni->ni_ic;
1209 struct ural_tx_data *data;
1210 struct ieee80211_frame *wh;
1211 const struct ieee80211_txparam *tp = ni->ni_txparms;
1212 struct ieee80211_key *k;
1213 uint32_t flags = 0;
1214 uint16_t dur;
1215 int error, rate;
1216
1217 RAL_LOCK_ASSERT(sc, MA_OWNED);
1218
1219 wh = mtod(m0, struct ieee80211_frame *);
1220
1221 if (m0->m_flags & M_EAPOL)
1222 rate = tp->mgmtrate;
1223 else if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1224 rate = tp->mcastrate;
1225 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
1226 rate = tp->ucastrate;
1227 else {
1228 (void) ieee80211_ratectl_rate(ni, NULL, 0);
1229 rate = ieee80211_node_get_txrate_dot11rate(ni);
1230 }
1231
1232 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1233 k = ieee80211_crypto_encap(ni, m0);
1234 if (k == NULL) {
1235 m_freem(m0);
1236 return ENOBUFS;
1237 }
1238 /* packet header may have moved, reset our local pointer */
1239 wh = mtod(m0, struct ieee80211_frame *);
1240 }
1241
1242 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1243 int prot = IEEE80211_PROT_NONE;
1244 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold)
1245 prot = IEEE80211_PROT_RTSCTS;
1246 else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
1247 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM)
1248 prot = ic->ic_protmode;
1249 if (prot != IEEE80211_PROT_NONE) {
1250 error = ural_sendprot(sc, m0, ni, prot, rate);
1251 if (error || sc->tx_nfree == 0) {
1252 m_freem(m0);
1253 return ENOBUFS;
1254 }
1255 flags |= RAL_TX_IFS_SIFS;
1256 }
1257 }
1258
1259 data = STAILQ_FIRST(&sc->tx_free);
1260 STAILQ_REMOVE_HEAD(&sc->tx_free, next);
1261 sc->tx_nfree--;
1262
1263 data->m = m0;
1264 data->ni = ni;
1265 data->rate = rate;
1266
1267 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1268 flags |= RAL_TX_ACK;
1269 flags |= RAL_TX_RETRY(7);
1270
1271 dur = ieee80211_ack_duration(ic->ic_rt, rate,
1272 ic->ic_flags & IEEE80211_F_SHPREAMBLE);
1273 USETW(wh->i_dur, dur);
1274 }
1275
1276 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate);
1277
1278 DPRINTFN(10, "sending data frame len=%u rate=%u\n",
1279 m0->m_pkthdr.len, rate);
1280
1281 STAILQ_INSERT_TAIL(&sc->tx_q, data, next);
1282 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]);
1283
1284 return 0;
1285 }
1286
1287 static int
ural_transmit(struct ieee80211com * ic,struct mbuf * m)1288 ural_transmit(struct ieee80211com *ic, struct mbuf *m)
1289 {
1290 struct ural_softc *sc = ic->ic_softc;
1291 int error;
1292
1293 RAL_LOCK(sc);
1294 if (!sc->sc_running) {
1295 RAL_UNLOCK(sc);
1296 return (ENXIO);
1297 }
1298 error = mbufq_enqueue(&sc->sc_snd, m);
1299 if (error) {
1300 RAL_UNLOCK(sc);
1301 return (error);
1302 }
1303 ural_start(sc);
1304 RAL_UNLOCK(sc);
1305
1306 return (0);
1307 }
1308
1309 static void
ural_start(struct ural_softc * sc)1310 ural_start(struct ural_softc *sc)
1311 {
1312 struct ieee80211_node *ni;
1313 struct mbuf *m;
1314
1315 RAL_LOCK_ASSERT(sc, MA_OWNED);
1316
1317 if (sc->sc_running == 0)
1318 return;
1319
1320 while (sc->tx_nfree >= RAL_TX_MINFREE &&
1321 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
1322 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1323 if (ural_tx_data(sc, m, ni) != 0) {
1324 if_inc_counter(ni->ni_vap->iv_ifp,
1325 IFCOUNTER_OERRORS, 1);
1326 ieee80211_free_node(ni);
1327 break;
1328 }
1329 }
1330 }
1331
1332 static void
ural_parent(struct ieee80211com * ic)1333 ural_parent(struct ieee80211com *ic)
1334 {
1335 struct ural_softc *sc = ic->ic_softc;
1336 int startall = 0;
1337
1338 RAL_LOCK(sc);
1339 if (sc->sc_detached) {
1340 RAL_UNLOCK(sc);
1341 return;
1342 }
1343 if (ic->ic_nrunning > 0) {
1344 if (sc->sc_running == 0) {
1345 ural_init(sc);
1346 startall = 1;
1347 } else
1348 ural_setpromisc(sc);
1349 } else if (sc->sc_running)
1350 ural_stop(sc);
1351 RAL_UNLOCK(sc);
1352 if (startall)
1353 ieee80211_start_all(ic);
1354 }
1355
1356 static void
ural_set_testmode(struct ural_softc * sc)1357 ural_set_testmode(struct ural_softc *sc)
1358 {
1359 struct usb_device_request req;
1360 usb_error_t error;
1361
1362 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1363 req.bRequest = RAL_VENDOR_REQUEST;
1364 USETW(req.wValue, 4);
1365 USETW(req.wIndex, 1);
1366 USETW(req.wLength, 0);
1367
1368 error = ural_do_request(sc, &req, NULL);
1369 if (error != 0) {
1370 device_printf(sc->sc_dev, "could not set test mode: %s\n",
1371 usbd_errstr(error));
1372 }
1373 }
1374
1375 static void
ural_eeprom_read(struct ural_softc * sc,uint16_t addr,void * buf,int len)1376 ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len)
1377 {
1378 struct usb_device_request req;
1379 usb_error_t error;
1380
1381 req.bmRequestType = UT_READ_VENDOR_DEVICE;
1382 req.bRequest = RAL_READ_EEPROM;
1383 USETW(req.wValue, 0);
1384 USETW(req.wIndex, addr);
1385 USETW(req.wLength, len);
1386
1387 error = ural_do_request(sc, &req, buf);
1388 if (error != 0) {
1389 device_printf(sc->sc_dev, "could not read EEPROM: %s\n",
1390 usbd_errstr(error));
1391 }
1392 }
1393
1394 static uint16_t
ural_read(struct ural_softc * sc,uint16_t reg)1395 ural_read(struct ural_softc *sc, uint16_t reg)
1396 {
1397 struct usb_device_request req;
1398 usb_error_t error;
1399 uint16_t val;
1400
1401 req.bmRequestType = UT_READ_VENDOR_DEVICE;
1402 req.bRequest = RAL_READ_MAC;
1403 USETW(req.wValue, 0);
1404 USETW(req.wIndex, reg);
1405 USETW(req.wLength, sizeof (uint16_t));
1406
1407 error = ural_do_request(sc, &req, &val);
1408 if (error != 0) {
1409 device_printf(sc->sc_dev, "could not read MAC register: %s\n",
1410 usbd_errstr(error));
1411 return 0;
1412 }
1413
1414 return le16toh(val);
1415 }
1416
1417 static void
ural_read_multi(struct ural_softc * sc,uint16_t reg,void * buf,int len)1418 ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len)
1419 {
1420 struct usb_device_request req;
1421 usb_error_t error;
1422
1423 req.bmRequestType = UT_READ_VENDOR_DEVICE;
1424 req.bRequest = RAL_READ_MULTI_MAC;
1425 USETW(req.wValue, 0);
1426 USETW(req.wIndex, reg);
1427 USETW(req.wLength, len);
1428
1429 error = ural_do_request(sc, &req, buf);
1430 if (error != 0) {
1431 device_printf(sc->sc_dev, "could not read MAC register: %s\n",
1432 usbd_errstr(error));
1433 }
1434 }
1435
1436 static void
ural_write(struct ural_softc * sc,uint16_t reg,uint16_t val)1437 ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val)
1438 {
1439 struct usb_device_request req;
1440 usb_error_t error;
1441
1442 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1443 req.bRequest = RAL_WRITE_MAC;
1444 USETW(req.wValue, val);
1445 USETW(req.wIndex, reg);
1446 USETW(req.wLength, 0);
1447
1448 error = ural_do_request(sc, &req, NULL);
1449 if (error != 0) {
1450 device_printf(sc->sc_dev, "could not write MAC register: %s\n",
1451 usbd_errstr(error));
1452 }
1453 }
1454
1455 static void
ural_write_multi(struct ural_softc * sc,uint16_t reg,void * buf,int len)1456 ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len)
1457 {
1458 struct usb_device_request req;
1459 usb_error_t error;
1460
1461 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1462 req.bRequest = RAL_WRITE_MULTI_MAC;
1463 USETW(req.wValue, 0);
1464 USETW(req.wIndex, reg);
1465 USETW(req.wLength, len);
1466
1467 error = ural_do_request(sc, &req, buf);
1468 if (error != 0) {
1469 device_printf(sc->sc_dev, "could not write MAC register: %s\n",
1470 usbd_errstr(error));
1471 }
1472 }
1473
1474 static void
ural_bbp_write(struct ural_softc * sc,uint8_t reg,uint8_t val)1475 ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val)
1476 {
1477 uint16_t tmp;
1478 int ntries;
1479
1480 for (ntries = 0; ntries < 100; ntries++) {
1481 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY))
1482 break;
1483 if (ural_pause(sc, hz / 100))
1484 break;
1485 }
1486 if (ntries == 100) {
1487 device_printf(sc->sc_dev, "could not write to BBP\n");
1488 return;
1489 }
1490
1491 tmp = reg << 8 | val;
1492 ural_write(sc, RAL_PHY_CSR7, tmp);
1493 }
1494
1495 static uint8_t
ural_bbp_read(struct ural_softc * sc,uint8_t reg)1496 ural_bbp_read(struct ural_softc *sc, uint8_t reg)
1497 {
1498 uint16_t val;
1499 int ntries;
1500
1501 val = RAL_BBP_WRITE | reg << 8;
1502 ural_write(sc, RAL_PHY_CSR7, val);
1503
1504 for (ntries = 0; ntries < 100; ntries++) {
1505 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY))
1506 break;
1507 if (ural_pause(sc, hz / 100))
1508 break;
1509 }
1510 if (ntries == 100) {
1511 device_printf(sc->sc_dev, "could not read BBP\n");
1512 return 0;
1513 }
1514
1515 return ural_read(sc, RAL_PHY_CSR7) & 0xff;
1516 }
1517
1518 static void
ural_rf_write(struct ural_softc * sc,uint8_t reg,uint32_t val)1519 ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val)
1520 {
1521 uint32_t tmp;
1522 int ntries;
1523
1524 for (ntries = 0; ntries < 100; ntries++) {
1525 if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY))
1526 break;
1527 if (ural_pause(sc, hz / 100))
1528 break;
1529 }
1530 if (ntries == 100) {
1531 device_printf(sc->sc_dev, "could not write to RF\n");
1532 return;
1533 }
1534
1535 tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3);
1536 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff);
1537 ural_write(sc, RAL_PHY_CSR10, tmp >> 16);
1538
1539 /* remember last written value in sc */
1540 sc->rf_regs[reg] = val;
1541
1542 DPRINTFN(15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff);
1543 }
1544
1545 static void
ural_scan_start(struct ieee80211com * ic)1546 ural_scan_start(struct ieee80211com *ic)
1547 {
1548 struct ural_softc *sc = ic->ic_softc;
1549
1550 RAL_LOCK(sc);
1551 ural_write(sc, RAL_TXRX_CSR19, 0);
1552 ural_set_bssid(sc, ieee80211broadcastaddr);
1553 RAL_UNLOCK(sc);
1554 }
1555
1556 static void
ural_scan_end(struct ieee80211com * ic)1557 ural_scan_end(struct ieee80211com *ic)
1558 {
1559 struct ural_softc *sc = ic->ic_softc;
1560
1561 RAL_LOCK(sc);
1562 ural_enable_tsf_sync(sc);
1563 ural_set_bssid(sc, sc->sc_bssid);
1564 RAL_UNLOCK(sc);
1565
1566 }
1567
1568 static void
ural_getradiocaps(struct ieee80211com * ic,int maxchans,int * nchans,struct ieee80211_channel chans[])1569 ural_getradiocaps(struct ieee80211com *ic,
1570 int maxchans, int *nchans, struct ieee80211_channel chans[])
1571 {
1572 struct ural_softc *sc = ic->ic_softc;
1573 uint8_t bands[IEEE80211_MODE_BYTES];
1574
1575 memset(bands, 0, sizeof(bands));
1576 setbit(bands, IEEE80211_MODE_11B);
1577 setbit(bands, IEEE80211_MODE_11G);
1578 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0);
1579
1580 if (sc->rf_rev == RAL_RF_5222) {
1581 setbit(bands, IEEE80211_MODE_11A);
1582 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans,
1583 ural_chan_5ghz, nitems(ural_chan_5ghz), bands, 0);
1584 }
1585 }
1586
1587 static void
ural_set_channel(struct ieee80211com * ic)1588 ural_set_channel(struct ieee80211com *ic)
1589 {
1590 struct ural_softc *sc = ic->ic_softc;
1591
1592 RAL_LOCK(sc);
1593 ural_set_chan(sc, ic->ic_curchan);
1594 RAL_UNLOCK(sc);
1595 }
1596
1597 static void
ural_set_chan(struct ural_softc * sc,struct ieee80211_channel * c)1598 ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c)
1599 {
1600 struct ieee80211com *ic = &sc->sc_ic;
1601 uint8_t power, tmp;
1602 int i, chan;
1603
1604 chan = ieee80211_chan2ieee(ic, c);
1605 if (chan == 0 || chan == IEEE80211_CHAN_ANY)
1606 return;
1607
1608 if (IEEE80211_IS_CHAN_2GHZ(c))
1609 power = min(sc->txpow[chan - 1], 31);
1610 else
1611 power = 31;
1612
1613 /* adjust txpower using ifconfig settings */
1614 power -= (100 - ic->ic_txpowlimit) / 8;
1615
1616 DPRINTFN(2, "setting channel to %u, txpower to %u\n", chan, power);
1617
1618 switch (sc->rf_rev) {
1619 case RAL_RF_2522:
1620 ural_rf_write(sc, RAL_RF1, 0x00814);
1621 ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]);
1622 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
1623 break;
1624
1625 case RAL_RF_2523:
1626 ural_rf_write(sc, RAL_RF1, 0x08804);
1627 ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]);
1628 ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044);
1629 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
1630 break;
1631
1632 case RAL_RF_2524:
1633 ural_rf_write(sc, RAL_RF1, 0x0c808);
1634 ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]);
1635 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
1636 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
1637 break;
1638
1639 case RAL_RF_2525:
1640 ural_rf_write(sc, RAL_RF1, 0x08808);
1641 ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]);
1642 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
1643 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
1644
1645 ural_rf_write(sc, RAL_RF1, 0x08808);
1646 ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]);
1647 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
1648 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
1649 break;
1650
1651 case RAL_RF_2525E:
1652 ural_rf_write(sc, RAL_RF1, 0x08808);
1653 ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]);
1654 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
1655 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282);
1656 break;
1657
1658 case RAL_RF_2526:
1659 ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]);
1660 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381);
1661 ural_rf_write(sc, RAL_RF1, 0x08804);
1662
1663 ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]);
1664 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
1665 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381);
1666 break;
1667
1668 /* dual-band RF */
1669 case RAL_RF_5222:
1670 for (i = 0; ural_rf5222[i].chan != chan; i++);
1671
1672 ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1);
1673 ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2);
1674 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
1675 ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4);
1676 break;
1677 }
1678
1679 if (ic->ic_opmode != IEEE80211_M_MONITOR &&
1680 (ic->ic_flags & IEEE80211_F_SCAN) == 0) {
1681 /* set Japan filter bit for channel 14 */
1682 tmp = ural_bbp_read(sc, 70);
1683
1684 tmp &= ~RAL_JAPAN_FILTER;
1685 if (chan == 14)
1686 tmp |= RAL_JAPAN_FILTER;
1687
1688 ural_bbp_write(sc, 70, tmp);
1689
1690 /* clear CRC errors */
1691 ural_read(sc, RAL_STA_CSR0);
1692
1693 ural_pause(sc, hz / 100);
1694 ural_disable_rf_tune(sc);
1695 }
1696
1697 /* XXX doesn't belong here */
1698 /* update basic rate set */
1699 ural_set_basicrates(sc, c);
1700
1701 /* give the hardware some time to do the switchover */
1702 ural_pause(sc, hz / 100);
1703 }
1704
1705 /*
1706 * Disable RF auto-tuning.
1707 */
1708 static void
ural_disable_rf_tune(struct ural_softc * sc)1709 ural_disable_rf_tune(struct ural_softc *sc)
1710 {
1711 uint32_t tmp;
1712
1713 if (sc->rf_rev != RAL_RF_2523) {
1714 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE;
1715 ural_rf_write(sc, RAL_RF1, tmp);
1716 }
1717
1718 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE;
1719 ural_rf_write(sc, RAL_RF3, tmp);
1720
1721 DPRINTFN(2, "disabling RF autotune\n");
1722 }
1723
1724 /*
1725 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF
1726 * synchronization.
1727 */
1728 static void
ural_enable_tsf_sync(struct ural_softc * sc)1729 ural_enable_tsf_sync(struct ural_softc *sc)
1730 {
1731 struct ieee80211com *ic = &sc->sc_ic;
1732 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1733 uint16_t logcwmin, preload, tmp;
1734
1735 /* first, disable TSF synchronization */
1736 ural_write(sc, RAL_TXRX_CSR19, 0);
1737
1738 tmp = (16 * vap->iv_bss->ni_intval) << 4;
1739 ural_write(sc, RAL_TXRX_CSR18, tmp);
1740
1741 logcwmin = (ic->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0;
1742 preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6;
1743 tmp = logcwmin << 12 | preload;
1744 ural_write(sc, RAL_TXRX_CSR20, tmp);
1745
1746 /* finally, enable TSF synchronization */
1747 tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN;
1748 if (ic->ic_opmode == IEEE80211_M_STA)
1749 tmp |= RAL_ENABLE_TSF_SYNC(1);
1750 else
1751 tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR;
1752 ural_write(sc, RAL_TXRX_CSR19, tmp);
1753
1754 DPRINTF("enabling TSF synchronization\n");
1755 }
1756
1757 static void
ural_enable_tsf(struct ural_softc * sc)1758 ural_enable_tsf(struct ural_softc *sc)
1759 {
1760 /* first, disable TSF synchronization */
1761 ural_write(sc, RAL_TXRX_CSR19, 0);
1762 ural_write(sc, RAL_TXRX_CSR19, RAL_ENABLE_TSF | RAL_ENABLE_TSF_SYNC(2));
1763 }
1764
1765 #define RAL_RXTX_TURNAROUND 5 /* us */
1766 static void
ural_update_slot(struct ural_softc * sc)1767 ural_update_slot(struct ural_softc *sc)
1768 {
1769 struct ieee80211com *ic = &sc->sc_ic;
1770 uint16_t slottime, sifs, eifs;
1771
1772 slottime = IEEE80211_GET_SLOTTIME(ic);
1773
1774 /*
1775 * These settings may sound a bit inconsistent but this is what the
1776 * reference driver does.
1777 */
1778 if (ic->ic_curmode == IEEE80211_MODE_11B) {
1779 sifs = 16 - RAL_RXTX_TURNAROUND;
1780 eifs = 364;
1781 } else {
1782 sifs = 10 - RAL_RXTX_TURNAROUND;
1783 eifs = 64;
1784 }
1785
1786 ural_write(sc, RAL_MAC_CSR10, slottime);
1787 ural_write(sc, RAL_MAC_CSR11, sifs);
1788 ural_write(sc, RAL_MAC_CSR12, eifs);
1789 }
1790
1791 static void
ural_set_txpreamble(struct ural_softc * sc)1792 ural_set_txpreamble(struct ural_softc *sc)
1793 {
1794 struct ieee80211com *ic = &sc->sc_ic;
1795 uint16_t tmp;
1796
1797 tmp = ural_read(sc, RAL_TXRX_CSR10);
1798
1799 tmp &= ~RAL_SHORT_PREAMBLE;
1800 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
1801 tmp |= RAL_SHORT_PREAMBLE;
1802
1803 ural_write(sc, RAL_TXRX_CSR10, tmp);
1804 }
1805
1806 static void
ural_set_basicrates(struct ural_softc * sc,const struct ieee80211_channel * c)1807 ural_set_basicrates(struct ural_softc *sc, const struct ieee80211_channel *c)
1808 {
1809 /* XXX wrong, take from rate set */
1810 /* update basic rate set */
1811 if (IEEE80211_IS_CHAN_5GHZ(c)) {
1812 /* 11a basic rates: 6, 12, 24Mbps */
1813 ural_write(sc, RAL_TXRX_CSR11, 0x150);
1814 } else if (IEEE80211_IS_CHAN_ANYG(c)) {
1815 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */
1816 ural_write(sc, RAL_TXRX_CSR11, 0x15f);
1817 } else {
1818 /* 11b basic rates: 1, 2Mbps */
1819 ural_write(sc, RAL_TXRX_CSR11, 0x3);
1820 }
1821 }
1822
1823 static void
ural_set_bssid(struct ural_softc * sc,const uint8_t * bssid)1824 ural_set_bssid(struct ural_softc *sc, const uint8_t *bssid)
1825 {
1826 uint16_t tmp;
1827
1828 tmp = bssid[0] | bssid[1] << 8;
1829 ural_write(sc, RAL_MAC_CSR5, tmp);
1830
1831 tmp = bssid[2] | bssid[3] << 8;
1832 ural_write(sc, RAL_MAC_CSR6, tmp);
1833
1834 tmp = bssid[4] | bssid[5] << 8;
1835 ural_write(sc, RAL_MAC_CSR7, tmp);
1836
1837 DPRINTF("setting BSSID to %6D\n", bssid, ":");
1838 }
1839
1840 static void
ural_set_macaddr(struct ural_softc * sc,const uint8_t * addr)1841 ural_set_macaddr(struct ural_softc *sc, const uint8_t *addr)
1842 {
1843 uint16_t tmp;
1844
1845 tmp = addr[0] | addr[1] << 8;
1846 ural_write(sc, RAL_MAC_CSR2, tmp);
1847
1848 tmp = addr[2] | addr[3] << 8;
1849 ural_write(sc, RAL_MAC_CSR3, tmp);
1850
1851 tmp = addr[4] | addr[5] << 8;
1852 ural_write(sc, RAL_MAC_CSR4, tmp);
1853
1854 DPRINTF("setting MAC address to %6D\n", addr, ":");
1855 }
1856
1857 static void
ural_setpromisc(struct ural_softc * sc)1858 ural_setpromisc(struct ural_softc *sc)
1859 {
1860 uint32_t tmp;
1861
1862 tmp = ural_read(sc, RAL_TXRX_CSR2);
1863
1864 tmp &= ~RAL_DROP_NOT_TO_ME;
1865 if (sc->sc_ic.ic_promisc == 0)
1866 tmp |= RAL_DROP_NOT_TO_ME;
1867
1868 ural_write(sc, RAL_TXRX_CSR2, tmp);
1869
1870 DPRINTF("%s promiscuous mode\n", sc->sc_ic.ic_promisc ?
1871 "entering" : "leaving");
1872 }
1873
1874 static void
ural_update_promisc(struct ieee80211com * ic)1875 ural_update_promisc(struct ieee80211com *ic)
1876 {
1877 struct ural_softc *sc = ic->ic_softc;
1878
1879 RAL_LOCK(sc);
1880 if (sc->sc_running)
1881 ural_setpromisc(sc);
1882 RAL_UNLOCK(sc);
1883 }
1884
1885 static const char *
ural_get_rf(int rev)1886 ural_get_rf(int rev)
1887 {
1888 switch (rev) {
1889 case RAL_RF_2522: return "RT2522";
1890 case RAL_RF_2523: return "RT2523";
1891 case RAL_RF_2524: return "RT2524";
1892 case RAL_RF_2525: return "RT2525";
1893 case RAL_RF_2525E: return "RT2525e";
1894 case RAL_RF_2526: return "RT2526";
1895 case RAL_RF_5222: return "RT5222";
1896 default: return "unknown";
1897 }
1898 }
1899
1900 static void
ural_read_eeprom(struct ural_softc * sc)1901 ural_read_eeprom(struct ural_softc *sc)
1902 {
1903 struct ieee80211com *ic = &sc->sc_ic;
1904 uint16_t val;
1905
1906 ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2);
1907 val = le16toh(val);
1908 sc->rf_rev = (val >> 11) & 0x7;
1909 sc->hw_radio = (val >> 10) & 0x1;
1910 sc->led_mode = (val >> 6) & 0x7;
1911 sc->rx_ant = (val >> 4) & 0x3;
1912 sc->tx_ant = (val >> 2) & 0x3;
1913 sc->nb_ant = val & 0x3;
1914
1915 /* read MAC address */
1916 ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, ic->ic_macaddr, 6);
1917
1918 /* read default values for BBP registers */
1919 ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16);
1920
1921 /* read Tx power for all b/g channels */
1922 ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14);
1923 }
1924
1925 static int
ural_bbp_init(struct ural_softc * sc)1926 ural_bbp_init(struct ural_softc *sc)
1927 {
1928 int i, ntries;
1929
1930 /* wait for BBP to be ready */
1931 for (ntries = 0; ntries < 100; ntries++) {
1932 if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0)
1933 break;
1934 if (ural_pause(sc, hz / 100))
1935 break;
1936 }
1937 if (ntries == 100) {
1938 device_printf(sc->sc_dev, "timeout waiting for BBP\n");
1939 return EIO;
1940 }
1941
1942 /* initialize BBP registers to default values */
1943 for (i = 0; i < nitems(ural_def_bbp); i++)
1944 ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val);
1945
1946 #if 0
1947 /* initialize BBP registers to values stored in EEPROM */
1948 for (i = 0; i < 16; i++) {
1949 if (sc->bbp_prom[i].reg == 0xff)
1950 continue;
1951 ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
1952 }
1953 #endif
1954
1955 return 0;
1956 }
1957
1958 static void
ural_set_txantenna(struct ural_softc * sc,int antenna)1959 ural_set_txantenna(struct ural_softc *sc, int antenna)
1960 {
1961 uint16_t tmp;
1962 uint8_t tx;
1963
1964 tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK;
1965 if (antenna == 1)
1966 tx |= RAL_BBP_ANTA;
1967 else if (antenna == 2)
1968 tx |= RAL_BBP_ANTB;
1969 else
1970 tx |= RAL_BBP_DIVERSITY;
1971
1972 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */
1973 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 ||
1974 sc->rf_rev == RAL_RF_5222)
1975 tx |= RAL_BBP_FLIPIQ;
1976
1977 ural_bbp_write(sc, RAL_BBP_TX, tx);
1978
1979 /* update values in PHY_CSR5 and PHY_CSR6 */
1980 tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7;
1981 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7));
1982
1983 tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7;
1984 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7));
1985 }
1986
1987 static void
ural_set_rxantenna(struct ural_softc * sc,int antenna)1988 ural_set_rxantenna(struct ural_softc *sc, int antenna)
1989 {
1990 uint8_t rx;
1991
1992 rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK;
1993 if (antenna == 1)
1994 rx |= RAL_BBP_ANTA;
1995 else if (antenna == 2)
1996 rx |= RAL_BBP_ANTB;
1997 else
1998 rx |= RAL_BBP_DIVERSITY;
1999
2000 /* need to force no I/Q flip for RF 2525e and 2526 */
2001 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526)
2002 rx &= ~RAL_BBP_FLIPIQ;
2003
2004 ural_bbp_write(sc, RAL_BBP_RX, rx);
2005 }
2006
2007 static void
ural_init(struct ural_softc * sc)2008 ural_init(struct ural_softc *sc)
2009 {
2010 struct ieee80211com *ic = &sc->sc_ic;
2011 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2012 uint16_t tmp;
2013 int i, ntries;
2014
2015 RAL_LOCK_ASSERT(sc, MA_OWNED);
2016
2017 ural_set_testmode(sc);
2018 ural_write(sc, 0x308, 0x00f0); /* XXX magic */
2019
2020 ural_stop(sc);
2021
2022 /* initialize MAC registers to default values */
2023 for (i = 0; i < nitems(ural_def_mac); i++)
2024 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val);
2025
2026 /* wait for BBP and RF to wake up (this can take a long time!) */
2027 for (ntries = 0; ntries < 100; ntries++) {
2028 tmp = ural_read(sc, RAL_MAC_CSR17);
2029 if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) ==
2030 (RAL_BBP_AWAKE | RAL_RF_AWAKE))
2031 break;
2032 if (ural_pause(sc, hz / 100))
2033 break;
2034 }
2035 if (ntries == 100) {
2036 device_printf(sc->sc_dev,
2037 "timeout waiting for BBP/RF to wakeup\n");
2038 goto fail;
2039 }
2040
2041 /* we're ready! */
2042 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY);
2043
2044 /* set basic rate set (will be updated later) */
2045 ural_write(sc, RAL_TXRX_CSR11, 0x15f);
2046
2047 if (ural_bbp_init(sc) != 0)
2048 goto fail;
2049
2050 ural_set_chan(sc, ic->ic_curchan);
2051
2052 /* clear statistic registers (STA_CSR0 to STA_CSR10) */
2053 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta);
2054
2055 ural_set_txantenna(sc, sc->tx_ant);
2056 ural_set_rxantenna(sc, sc->rx_ant);
2057
2058 ural_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr);
2059
2060 /*
2061 * Allocate Tx and Rx xfer queues.
2062 */
2063 ural_setup_tx_list(sc);
2064
2065 /* kick Rx */
2066 tmp = RAL_DROP_PHY | RAL_DROP_CRC;
2067 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2068 tmp |= RAL_DROP_CTL | RAL_DROP_BAD_VERSION;
2069 if (ic->ic_opmode != IEEE80211_M_HOSTAP)
2070 tmp |= RAL_DROP_TODS;
2071 if (ic->ic_promisc == 0)
2072 tmp |= RAL_DROP_NOT_TO_ME;
2073 }
2074 ural_write(sc, RAL_TXRX_CSR2, tmp);
2075
2076 sc->sc_running = 1;
2077 usbd_xfer_set_stall(sc->sc_xfer[URAL_BULK_WR]);
2078 usbd_transfer_start(sc->sc_xfer[URAL_BULK_RD]);
2079 return;
2080
2081 fail: ural_stop(sc);
2082 }
2083
2084 static void
ural_stop(struct ural_softc * sc)2085 ural_stop(struct ural_softc *sc)
2086 {
2087
2088 RAL_LOCK_ASSERT(sc, MA_OWNED);
2089
2090 sc->sc_running = 0;
2091
2092 /*
2093 * Drain all the transfers, if not already drained:
2094 */
2095 RAL_UNLOCK(sc);
2096 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_WR]);
2097 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_RD]);
2098 RAL_LOCK(sc);
2099
2100 ural_unsetup_tx_list(sc);
2101
2102 /* disable Rx */
2103 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX);
2104 /* reset ASIC and BBP (but won't reset MAC registers!) */
2105 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP);
2106 /* wait a little */
2107 ural_pause(sc, hz / 10);
2108 ural_write(sc, RAL_MAC_CSR1, 0);
2109 /* wait a little */
2110 ural_pause(sc, hz / 10);
2111 }
2112
2113 static int
ural_raw_xmit(struct ieee80211_node * ni,struct mbuf * m,const struct ieee80211_bpf_params * params)2114 ural_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
2115 const struct ieee80211_bpf_params *params)
2116 {
2117 struct ieee80211com *ic = ni->ni_ic;
2118 struct ural_softc *sc = ic->ic_softc;
2119
2120 RAL_LOCK(sc);
2121 /* prevent management frames from being sent if we're not ready */
2122 if (!sc->sc_running) {
2123 RAL_UNLOCK(sc);
2124 m_freem(m);
2125 return ENETDOWN;
2126 }
2127 if (sc->tx_nfree < RAL_TX_MINFREE) {
2128 RAL_UNLOCK(sc);
2129 m_freem(m);
2130 return EIO;
2131 }
2132
2133 if (params == NULL) {
2134 /*
2135 * Legacy path; interpret frame contents to decide
2136 * precisely how to send the frame.
2137 */
2138 if (ural_tx_mgt(sc, m, ni) != 0)
2139 goto bad;
2140 } else {
2141 /*
2142 * Caller supplied explicit parameters to use in
2143 * sending the frame.
2144 */
2145 if (ural_tx_raw(sc, m, ni, params) != 0)
2146 goto bad;
2147 }
2148 RAL_UNLOCK(sc);
2149 return 0;
2150 bad:
2151 RAL_UNLOCK(sc);
2152 return EIO; /* XXX */
2153 }
2154
2155 static void
ural_ratectl_start(struct ural_softc * sc,struct ieee80211_node * ni)2156 ural_ratectl_start(struct ural_softc *sc, struct ieee80211_node *ni)
2157 {
2158 struct ieee80211vap *vap = ni->ni_vap;
2159 struct ural_vap *uvp = URAL_VAP(vap);
2160
2161 /* clear statistic registers (STA_CSR0 to STA_CSR10) */
2162 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta);
2163
2164 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp);
2165 }
2166
2167 static void
ural_ratectl_timeout(void * arg)2168 ural_ratectl_timeout(void *arg)
2169 {
2170 struct ural_vap *uvp = arg;
2171 struct ieee80211vap *vap = &uvp->vap;
2172 struct ieee80211com *ic = vap->iv_ic;
2173
2174 ieee80211_runtask(ic, &uvp->ratectl_task);
2175 }
2176
2177 static void
ural_ratectl_task(void * arg,int pending)2178 ural_ratectl_task(void *arg, int pending)
2179 {
2180 struct ural_vap *uvp = arg;
2181 struct ieee80211vap *vap = &uvp->vap;
2182 struct ural_softc *sc = vap->iv_ic->ic_softc;
2183 struct ieee80211_ratectl_tx_stats *txs = &sc->sc_txs;
2184 int fail;
2185
2186 RAL_LOCK(sc);
2187 /* read and clear statistic registers (STA_CSR0 to STA_CSR10) */
2188 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof(sc->sta));
2189
2190 txs->flags = IEEE80211_RATECTL_TX_STATS_RETRIES;
2191 txs->nsuccess = sc->sta[7] + /* TX ok w/o retry */
2192 sc->sta[8]; /* TX ok w/ retry */
2193 fail = sc->sta[9]; /* TX retry-fail count */
2194 txs->nframes = txs->nsuccess + fail;
2195 /* XXX fail * maxretry */
2196 txs->nretries = sc->sta[8] + fail;
2197
2198 ieee80211_ratectl_tx_update(vap, txs);
2199
2200 /* count TX retry-fail as Tx errors */
2201 if_inc_counter(vap->iv_ifp, IFCOUNTER_OERRORS, fail);
2202
2203 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp);
2204 RAL_UNLOCK(sc);
2205 }
2206
2207 static int
ural_pause(struct ural_softc * sc,int timeout)2208 ural_pause(struct ural_softc *sc, int timeout)
2209 {
2210
2211 usb_pause_mtx(&sc->sc_mtx, timeout);
2212 return (0);
2213 }
2214