1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Definitions of T4 work request and CPL5 commands and status codes. 14 * 15 * Copyright (C) 2008-2013 Chelsio Communications. All rights reserved. 16 * 17 * Written by Dimitris Michailidis (dm@chelsio.com) 18 * 19 * This program is distributed in the hope that it will be useful, but WITHOUT 20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 21 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 22 * release for licensing terms and conditions. 23 */ 24 25 #ifndef __CXGBE_T4_MSG_H 26 #define __CXGBE_T4_MSG_H 27 28 enum { 29 CPL_PASS_OPEN_REQ = 0x1, 30 CPL_PASS_ACCEPT_RPL = 0x2, 31 CPL_ACT_OPEN_REQ = 0x3, 32 CPL_SET_TCB = 0x4, 33 CPL_SET_TCB_FIELD = 0x5, 34 CPL_GET_TCB = 0x6, 35 CPL_PCMD = 0x7, 36 CPL_CLOSE_CON_REQ = 0x8, 37 CPL_CLOSE_LISTSRV_REQ = 0x9, 38 CPL_ABORT_REQ = 0xA, 39 CPL_ABORT_RPL = 0xB, 40 CPL_TX_DATA = 0xC, 41 CPL_RX_DATA_ACK = 0xD, 42 CPL_TX_PKT = 0xE, 43 CPL_RTE_DELETE_REQ = 0xF, 44 CPL_RTE_WRITE_REQ = 0x10, 45 CPL_RTE_READ_REQ = 0x11, 46 CPL_L2T_WRITE_REQ = 0x12, 47 CPL_L2T_READ_REQ = 0x13, 48 CPL_SMT_WRITE_REQ = 0x14, 49 CPL_SMT_READ_REQ = 0x15, 50 CPL_BARRIER = 0x18, 51 CPL_TID_RELEASE = 0x1A, 52 CPL_RX_MPS_PKT = 0x1B, 53 54 CPL_CLOSE_LISTSRV_RPL = 0x20, 55 CPL_ERROR = 0x21, 56 CPL_GET_TCB_RPL = 0x22, 57 CPL_L2T_WRITE_RPL = 0x23, 58 CPL_PASS_OPEN_RPL = 0x24, 59 CPL_ACT_OPEN_RPL = 0x25, 60 CPL_PEER_CLOSE = 0x26, 61 CPL_RTE_DELETE_RPL = 0x27, 62 CPL_RTE_WRITE_RPL = 0x28, 63 CPL_RX_URG_PKT = 0x29, 64 CPL_ABORT_REQ_RSS = 0x2B, 65 CPL_RX_URG_NOTIFY = 0x2C, 66 CPL_ABORT_RPL_RSS = 0x2D, 67 CPL_SMT_WRITE_RPL = 0x2E, 68 CPL_TX_DATA_ACK = 0x2F, 69 70 CPL_RX_PHYS_ADDR = 0x30, 71 CPL_PCMD_READ_RPL = 0x31, 72 CPL_CLOSE_CON_RPL = 0x32, 73 CPL_ISCSI_HDR = 0x33, 74 CPL_L2T_READ_RPL = 0x34, 75 CPL_RDMA_CQE = 0x35, 76 CPL_RDMA_CQE_READ_RSP = 0x36, 77 CPL_RDMA_CQE_ERR = 0x37, 78 CPL_RTE_READ_RPL = 0x38, 79 CPL_RX_DATA = 0x39, 80 CPL_SET_TCB_RPL = 0x3A, 81 CPL_RX_PKT = 0x3B, 82 CPL_PCMD_RPL = 0x3C, 83 CPL_HIT_NOTIFY = 0x3D, 84 CPL_PKT_NOTIFY = 0x3E, 85 CPL_RX_DDP_COMPLETE = 0x3F, 86 87 CPL_ACT_ESTABLISH = 0x40, 88 CPL_PASS_ESTABLISH = 0x41, 89 CPL_RX_DATA_DDP = 0x42, 90 CPL_SMT_READ_RPL = 0x43, 91 CPL_PASS_ACCEPT_REQ = 0x44, 92 CPL_RX2TX_PKT = 0x45, 93 CPL_RX_FCOE_DDP = 0x46, 94 CPL_FCOE_HDR = 0x47, 95 96 CPL_RDMA_READ_REQ = 0x60, 97 98 CPL_SET_LE_REQ = 0x80, 99 CPL_PASS_OPEN_REQ6 = 0x81, 100 CPL_ACT_OPEN_REQ6 = 0x83, 101 102 CPL_TX_DMA_ACK = 0xA0, 103 CPL_RDMA_TERMINATE = 0xA2, 104 CPL_RDMA_WRITE = 0xA4, 105 CPL_SGE_EGR_UPDATE = 0xA5, 106 CPL_SET_LE_RPL = 0xA6, 107 CPL_FW2_MSG = 0xA7, 108 CPL_FW2_PLD = 0xA8, 109 110 CPL_TRACE_PKT = 0xB0, 111 CPL_RX2TX_DATA = 0xB1, 112 113 CPL_FW4_MSG = 0xC0, 114 CPL_FW4_PLD = 0xC1, 115 CPL_FW4_ACK = 0xC3, 116 117 CPL_FW6_MSG = 0xE0, 118 CPL_FW6_PLD = 0xE1, 119 CPL_TX_PKT_LSO = 0xED, 120 CPL_TX_PKT_XT = 0xEE, 121 122 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 123 }; 124 125 enum CPL_error { 126 CPL_ERR_NONE = 0, 127 CPL_ERR_TCAM_PARITY = 1, 128 CPL_ERR_TCAM_FULL = 3, 129 CPL_ERR_BAD_LENGTH = 15, 130 CPL_ERR_BAD_ROUTE = 18, 131 CPL_ERR_CONN_RESET = 20, 132 CPL_ERR_CONN_EXIST_SYNRECV = 21, 133 CPL_ERR_CONN_EXIST = 22, 134 CPL_ERR_ARP_MISS = 23, 135 CPL_ERR_BAD_SYN = 24, 136 CPL_ERR_CONN_TIMEDOUT = 30, 137 CPL_ERR_XMIT_TIMEDOUT = 31, 138 CPL_ERR_PERSIST_TIMEDOUT = 32, 139 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 140 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 141 CPL_ERR_RTX_NEG_ADVICE = 35, 142 CPL_ERR_PERSIST_NEG_ADVICE = 36, 143 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 144 CPL_ERR_WAIT_ARP_RPL = 41, 145 CPL_ERR_ABORT_FAILED = 42, 146 CPL_ERR_IWARP_FLM = 50, 147 }; 148 149 enum { 150 CPL_CONN_POLICY_AUTO = 0, 151 CPL_CONN_POLICY_ASK = 1, 152 CPL_CONN_POLICY_FILTER = 2, 153 CPL_CONN_POLICY_DENY = 3 154 }; 155 156 enum { 157 ULP_MODE_NONE = 0, 158 ULP_MODE_ISCSI = 2, 159 ULP_MODE_RDMA = 4, 160 ULP_MODE_TCPDDP = 5, 161 ULP_MODE_FCOE = 6, 162 }; 163 164 enum { 165 ULP_CRC_HEADER = 1 << 0, 166 ULP_CRC_DATA = 1 << 1 167 }; 168 169 enum { 170 CPL_PASS_OPEN_ACCEPT, 171 CPL_PASS_OPEN_REJECT, 172 CPL_PASS_OPEN_ACCEPT_TNL 173 }; 174 175 enum { 176 CPL_ABORT_SEND_RST = 0, 177 CPL_ABORT_NO_RST, 178 }; 179 180 enum { /* TX_PKT_XT checksum types */ 181 TX_CSUM_TCP = 0, 182 TX_CSUM_UDP = 1, 183 TX_CSUM_CRC16 = 4, 184 TX_CSUM_CRC32 = 5, 185 TX_CSUM_CRC32C = 6, 186 TX_CSUM_FCOE = 7, 187 TX_CSUM_TCPIP = 8, 188 TX_CSUM_UDPIP = 9, 189 TX_CSUM_TCPIP6 = 10, 190 TX_CSUM_UDPIP6 = 11, 191 TX_CSUM_IP = 12, 192 }; 193 194 enum { /* packet type in CPL_RX_PKT */ 195 PKTYPE_XACT_UCAST = 0, 196 PKTYPE_HASH_UCAST = 1, 197 PKTYPE_XACT_MCAST = 2, 198 PKTYPE_HASH_MCAST = 3, 199 PKTYPE_PROMISC = 4, 200 PKTYPE_HPROMISC = 5, 201 PKTYPE_BCAST = 6 202 }; 203 204 enum { /* DMAC type in CPL_RX_PKT */ 205 DATYPE_UCAST, 206 DATYPE_MCAST, 207 DATYPE_BCAST 208 }; 209 210 enum { /* TCP congestion control algorithms */ 211 CONG_ALG_RENO, 212 CONG_ALG_TAHOE, 213 CONG_ALG_NEWRENO, 214 CONG_ALG_HIGHSPEED 215 }; 216 217 enum { /* RSS hash type */ 218 RSS_HASH_NONE = 0, /* no hash computed */ 219 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */ 220 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */ 221 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */ 222 }; 223 224 enum { /* LE commands */ 225 LE_CMD_READ = 0x4, 226 LE_CMD_WRITE = 0xb 227 }; 228 229 enum { /* LE request size */ 230 LE_SZ_NONE = 0, 231 LE_SZ_33 = 1, 232 LE_SZ_66 = 2, 233 LE_SZ_132 = 3, 234 LE_SZ_264 = 4, 235 LE_SZ_528 = 5 236 }; 237 238 union opcode_tid { 239 __be32 opcode_tid; 240 __u8 opcode; 241 }; 242 243 #define S_CPL_OPCODE 24 244 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 245 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF) 246 #define G_TID(x) ((x) & 0xFFFFFF) 247 248 /* tid is assumed to be 24-bits */ 249 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) 250 251 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 252 253 /* extract the TID from a CPL command */ 254 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 255 256 /* partitioning of TID fields that also carry a queue id */ 257 #define S_TID_TID 0 258 #define M_TID_TID 0x3fff 259 #define V_TID_TID(x) ((x) << S_TID_TID) 260 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) 261 262 #define S_TID_QID 14 263 #define M_TID_QID 0x3ff 264 #define V_TID_QID(x) ((x) << S_TID_QID) 265 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) 266 267 union opcode_info { 268 __be64 opcode_info; 269 __u8 opcode; 270 }; 271 272 struct tcp_options { 273 __be16 mss; 274 __u8 wsf; 275 #if defined(__LITTLE_ENDIAN_BITFIELD) 276 __u8 :4; 277 __u8 unknown:1; 278 __u8 :1; 279 __u8 sack:1; 280 __u8 tstamp:1; 281 #else 282 __u8 tstamp:1; 283 __u8 sack:1; 284 __u8 :1; 285 __u8 unknown:1; 286 __u8 :4; 287 #endif 288 }; 289 290 struct rss_header { 291 __u8 opcode; 292 #if defined(__LITTLE_ENDIAN_BITFIELD) 293 __u8 channel:2; 294 __u8 filter_hit:1; 295 __u8 filter_tid:1; 296 __u8 hash_type:2; 297 __u8 ipv6:1; 298 __u8 send2fw:1; 299 #else 300 __u8 send2fw:1; 301 __u8 ipv6:1; 302 __u8 hash_type:2; 303 __u8 filter_tid:1; 304 __u8 filter_hit:1; 305 __u8 channel:2; 306 #endif 307 __be16 qid; 308 __be32 hash_val; 309 }; 310 311 #define S_HASHTYPE 20 312 #define M_HASHTYPE 0x3 313 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 314 315 #define S_QNUM 0 316 #define M_QNUM 0xFFFF 317 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 318 319 #ifndef CHELSIO_FW 320 struct work_request_hdr { 321 __be32 wr_hi; 322 __be32 wr_mid; 323 __be64 wr_lo; 324 }; 325 326 /* wr_mid fields */ 327 #define S_WR_LEN16 0 328 #define M_WR_LEN16 0xFF 329 #define V_WR_LEN16(x) ((x) << S_WR_LEN16) 330 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16) 331 332 /* wr_hi fields */ 333 #define S_WR_OP 24 334 #define M_WR_OP 0xFF 335 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 336 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 337 338 #define WR_HDR struct work_request_hdr wr 339 #define WR_HDR_SIZE sizeof (struct work_request_hdr) 340 #define RSS_HDR 341 #else 342 #define WR_HDR 343 #define WR_HDR_SIZE 0 344 #define RSS_HDR struct rss_header rss_hdr; 345 #endif 346 347 /* option 0 fields */ 348 #define S_ACCEPT_MODE 0 349 #define M_ACCEPT_MODE 0x3 350 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) 351 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) 352 353 #define S_TX_CHAN 2 354 #define M_TX_CHAN 0x3 355 #define V_TX_CHAN(x) ((x) << S_TX_CHAN) 356 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) 357 358 #define S_NO_CONG 4 359 #define V_NO_CONG(x) ((x) << S_NO_CONG) 360 #define F_NO_CONG V_NO_CONG(1U) 361 362 #define S_DELACK 5 363 #define V_DELACK(x) ((x) << S_DELACK) 364 #define F_DELACK V_DELACK(1U) 365 366 #define S_INJECT_TIMER 6 367 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 368 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 369 370 #define S_NON_OFFLOAD 7 371 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD) 372 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U) 373 374 #define S_ULP_MODE 8 375 #define M_ULP_MODE 0xF 376 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 377 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 378 379 #define S_RCV_BUFSIZ 12 380 #define M_RCV_BUFSIZ 0x3FFU 381 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 382 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 383 384 #define S_DSCP 22 385 #define M_DSCP 0x3F 386 #define V_DSCP(x) ((x) << S_DSCP) 387 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) 388 389 #define S_SMAC_SEL 28 390 #define M_SMAC_SEL 0xFF 391 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL) 392 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) 393 394 #define S_L2T_IDX 36 395 #define M_L2T_IDX 0xFFF 396 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX) 397 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 398 399 #define S_TCAM_BYPASS 48 400 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS) 401 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL) 402 403 #define S_NAGLE 49 404 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE) 405 #define F_NAGLE V_NAGLE(1ULL) 406 407 #define S_WND_SCALE 50 408 #define M_WND_SCALE 0xF 409 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE) 410 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 411 412 #define S_KEEP_ALIVE 54 413 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE) 414 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL) 415 416 #define S_MAX_RT 55 417 #define M_MAX_RT 0xF 418 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) 419 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) 420 421 #define S_MAX_RT_OVERRIDE 59 422 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE) 423 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL) 424 425 #define S_MSS_IDX 60 426 #define M_MSS_IDX 0xF 427 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 428 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 429 430 /* option 1 fields */ 431 #define S_SYN_RSS_ENABLE 0 432 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE) 433 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U) 434 435 #define S_SYN_RSS_USE_HASH 1 436 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH) 437 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U) 438 439 #define S_SYN_RSS_QUEUE 2 440 #define M_SYN_RSS_QUEUE 0x3FF 441 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE) 442 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) 443 444 #define S_LISTEN_INTF 12 445 #define M_LISTEN_INTF 0xFF 446 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) 447 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) 448 449 #define S_LISTEN_FILTER 20 450 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER) 451 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U) 452 453 #define S_SYN_DEFENSE 21 454 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 455 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 456 457 #define S_CONN_POLICY 22 458 #define M_CONN_POLICY 0x3 459 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 460 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 461 462 /* option 2 fields */ 463 #define S_RSS_QUEUE 0 464 #define M_RSS_QUEUE 0x3FF 465 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 466 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 467 468 #define S_RSS_QUEUE_VALID 10 469 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID) 470 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U) 471 472 #define S_RX_COALESCE_VALID 11 473 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 474 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 475 476 #define S_RX_COALESCE 12 477 #define M_RX_COALESCE 0x3 478 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 479 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 480 481 #define S_CONG_CNTRL 14 482 #define M_CONG_CNTRL 0x3 483 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL) 484 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) 485 486 #define S_PACE 16 487 #define M_PACE 0x3 488 #define V_PACE(x) ((x) << S_PACE) 489 #define G_PACE(x) (((x) >> S_PACE) & M_PACE) 490 491 #define S_CONG_CNTRL_VALID 18 492 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID) 493 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U) 494 495 #define S_PACE_VALID 19 496 #define V_PACE_VALID(x) ((x) << S_PACE_VALID) 497 #define F_PACE_VALID V_PACE_VALID(1U) 498 499 #define S_RX_FC_DISABLE 20 500 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 501 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 502 503 #define S_RX_FC_DDP 21 504 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP) 505 #define F_RX_FC_DDP V_RX_FC_DDP(1U) 506 507 #define S_RX_FC_VALID 22 508 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 509 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 510 511 #define S_TX_QUEUE 23 512 #define M_TX_QUEUE 0x7 513 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE) 514 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) 515 516 #define S_RX_CHANNEL 26 517 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL) 518 #define F_RX_CHANNEL V_RX_CHANNEL(1U) 519 520 #define S_CCTRL_ECN 27 521 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN) 522 #define F_CCTRL_ECN V_CCTRL_ECN(1U) 523 524 #define S_WND_SCALE_EN 28 525 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN) 526 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U) 527 528 #define S_TSTAMPS_EN 29 529 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN) 530 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U) 531 532 #define S_SACK_EN 30 533 #define V_SACK_EN(x) ((x) << S_SACK_EN) 534 #define F_SACK_EN V_SACK_EN(1U) 535 536 struct cpl_pass_open_req { 537 WR_HDR; 538 union opcode_tid ot; 539 __be16 local_port; 540 __be16 peer_port; 541 __be32 local_ip; 542 __be32 peer_ip; 543 __be64 opt0; 544 __be64 opt1; 545 }; 546 547 struct cpl_pass_open_req6 { 548 WR_HDR; 549 union opcode_tid ot; 550 __be16 local_port; 551 __be16 peer_port; 552 __be64 local_ip_hi; 553 __be64 local_ip_lo; 554 __be64 peer_ip_hi; 555 __be64 peer_ip_lo; 556 __be64 opt0; 557 __be64 opt1; 558 }; 559 560 struct cpl_pass_open_rpl { 561 RSS_HDR 562 union opcode_tid ot; 563 __u8 rsvd[3]; 564 __u8 status; 565 }; 566 567 struct cpl_pass_establish { 568 RSS_HDR 569 union opcode_tid ot; 570 __be32 rsvd; 571 __be32 tos_stid; 572 __be16 mac_idx; 573 __be16 tcp_opt; 574 __be32 snd_isn; 575 __be32 rcv_isn; 576 }; 577 578 /* cpl_pass_establish.tos_stid fields */ 579 #define S_PASS_OPEN_TID 0 580 #define M_PASS_OPEN_TID 0xFFFFFF 581 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 582 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 583 584 #define S_PASS_OPEN_TOS 24 585 #define M_PASS_OPEN_TOS 0xFF 586 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 587 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 588 589 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 590 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 591 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1) 592 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 593 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 594 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 595 596 struct cpl_pass_accept_req { 597 RSS_HDR 598 union opcode_tid ot; 599 __be16 rsvd; 600 __be16 len; 601 __be32 hdr_len; 602 __be16 vlan; 603 __be16 l2info; 604 __be32 tos_stid; 605 struct tcp_options tcpopt; 606 }; 607 608 /* cpl_pass_accept_req.hdr_len fields */ 609 #define S_SYN_RX_CHAN 0 610 #define M_SYN_RX_CHAN 0xF 611 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) 612 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) 613 614 #define S_TCP_HDR_LEN 10 615 #define M_TCP_HDR_LEN 0x3F 616 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) 617 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 618 619 #define S_IP_HDR_LEN 16 620 #define M_IP_HDR_LEN 0x3FF 621 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 622 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 623 624 #define S_ETH_HDR_LEN 26 625 #define M_ETH_HDR_LEN 0x1F 626 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 627 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 628 629 /* cpl_pass_accept_req.l2info fields */ 630 #define S_SYN_MAC_IDX 0 631 #define M_SYN_MAC_IDX 0x1FF 632 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 633 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) 634 635 #define S_SYN_XACT_MATCH 9 636 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH) 637 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U) 638 639 #define S_SYN_INTF 12 640 #define M_SYN_INTF 0xF 641 #define V_SYN_INTF(x) ((x) << S_SYN_INTF) 642 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF) 643 644 struct cpl_pass_accept_rpl { 645 WR_HDR; 646 union opcode_tid ot; 647 __be32 opt2; 648 __be64 opt0; 649 }; 650 651 struct cpl_act_open_req { 652 WR_HDR; 653 union opcode_tid ot; 654 __be16 local_port; 655 __be16 peer_port; 656 __be32 local_ip; 657 __be32 peer_ip; 658 __be64 opt0; 659 __be32 params; 660 __be32 opt2; 661 }; 662 663 struct cpl_act_open_req6 { 664 WR_HDR; 665 union opcode_tid ot; 666 __be16 local_port; 667 __be16 peer_port; 668 __be64 local_ip_hi; 669 __be64 local_ip_lo; 670 __be64 peer_ip_hi; 671 __be64 peer_ip_lo; 672 __be64 opt0; 673 __be32 params; 674 __be32 opt2; 675 }; 676 677 struct cpl_act_open_rpl { 678 RSS_HDR 679 union opcode_tid ot; 680 __be32 atid_status; 681 }; 682 683 /* cpl_act_open_rpl.atid_status fields */ 684 #define S_AOPEN_STATUS 0 685 #define M_AOPEN_STATUS 0xFF 686 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) 687 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS) 688 689 #define S_AOPEN_ATID 8 690 #define M_AOPEN_ATID 0xFFFFFF 691 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) 692 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID) 693 694 struct cpl_act_establish { 695 RSS_HDR 696 union opcode_tid ot; 697 __be32 rsvd; 698 __be32 tos_atid; 699 __be16 mac_idx; 700 __be16 tcp_opt; 701 __be32 snd_isn; 702 __be32 rcv_isn; 703 }; 704 705 struct cpl_get_tcb { 706 WR_HDR; 707 union opcode_tid ot; 708 __be16 reply_ctrl; 709 __be16 cookie; 710 }; 711 712 /* cpl_get_tcb.reply_ctrl fields */ 713 #define S_QUEUENO 0 714 #define M_QUEUENO 0x3FF 715 #define V_QUEUENO(x) ((x) << S_QUEUENO) 716 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) 717 718 #define S_REPLY_CHAN 14 719 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) 720 #define F_REPLY_CHAN V_REPLY_CHAN(1U) 721 722 #define S_NO_REPLY 15 723 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 724 #define F_NO_REPLY V_NO_REPLY(1U) 725 726 struct cpl_get_tcb_rpl { 727 RSS_HDR 728 union opcode_tid ot; 729 __u8 cookie; 730 __u8 status; 731 __be16 len; 732 }; 733 734 struct cpl_set_tcb { 735 WR_HDR; 736 union opcode_tid ot; 737 __be16 reply_ctrl; 738 __be16 cookie; 739 }; 740 741 struct cpl_set_tcb_field { 742 WR_HDR; 743 union opcode_tid ot; 744 __be16 reply_ctrl; 745 __be16 word_cookie; 746 __be64 mask; 747 __be64 val; 748 }; 749 750 /* cpl_set_tcb_field.word_cookie fields */ 751 #define S_WORD 0 752 #define M_WORD 0x1F 753 #define V_WORD(x) ((x) << S_WORD) 754 #define G_WORD(x) (((x) >> S_WORD) & M_WORD) 755 756 #define S_COOKIE 5 757 #define M_COOKIE 0x7 758 #define V_COOKIE(x) ((x) << S_COOKIE) 759 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE) 760 761 struct cpl_set_tcb_rpl { 762 RSS_HDR 763 union opcode_tid ot; 764 __be16 rsvd; 765 __u8 cookie; 766 __u8 status; 767 __be64 oldval; 768 }; 769 770 struct cpl_close_con_req { 771 WR_HDR; 772 union opcode_tid ot; 773 __be32 rsvd; 774 }; 775 776 struct cpl_close_con_rpl { 777 RSS_HDR 778 union opcode_tid ot; 779 __u8 rsvd[3]; 780 __u8 status; 781 __be32 snd_nxt; 782 __be32 rcv_nxt; 783 }; 784 785 struct cpl_close_listsvr_req { 786 WR_HDR; 787 union opcode_tid ot; 788 __be16 reply_ctrl; 789 __be16 rsvd; 790 }; 791 792 /* additional cpl_close_listsvr_req.reply_ctrl field */ 793 #define S_LISTSVR_IPV6 14 794 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6) 795 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U) 796 797 struct cpl_close_listsvr_rpl { 798 RSS_HDR 799 union opcode_tid ot; 800 __u8 rsvd[3]; 801 __u8 status; 802 }; 803 804 struct cpl_abort_req_rss { 805 RSS_HDR 806 union opcode_tid ot; 807 __u8 rsvd[3]; 808 __u8 status; 809 }; 810 811 struct cpl_abort_req { 812 WR_HDR; 813 union opcode_tid ot; 814 __be32 rsvd0; 815 __u8 rsvd1; 816 __u8 cmd; 817 __u8 rsvd2[6]; 818 }; 819 820 struct cpl_abort_rpl_rss { 821 RSS_HDR 822 union opcode_tid ot; 823 __u8 rsvd[3]; 824 __u8 status; 825 }; 826 827 struct cpl_abort_rpl { 828 WR_HDR; 829 union opcode_tid ot; 830 __be32 rsvd0; 831 __u8 rsvd1; 832 __u8 cmd; 833 __u8 rsvd2[6]; 834 }; 835 836 struct cpl_peer_close { 837 RSS_HDR 838 union opcode_tid ot; 839 __be32 rcv_nxt; 840 }; 841 842 struct cpl_tid_release { 843 WR_HDR; 844 union opcode_tid ot; 845 __be32 rsvd; 846 }; 847 848 struct tx_data_wr { 849 __be32 wr_hi; 850 __be32 wr_lo; 851 __be32 len; 852 __be32 flags; 853 __be32 sndseq; 854 __be32 param; 855 }; 856 857 /* tx_data_wr.flags fields */ 858 #define S_TX_ACK_PAGES 21 859 #define M_TX_ACK_PAGES 0x7 860 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 861 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 862 863 /* tx_data_wr.param fields */ 864 #define S_TX_PORT 0 865 #define M_TX_PORT 0x7 866 #define V_TX_PORT(x) ((x) << S_TX_PORT) 867 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 868 869 #define S_TX_MSS 4 870 #define M_TX_MSS 0xF 871 #define V_TX_MSS(x) ((x) << S_TX_MSS) 872 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 873 874 #define S_TX_QOS 8 875 #define M_TX_QOS 0xFF 876 #define V_TX_QOS(x) ((x) << S_TX_QOS) 877 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 878 879 #define S_TX_SNDBUF 16 880 #define M_TX_SNDBUF 0xFFFF 881 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 882 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 883 884 struct cpl_tx_data { 885 union opcode_tid ot; 886 __be32 len; 887 __be32 rsvd; 888 __be32 flags; 889 }; 890 891 /* cpl_tx_data.flags fields */ 892 #define S_TX_PROXY 5 893 #define V_TX_PROXY(x) ((x) << S_TX_PROXY) 894 #define F_TX_PROXY V_TX_PROXY(1U) 895 896 #define S_TX_ULP_SUBMODE 6 897 #define M_TX_ULP_SUBMODE 0xF 898 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 899 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 900 901 #define S_TX_ULP_MODE 10 902 #define M_TX_ULP_MODE 0xF 903 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 904 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 905 906 #define S_TX_SHOVE 14 907 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 908 #define F_TX_SHOVE V_TX_SHOVE(1U) 909 910 #define S_TX_MORE 15 911 #define V_TX_MORE(x) ((x) << S_TX_MORE) 912 #define F_TX_MORE V_TX_MORE(1U) 913 914 #define S_TX_URG 16 915 #define V_TX_URG(x) ((x) << S_TX_URG) 916 #define F_TX_URG V_TX_URG(1U) 917 918 #define S_TX_FLUSH 17 919 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH) 920 #define F_TX_FLUSH V_TX_FLUSH(1U) 921 922 #define S_TX_SAVE 18 923 #define V_TX_SAVE(x) ((x) << S_TX_SAVE) 924 #define F_TX_SAVE V_TX_SAVE(1U) 925 926 #define S_TX_TNL 19 927 #define V_TX_TNL(x) ((x) << S_TX_TNL) 928 #define F_TX_TNL V_TX_TNL(1U) 929 930 /* additional tx_data_wr.flags fields */ 931 #define S_TX_CPU_IDX 0 932 #define M_TX_CPU_IDX 0x3F 933 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 934 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 935 936 #define S_TX_CLOSE 17 937 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 938 #define F_TX_CLOSE V_TX_CLOSE(1U) 939 940 #define S_TX_INIT 18 941 #define V_TX_INIT(x) ((x) << S_TX_INIT) 942 #define F_TX_INIT V_TX_INIT(1U) 943 944 #define S_TX_IMM_ACK 19 945 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 946 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 947 948 #define S_TX_IMM_DMA 20 949 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 950 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 951 952 struct cpl_tx_data_ack { 953 RSS_HDR 954 union opcode_tid ot; 955 __be32 snd_una; 956 }; 957 958 struct cpl_wr_ack { /* TODO */ 959 RSS_HDR 960 union opcode_tid ot; 961 __be16 credits; 962 __be16 rsvd; 963 __be32 snd_nxt; 964 __be32 snd_una; 965 }; 966 967 struct cpl_tx_pkt_core { 968 __be32 ctrl0; 969 __be16 pack; 970 __be16 len; 971 __be64 ctrl1; 972 }; 973 974 struct cpl_tx_pkt { 975 WR_HDR; 976 struct cpl_tx_pkt_core c; 977 }; 978 979 #define cpl_tx_pkt_xt cpl_tx_pkt 980 981 /* cpl_tx_pkt_core.ctrl0 fields */ 982 #define S_TXPKT_VF 0 983 #define M_TXPKT_VF 0xFF 984 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF) 985 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) 986 987 #define S_TXPKT_PF 8 988 #define M_TXPKT_PF 0x7 989 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 990 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 991 992 #define S_TXPKT_VF_VLD 11 993 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD) 994 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U) 995 996 #define S_TXPKT_OVLAN_IDX 12 997 #define M_TXPKT_OVLAN_IDX 0xF 998 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) 999 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) 1000 1001 #define S_TXPKT_INTF 16 1002 #define M_TXPKT_INTF 0xF 1003 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1004 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1005 1006 #define S_TXPKT_SPECIAL_STAT 20 1007 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) 1008 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) 1009 1010 #define S_TXPKT_INS_OVLAN 21 1011 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) 1012 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) 1013 1014 #define S_TXPKT_STAT_DIS 22 1015 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1016 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1017 1018 #define S_TXPKT_LOOPBACK 23 1019 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1020 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1021 1022 #define S_TXPKT_OPCODE 24 1023 #define M_TXPKT_OPCODE 0xFF 1024 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1025 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1026 1027 /* cpl_tx_pkt_core.ctrl1 fields */ 1028 #define S_TXPKT_SA_IDX 0 1029 #define M_TXPKT_SA_IDX 0xFFF 1030 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) 1031 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) 1032 1033 #define S_TXPKT_CSUM_END 12 1034 #define M_TXPKT_CSUM_END 0xFF 1035 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) 1036 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) 1037 1038 #define S_TXPKT_CSUM_START 20 1039 #define M_TXPKT_CSUM_START 0x3FF 1040 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) 1041 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) 1042 1043 #define S_TXPKT_IPHDR_LEN 20 1044 #define M_TXPKT_IPHDR_LEN 0x3FFF 1045 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 1046 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 1047 1048 #define S_TXPKT_CSUM_LOC 30 1049 #define M_TXPKT_CSUM_LOC 0x3FF 1050 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) 1051 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) 1052 1053 #define S_TXPKT_ETHHDR_LEN 34 1054 #define M_TXPKT_ETHHDR_LEN 0x3F 1055 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 1056 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 1057 1058 #define S_TXPKT_CSUM_TYPE 40 1059 #define M_TXPKT_CSUM_TYPE 0xF 1060 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 1061 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 1062 1063 #define S_TXPKT_VLAN 44 1064 #define M_TXPKT_VLAN 0xFFFF 1065 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 1066 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1067 1068 #define S_TXPKT_VLAN_VLD 60 1069 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 1070 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 1071 1072 #define S_TXPKT_IPSEC 61 1073 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC) 1074 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL) 1075 1076 #define S_TXPKT_IPCSUM_DIS 62 1077 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1078 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1079 1080 #define S_TXPKT_L4CSUM_DIS 63 1081 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1082 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1083 1084 struct cpl_tx_pkt_lso { 1085 __be32 lso_ctrl; 1086 __be16 ipid_ofst; 1087 __be16 mss; 1088 __be32 seqno_offset; 1089 __be32 len; 1090 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1091 }; 1092 1093 /* cpl_tx_pkt_lso.lso_ctrl fields */ 1094 #define S_LSO_TCPHDR_LEN 0 1095 #define M_LSO_TCPHDR_LEN 0xF 1096 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 1097 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 1098 1099 #define S_LSO_IPHDR_LEN 4 1100 #define M_LSO_IPHDR_LEN 0xFFF 1101 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 1102 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 1103 1104 #define S_LSO_ETHHDR_LEN 16 1105 #define M_LSO_ETHHDR_LEN 0xF 1106 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 1107 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 1108 1109 #define S_LSO_IPV6 20 1110 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1111 #define F_LSO_IPV6 V_LSO_IPV6(1U) 1112 1113 #define S_LSO_OFLD_ENCAP 21 1114 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP) 1115 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U) 1116 1117 #define S_LSO_LAST_SLICE 22 1118 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 1119 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 1120 1121 #define S_LSO_FIRST_SLICE 23 1122 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 1123 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 1124 1125 #define S_LSO_OPCODE 24 1126 #define M_LSO_OPCODE 0xFF 1127 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 1128 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 1129 1130 /* cpl_tx_pkt_lso.mss fields */ 1131 #define S_LSO_MSS 0 1132 #define M_LSO_MSS 0x3FFF 1133 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1134 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1135 1136 #define S_LSO_IPID_SPLIT 15 1137 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 1138 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 1139 1140 struct cpl_tx_pkt_coalesce { 1141 __be32 cntrl; 1142 __be32 len; 1143 __be64 addr; 1144 }; 1145 1146 struct tx_pkt_coalesce_wr { 1147 WR_HDR; 1148 #if !(defined C99_NOT_SUPPORTED) 1149 struct cpl_tx_pkt_coalesce cpl[]; 1150 #endif 1151 }; 1152 1153 struct mngt_pktsched_wr { 1154 __be32 wr_hi; 1155 __be32 wr_lo; 1156 __u8 mngt_opcode; 1157 __u8 rsvd[7]; 1158 __u8 sched; 1159 __u8 idx; 1160 __u8 min; 1161 __u8 max; 1162 __u8 binding; 1163 __u8 rsvd1[3]; 1164 }; 1165 1166 struct cpl_iscsi_hdr_no_rss { 1167 union opcode_tid ot; 1168 __be16 pdu_len_ddp; 1169 __be16 len; 1170 __be32 seq; 1171 __be16 urg; 1172 __u8 rsvd; 1173 __u8 status; 1174 }; 1175 1176 struct cpl_iscsi_hdr { 1177 RSS_HDR 1178 union opcode_tid ot; 1179 __be16 pdu_len_ddp; 1180 __be16 len; 1181 __be32 seq; 1182 __be16 urg; 1183 __u8 rsvd; 1184 __u8 status; 1185 }; 1186 1187 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 1188 #define S_ISCSI_PDU_LEN 0 1189 #define M_ISCSI_PDU_LEN 0x7FFF 1190 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 1191 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 1192 1193 #define S_ISCSI_DDP 15 1194 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 1195 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 1196 1197 struct cpl_rx_data { 1198 RSS_HDR 1199 union opcode_tid ot; 1200 __be16 rsvd; 1201 __be16 len; 1202 __be32 seq; 1203 __be16 urg; 1204 #if defined(__LITTLE_ENDIAN_BITFIELD) 1205 __u8 dack_mode:2; 1206 __u8 psh:1; 1207 __u8 heartbeat:1; 1208 __u8 ddp_off:1; 1209 __u8 :3; 1210 #else 1211 __u8 :3; 1212 __u8 ddp_off:1; 1213 __u8 heartbeat:1; 1214 __u8 psh:1; 1215 __u8 dack_mode:2; 1216 #endif 1217 __u8 status; 1218 }; 1219 1220 struct cpl_fcoe_hdr { 1221 RSS_HDR 1222 union opcode_tid ot; 1223 __be16 oxid; 1224 __be16 len; 1225 __be32 rctl_fctl; 1226 __u8 cs_ctl; 1227 __u8 df_ctl; 1228 __u8 sof; 1229 __u8 eof; 1230 __be16 seq_cnt; 1231 __u8 seq_id; 1232 __u8 type; 1233 __be32 param; 1234 }; 1235 1236 struct cpl_rx_urg_notify { 1237 RSS_HDR 1238 union opcode_tid ot; 1239 __be32 seq; 1240 }; 1241 1242 struct cpl_rx_urg_pkt { 1243 RSS_HDR 1244 union opcode_tid ot; 1245 __be16 rsvd; 1246 __be16 len; 1247 }; 1248 1249 struct cpl_rx_data_ack { 1250 WR_HDR; 1251 union opcode_tid ot; 1252 __be32 credit_dack; 1253 }; 1254 1255 /* cpl_rx_data_ack.ack_seq fields */ 1256 #define S_RX_CREDITS 0 1257 #define M_RX_CREDITS 0x3FFFFFF 1258 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 1259 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 1260 1261 #define S_RX_MODULATE_TX 26 1262 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX) 1263 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U) 1264 1265 #define S_RX_MODULATE_RX 27 1266 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX) 1267 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U) 1268 1269 #define S_RX_FORCE_ACK 28 1270 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1271 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1272 1273 #define S_RX_DACK_MODE 29 1274 #define M_RX_DACK_MODE 0x3 1275 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1276 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1277 1278 #define S_RX_DACK_CHANGE 31 1279 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1280 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1281 1282 struct cpl_rx_ddp_complete { 1283 RSS_HDR 1284 union opcode_tid ot; 1285 __be32 ddp_report; 1286 __be32 rcv_nxt; 1287 __be32 rsvd; 1288 }; 1289 1290 struct cpl_rx_data_ddp { 1291 RSS_HDR 1292 union opcode_tid ot; 1293 __be16 urg; 1294 __be16 len; 1295 __be32 seq; 1296 union { 1297 __be32 nxt_seq; 1298 __be32 ddp_report; 1299 } u; 1300 __be32 ulp_crc; 1301 __be32 ddpvld; 1302 }; 1303 1304 struct cpl_rx_fcoe_ddp { 1305 RSS_HDR 1306 union opcode_tid ot; 1307 __be16 rsvd; 1308 __be16 len; 1309 __be32 seq; 1310 __be32 ddp_report; 1311 __be32 ulp_crc; 1312 __be32 ddpvld; 1313 }; 1314 1315 /* cpl_rx_{data,fcoe}_ddp.ddpvld fields */ 1316 #define S_DDP_VALID 15 1317 #define M_DDP_VALID 0x1FFFF 1318 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1319 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1320 1321 #define S_DDP_PPOD_MISMATCH 15 1322 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1323 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1324 1325 #define S_DDP_PDU 16 1326 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1327 #define F_DDP_PDU V_DDP_PDU(1U) 1328 1329 #define S_DDP_LLIMIT_ERR 17 1330 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1331 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1332 1333 #define S_DDP_PPOD_PARITY_ERR 18 1334 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1335 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1336 1337 #define S_DDP_PADDING_ERR 19 1338 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1339 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1340 1341 #define S_DDP_HDRCRC_ERR 20 1342 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1343 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1344 1345 #define S_DDP_DATACRC_ERR 21 1346 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1347 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1348 1349 #define S_DDP_INVALID_TAG 22 1350 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1351 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1352 1353 #define S_DDP_ULIMIT_ERR 23 1354 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1355 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1356 1357 #define S_DDP_OFFSET_ERR 24 1358 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1359 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1360 1361 #define S_DDP_COLOR_ERR 25 1362 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1363 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1364 1365 #define S_DDP_TID_MISMATCH 26 1366 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1367 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1368 1369 #define S_DDP_INVALID_PPOD 27 1370 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1371 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1372 1373 #define S_DDP_ULP_MODE 28 1374 #define M_DDP_ULP_MODE 0xF 1375 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1376 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1377 1378 /* cpl_rx_{data,fcoe}_ddp.ddp_report fields */ 1379 #define S_DDP_OFFSET 0 1380 #define M_DDP_OFFSET 0xFFFFFF 1381 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1382 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1383 1384 #define S_DDP_DACK_MODE 24 1385 #define M_DDP_DACK_MODE 0x3 1386 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1387 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1388 1389 #define S_DDP_BUF_IDX 26 1390 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1391 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1392 1393 #define S_DDP_URG 27 1394 #define V_DDP_URG(x) ((x) << S_DDP_URG) 1395 #define F_DDP_URG V_DDP_URG(1U) 1396 1397 #define S_DDP_PSH 28 1398 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1399 #define F_DDP_PSH V_DDP_PSH(1U) 1400 1401 #define S_DDP_BUF_COMPLETE 29 1402 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1403 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1404 1405 #define S_DDP_BUF_TIMED_OUT 30 1406 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1407 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1408 1409 #define S_DDP_INV 31 1410 #define V_DDP_INV(x) ((x) << S_DDP_INV) 1411 #define F_DDP_INV V_DDP_INV(1U) 1412 1413 struct cpl_rx_pkt { 1414 RSS_HDR 1415 __u8 opcode; 1416 #if defined(__LITTLE_ENDIAN_BITFIELD) 1417 __u8 iff:4; 1418 __u8 csum_calc:1; 1419 __u8 ipmi_pkt:1; 1420 __u8 vlan_ex:1; 1421 __u8 ip_frag:1; 1422 #else 1423 __u8 ip_frag:1; 1424 __u8 vlan_ex:1; 1425 __u8 ipmi_pkt:1; 1426 __u8 csum_calc:1; 1427 __u8 iff:4; 1428 #endif 1429 __be16 csum; 1430 __be16 vlan; 1431 __be16 len; 1432 __be32 l2info; 1433 __be16 hdr_len; 1434 __be16 err_vec; 1435 }; 1436 1437 /* rx_pkt.l2info fields */ 1438 #define S_RX_ETHHDR_LEN 0 1439 #define M_RX_ETHHDR_LEN 0x1F 1440 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 1441 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 1442 1443 #define S_RX_PKTYPE 5 1444 #define M_RX_PKTYPE 0x7 1445 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 1446 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 1447 1448 #define S_RX_MACIDX 8 1449 #define M_RX_MACIDX 0x1FF 1450 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 1451 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 1452 1453 #define S_RX_DATYPE 18 1454 #define M_RX_DATYPE 0x3 1455 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 1456 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 1457 1458 #define S_RXF_PSH 20 1459 #define V_RXF_PSH(x) ((x) << S_RXF_PSH) 1460 #define F_RXF_PSH V_RXF_PSH(1U) 1461 1462 #define S_RXF_SYN 21 1463 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 1464 #define F_RXF_SYN V_RXF_SYN(1U) 1465 1466 #define S_RXF_UDP 22 1467 #define V_RXF_UDP(x) ((x) << S_RXF_UDP) 1468 #define F_RXF_UDP V_RXF_UDP(1U) 1469 1470 #define S_RXF_TCP 23 1471 #define V_RXF_TCP(x) ((x) << S_RXF_TCP) 1472 #define F_RXF_TCP V_RXF_TCP(1U) 1473 1474 #define S_RXF_IP 24 1475 #define V_RXF_IP(x) ((x) << S_RXF_IP) 1476 #define F_RXF_IP V_RXF_IP(1U) 1477 1478 #define S_RXF_IP6 25 1479 #define V_RXF_IP6(x) ((x) << S_RXF_IP6) 1480 #define F_RXF_IP6 V_RXF_IP6(1U) 1481 1482 #define S_RXF_SYN_COOKIE 26 1483 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE) 1484 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U) 1485 1486 #define S_RXF_FCOE 26 1487 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE) 1488 #define F_RXF_FCOE V_RXF_FCOE(1U) 1489 1490 #define S_RXF_LRO 27 1491 #define V_RXF_LRO(x) ((x) << S_RXF_LRO) 1492 #define F_RXF_LRO V_RXF_LRO(1U) 1493 1494 #define S_RX_CHAN 28 1495 #define M_RX_CHAN 0xF 1496 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 1497 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 1498 1499 /* rx_pkt.hdr_len fields */ 1500 #define S_RX_TCPHDR_LEN 0 1501 #define M_RX_TCPHDR_LEN 0x3F 1502 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 1503 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 1504 1505 #define S_RX_IPHDR_LEN 6 1506 #define M_RX_IPHDR_LEN 0x3FF 1507 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 1508 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 1509 1510 /* rx_pkt.err_vec fields */ 1511 #define S_RXERR_OR 0 1512 #define V_RXERR_OR(x) ((x) << S_RXERR_OR) 1513 #define F_RXERR_OR V_RXERR_OR(1U) 1514 1515 #define S_RXERR_MAC 1 1516 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC) 1517 #define F_RXERR_MAC V_RXERR_MAC(1U) 1518 1519 #define S_RXERR_IPVERS 2 1520 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS) 1521 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U) 1522 1523 #define S_RXERR_FRAG 3 1524 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG) 1525 #define F_RXERR_FRAG V_RXERR_FRAG(1U) 1526 1527 #define S_RXERR_ATTACK 4 1528 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK) 1529 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U) 1530 1531 #define S_RXERR_ETHHDR_LEN 5 1532 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN) 1533 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U) 1534 1535 #define S_RXERR_IPHDR_LEN 6 1536 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN) 1537 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U) 1538 1539 #define S_RXERR_TCPHDR_LEN 7 1540 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN) 1541 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U) 1542 1543 #define S_RXERR_PKT_LEN 8 1544 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN) 1545 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U) 1546 1547 #define S_RXERR_TCP_OPT 9 1548 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT) 1549 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U) 1550 1551 #define S_RXERR_IPCSUM 12 1552 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM) 1553 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U) 1554 1555 #define S_RXERR_CSUM 13 1556 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM) 1557 #define F_RXERR_CSUM V_RXERR_CSUM(1U) 1558 1559 #define S_RXERR_PING 14 1560 #define V_RXERR_PING(x) ((x) << S_RXERR_PING) 1561 #define F_RXERR_PING V_RXERR_PING(1U) 1562 1563 struct cpl_trace_pkt { 1564 RSS_HDR 1565 __u8 opcode; 1566 __u8 intf; 1567 #if defined(__LITTLE_ENDIAN_BITFIELD) 1568 __u8 runt:4; 1569 __u8 filter_hit:4; 1570 __u8 :6; 1571 __u8 err:1; 1572 __u8 trunc:1; 1573 #else 1574 __u8 filter_hit:4; 1575 __u8 runt:4; 1576 __u8 trunc:1; 1577 __u8 err:1; 1578 __u8 :6; 1579 #endif 1580 __be16 rsvd; 1581 __be16 len; 1582 __be64 tstamp; 1583 }; 1584 1585 struct cpl_rte_delete_req { 1586 WR_HDR; 1587 union opcode_tid ot; 1588 __be32 params; 1589 }; 1590 1591 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 1592 #define S_RTE_REQ_LUT_IX 8 1593 #define M_RTE_REQ_LUT_IX 0x7FF 1594 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 1595 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 1596 1597 #define S_RTE_REQ_LUT_BASE 19 1598 #define M_RTE_REQ_LUT_BASE 0x7FF 1599 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 1600 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 1601 1602 #define S_RTE_READ_REQ_SELECT 31 1603 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 1604 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 1605 1606 struct cpl_rte_delete_rpl { 1607 RSS_HDR 1608 union opcode_tid ot; 1609 __u8 status; 1610 __u8 rsvd[3]; 1611 }; 1612 1613 struct cpl_rte_write_req { 1614 WR_HDR; 1615 union opcode_tid ot; 1616 __u32 write_sel; 1617 __be32 lut_params; 1618 __be32 l2t_idx; 1619 __be32 netmask; 1620 __be32 faddr; 1621 }; 1622 1623 /* cpl_rte_write_req.write_sel fields */ 1624 #define S_RTE_WR_L2TIDX 31 1625 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX) 1626 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U) 1627 1628 #define S_RTE_WR_FADDR 30 1629 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR) 1630 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U) 1631 1632 /* cpl_rte_write_req.lut_params fields */ 1633 #define S_RTE_WR_LUT_IX 10 1634 #define M_RTE_WR_LUT_IX 0x7FF 1635 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) 1636 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) 1637 1638 #define S_RTE_WR_LUT_BASE 21 1639 #define M_RTE_WR_LUT_BASE 0x7FF 1640 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) 1641 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) 1642 1643 struct cpl_rte_write_rpl { 1644 RSS_HDR 1645 union opcode_tid ot; 1646 __u8 status; 1647 __u8 rsvd[3]; 1648 }; 1649 1650 struct cpl_rte_read_req { 1651 WR_HDR; 1652 union opcode_tid ot; 1653 __be32 params; 1654 }; 1655 1656 struct cpl_rte_read_rpl { 1657 RSS_HDR 1658 union opcode_tid ot; 1659 __u8 status; 1660 __u8 rsvd; 1661 __be16 l2t_idx; 1662 #if defined(__LITTLE_ENDIAN_BITFIELD) 1663 __u32 :30; 1664 __u32 select:1; 1665 #else 1666 __u32 select:1; 1667 __u32 :30; 1668 #endif 1669 __be32 addr; 1670 }; 1671 1672 struct cpl_l2t_write_req { 1673 WR_HDR; 1674 union opcode_tid ot; 1675 __be16 params; 1676 __be16 l2t_idx; 1677 __be16 vlan; 1678 __u8 dst_mac[6]; 1679 }; 1680 1681 /* cpl_l2t_write_req.params fields */ 1682 #define S_L2T_W_INFO 2 1683 #define M_L2T_W_INFO 0x3F 1684 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO) 1685 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) 1686 1687 #define S_L2T_W_PORT 8 1688 #define M_L2T_W_PORT 0xF 1689 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) 1690 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) 1691 1692 #define S_L2T_W_NOREPLY 15 1693 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) 1694 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) 1695 1696 struct cpl_l2t_write_rpl { 1697 RSS_HDR 1698 union opcode_tid ot; 1699 __u8 status; 1700 __u8 rsvd[3]; 1701 }; 1702 1703 struct cpl_l2t_read_req { 1704 WR_HDR; 1705 union opcode_tid ot; 1706 __be32 l2t_idx; 1707 }; 1708 1709 struct cpl_l2t_read_rpl { 1710 RSS_HDR 1711 union opcode_tid ot; 1712 __u8 status; 1713 #if defined(__LITTLE_ENDIAN_BITFIELD) 1714 __u8 :4; 1715 __u8 iff:4; 1716 #else 1717 __u8 iff:4; 1718 __u8 :4; 1719 #endif 1720 __be16 vlan; 1721 __be16 info; 1722 __u8 dst_mac[6]; 1723 }; 1724 1725 struct cpl_smt_write_req { 1726 WR_HDR; 1727 union opcode_tid ot; 1728 __be32 params; 1729 __be16 pfvf1; 1730 __u8 src_mac1[6]; 1731 __be16 pfvf0; 1732 __u8 src_mac0[6]; 1733 }; 1734 1735 /* cpl_smt_{read,write}_req.params fields */ 1736 #define S_SMTW_OVLAN_IDX 16 1737 #define M_SMTW_OVLAN_IDX 0xF 1738 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 1739 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 1740 1741 #define S_SMTW_IDX 20 1742 #define M_SMTW_IDX 0x7F 1743 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) 1744 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) 1745 1746 #define S_SMTW_NORPL 31 1747 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL) 1748 #define F_SMTW_NORPL V_SMTW_NORPL(1U) 1749 1750 /* cpl_smt_{read,write}_req.pfvf? fields */ 1751 #define S_SMTW_VF 0 1752 #define M_SMTW_VF 0xFF 1753 #define V_SMTW_VF(x) ((x) << S_SMTW_VF) 1754 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) 1755 1756 #define S_SMTW_PF 8 1757 #define M_SMTW_PF 0x7 1758 #define V_SMTW_PF(x) ((x) << S_SMTW_PF) 1759 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 1760 1761 #define S_SMTW_VF_VLD 11 1762 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 1763 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 1764 1765 struct cpl_smt_write_rpl { 1766 RSS_HDR 1767 union opcode_tid ot; 1768 __u8 status; 1769 __u8 rsvd[3]; 1770 }; 1771 1772 struct cpl_smt_read_req { 1773 WR_HDR; 1774 union opcode_tid ot; 1775 __be32 params; 1776 }; 1777 1778 struct cpl_smt_read_rpl { 1779 RSS_HDR 1780 union opcode_tid ot; 1781 __u8 status; 1782 __u8 ovlan_idx; 1783 __be16 rsvd; 1784 __be16 pfvf1; 1785 __u8 src_mac1[6]; 1786 __be16 pfvf0; 1787 __u8 src_mac0[6]; 1788 }; 1789 1790 struct cpl_barrier { 1791 WR_HDR; 1792 __u8 opcode; 1793 __u8 chan_map; 1794 __be16 rsvd0; 1795 __be32 rsvd1; 1796 }; 1797 1798 /* cpl_barrier.chan_map fields */ 1799 #define S_CHAN_MAP 4 1800 #define M_CHAN_MAP 0xF 1801 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) 1802 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) 1803 1804 struct cpl_error { 1805 RSS_HDR 1806 union opcode_tid ot; 1807 __be32 error; 1808 }; 1809 1810 struct cpl_hit_notify { 1811 RSS_HDR 1812 union opcode_tid ot; 1813 __be32 rsvd; 1814 __be32 info; 1815 __be32 reason; 1816 }; 1817 1818 struct cpl_pkt_notify { 1819 RSS_HDR 1820 union opcode_tid ot; 1821 __be16 rsvd; 1822 __be16 len; 1823 __be32 info; 1824 __be32 reason; 1825 }; 1826 1827 /* cpl_{hit,pkt}_notify.info fields */ 1828 #define S_NTFY_MAC_IDX 0 1829 #define M_NTFY_MAC_IDX 0x1FF 1830 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) 1831 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) 1832 1833 #define S_NTFY_INTF 10 1834 #define M_NTFY_INTF 0xF 1835 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) 1836 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) 1837 1838 #define S_NTFY_TCPHDR_LEN 14 1839 #define M_NTFY_TCPHDR_LEN 0xF 1840 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) 1841 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) 1842 1843 #define S_NTFY_IPHDR_LEN 18 1844 #define M_NTFY_IPHDR_LEN 0x1FF 1845 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 1846 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 1847 1848 #define S_NTFY_ETHHDR_LEN 27 1849 #define M_NTFY_ETHHDR_LEN 0x1F 1850 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 1851 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 1852 1853 struct cpl_rdma_terminate { 1854 RSS_HDR 1855 union opcode_tid ot; 1856 __be16 rsvd; 1857 __be16 len; 1858 }; 1859 1860 struct cpl_set_le_req { 1861 WR_HDR; 1862 union opcode_tid ot; 1863 __be16 reply_ctrl; 1864 __be16 params; 1865 __be64 mask_hi; 1866 __be64 mask_lo; 1867 __be64 val_hi; 1868 __be64 val_lo; 1869 }; 1870 1871 /* cpl_set_le_req.reply_ctrl additional fields */ 1872 #define S_LE_REQ_IP6 13 1873 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6) 1874 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U) 1875 1876 /* cpl_set_le_req.params fields */ 1877 #define S_LE_CHAN 0 1878 #define M_LE_CHAN 0x3 1879 #define V_LE_CHAN(x) ((x) << S_LE_CHAN) 1880 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) 1881 1882 #define S_LE_OFFSET 5 1883 #define M_LE_OFFSET 0x7 1884 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) 1885 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) 1886 1887 #define S_LE_MORE 8 1888 #define V_LE_MORE(x) ((x) << S_LE_MORE) 1889 #define F_LE_MORE V_LE_MORE(1U) 1890 1891 #define S_LE_REQSIZE 9 1892 #define M_LE_REQSIZE 0x7 1893 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) 1894 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) 1895 1896 #define S_LE_REQCMD 12 1897 #define M_LE_REQCMD 0xF 1898 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) 1899 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) 1900 1901 struct cpl_set_le_rpl { 1902 RSS_HDR 1903 union opcode_tid ot; 1904 __u8 chan; 1905 __u8 info; 1906 __be16 len; 1907 }; 1908 1909 /* cpl_set_le_rpl.info fields */ 1910 #define S_LE_RSPCMD 0 1911 #define M_LE_RSPCMD 0xF 1912 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) 1913 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) 1914 1915 #define S_LE_RSPSIZE 4 1916 #define M_LE_RSPSIZE 0x7 1917 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) 1918 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) 1919 1920 #define S_LE_RSPTYPE 7 1921 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE) 1922 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U) 1923 1924 struct cpl_sge_egr_update { 1925 RSS_HDR 1926 __be32 opcode_qid; 1927 __be16 cidx; 1928 __be16 pidx; 1929 }; 1930 1931 /* cpl_sge_egr_update.ot fields */ 1932 #define S_EGR_QID 0 1933 #define M_EGR_QID 0x1FFFF 1934 #define V_EGR_QID(x) ((x) << S_EGR_QID) 1935 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) 1936 1937 struct cpl_fw2_pld { 1938 RSS_HDR 1939 u8 opcode; 1940 u8 rsvd[5]; 1941 __be16 len; 1942 }; 1943 1944 struct cpl_fw4_pld { 1945 RSS_HDR 1946 u8 opcode; 1947 u8 rsvd0[3]; 1948 u8 type; 1949 u8 rsvd1; 1950 __be16 len; 1951 __be64 data; 1952 __be64 rsvd2; 1953 }; 1954 1955 struct cpl_fw6_pld { 1956 RSS_HDR 1957 u8 opcode; 1958 u8 rsvd[5]; 1959 __be16 len; 1960 __be64 data[4]; 1961 }; 1962 1963 struct cpl_fw2_msg { 1964 RSS_HDR 1965 union opcode_info oi; 1966 }; 1967 1968 struct cpl_fw4_msg { 1969 RSS_HDR 1970 u8 opcode; 1971 u8 type; 1972 __be16 rsvd0; 1973 __be32 rsvd1; 1974 __be64 data[2]; 1975 }; 1976 1977 struct cpl_fw4_ack { 1978 RSS_HDR 1979 union opcode_tid ot; 1980 u8 credits; 1981 u8 rsvd0[2]; 1982 u8 flags; 1983 __be32 snd_nxt; 1984 __be32 snd_una; 1985 __be64 rsvd1; 1986 }; 1987 1988 enum { 1989 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 1990 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 1991 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 1992 }; 1993 1994 struct cpl_fw6_msg { 1995 RSS_HDR 1996 u8 opcode; 1997 u8 type; 1998 __be16 rsvd0; 1999 __be32 rsvd1; 2000 __be64 data[4]; 2001 }; 2002 2003 /* cpl_fw6_msg.type values */ 2004 enum { 2005 FW6_TYPE_CMD_RPL = 0, 2006 }; 2007 2008 /* ULP_TX opcodes */ 2009 enum { 2010 ULP_TX_MEM_READ = 2, 2011 ULP_TX_MEM_WRITE = 3, 2012 ULP_TX_PKT = 4 2013 }; 2014 2015 enum { 2016 ULP_TX_SC_NOOP = 0x80, 2017 ULP_TX_SC_IMM = 0x81, 2018 ULP_TX_SC_DSGL = 0x82, 2019 ULP_TX_SC_ISGL = 0x83 2020 }; 2021 2022 #define S_ULPTX_CMD 24 2023 #define M_ULPTX_CMD 0xFF 2024 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 2025 2026 #define S_ULPTX_LEN16 0 2027 #define M_ULPTX_LEN16 0xFF 2028 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16) 2029 2030 #define S_ULP_TX_SC_MORE 23 2031 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 2032 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 2033 2034 struct ulptx_sge_pair { 2035 __be32 len[2]; 2036 __be64 addr[2]; 2037 }; 2038 2039 struct ulptx_sgl { 2040 __be32 cmd_nsge; 2041 __be32 len0; 2042 __be64 addr0; 2043 #if !(defined C99_NOT_SUPPORTED) 2044 struct ulptx_sge_pair sge[]; 2045 #endif 2046 }; 2047 2048 struct ulptx_isge { 2049 __be32 stag; 2050 __be32 len; 2051 __be64 target_ofst; 2052 }; 2053 2054 struct ulptx_isgl { 2055 __be32 cmd_nisge; 2056 __be32 rsvd; 2057 #if !(defined C99_NOT_SUPPORTED) 2058 struct ulptx_isge sge[]; 2059 #endif 2060 }; 2061 2062 struct ulptx_idata { 2063 __be32 cmd_more; 2064 __be32 len; 2065 }; 2066 2067 #define S_ULPTX_NSGE 0 2068 #define M_ULPTX_NSGE 0xFFFF 2069 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 2070 2071 struct ulp_mem_io { 2072 WR_HDR; 2073 __be32 cmd; 2074 __be32 len16; /* command length */ 2075 __be32 dlen; /* data length in 32-byte units */ 2076 __be32 lock_addr; 2077 }; 2078 2079 /* additional ulp_mem_io.cmd fields */ 2080 #define S_ULP_MEMIO_ORDER 23 2081 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) 2082 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) 2083 2084 /* ulp_mem_io.lock_addr fields */ 2085 #define S_ULP_MEMIO_ADDR 0 2086 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 2087 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 2088 2089 #define S_ULP_MEMIO_LOCK 31 2090 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 2091 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 2092 2093 /* ulp_mem_io.dlen fields */ 2094 #define S_ULP_MEMIO_DATA_LEN 0 2095 #define M_ULP_MEMIO_DATA_LEN 0x1F 2096 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 2097 2098 struct ulp_txpkt { 2099 __be32 cmd_dest; 2100 __be32 len; 2101 }; 2102 2103 /* ulp_txpkt.cmd_dest fields */ 2104 #define S_ULP_TXPKT_DEST 16 2105 #define M_ULP_TXPKT_DEST 0x3 2106 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 2107 2108 #define S_ULP_TXPKT_FID 4 2109 #define M_ULP_TXPKT_FID 0x7ff 2110 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 2111 2112 #endif /* __CXGBE_T4_MSG_H */ 2113