1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart@augustsson.net) at 9 * Carlstedt Research & Technology. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _UHCIREG_H_ 34 #define _UHCIREG_H_ 35 36 #define PCI_UHCI_BASE_REG 0x20 37 38 /* PCI config registers */ 39 #define PCI_USBREV 0x60 /* USB protocol revision */ 40 #define PCI_USB_REV_MASK 0xff 41 #define PCI_USB_REV_PRE_1_0 0x00 42 #define PCI_USB_REV_1_0 0x10 43 #define PCI_USB_REV_1_1 0x11 44 #define PCI_LEGSUP 0xc0 /* Legacy Support register */ 45 #define PCI_LEGSUP_USBPIRQDEN 0x2000 /* USB PIRQ D Enable */ 46 #define PCI_CBIO 0x20 /* configuration base IO */ 47 #define PCI_INTERFACE_UHCI 0x00 48 49 /* UHCI registers */ 50 #define UHCI_CMD 0x00 51 #define UHCI_CMD_RS 0x0001 52 #define UHCI_CMD_HCRESET 0x0002 53 #define UHCI_CMD_GRESET 0x0004 54 #define UHCI_CMD_EGSM 0x0008 55 #define UHCI_CMD_FGR 0x0010 56 #define UHCI_CMD_SWDBG 0x0020 57 #define UHCI_CMD_CF 0x0040 58 #define UHCI_CMD_MAXP 0x0080 59 #define UHCI_STS 0x02 60 #define UHCI_STS_USBINT 0x0001 61 #define UHCI_STS_USBEI 0x0002 62 #define UHCI_STS_RD 0x0004 63 #define UHCI_STS_HSE 0x0008 64 #define UHCI_STS_HCPE 0x0010 65 #define UHCI_STS_HCH 0x0020 66 #define UHCI_STS_ALLINTRS 0x003f 67 #define UHCI_INTR 0x04 68 #define UHCI_INTR_TOCRCIE 0x0001 69 #define UHCI_INTR_RIE 0x0002 70 #define UHCI_INTR_IOCE 0x0004 71 #define UHCI_INTR_SPIE 0x0008 72 #define UHCI_FRNUM 0x06 73 #define UHCI_FRNUM_MASK 0x03ff 74 #define UHCI_FLBASEADDR 0x08 75 #define UHCI_SOF 0x0c 76 #define UHCI_SOF_MASK 0x7f 77 #define UHCI_PORTSC1 0x010 78 #define UHCI_PORTSC2 0x012 79 #define UHCI_PORTSC_CCS 0x0001 80 #define UHCI_PORTSC_CSC 0x0002 81 #define UHCI_PORTSC_PE 0x0004 82 #define UHCI_PORTSC_POEDC 0x0008 83 #define UHCI_PORTSC_LS 0x0030 84 #define UHCI_PORTSC_LS_SHIFT 4 85 #define UHCI_PORTSC_RD 0x0040 86 #define UHCI_PORTSC_LSDA 0x0100 87 #define UHCI_PORTSC_PR 0x0200 88 #define UHCI_PORTSC_OCI 0x0400 89 #define UHCI_PORTSC_OCIC 0x0800 90 #define UHCI_PORTSC_SUSP 0x1000 91 92 #define URWMASK(x) ((x) & (UHCI_PORTSC_SUSP | \ 93 UHCI_PORTSC_PR | UHCI_PORTSC_RD | \ 94 UHCI_PORTSC_PE)) 95 96 #endif /* _UHCIREG_H_ */ 97