xref: /titanic_41/usr/src/uts/sun4u/io/px/oberon_regs.h (revision 269473047d747f7815af570197e4ef7322d3632c)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _SYS_OBERON_REGS_H
27 #define	_SYS_OBERON_REGS_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 
34 #define	UBC_ERROR_LOG_ENABLE			0x471000
35 #define	UBC_ERROR_STATUS_CLEAR			0x471018
36 #define	UBC_INTERRUPT_ENABLE			0x471008
37 #define	UBC_INTERRUPT_STATUS			0x471010
38 #define	UBC_INTERRUPT_STATUS_DMARDUEA_P		0
39 #define	UBC_INTERRUPT_STATUS_DMAWTUEA_P		1
40 #define	UBC_INTERRUPT_STATUS_MEMRDAXA_P		2
41 #define	UBC_INTERRUPT_STATUS_MEMWTAXA_P		3
42 #define	UBC_INTERRUPT_STATUS_DMARDUEB_P		8
43 #define	UBC_INTERRUPT_STATUS_DMAWTUEB_P		9
44 #define	UBC_INTERRUPT_STATUS_MEMRDAXB_P		10
45 #define	UBC_INTERRUPT_STATUS_MEMWTAXB_P		11
46 #define	UBC_INTERRUPT_STATUS_PIOWTUE_P		16
47 #define	UBC_INTERRUPT_STATUS_PIOWBEUE_P		17
48 #define	UBC_INTERRUPT_STATUS_PIORBEUE_P		18
49 #define	UBC_INTERRUPT_STATUS_DMARDUEA_S		32
50 #define	UBC_INTERRUPT_STATUS_DMAWTUEA_S		33
51 #define	UBC_INTERRUPT_STATUS_MEMRDAXA_S		34
52 #define	UBC_INTERRUPT_STATUS_MEMWTAXA_S		35
53 #define	UBC_INTERRUPT_STATUS_DMARDUEB_S		40
54 #define	UBC_INTERRUPT_STATUS_DMAWTUEB_S		41
55 #define	UBC_INTERRUPT_STATUS_MEMRDAXB_S		42
56 #define	UBC_INTERRUPT_STATUS_MEMWTAXB_S		43
57 #define	UBC_INTERRUPT_STATUS_PIOWTUE_S		48
58 #define	UBC_INTERRUPT_STATUS_PIOWBEUE_S		49
59 #define	UBC_INTERRUPT_STATUS_PIORBEUE_S		50
60 #define	UBC_ERROR_STATUS_SET			0x471020
61 #define	UBC_PERFORMANCE_COUNTER_SELECT		0x472000
62 #define	UBC_PERFORMANCE_COUNTER_ZERO		0x472008
63 #define	UBC_PERFORMANCE_COUNTER_ONE		0x472010
64 #define	UBC_PERFORMANCE_COUNTER_SEL_MASKS	0x3f3f
65 #define	UBC_MEMORY_UE_LOG			0x471028
66 #define	UBC_MEMORY_UE_LOG_EID			60
67 #define	UBC_MEMORY_UE_LOG_EID_MASK		0x3
68 #define	UBC_MEMORY_UE_LOG_MARKED		48
69 #define	UBC_MEMORY_UE_LOG_MARKED_MASK		0x3fff
70 #define	UBC_MARKED_MAX_CPUID_MASK		0x1ff
71 /*
72  * Class qualifiers on errors for which EID is valid.
73  */
74 #define	UBC_EID_MEM	0
75 #define	UBC_EID_CHANNEL	1
76 #define	UBC_EID_CPU	2
77 #define	UBC_EID_PATH	3
78 /*
79  * Mask within UBC_INTERRUPT_STATUS for Leaf-A errors
80  */
81 #define	UBC_INTERRUPT_STATUS_LEAFA	\
82 	((1UL << UBC_INTERRUPT_STATUS_DMARDUEA_P) |\
83 	(1UL << UBC_INTERRUPT_STATUS_DMAWTUEA_P) |\
84 	(1UL << UBC_INTERRUPT_STATUS_MEMRDAXA_P) |\
85 	(1UL << UBC_INTERRUPT_STATUS_MEMWTAXA_P) |\
86 	(1UL << UBC_INTERRUPT_STATUS_DMARDUEA_S) |\
87 	(1UL << UBC_INTERRUPT_STATUS_DMAWTUEA_S) |\
88 	(1UL << UBC_INTERRUPT_STATUS_MEMRDAXA_S) |\
89 	(1UL << UBC_INTERRUPT_STATUS_MEMWTAXA_S))
90 /*
91  * Mask within UBC_INTERRUPT_STATUS for Leaf-B errors
92  */
93 #define	UBC_INTERRUPT_STATUS_LEAFB	\
94 	((1UL << UBC_INTERRUPT_STATUS_DMARDUEB_P) |\
95 	(1UL << UBC_INTERRUPT_STATUS_DMAWTUEB_P) |\
96 	(1UL << UBC_INTERRUPT_STATUS_MEMRDAXB_P) |\
97 	(1UL << UBC_INTERRUPT_STATUS_MEMWTAXB_P) |\
98 	(1UL << UBC_INTERRUPT_STATUS_DMARDUEB_S) |\
99 	(1UL << UBC_INTERRUPT_STATUS_DMAWTUEB_S) |\
100 	(1UL << UBC_INTERRUPT_STATUS_MEMRDAXB_S) |\
101 	(1UL << UBC_INTERRUPT_STATUS_MEMWTAXB_S))
102 
103 #define	OBERON_UBC_ID_MAX		64
104 #define	OBERON_UBC_ID_IOC		0
105 #define	OBERON_UBC_ID_LSB		2
106 
107 #define	OBERON_PORT_ID_LEAF		0
108 #define	OBERON_PORT_ID_LEAF_MASK	0x1
109 #define	OBERON_PORT_ID_IOC		1
110 #define	OBERON_PORT_ID_IOC_MASK		0x03
111 #define	OBERON_PORT_ID_LSB		4
112 #define	OBERON_PORT_ID_LSB_MASK		0x0F
113 
114 /* values for OBERON_PORT_ID_LEAF field */
115 #define	OBERON_PORT_ID_LEAF_A		0
116 #define	OBERON_PORT_ID_LEAF_B		1
117 
118 #define	INTERRUPT_MAPPING_ENTRIES_T_DESTID	21
119 #define	INTERRUPT_MAPPING_ENTRIES_T_DESTID_MASK	0x3ff
120 
121 #define	OBERON_TLU_CONTROL_DRN_TR_DIS		35
122 #define	OBERON_TLU_CONTROL_CPLEP_DEN		34
123 #define	OBERON_TLU_CONTROL_ECRCCHK_DIS		33
124 #define	OBERON_TLU_CONTROL_ECRCGEN_DIS		32
125 
126 #define	TLU_SLOT_CAPABILITIES_HP		6
127 #define	TLU_SLOT_CAPABILITIES_HPSUP		5
128 #define	TLU_SLOT_CAPABILITIES_PWINDP		4
129 #define	TLU_SLOT_CAPABILITIES_ATINDP		3
130 #define	TLU_SLOT_CAPABILITIES_MRLSP		2
131 #define	TLU_SLOT_CAPABILITIES_PWCNTLP		1
132 #define	TLU_SLOT_CAPABILITIES_ATBTNP		0
133 
134 #define	DLU_INTERRUPT_MASK					0xe2048
135 #define	DLU_INTERRUPT_MASK_MSK_INTERRUPT_EN			31
136 #define	DLU_INTERRUPT_MASK_MSK_LINK_LAYER			5
137 #define	DLU_INTERRUPT_MASK_MSK_PHY_ERROR			4
138 #define	DLU_LINK_LAYER_CONFIG					0xe2200
139 #define	DLU_LINK_LAYER_CONFIG_VC0_EN				8
140 #define	DLU_LINK_LAYER_CONFIG_TLP_XMIT_FC_EN			3
141 #define	DLU_LINK_LAYER_CONFIG_FREQ_ACK_ENABLE			2
142 #define	DLU_LINK_LAYER_CONFIG_RETRY_DISABLE			1
143 #define	DLU_LINK_LAYER_STATUS					0xe2208
144 #define	DLU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS_MASK		0x7
145 #define	DLU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS_DL_INACTIVE	0x1
146 #define	DLU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS_DL_INIT	0x2
147 #define	DLU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS_DL_ACTIVE	0x4
148 #define	DLU_LINK_LAYER_STATUS_DLUP_STS				3
149 #define	DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS			4
150 #define	DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS_MASK		0x3
151 #define	DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS_FC_IDLE		0x0
152 #define	DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS_FC_INIT_1		0x1
153 #define	DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS_FC_INIT_2		0x3
154 #define	DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS_FC_INIT_DONE	0x2
155 #define	DLU_LINK_LAYER_INTERRUPT_AND_STATUS			0xe2210
156 #define	DLU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_LINK_ERR_ACT	31
157 #define	DLU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_PARABUS_PE	23
158 #define	DLU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_UNSPRTD_DLLP	22
159 #define	DLU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_SRC_ERR_TLP	17
160 #define	DLU_LINK_LAYER_INTERRUPT_MASK				0xe2220
161 #define	DLU_LINK_LAYER_INTERRUPT_MASK_MSK_LINK_ERR_ACT		31
162 #define	DLU_LINK_LAYER_INTERRUPT_MASK_MSK_PARABUS_PE		23
163 #define	DLU_LINK_LAYER_INTERRUPT_MASK_MSK_UNSPRTD_DLLP		22
164 #define	DLU_LINK_LAYER_INTERRUPT_MASK_MSK_SRC_ERR_TLP		17
165 #define	DLU_FLOW_CONTROL_UPDATE_CONTROL				0xe2240
166 #define	DLU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_C_EN		2
167 #define	DLU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_NP_EN		1
168 #define	DLU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_P_EN		0
169 #define	DLU_TXLINK_REPLAY_TIMER_THRESHOLD			0xe2410
170 #define	DLU_TXLINK_REPLAY_TIMER_THRESHOLD_RPLAY_TMR_THR		0
171 #define	DLU_TXLINK_REPLAY_TIMER_THRESHOLD_RPLAY_TMR_THR_MASK	0xfffff
172 #define	DLU_TXLINK_REPLAY_TIMER_THRESHOLD_DEFAULT		0xc9
173 #define	DLU_PORT_CONTROL					0xe2b00
174 #define	DLU_PORT_CONTROL_CK_EN					0
175 #define	DLU_PORT_STATUS						0xe2b08
176 
177 #define	MMU_INTERRUPT_STATUS_TTC_DUE_P				8
178 #define	MMU_INTERRUPT_STATUS_TTC_DUE_S				40
179 #define	ILU_INTERRUPT_STATUS_IHB_UE_P				4
180 #define	ILU_INTERRUPT_STATUS_IHB_UE_S				36
181 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ECRC_P		19
182 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ECRC_S		51
183 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_POIS_P		12
184 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_POIS_S		44
185 #define	TLU_OTHER_EVENT_STATUS_CLEAR_EIUE_P			0
186 #define	TLU_OTHER_EVENT_STATUS_CLEAR_EIUE_S			32
187 #define	TLU_OTHER_EVENT_STATUS_CLEAR_ERBUE_P			1
188 #define	TLU_OTHER_EVENT_STATUS_CLEAR_ERBUE_S			33
189 #define	TLU_OTHER_EVENT_STATUS_CLEAR_TLUEITMO_P			7
190 #define	TLU_OTHER_EVENT_STATUS_CLEAR_TLUEITMO_S			39
191 #define	TLU_OTHER_EVENT_STATUS_CLEAR_EHBUE_P			12
192 #define	TLU_OTHER_EVENT_STATUS_CLEAR_EHBUE_S			44
193 #define	TLU_OTHER_EVENT_STATUS_CLEAR_EDBUE_P			12
194 #define	TLU_OTHER_EVENT_STATUS_CLEAR_EDBUE_S			44
195 
196 #define	TLU_CONTROL_DRN_TR_DIS					35
197 
198 #define	TLU_SLOT_CONTROL					0x90038
199 #define	TLU_SLOT_CONTROL_PWFDEN					1
200 #define	TLU_SLOT_STATUS						0x90040
201 #define	TLU_SLOT_STATUS_PSD					6
202 #define	TLU_SLOT_STATUS_MRLS					5
203 #define	TLU_SLOT_STATUS_CMDCPLT					4
204 #define	TLU_SLOT_STATUS_PSDC					3
205 #define	TLU_SLOT_STATUS_MRLC					2
206 #define	TLU_SLOT_STATUS_PWFD					1
207 #define	TLU_SLOT_STATUS_ABTN					0
208 
209 #define	FLP_PORT_LINK_CONTROL					0xe5008
210 #define	FLP_PORT_LINK_CONTROL_RETRAIN				5
211 
212 #define	FLP_PORT_CONTROL					0xe5200
213 #define	FLP_PORT_CONTROL_PORT_DIS				0
214 
215 #define	FLP_PORT_ACTIVE_STATUS					0xe5240
216 #define	FLP_PORT_ACTIVE_STATUS_TRAIN_ERROR			1
217 
218 #define	HOTPLUG_CONTROL						0x88000
219 #define	HOTPLUG_CONTROL_SLOTPON					3
220 #define	HOTPLUG_CONTROL_PWREN					2
221 #define	HOTPLUG_CONTROL_CLKEN					1
222 #define	HOTPLUG_CONTROL_N_PERST					0
223 
224 #define	DRAIN_CONTROL_STATUS					0x51100
225 #define	DRAIN_CONTROL_STATUS_DRAIN				0
226 
227 #ifdef	__cplusplus
228 }
229 #endif
230 
231 #endif	/* _SYS_OBERON_REGS_H */
232