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Searched defs:Tmp1 (Results 1 – 25 of 28) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DIntrinsicLowering.cpp63 Value *Tmp1 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
77 Value *Tmp1 = Builder.CreateLShr(V,ConstantInt::get(V->getType(), 24), in LowerBSWAP() local
107 Value* Tmp1 = Builder.CreateLShr(V, in LowerBSWAP() local
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp122 Value *Tmp1 = Builder.CreateAShr(Divisor, Shift); in generateSignedDivisionCode() local
235 Value *Tmp1 = Builder.CreateCall(CTLZ, {Dividend, True}); in generateUnsignedDivisionCode() local
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp2029 Register Tmp1 = MRI.createVirtualRegister(RC); in prepareMBB() local
2093 Register Tmp1 = MRI.createVirtualRegister(RC); in prepareSymbol() local
2111 Register Tmp1 = MRI.createVirtualRegister(RC); in prepareSymbol() local
2136 Register Tmp1 = MRI.createVirtualRegister(RC); in prepareSymbol() local
2522 Register Tmp1 = MRI.createVirtualRegister(RC); in emitSjLjDispatchBlock() local
2567 Register Tmp1 = MRI.createVirtualRegister(RC); in emitSjLjDispatchBlock() local
2593 Register Tmp1 = MRI.createVirtualRegister(RC); in emitSjLjDispatchBlock() local
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4190 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchBEXTRFromAndImm() local
4227 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPISTR() local
4260 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPESTR() local
4553 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchVPTERNLOG() local
4939 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in tryVPTESTM() local
5515 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
5568 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
5654 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
5788 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
5796 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain; in Select() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2467 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); in LowerShiftRightParts() local
2527 SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); in LowerShiftLeftParts() local
2833 SDValue Tmp1 = Node->getOperand(0); in LowerVAARG() local
3098 SDValue Tmp1 = ST->getChain(); in LowerSTOREi1() local
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp1738 SDValue Tmp1 = SDValue(Node, 0); in ExpandDYNAMIC_STACKALLOC() local
2795 SDValue Tmp1; in ExpandLegalINT_TO_FP() local
3058 SDValue Tmp1, Tmp2, Tmp3, Tmp4; in ExpandNode() local
5112 SDValue Tmp1, Tmp2, Tmp3, Tmp4; in PromoteNode() local
H A DTargetLowering.cpp8139 SDValue Tmp1 = IsSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, in expandShiftParts() local
8930 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5; in expandVPCTPOP() local
9370 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; in expandBSWAP() local
9430 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; in expandVPBSWAP() local
H A DLegalizeFloatTypes.cpp2128 SDValue Tmp1, Tmp2, Tmp3, OutputChain; in FloatExpandSetCCOperands() local
H A DSelectionDAG.cpp2419 SDValue Tmp1 = Node->getOperand(0); in expandVAArg() local
2455 SDValue Tmp1 = in expandVACopy() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp687 auto *Tmp1 = MF.getMachineMemOperand(Ptr, F, 4 /*size*/, A); in splitMemRef() local
H A DHexagonHardwareLoops.cpp1859 SmallVector<MachineOperand,2> Tmp1; in createPreheaderForLoop() local
H A DHexagonISelLoweringHVX.cpp2465 SDValue Tmp1 = DAG.getNode(ShRight, dl, IntTy, Inp, AmtM1); emitHvxShiftRightRnd() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPromoteAlloca.cpp1482 Value *Tmp1 = Builder.CreateMul(TIdY, TCntZ, "", true, true); in tryPromoteAllocaToLDS() local
H A DAMDGPUISelLowering.cpp2444 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC() local
2463 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFROUNDEVEN() local
5840 unsigned Tmp1 = DAG.ComputeNumSignBits(Op.getOperand(1), Depth + 1); in ComputeNumSignBitsForTargetNode() local
5879 unsigned Tmp1 = Analysis.computeNumSignBits(Src1, DemandedElts, Depth + 1); in computeNumSignBitsForTargetInstr() local
H A DAMDGPULegalizerInfo.cpp2435 auto Tmp1 = B.buildFAdd(Ty, Src, CopySign); in legalizeFroundeven() local
2549 auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0); in legalizeIntrinsicTrunc() local
4864 auto Tmp1 = B.buildFMA(ResTy, NegY, R, One); in legalizeFastUnsafeFDIV64() local
H A DSIISelLowering.cpp3966 SDValue Tmp1 = Op; in lowerDYNAMIC_STACKALLOCImpl() local
10517 SDValue Tmp1 = DAG.getNode(ISD::FMA, SL, VT, NegY, R, One); in lowerFastUnsafeFDIV64() local
/freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/
H A DCheckerManager.cpp123 ExplodedNodeSet Tmp1, Tmp2; in expandGraphWithCheckers() local
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGExprComplex.cpp1091 llvm::Value *Tmp1 = Builder.CreateMul(LHSr, RHSr); // a*c in EmitBinDiv() local
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp6268 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select() local
6282 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select() local
H A DPPCISelLowering.cpp9115 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, in LowerSHL_PARTS() local
9144 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, in LowerSRL_PARTS() local
9172 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, in LowerSRA_PARTS() local
/freebsd/contrib/llvm-project/llvm/lib/Support/
H A DAPInt.cpp722 uint64_t Tmp1 = llvm::byteswap<uint64_t>(U.VAL); in byteSwap() local
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp503 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp3196 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt); in LowerUMULO_SMULO() local
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp2882 SDValue Tmp1, Tmp2; in ReplaceNodeResults() local
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp6040 SDValue Tmp1 = Op.getOperand(1); in LowerFCOPYSIGN() local
6338 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); in LowerShiftRightParts() local
6380 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); in LowerShiftLeftParts() local

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