1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #ifndef _TXGBE_TYPE_H_ 5 #define _TXGBE_TYPE_H_ 6 7 #include <linux/property.h> 8 #include <linux/irq.h> 9 10 /* Device IDs */ 11 #define TXGBE_DEV_ID_SP1000 0x1001 12 #define TXGBE_DEV_ID_WX1820 0x2001 13 14 /* Subsystem IDs */ 15 /* SFP */ 16 #define TXGBE_ID_SP1000_SFP 0x0000 17 #define TXGBE_ID_WX1820_SFP 0x2000 18 #define TXGBE_ID_SFP 0x00 19 20 /* copper */ 21 #define TXGBE_ID_SP1000_XAUI 0x1010 22 #define TXGBE_ID_WX1820_XAUI 0x2010 23 #define TXGBE_ID_XAUI 0x10 24 #define TXGBE_ID_SP1000_SGMII 0x1020 25 #define TXGBE_ID_WX1820_SGMII 0x2020 26 #define TXGBE_ID_SGMII 0x20 27 /* backplane */ 28 #define TXGBE_ID_SP1000_KR_KX_KX4 0x1030 29 #define TXGBE_ID_WX1820_KR_KX_KX4 0x2030 30 #define TXGBE_ID_KR_KX_KX4 0x30 31 /* MAC Interface */ 32 #define TXGBE_ID_SP1000_MAC_XAUI 0x1040 33 #define TXGBE_ID_WX1820_MAC_XAUI 0x2040 34 #define TXGBE_ID_MAC_XAUI 0x40 35 #define TXGBE_ID_SP1000_MAC_SGMII 0x1060 36 #define TXGBE_ID_WX1820_MAC_SGMII 0x2060 37 #define TXGBE_ID_MAC_SGMII 0x60 38 39 /* Combined interface*/ 40 #define TXGBE_ID_SFI_XAUI 0x50 41 42 /* Revision ID */ 43 #define TXGBE_SP_MPW 1 44 45 /**************** SP Registers ****************************/ 46 /* chip control Registers */ 47 #define TXGBE_MIS_PRB_CTL 0x10010 48 #define TXGBE_MIS_PRB_CTL_LAN_UP(_i) BIT(1 - (_i)) 49 /* FMGR Registers */ 50 #define TXGBE_SPI_ILDR_STATUS 0x10120 51 #define TXGBE_SPI_ILDR_STATUS_PERST BIT(0) /* PCIE_PERST is done */ 52 #define TXGBE_SPI_ILDR_STATUS_PWRRST BIT(1) /* Power on reset is done */ 53 #define TXGBE_SPI_ILDR_STATUS_LAN_SW_RST(_i) BIT((_i) + 9) /* lan soft reset done */ 54 55 /* Sensors for PVT(Process Voltage Temperature) */ 56 #define TXGBE_TS_CTL 0x10300 57 #define TXGBE_TS_CTL_EVAL_MD BIT(31) 58 59 /* GPIO register bit */ 60 #define TXGBE_GPIOBIT_0 BIT(0) /* I:tx fault */ 61 #define TXGBE_GPIOBIT_1 BIT(1) /* O:tx disabled */ 62 #define TXGBE_GPIOBIT_2 BIT(2) /* I:sfp module absent */ 63 #define TXGBE_GPIOBIT_3 BIT(3) /* I:rx signal lost */ 64 #define TXGBE_GPIOBIT_4 BIT(4) /* O:rate select, 1G(0) 10G(1) */ 65 #define TXGBE_GPIOBIT_5 BIT(5) /* O:rate select, 1G(0) 10G(1) */ 66 67 /* Extended Interrupt Enable Set */ 68 #define TXGBE_PX_MISC_ETH_LKDN BIT(8) 69 #define TXGBE_PX_MISC_DEV_RST BIT(10) 70 #define TXGBE_PX_MISC_ETH_EVENT BIT(17) 71 #define TXGBE_PX_MISC_ETH_LK BIT(18) 72 #define TXGBE_PX_MISC_ETH_AN BIT(19) 73 #define TXGBE_PX_MISC_INT_ERR BIT(20) 74 #define TXGBE_PX_MISC_GPIO BIT(26) 75 #define TXGBE_PX_MISC_IEN_MASK \ 76 (TXGBE_PX_MISC_ETH_LKDN | TXGBE_PX_MISC_DEV_RST | \ 77 TXGBE_PX_MISC_ETH_EVENT | TXGBE_PX_MISC_ETH_LK | \ 78 TXGBE_PX_MISC_ETH_AN | TXGBE_PX_MISC_INT_ERR | \ 79 TXGBE_PX_MISC_GPIO) 80 81 /* Port cfg registers */ 82 #define TXGBE_CFG_PORT_ST 0x14404 83 #define TXGBE_CFG_PORT_ST_LINK_UP BIT(0) 84 85 /* I2C registers */ 86 #define TXGBE_I2C_BASE 0x14900 87 88 /************************************** ETH PHY ******************************/ 89 #define TXGBE_XPCS_IDA_ADDR 0x13000 90 #define TXGBE_XPCS_IDA_DATA 0x13004 91 92 /********************************* Flow Director *****************************/ 93 #define TXGBE_RDB_FDIR_DROP_QUEUE 127 94 #define TXGBE_RDB_FDIR_CTL 0x19500 95 #define TXGBE_RDB_FDIR_CTL_INIT_DONE BIT(3) 96 #define TXGBE_RDB_FDIR_CTL_PERFECT_MATCH BIT(4) 97 #define TXGBE_RDB_FDIR_CTL_DROP_Q(v) FIELD_PREP(GENMASK(14, 8), v) 98 #define TXGBE_RDB_FDIR_CTL_HASH_BITS(v) FIELD_PREP(GENMASK(23, 20), v) 99 #define TXGBE_RDB_FDIR_CTL_MAX_LENGTH(v) FIELD_PREP(GENMASK(27, 24), v) 100 #define TXGBE_RDB_FDIR_CTL_FULL_THRESH(v) FIELD_PREP(GENMASK(31, 28), v) 101 #define TXGBE_RDB_FDIR_IP6(_i) (0x1950C + ((_i) * 4)) /* 0-2 */ 102 #define TXGBE_RDB_FDIR_SA 0x19518 103 #define TXGBE_RDB_FDIR_DA 0x1951C 104 #define TXGBE_RDB_FDIR_PORT 0x19520 105 #define TXGBE_RDB_FDIR_PORT_DESTINATION_SHIFT 16 106 #define TXGBE_RDB_FDIR_FLEX 0x19524 107 #define TXGBE_RDB_FDIR_FLEX_FLEX_SHIFT 16 108 #define TXGBE_RDB_FDIR_HASH 0x19528 109 #define TXGBE_RDB_FDIR_HASH_SIG_SW_INDEX(v) FIELD_PREP(GENMASK(31, 16), v) 110 #define TXGBE_RDB_FDIR_HASH_BUCKET_VALID BIT(15) 111 #define TXGBE_RDB_FDIR_CMD 0x1952C 112 #define TXGBE_RDB_FDIR_CMD_CMD_MASK GENMASK(1, 0) 113 #define TXGBE_RDB_FDIR_CMD_CMD(v) FIELD_PREP(GENMASK(1, 0), v) 114 #define TXGBE_RDB_FDIR_CMD_CMD_ADD_FLOW TXGBE_RDB_FDIR_CMD_CMD(1) 115 #define TXGBE_RDB_FDIR_CMD_CMD_REMOVE_FLOW TXGBE_RDB_FDIR_CMD_CMD(2) 116 #define TXGBE_RDB_FDIR_CMD_CMD_QUERY_REM_FILT TXGBE_RDB_FDIR_CMD_CMD(3) 117 #define TXGBE_RDB_FDIR_CMD_FILTER_VALID BIT(2) 118 #define TXGBE_RDB_FDIR_CMD_FILTER_UPDATE BIT(3) 119 #define TXGBE_RDB_FDIR_CMD_FLOW_TYPE(v) FIELD_PREP(GENMASK(6, 5), v) 120 #define TXGBE_RDB_FDIR_CMD_DROP BIT(9) 121 #define TXGBE_RDB_FDIR_CMD_LAST BIT(11) 122 #define TXGBE_RDB_FDIR_CMD_QUEUE_EN BIT(15) 123 #define TXGBE_RDB_FDIR_CMD_RX_QUEUE(v) FIELD_PREP(GENMASK(22, 16), v) 124 #define TXGBE_RDB_FDIR_CMD_VT_POOL(v) FIELD_PREP(GENMASK(29, 24), v) 125 #define TXGBE_RDB_FDIR_DA4_MSK 0x1953C 126 #define TXGBE_RDB_FDIR_SA4_MSK 0x19540 127 #define TXGBE_RDB_FDIR_TCP_MSK 0x19544 128 #define TXGBE_RDB_FDIR_UDP_MSK 0x19548 129 #define TXGBE_RDB_FDIR_SCTP_MSK 0x19560 130 #define TXGBE_RDB_FDIR_HKEY 0x19568 131 #define TXGBE_RDB_FDIR_SKEY 0x1956C 132 #define TXGBE_RDB_FDIR_OTHER_MSK 0x19570 133 #define TXGBE_RDB_FDIR_OTHER_MSK_POOL BIT(2) 134 #define TXGBE_RDB_FDIR_OTHER_MSK_L4P BIT(3) 135 #define TXGBE_RDB_FDIR_FLEX_CFG(_i) (0x19580 + ((_i) * 4)) 136 #define TXGBE_RDB_FDIR_FLEX_CFG_FIELD0 GENMASK(7, 0) 137 #define TXGBE_RDB_FDIR_FLEX_CFG_BASE_MAC FIELD_PREP(GENMASK(1, 0), 0) 138 #define TXGBE_RDB_FDIR_FLEX_CFG_MSK BIT(2) 139 #define TXGBE_RDB_FDIR_FLEX_CFG_OFST(v) FIELD_PREP(GENMASK(7, 3), v) 140 141 /* Checksum and EEPROM pointers */ 142 #define TXGBE_EEPROM_LAST_WORD 0x800 143 #define TXGBE_EEPROM_CHECKSUM 0x2F 144 #define TXGBE_EEPROM_SUM 0xBABA 145 #define TXGBE_EEPROM_VERSION_L 0x1D 146 #define TXGBE_EEPROM_VERSION_H 0x1E 147 #define TXGBE_ISCSI_BOOT_CONFIG 0x07 148 149 #define TXGBE_MAX_MSIX_VECTORS 64 150 #define TXGBE_MAX_FDIR_INDICES 63 151 #define TXGBE_MAX_RSS_INDICES 63 152 153 #define TXGBE_MAX_RX_QUEUES (TXGBE_MAX_FDIR_INDICES + 1) 154 #define TXGBE_MAX_TX_QUEUES (TXGBE_MAX_FDIR_INDICES + 1) 155 156 #define TXGBE_SP_MAX_TX_QUEUES 128 157 #define TXGBE_SP_MAX_RX_QUEUES 128 158 #define TXGBE_SP_RAR_ENTRIES 128 159 #define TXGBE_SP_MC_TBL_SIZE 128 160 #define TXGBE_SP_VFT_TBL_SIZE 128 161 #define TXGBE_SP_RX_PB_SIZE 512 162 #define TXGBE_SP_TDB_PB_SZ (160 * 1024) /* 160KB Packet Buffer */ 163 164 #define TXGBE_DEFAULT_ATR_SAMPLE_RATE 20 165 166 /* Software ATR hash keys */ 167 #define TXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2 168 #define TXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614 169 170 /* Software ATR input stream values and masks */ 171 #define TXGBE_ATR_HASH_MASK 0x7fff 172 #define TXGBE_ATR_L4TYPE_MASK 0x3 173 #define TXGBE_ATR_L4TYPE_UDP 0x1 174 #define TXGBE_ATR_L4TYPE_TCP 0x2 175 #define TXGBE_ATR_L4TYPE_SCTP 0x3 176 #define TXGBE_ATR_L4TYPE_IPV6_MASK 0x4 177 #define TXGBE_ATR_L4TYPE_TUNNEL_MASK 0x10 178 179 enum txgbe_atr_flow_type { 180 TXGBE_ATR_FLOW_TYPE_IPV4 = 0x0, 181 TXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1, 182 TXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2, 183 TXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3, 184 TXGBE_ATR_FLOW_TYPE_IPV6 = 0x4, 185 TXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5, 186 TXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6, 187 TXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7, 188 TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4 = 0x10, 189 TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4 = 0x11, 190 TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4 = 0x12, 191 TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4 = 0x13, 192 TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6 = 0x14, 193 TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6 = 0x15, 194 TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6 = 0x16, 195 TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6 = 0x17, 196 }; 197 198 /* Flow Director ATR input struct. */ 199 union txgbe_atr_input { 200 /* Byte layout in order, all values with MSB first: 201 * 202 * vm_pool - 1 byte 203 * flow_type - 1 byte 204 * vlan_id - 2 bytes 205 * dst_ip - 16 bytes 206 * src_ip - 16 bytes 207 * src_port - 2 bytes 208 * dst_port - 2 bytes 209 * flex_bytes - 2 bytes 210 * bkt_hash - 2 bytes 211 */ 212 struct { 213 u8 vm_pool; 214 u8 flow_type; 215 __be16 vlan_id; 216 __be32 dst_ip[4]; 217 __be32 src_ip[4]; 218 __be16 src_port; 219 __be16 dst_port; 220 __be16 flex_bytes; 221 __be16 bkt_hash; 222 } formatted; 223 __be32 dword_stream[11]; 224 }; 225 226 /* Flow Director compressed ATR hash input struct */ 227 union txgbe_atr_hash_dword { 228 struct { 229 u8 vm_pool; 230 u8 flow_type; 231 __be16 vlan_id; 232 } formatted; 233 __be32 ip; 234 struct { 235 __be16 src; 236 __be16 dst; 237 } port; 238 __be16 flex_bytes; 239 __be32 dword; 240 }; 241 242 enum txgbe_fdir_pballoc_type { 243 TXGBE_FDIR_PBALLOC_NONE = 0, 244 TXGBE_FDIR_PBALLOC_64K = 1, 245 TXGBE_FDIR_PBALLOC_128K = 2, 246 TXGBE_FDIR_PBALLOC_256K = 3, 247 }; 248 249 struct txgbe_fdir_filter { 250 struct hlist_node fdir_node; 251 union txgbe_atr_input filter; 252 u16 sw_idx; 253 u16 action; 254 }; 255 256 /* TX/RX descriptor defines */ 257 #define TXGBE_DEFAULT_TXD 512 258 #define TXGBE_DEFAULT_TX_WORK 256 259 260 #if (PAGE_SIZE < 8192) 261 #define TXGBE_DEFAULT_RXD 512 262 #define TXGBE_DEFAULT_RX_WORK 256 263 #else 264 #define TXGBE_DEFAULT_RXD 256 265 #define TXGBE_DEFAULT_RX_WORK 128 266 #endif 267 268 #define TXGBE_INTR_MISC BIT(0) 269 #define TXGBE_INTR_QALL(A) GENMASK((A)->num_q_vectors, 1) 270 271 #define TXGBE_MAX_EITR GENMASK(11, 3) 272 273 extern char txgbe_driver_name[]; 274 275 void txgbe_down(struct wx *wx); 276 void txgbe_up(struct wx *wx); 277 int txgbe_setup_tc(struct net_device *dev, u8 tc); 278 void txgbe_do_reset(struct net_device *netdev); 279 280 #define NODE_PROP(_NAME, _PROP) \ 281 (const struct software_node) { \ 282 .name = _NAME, \ 283 .properties = _PROP, \ 284 } 285 286 enum txgbe_swnodes { 287 SWNODE_GPIO = 0, 288 SWNODE_I2C, 289 SWNODE_SFP, 290 SWNODE_PHYLINK, 291 SWNODE_MAX 292 }; 293 294 struct txgbe_nodes { 295 char gpio_name[32]; 296 char i2c_name[32]; 297 char sfp_name[32]; 298 char phylink_name[32]; 299 struct property_entry gpio_props[1]; 300 struct property_entry i2c_props[3]; 301 struct property_entry sfp_props[8]; 302 struct property_entry phylink_props[2]; 303 struct software_node_ref_args i2c_ref[1]; 304 struct software_node_ref_args gpio0_ref[1]; 305 struct software_node_ref_args gpio1_ref[1]; 306 struct software_node_ref_args gpio2_ref[1]; 307 struct software_node_ref_args gpio3_ref[1]; 308 struct software_node_ref_args gpio4_ref[1]; 309 struct software_node_ref_args gpio5_ref[1]; 310 struct software_node_ref_args sfp_ref[1]; 311 struct software_node swnodes[SWNODE_MAX]; 312 const struct software_node *group[SWNODE_MAX + 1]; 313 }; 314 315 enum txgbe_misc_irqs { 316 TXGBE_IRQ_GPIO = 0, 317 TXGBE_IRQ_LINK, 318 TXGBE_IRQ_MAX 319 }; 320 321 struct txgbe_irq { 322 struct irq_chip chip; 323 struct irq_domain *domain; 324 int nirqs; 325 int irq; 326 }; 327 328 struct txgbe { 329 struct wx *wx; 330 struct txgbe_nodes nodes; 331 struct txgbe_irq misc; 332 struct dw_xpcs *xpcs; 333 struct platform_device *sfp_dev; 334 struct platform_device *i2c_dev; 335 struct clk_lookup *clock; 336 struct clk *clk; 337 struct gpio_chip *gpio; 338 unsigned int gpio_irq; 339 unsigned int link_irq; 340 341 /* flow director */ 342 struct hlist_head fdir_filter_list; 343 union txgbe_atr_input fdir_mask; 344 int fdir_filter_count; 345 spinlock_t fdir_perfect_lock; /* spinlock for FDIR */ 346 }; 347 348 #endif /* _TXGBE_TYPE_H_ */ 349