1 // SPDX-License-Identifier: GPL-2.0-only
2 /* CAN bus driver for Microchip 251x/25625 CAN Controller with SPI Interface
3 *
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
6 *
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
8 *
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
12 *
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
15 *
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
19 * Copyright 2007
20 */
21
22 #include <linux/bitfield.h>
23 #include <linux/can/core.h>
24 #include <linux/can/dev.h>
25 #include <linux/clk.h>
26 #include <linux/completion.h>
27 #include <linux/delay.h>
28 #include <linux/device.h>
29 #include <linux/ethtool.h>
30 #include <linux/freezer.h>
31 #include <linux/gpio/driver.h>
32 #include <linux/interrupt.h>
33 #include <linux/io.h>
34 #include <linux/iopoll.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/netdevice.h>
38 #include <linux/platform_device.h>
39 #include <linux/property.h>
40 #include <linux/regulator/consumer.h>
41 #include <linux/slab.h>
42 #include <linux/spi/spi.h>
43 #include <linux/uaccess.h>
44
45 /* SPI interface instruction set */
46 #define INSTRUCTION_WRITE 0x02
47 #define INSTRUCTION_READ 0x03
48 #define INSTRUCTION_BIT_MODIFY 0x05
49 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
50 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
51 #define INSTRUCTION_RESET 0xC0
52 #define RTS_TXB0 0x01
53 #define RTS_TXB1 0x02
54 #define RTS_TXB2 0x04
55 #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
56
57 /* MPC251x registers */
58 #define BFPCTRL 0x0c
59 # define BFPCTRL_B0BFM BIT(0)
60 # define BFPCTRL_B1BFM BIT(1)
61 # define BFPCTRL_BFM(n) (BFPCTRL_B0BFM << (n))
62 # define BFPCTRL_BFM_MASK GENMASK(1, 0)
63 # define BFPCTRL_B0BFE BIT(2)
64 # define BFPCTRL_B1BFE BIT(3)
65 # define BFPCTRL_BFE(n) (BFPCTRL_B0BFE << (n))
66 # define BFPCTRL_BFE_MASK GENMASK(3, 2)
67 # define BFPCTRL_B0BFS BIT(4)
68 # define BFPCTRL_B1BFS BIT(5)
69 # define BFPCTRL_BFS(n) (BFPCTRL_B0BFS << (n))
70 # define BFPCTRL_BFS_MASK GENMASK(5, 4)
71 #define TXRTSCTRL 0x0d
72 # define TXRTSCTRL_B0RTSM BIT(0)
73 # define TXRTSCTRL_B1RTSM BIT(1)
74 # define TXRTSCTRL_B2RTSM BIT(2)
75 # define TXRTSCTRL_RTSM(n) (TXRTSCTRL_B0RTSM << (n))
76 # define TXRTSCTRL_RTSM_MASK GENMASK(2, 0)
77 # define TXRTSCTRL_B0RTS BIT(3)
78 # define TXRTSCTRL_B1RTS BIT(4)
79 # define TXRTSCTRL_B2RTS BIT(5)
80 # define TXRTSCTRL_RTS(n) (TXRTSCTRL_B0RTS << (n))
81 # define TXRTSCTRL_RTS_MASK GENMASK(5, 3)
82 #define CANSTAT 0x0e
83 #define CANCTRL 0x0f
84 # define CANCTRL_REQOP_MASK 0xe0
85 # define CANCTRL_REQOP_CONF 0x80
86 # define CANCTRL_REQOP_LISTEN_ONLY 0x60
87 # define CANCTRL_REQOP_LOOPBACK 0x40
88 # define CANCTRL_REQOP_SLEEP 0x20
89 # define CANCTRL_REQOP_NORMAL 0x00
90 # define CANCTRL_OSM 0x08
91 # define CANCTRL_ABAT 0x10
92 #define TEC 0x1c
93 #define REC 0x1d
94 #define CNF1 0x2a
95 # define CNF1_SJW_SHIFT 6
96 #define CNF2 0x29
97 # define CNF2_BTLMODE 0x80
98 # define CNF2_SAM 0x40
99 # define CNF2_PS1_SHIFT 3
100 #define CNF3 0x28
101 # define CNF3_SOF 0x08
102 # define CNF3_WAKFIL 0x04
103 # define CNF3_PHSEG2_MASK 0x07
104 #define CANINTE 0x2b
105 # define CANINTE_MERRE 0x80
106 # define CANINTE_WAKIE 0x40
107 # define CANINTE_ERRIE 0x20
108 # define CANINTE_TX2IE 0x10
109 # define CANINTE_TX1IE 0x08
110 # define CANINTE_TX0IE 0x04
111 # define CANINTE_RX1IE 0x02
112 # define CANINTE_RX0IE 0x01
113 #define CANINTF 0x2c
114 # define CANINTF_MERRF 0x80
115 # define CANINTF_WAKIF 0x40
116 # define CANINTF_ERRIF 0x20
117 # define CANINTF_TX2IF 0x10
118 # define CANINTF_TX1IF 0x08
119 # define CANINTF_TX0IF 0x04
120 # define CANINTF_RX1IF 0x02
121 # define CANINTF_RX0IF 0x01
122 # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
123 # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
124 # define CANINTF_ERR (CANINTF_ERRIF)
125 #define EFLG 0x2d
126 # define EFLG_EWARN 0x01
127 # define EFLG_RXWAR 0x02
128 # define EFLG_TXWAR 0x04
129 # define EFLG_RXEP 0x08
130 # define EFLG_TXEP 0x10
131 # define EFLG_TXBO 0x20
132 # define EFLG_RX0OVR 0x40
133 # define EFLG_RX1OVR 0x80
134 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
135 # define TXBCTRL_ABTF 0x40
136 # define TXBCTRL_MLOA 0x20
137 # define TXBCTRL_TXERR 0x10
138 # define TXBCTRL_TXREQ 0x08
139 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
140 # define SIDH_SHIFT 3
141 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
142 # define SIDL_SID_MASK 7
143 # define SIDL_SID_SHIFT 5
144 # define SIDL_EXIDE_SHIFT 3
145 # define SIDL_EID_SHIFT 16
146 # define SIDL_EID_MASK 3
147 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
148 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
149 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
150 # define DLC_RTR_SHIFT 6
151 #define TXBCTRL_OFF 0
152 #define TXBSIDH_OFF 1
153 #define TXBSIDL_OFF 2
154 #define TXBEID8_OFF 3
155 #define TXBEID0_OFF 4
156 #define TXBDLC_OFF 5
157 #define TXBDAT_OFF 6
158 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
159 # define RXBCTRL_BUKT 0x04
160 # define RXBCTRL_RXM0 0x20
161 # define RXBCTRL_RXM1 0x40
162 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
163 # define RXBSIDH_SHIFT 3
164 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
165 # define RXBSIDL_IDE 0x08
166 # define RXBSIDL_SRR 0x10
167 # define RXBSIDL_EID 3
168 # define RXBSIDL_SHIFT 5
169 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
170 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
171 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
172 # define RXBDLC_LEN_MASK 0x0f
173 # define RXBDLC_RTR 0x40
174 #define RXBCTRL_OFF 0
175 #define RXBSIDH_OFF 1
176 #define RXBSIDL_OFF 2
177 #define RXBEID8_OFF 3
178 #define RXBEID0_OFF 4
179 #define RXBDLC_OFF 5
180 #define RXBDAT_OFF 6
181 #define RXFSID(n) ((n < 3) ? 0 : 4)
182 #define RXFSIDH(n) ((n) * 4 + RXFSID(n))
183 #define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n))
184 #define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n))
185 #define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n))
186 #define RXMSIDH(n) ((n) * 4 + 0x20)
187 #define RXMSIDL(n) ((n) * 4 + 0x21)
188 #define RXMEID8(n) ((n) * 4 + 0x22)
189 #define RXMEID0(n) ((n) * 4 + 0x23)
190
191 #define GET_BYTE(val, byte) \
192 (((val) >> ((byte) * 8)) & 0xff)
193 #define SET_BYTE(val, byte) \
194 (((val) & 0xff) << ((byte) * 8))
195
196 /* Buffer size required for the largest SPI transfer (i.e., reading a
197 * frame)
198 */
199 #define CAN_FRAME_MAX_DATA_LEN 8
200 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
201 #define CAN_FRAME_MAX_BITS 128
202
203 #define TX_ECHO_SKB_MAX 1
204
205 #define MCP251X_OST_DELAY_MS (5)
206
207 #define DEVICE_NAME "mcp251x"
208
209 static const struct can_bittiming_const mcp251x_bittiming_const = {
210 .name = DEVICE_NAME,
211 .tseg1_min = 3,
212 .tseg1_max = 16,
213 .tseg2_min = 2,
214 .tseg2_max = 8,
215 .sjw_max = 4,
216 .brp_min = 1,
217 .brp_max = 64,
218 .brp_inc = 1,
219 };
220
221 enum mcp251x_model {
222 CAN_MCP251X_MCP2510 = 0x2510,
223 CAN_MCP251X_MCP2515 = 0x2515,
224 CAN_MCP251X_MCP25625 = 0x25625,
225 };
226
227 struct mcp251x_priv {
228 struct can_priv can;
229 struct net_device *net;
230 struct spi_device *spi;
231 enum mcp251x_model model;
232
233 struct mutex mcp_lock; /* SPI device lock */
234
235 u8 *spi_tx_buf;
236 u8 *spi_rx_buf;
237
238 struct sk_buff *tx_skb;
239
240 struct workqueue_struct *wq;
241 struct work_struct tx_work;
242 struct work_struct restart_work;
243
244 int force_quit;
245 int after_suspend;
246 #define AFTER_SUSPEND_UP 1
247 #define AFTER_SUSPEND_DOWN 2
248 #define AFTER_SUSPEND_POWER 4
249 #define AFTER_SUSPEND_RESTART 8
250 int restart_tx;
251 bool tx_busy;
252
253 struct regulator *power;
254 struct regulator *transceiver;
255 struct clk *clk;
256 #ifdef CONFIG_GPIOLIB
257 struct gpio_chip gpio;
258 u8 reg_bfpctrl;
259 #endif
260 };
261
262 #define MCP251X_IS(_model) \
263 static inline int mcp251x_is_##_model(struct spi_device *spi) \
264 { \
265 struct mcp251x_priv *priv = spi_get_drvdata(spi); \
266 return priv->model == CAN_MCP251X_MCP##_model; \
267 }
268
269 MCP251X_IS(2510);
270
mcp251x_clean(struct net_device * net)271 static void mcp251x_clean(struct net_device *net)
272 {
273 struct mcp251x_priv *priv = netdev_priv(net);
274
275 if (priv->tx_skb || priv->tx_busy)
276 net->stats.tx_errors++;
277 dev_kfree_skb(priv->tx_skb);
278 if (priv->tx_busy)
279 can_free_echo_skb(priv->net, 0, NULL);
280 priv->tx_skb = NULL;
281 priv->tx_busy = false;
282 }
283
284 /* Note about handling of error return of mcp251x_spi_trans: accessing
285 * registers via SPI is not really different conceptually than using
286 * normal I/O assembler instructions, although it's much more
287 * complicated from a practical POV. So it's not advisable to always
288 * check the return value of this function. Imagine that every
289 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
290 * error();", it would be a great mess (well there are some situation
291 * when exception handling C++ like could be useful after all). So we
292 * just check that transfers are OK at the beginning of our
293 * conversation with the chip and to avoid doing really nasty things
294 * (like injecting bogus packets in the network stack).
295 */
mcp251x_spi_trans(struct spi_device * spi,int len)296 static int mcp251x_spi_trans(struct spi_device *spi, int len)
297 {
298 struct mcp251x_priv *priv = spi_get_drvdata(spi);
299 struct spi_transfer t = {
300 .tx_buf = priv->spi_tx_buf,
301 .rx_buf = priv->spi_rx_buf,
302 .len = len,
303 .cs_change = 0,
304 };
305 struct spi_message m;
306 int ret;
307
308 spi_message_init(&m);
309 spi_message_add_tail(&t, &m);
310
311 ret = spi_sync(spi, &m);
312 if (ret)
313 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
314 return ret;
315 }
316
mcp251x_spi_write(struct spi_device * spi,int len)317 static int mcp251x_spi_write(struct spi_device *spi, int len)
318 {
319 struct mcp251x_priv *priv = spi_get_drvdata(spi);
320 int ret;
321
322 ret = spi_write(spi, priv->spi_tx_buf, len);
323 if (ret)
324 dev_err(&spi->dev, "spi write failed: ret = %d\n", ret);
325
326 return ret;
327 }
328
mcp251x_read_reg(struct spi_device * spi,u8 reg)329 static u8 mcp251x_read_reg(struct spi_device *spi, u8 reg)
330 {
331 struct mcp251x_priv *priv = spi_get_drvdata(spi);
332 u8 val = 0;
333
334 priv->spi_tx_buf[0] = INSTRUCTION_READ;
335 priv->spi_tx_buf[1] = reg;
336
337 if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
338 spi_write_then_read(spi, priv->spi_tx_buf, 2, &val, 1);
339 } else {
340 mcp251x_spi_trans(spi, 3);
341 val = priv->spi_rx_buf[2];
342 }
343
344 return val;
345 }
346
mcp251x_read_2regs(struct spi_device * spi,u8 reg,u8 * v1,u8 * v2)347 static void mcp251x_read_2regs(struct spi_device *spi, u8 reg, u8 *v1, u8 *v2)
348 {
349 struct mcp251x_priv *priv = spi_get_drvdata(spi);
350
351 priv->spi_tx_buf[0] = INSTRUCTION_READ;
352 priv->spi_tx_buf[1] = reg;
353
354 if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
355 u8 val[2] = { 0 };
356
357 spi_write_then_read(spi, priv->spi_tx_buf, 2, val, 2);
358 *v1 = val[0];
359 *v2 = val[1];
360 } else {
361 mcp251x_spi_trans(spi, 4);
362
363 *v1 = priv->spi_rx_buf[2];
364 *v2 = priv->spi_rx_buf[3];
365 }
366 }
367
mcp251x_write_reg(struct spi_device * spi,u8 reg,u8 val)368 static void mcp251x_write_reg(struct spi_device *spi, u8 reg, u8 val)
369 {
370 struct mcp251x_priv *priv = spi_get_drvdata(spi);
371
372 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
373 priv->spi_tx_buf[1] = reg;
374 priv->spi_tx_buf[2] = val;
375
376 mcp251x_spi_write(spi, 3);
377 }
378
mcp251x_write_2regs(struct spi_device * spi,u8 reg,u8 v1,u8 v2)379 static void mcp251x_write_2regs(struct spi_device *spi, u8 reg, u8 v1, u8 v2)
380 {
381 struct mcp251x_priv *priv = spi_get_drvdata(spi);
382
383 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
384 priv->spi_tx_buf[1] = reg;
385 priv->spi_tx_buf[2] = v1;
386 priv->spi_tx_buf[3] = v2;
387
388 mcp251x_spi_write(spi, 4);
389 }
390
mcp251x_write_bits(struct spi_device * spi,u8 reg,u8 mask,u8 val)391 static int mcp251x_write_bits(struct spi_device *spi, u8 reg,
392 u8 mask, u8 val)
393 {
394 struct mcp251x_priv *priv = spi_get_drvdata(spi);
395
396 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
397 priv->spi_tx_buf[1] = reg;
398 priv->spi_tx_buf[2] = mask;
399 priv->spi_tx_buf[3] = val;
400
401 return mcp251x_spi_write(spi, 4);
402 }
403
mcp251x_read_stat(struct spi_device * spi)404 static u8 mcp251x_read_stat(struct spi_device *spi)
405 {
406 return mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK;
407 }
408
409 #define mcp251x_read_stat_poll_timeout(addr, val, cond, delay_us, timeout_us) \
410 readx_poll_timeout(mcp251x_read_stat, addr, val, cond, \
411 delay_us, timeout_us)
412
413 #ifdef CONFIG_GPIOLIB
414 enum {
415 MCP251X_GPIO_TX0RTS = 0, /* inputs */
416 MCP251X_GPIO_TX1RTS,
417 MCP251X_GPIO_TX2RTS,
418 MCP251X_GPIO_RX0BF, /* outputs */
419 MCP251X_GPIO_RX1BF,
420 };
421
422 #define MCP251X_GPIO_INPUT_MASK \
423 GENMASK(MCP251X_GPIO_TX2RTS, MCP251X_GPIO_TX0RTS)
424 #define MCP251X_GPIO_OUTPUT_MASK \
425 GENMASK(MCP251X_GPIO_RX1BF, MCP251X_GPIO_RX0BF)
426
427 static const char * const mcp251x_gpio_names[] = {
428 [MCP251X_GPIO_TX0RTS] = "TX0RTS", /* inputs */
429 [MCP251X_GPIO_TX1RTS] = "TX1RTS",
430 [MCP251X_GPIO_TX2RTS] = "TX2RTS",
431 [MCP251X_GPIO_RX0BF] = "RX0BF", /* outputs */
432 [MCP251X_GPIO_RX1BF] = "RX1BF",
433 };
434
mcp251x_gpio_is_input(unsigned int offset)435 static inline bool mcp251x_gpio_is_input(unsigned int offset)
436 {
437 return offset <= MCP251X_GPIO_TX2RTS;
438 }
439
mcp251x_gpio_request(struct gpio_chip * chip,unsigned int offset)440 static int mcp251x_gpio_request(struct gpio_chip *chip,
441 unsigned int offset)
442 {
443 struct mcp251x_priv *priv = gpiochip_get_data(chip);
444 int ret;
445 u8 val;
446
447 /* nothing to be done for inputs */
448 if (mcp251x_gpio_is_input(offset))
449 return 0;
450
451 val = BFPCTRL_BFE(offset - MCP251X_GPIO_RX0BF);
452
453 mutex_lock(&priv->mcp_lock);
454 ret = mcp251x_write_bits(priv->spi, BFPCTRL, val, val);
455 mutex_unlock(&priv->mcp_lock);
456 if (ret)
457 return ret;
458
459 priv->reg_bfpctrl |= val;
460
461 return 0;
462 }
463
mcp251x_gpio_free(struct gpio_chip * chip,unsigned int offset)464 static void mcp251x_gpio_free(struct gpio_chip *chip,
465 unsigned int offset)
466 {
467 struct mcp251x_priv *priv = gpiochip_get_data(chip);
468 u8 val;
469
470 /* nothing to be done for inputs */
471 if (mcp251x_gpio_is_input(offset))
472 return;
473
474 val = BFPCTRL_BFE(offset - MCP251X_GPIO_RX0BF);
475
476 mutex_lock(&priv->mcp_lock);
477 mcp251x_write_bits(priv->spi, BFPCTRL, val, 0);
478 mutex_unlock(&priv->mcp_lock);
479
480 priv->reg_bfpctrl &= ~val;
481 }
482
mcp251x_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)483 static int mcp251x_gpio_get_direction(struct gpio_chip *chip,
484 unsigned int offset)
485 {
486 if (mcp251x_gpio_is_input(offset))
487 return GPIO_LINE_DIRECTION_IN;
488
489 return GPIO_LINE_DIRECTION_OUT;
490 }
491
mcp251x_gpio_get(struct gpio_chip * chip,unsigned int offset)492 static int mcp251x_gpio_get(struct gpio_chip *chip, unsigned int offset)
493 {
494 struct mcp251x_priv *priv = gpiochip_get_data(chip);
495 u8 reg, mask, val;
496
497 if (mcp251x_gpio_is_input(offset)) {
498 reg = TXRTSCTRL;
499 mask = TXRTSCTRL_RTS(offset);
500 } else {
501 reg = BFPCTRL;
502 mask = BFPCTRL_BFS(offset - MCP251X_GPIO_RX0BF);
503 }
504
505 mutex_lock(&priv->mcp_lock);
506 val = mcp251x_read_reg(priv->spi, reg);
507 mutex_unlock(&priv->mcp_lock);
508
509 return !!(val & mask);
510 }
511
mcp251x_gpio_get_multiple(struct gpio_chip * chip,unsigned long * maskp,unsigned long * bitsp)512 static int mcp251x_gpio_get_multiple(struct gpio_chip *chip,
513 unsigned long *maskp, unsigned long *bitsp)
514 {
515 struct mcp251x_priv *priv = gpiochip_get_data(chip);
516 unsigned long bits = 0;
517 u8 val;
518
519 mutex_lock(&priv->mcp_lock);
520 if (maskp[0] & MCP251X_GPIO_INPUT_MASK) {
521 val = mcp251x_read_reg(priv->spi, TXRTSCTRL);
522 val = FIELD_GET(TXRTSCTRL_RTS_MASK, val);
523 bits |= FIELD_PREP(MCP251X_GPIO_INPUT_MASK, val);
524 }
525 if (maskp[0] & MCP251X_GPIO_OUTPUT_MASK) {
526 val = mcp251x_read_reg(priv->spi, BFPCTRL);
527 val = FIELD_GET(BFPCTRL_BFS_MASK, val);
528 bits |= FIELD_PREP(MCP251X_GPIO_OUTPUT_MASK, val);
529 }
530 mutex_unlock(&priv->mcp_lock);
531
532 bitsp[0] = bits;
533 return 0;
534 }
535
mcp251x_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)536 static int mcp251x_gpio_set(struct gpio_chip *chip, unsigned int offset,
537 int value)
538 {
539 struct mcp251x_priv *priv = gpiochip_get_data(chip);
540 u8 mask, val;
541 int ret;
542
543 mask = BFPCTRL_BFS(offset - MCP251X_GPIO_RX0BF);
544 val = value ? mask : 0;
545
546 mutex_lock(&priv->mcp_lock);
547 ret = mcp251x_write_bits(priv->spi, BFPCTRL, mask, val);
548 mutex_unlock(&priv->mcp_lock);
549 if (ret)
550 return ret;
551
552 priv->reg_bfpctrl &= ~mask;
553 priv->reg_bfpctrl |= val;
554
555 return 0;
556 }
557
558 static int
mcp251x_gpio_set_multiple(struct gpio_chip * chip,unsigned long * maskp,unsigned long * bitsp)559 mcp251x_gpio_set_multiple(struct gpio_chip *chip,
560 unsigned long *maskp, unsigned long *bitsp)
561 {
562 struct mcp251x_priv *priv = gpiochip_get_data(chip);
563 u8 mask, val;
564 int ret;
565
566 mask = FIELD_GET(MCP251X_GPIO_OUTPUT_MASK, maskp[0]);
567 mask = FIELD_PREP(BFPCTRL_BFS_MASK, mask);
568
569 val = FIELD_GET(MCP251X_GPIO_OUTPUT_MASK, bitsp[0]);
570 val = FIELD_PREP(BFPCTRL_BFS_MASK, val);
571
572 if (!mask)
573 return 0;
574
575 mutex_lock(&priv->mcp_lock);
576 ret = mcp251x_write_bits(priv->spi, BFPCTRL, mask, val);
577 mutex_unlock(&priv->mcp_lock);
578 if (ret)
579 return ret;
580
581 priv->reg_bfpctrl &= ~mask;
582 priv->reg_bfpctrl |= val;
583
584 return 0;
585 }
586
mcp251x_gpio_restore(struct spi_device * spi)587 static void mcp251x_gpio_restore(struct spi_device *spi)
588 {
589 struct mcp251x_priv *priv = spi_get_drvdata(spi);
590
591 mcp251x_write_reg(spi, BFPCTRL, priv->reg_bfpctrl);
592 }
593
mcp251x_gpio_setup(struct mcp251x_priv * priv)594 static int mcp251x_gpio_setup(struct mcp251x_priv *priv)
595 {
596 struct gpio_chip *gpio = &priv->gpio;
597
598 if (!device_property_present(&priv->spi->dev, "gpio-controller"))
599 return 0;
600
601 /* gpiochip handles TX[0..2]RTS and RX[0..1]BF */
602 gpio->label = priv->spi->modalias;
603 gpio->parent = &priv->spi->dev;
604 gpio->owner = THIS_MODULE;
605 gpio->request = mcp251x_gpio_request;
606 gpio->free = mcp251x_gpio_free;
607 gpio->get_direction = mcp251x_gpio_get_direction;
608 gpio->get = mcp251x_gpio_get;
609 gpio->get_multiple = mcp251x_gpio_get_multiple;
610 gpio->set_rv = mcp251x_gpio_set;
611 gpio->set_multiple_rv = mcp251x_gpio_set_multiple;
612 gpio->base = -1;
613 gpio->ngpio = ARRAY_SIZE(mcp251x_gpio_names);
614 gpio->names = mcp251x_gpio_names;
615 gpio->can_sleep = true;
616
617 return devm_gpiochip_add_data(&priv->spi->dev, gpio, priv);
618 }
619 #else
mcp251x_gpio_restore(struct spi_device * spi)620 static inline void mcp251x_gpio_restore(struct spi_device *spi)
621 {
622 }
623
mcp251x_gpio_setup(struct mcp251x_priv * priv)624 static inline int mcp251x_gpio_setup(struct mcp251x_priv *priv)
625 {
626 return 0;
627 }
628 #endif
629
mcp251x_hw_tx_frame(struct spi_device * spi,u8 * buf,int len,int tx_buf_idx)630 static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
631 int len, int tx_buf_idx)
632 {
633 struct mcp251x_priv *priv = spi_get_drvdata(spi);
634
635 if (mcp251x_is_2510(spi)) {
636 int i;
637
638 for (i = 1; i < TXBDAT_OFF + len; i++)
639 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
640 buf[i]);
641 } else {
642 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
643 mcp251x_spi_write(spi, TXBDAT_OFF + len);
644 }
645 }
646
mcp251x_hw_tx(struct spi_device * spi,struct can_frame * frame,int tx_buf_idx)647 static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
648 int tx_buf_idx)
649 {
650 struct mcp251x_priv *priv = spi_get_drvdata(spi);
651 u32 sid, eid, exide, rtr;
652 u8 buf[SPI_TRANSFER_BUF_LEN];
653
654 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
655 if (exide)
656 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
657 else
658 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
659 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
660 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
661
662 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
663 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
664 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
665 (exide << SIDL_EXIDE_SHIFT) |
666 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
667 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
668 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
669 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->len;
670 memcpy(buf + TXBDAT_OFF, frame->data, frame->len);
671 mcp251x_hw_tx_frame(spi, buf, frame->len, tx_buf_idx);
672
673 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
674 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
675 mcp251x_spi_write(priv->spi, 1);
676 }
677
mcp251x_hw_rx_frame(struct spi_device * spi,u8 * buf,int buf_idx)678 static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
679 int buf_idx)
680 {
681 struct mcp251x_priv *priv = spi_get_drvdata(spi);
682
683 if (mcp251x_is_2510(spi)) {
684 int i, len;
685
686 for (i = 1; i < RXBDAT_OFF; i++)
687 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
688
689 len = can_cc_dlc2len(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
690 for (; i < (RXBDAT_OFF + len); i++)
691 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
692 } else {
693 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
694 if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
695 spi_write_then_read(spi, priv->spi_tx_buf, 1,
696 priv->spi_rx_buf,
697 SPI_TRANSFER_BUF_LEN);
698 memcpy(buf + 1, priv->spi_rx_buf,
699 SPI_TRANSFER_BUF_LEN - 1);
700 } else {
701 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
702 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
703 }
704 }
705 }
706
mcp251x_hw_rx(struct spi_device * spi,int buf_idx)707 static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
708 {
709 struct mcp251x_priv *priv = spi_get_drvdata(spi);
710 struct sk_buff *skb;
711 struct can_frame *frame;
712 u8 buf[SPI_TRANSFER_BUF_LEN];
713
714 skb = alloc_can_skb(priv->net, &frame);
715 if (!skb) {
716 dev_err(&spi->dev, "cannot allocate RX skb\n");
717 priv->net->stats.rx_dropped++;
718 return;
719 }
720
721 mcp251x_hw_rx_frame(spi, buf, buf_idx);
722 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
723 /* Extended ID format */
724 frame->can_id = CAN_EFF_FLAG;
725 frame->can_id |=
726 /* Extended ID part */
727 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
728 SET_BYTE(buf[RXBEID8_OFF], 1) |
729 SET_BYTE(buf[RXBEID0_OFF], 0) |
730 /* Standard ID part */
731 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
732 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
733 /* Remote transmission request */
734 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
735 frame->can_id |= CAN_RTR_FLAG;
736 } else {
737 /* Standard ID format */
738 frame->can_id =
739 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
740 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
741 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
742 frame->can_id |= CAN_RTR_FLAG;
743 }
744 /* Data length */
745 frame->len = can_cc_dlc2len(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
746 if (!(frame->can_id & CAN_RTR_FLAG)) {
747 memcpy(frame->data, buf + RXBDAT_OFF, frame->len);
748
749 priv->net->stats.rx_bytes += frame->len;
750 }
751 priv->net->stats.rx_packets++;
752
753 netif_rx(skb);
754 }
755
mcp251x_hw_sleep(struct spi_device * spi)756 static void mcp251x_hw_sleep(struct spi_device *spi)
757 {
758 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
759 }
760
761 /* May only be called when device is sleeping! */
mcp251x_hw_wake(struct spi_device * spi)762 static int mcp251x_hw_wake(struct spi_device *spi)
763 {
764 u8 value;
765 int ret;
766
767 /* Force wakeup interrupt to wake device, but don't execute IST */
768 disable_irq_nosync(spi->irq);
769 mcp251x_write_2regs(spi, CANINTE, CANINTE_WAKIE, CANINTF_WAKIF);
770
771 /* Wait for oscillator startup timer after wake up */
772 mdelay(MCP251X_OST_DELAY_MS);
773
774 /* Put device into config mode */
775 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_CONF);
776
777 /* Wait for the device to enter config mode */
778 ret = mcp251x_read_stat_poll_timeout(spi, value, value == CANCTRL_REQOP_CONF,
779 MCP251X_OST_DELAY_MS * 1000,
780 USEC_PER_SEC);
781 if (ret) {
782 dev_err(&spi->dev, "MCP251x didn't enter in config mode\n");
783 return ret;
784 }
785
786 /* Disable and clear pending interrupts */
787 mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00);
788 enable_irq(spi->irq);
789
790 return 0;
791 }
792
mcp251x_hard_start_xmit(struct sk_buff * skb,struct net_device * net)793 static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
794 struct net_device *net)
795 {
796 struct mcp251x_priv *priv = netdev_priv(net);
797 struct spi_device *spi = priv->spi;
798
799 if (priv->tx_skb || priv->tx_busy) {
800 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
801 return NETDEV_TX_BUSY;
802 }
803
804 if (can_dev_dropped_skb(net, skb))
805 return NETDEV_TX_OK;
806
807 netif_stop_queue(net);
808 priv->tx_skb = skb;
809 queue_work(priv->wq, &priv->tx_work);
810
811 return NETDEV_TX_OK;
812 }
813
mcp251x_do_set_mode(struct net_device * net,enum can_mode mode)814 static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
815 {
816 struct mcp251x_priv *priv = netdev_priv(net);
817
818 switch (mode) {
819 case CAN_MODE_START:
820 mcp251x_clean(net);
821 /* We have to delay work since SPI I/O may sleep */
822 priv->can.state = CAN_STATE_ERROR_ACTIVE;
823 priv->restart_tx = 1;
824 if (priv->can.restart_ms == 0)
825 priv->after_suspend = AFTER_SUSPEND_RESTART;
826 queue_work(priv->wq, &priv->restart_work);
827 break;
828 default:
829 return -EOPNOTSUPP;
830 }
831
832 return 0;
833 }
834
mcp251x_set_normal_mode(struct spi_device * spi)835 static int mcp251x_set_normal_mode(struct spi_device *spi)
836 {
837 struct mcp251x_priv *priv = spi_get_drvdata(spi);
838 u8 value;
839 int ret;
840
841 /* Enable interrupts */
842 mcp251x_write_reg(spi, CANINTE,
843 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
844 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
845
846 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
847 /* Put device into loopback mode */
848 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
849 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
850 /* Put device into listen-only mode */
851 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
852 } else {
853 /* Put device into normal mode */
854 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
855
856 /* Wait for the device to enter normal mode */
857 ret = mcp251x_read_stat_poll_timeout(spi, value, value == 0,
858 MCP251X_OST_DELAY_MS * 1000,
859 USEC_PER_SEC);
860 if (ret) {
861 dev_err(&spi->dev, "MCP251x didn't enter in normal mode\n");
862 return ret;
863 }
864 }
865 priv->can.state = CAN_STATE_ERROR_ACTIVE;
866 return 0;
867 }
868
mcp251x_do_set_bittiming(struct net_device * net)869 static int mcp251x_do_set_bittiming(struct net_device *net)
870 {
871 struct mcp251x_priv *priv = netdev_priv(net);
872 struct can_bittiming *bt = &priv->can.bittiming;
873 struct spi_device *spi = priv->spi;
874
875 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
876 (bt->brp - 1));
877 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
878 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
879 CNF2_SAM : 0) |
880 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
881 (bt->prop_seg - 1));
882 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
883 (bt->phase_seg2 - 1));
884 dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
885 mcp251x_read_reg(spi, CNF1),
886 mcp251x_read_reg(spi, CNF2),
887 mcp251x_read_reg(spi, CNF3));
888
889 return 0;
890 }
891
mcp251x_setup(struct net_device * net,struct spi_device * spi)892 static int mcp251x_setup(struct net_device *net, struct spi_device *spi)
893 {
894 mcp251x_do_set_bittiming(net);
895
896 mcp251x_write_reg(spi, RXBCTRL(0),
897 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
898 mcp251x_write_reg(spi, RXBCTRL(1),
899 RXBCTRL_RXM0 | RXBCTRL_RXM1);
900 return 0;
901 }
902
mcp251x_hw_reset(struct spi_device * spi)903 static int mcp251x_hw_reset(struct spi_device *spi)
904 {
905 struct mcp251x_priv *priv = spi_get_drvdata(spi);
906 u8 value;
907 int ret;
908
909 /* Wait for oscillator startup timer after power up */
910 mdelay(MCP251X_OST_DELAY_MS);
911
912 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
913 ret = mcp251x_spi_write(spi, 1);
914 if (ret)
915 return ret;
916
917 /* Wait for oscillator startup timer after reset */
918 mdelay(MCP251X_OST_DELAY_MS);
919
920 /* Wait for reset to finish */
921 ret = mcp251x_read_stat_poll_timeout(spi, value, value == CANCTRL_REQOP_CONF,
922 MCP251X_OST_DELAY_MS * 1000,
923 USEC_PER_SEC);
924 if (ret)
925 dev_err(&spi->dev, "MCP251x didn't enter in conf mode after reset\n");
926 return ret;
927 }
928
mcp251x_hw_probe(struct spi_device * spi)929 static int mcp251x_hw_probe(struct spi_device *spi)
930 {
931 u8 ctrl;
932 int ret;
933
934 ret = mcp251x_hw_reset(spi);
935 if (ret)
936 return ret;
937
938 ctrl = mcp251x_read_reg(spi, CANCTRL);
939
940 dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl);
941
942 /* Check for power up default value */
943 if ((ctrl & 0x17) != 0x07)
944 return -ENODEV;
945
946 return 0;
947 }
948
mcp251x_power_enable(struct regulator * reg,int enable)949 static int mcp251x_power_enable(struct regulator *reg, int enable)
950 {
951 if (IS_ERR_OR_NULL(reg))
952 return 0;
953
954 if (enable)
955 return regulator_enable(reg);
956 else
957 return regulator_disable(reg);
958 }
959
mcp251x_stop(struct net_device * net)960 static int mcp251x_stop(struct net_device *net)
961 {
962 struct mcp251x_priv *priv = netdev_priv(net);
963 struct spi_device *spi = priv->spi;
964
965 close_candev(net);
966
967 priv->force_quit = 1;
968 free_irq(spi->irq, priv);
969
970 mutex_lock(&priv->mcp_lock);
971
972 /* Disable and clear pending interrupts */
973 mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00);
974
975 mcp251x_write_reg(spi, TXBCTRL(0), 0);
976 mcp251x_clean(net);
977
978 mcp251x_hw_sleep(spi);
979
980 mcp251x_power_enable(priv->transceiver, 0);
981
982 priv->can.state = CAN_STATE_STOPPED;
983
984 mutex_unlock(&priv->mcp_lock);
985
986 return 0;
987 }
988
mcp251x_error_skb(struct net_device * net,int can_id,int data1)989 static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
990 {
991 struct sk_buff *skb;
992 struct can_frame *frame;
993
994 skb = alloc_can_err_skb(net, &frame);
995 if (skb) {
996 frame->can_id |= can_id;
997 frame->data[1] = data1;
998 netif_rx(skb);
999 } else {
1000 netdev_err(net, "cannot allocate error skb\n");
1001 }
1002 }
1003
mcp251x_tx_work_handler(struct work_struct * ws)1004 static void mcp251x_tx_work_handler(struct work_struct *ws)
1005 {
1006 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
1007 tx_work);
1008 struct spi_device *spi = priv->spi;
1009 struct net_device *net = priv->net;
1010 struct can_frame *frame;
1011
1012 mutex_lock(&priv->mcp_lock);
1013 if (priv->tx_skb) {
1014 if (priv->can.state == CAN_STATE_BUS_OFF) {
1015 mcp251x_clean(net);
1016 } else {
1017 frame = (struct can_frame *)priv->tx_skb->data;
1018
1019 if (frame->len > CAN_FRAME_MAX_DATA_LEN)
1020 frame->len = CAN_FRAME_MAX_DATA_LEN;
1021 mcp251x_hw_tx(spi, frame, 0);
1022 priv->tx_busy = true;
1023 can_put_echo_skb(priv->tx_skb, net, 0, 0);
1024 priv->tx_skb = NULL;
1025 }
1026 }
1027 mutex_unlock(&priv->mcp_lock);
1028 }
1029
mcp251x_restart_work_handler(struct work_struct * ws)1030 static void mcp251x_restart_work_handler(struct work_struct *ws)
1031 {
1032 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
1033 restart_work);
1034 struct spi_device *spi = priv->spi;
1035 struct net_device *net = priv->net;
1036
1037 mutex_lock(&priv->mcp_lock);
1038 if (priv->after_suspend) {
1039 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1040 mcp251x_hw_reset(spi);
1041 mcp251x_setup(net, spi);
1042 mcp251x_gpio_restore(spi);
1043 } else {
1044 mcp251x_hw_wake(spi);
1045 }
1046 priv->force_quit = 0;
1047 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
1048 mcp251x_set_normal_mode(spi);
1049 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
1050 netif_device_attach(net);
1051 mcp251x_clean(net);
1052 mcp251x_set_normal_mode(spi);
1053 netif_wake_queue(net);
1054 } else {
1055 mcp251x_hw_sleep(spi);
1056 }
1057 priv->after_suspend = 0;
1058 }
1059
1060 if (priv->restart_tx) {
1061 priv->restart_tx = 0;
1062 mcp251x_write_reg(spi, TXBCTRL(0), 0);
1063 mcp251x_clean(net);
1064 netif_wake_queue(net);
1065 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
1066 }
1067 mutex_unlock(&priv->mcp_lock);
1068 }
1069
mcp251x_can_ist(int irq,void * dev_id)1070 static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
1071 {
1072 struct mcp251x_priv *priv = dev_id;
1073 struct spi_device *spi = priv->spi;
1074 struct net_device *net = priv->net;
1075
1076 mutex_lock(&priv->mcp_lock);
1077 while (!priv->force_quit) {
1078 enum can_state new_state;
1079 u8 intf, eflag;
1080 u8 clear_intf = 0;
1081 int can_id = 0, data1 = 0;
1082
1083 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
1084
1085 /* receive buffer 0 */
1086 if (intf & CANINTF_RX0IF) {
1087 mcp251x_hw_rx(spi, 0);
1088 /* Free one buffer ASAP
1089 * (The MCP2515/25625 does this automatically.)
1090 */
1091 if (mcp251x_is_2510(spi))
1092 mcp251x_write_bits(spi, CANINTF,
1093 CANINTF_RX0IF, 0x00);
1094
1095 /* check if buffer 1 is already known to be full, no need to re-read */
1096 if (!(intf & CANINTF_RX1IF)) {
1097 u8 intf1, eflag1;
1098
1099 /* intf needs to be read again to avoid a race condition */
1100 mcp251x_read_2regs(spi, CANINTF, &intf1, &eflag1);
1101
1102 /* combine flags from both operations for error handling */
1103 intf |= intf1;
1104 eflag |= eflag1;
1105 }
1106 }
1107
1108 /* receive buffer 1 */
1109 if (intf & CANINTF_RX1IF) {
1110 mcp251x_hw_rx(spi, 1);
1111 /* The MCP2515/25625 does this automatically. */
1112 if (mcp251x_is_2510(spi))
1113 clear_intf |= CANINTF_RX1IF;
1114 }
1115
1116 /* mask out flags we don't care about */
1117 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
1118
1119 /* any error or tx interrupt we need to clear? */
1120 if (intf & (CANINTF_ERR | CANINTF_TX))
1121 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
1122 if (clear_intf)
1123 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
1124
1125 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR))
1126 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
1127
1128 /* Update can state */
1129 if (eflag & EFLG_TXBO) {
1130 new_state = CAN_STATE_BUS_OFF;
1131 can_id |= CAN_ERR_BUSOFF;
1132 } else if (eflag & EFLG_TXEP) {
1133 new_state = CAN_STATE_ERROR_PASSIVE;
1134 can_id |= CAN_ERR_CRTL;
1135 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
1136 } else if (eflag & EFLG_RXEP) {
1137 new_state = CAN_STATE_ERROR_PASSIVE;
1138 can_id |= CAN_ERR_CRTL;
1139 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
1140 } else if (eflag & EFLG_TXWAR) {
1141 new_state = CAN_STATE_ERROR_WARNING;
1142 can_id |= CAN_ERR_CRTL;
1143 data1 |= CAN_ERR_CRTL_TX_WARNING;
1144 } else if (eflag & EFLG_RXWAR) {
1145 new_state = CAN_STATE_ERROR_WARNING;
1146 can_id |= CAN_ERR_CRTL;
1147 data1 |= CAN_ERR_CRTL_RX_WARNING;
1148 } else {
1149 new_state = CAN_STATE_ERROR_ACTIVE;
1150 }
1151
1152 /* Update can state statistics */
1153 switch (priv->can.state) {
1154 case CAN_STATE_ERROR_ACTIVE:
1155 if (new_state >= CAN_STATE_ERROR_WARNING &&
1156 new_state <= CAN_STATE_BUS_OFF)
1157 priv->can.can_stats.error_warning++;
1158 fallthrough;
1159 case CAN_STATE_ERROR_WARNING:
1160 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
1161 new_state <= CAN_STATE_BUS_OFF)
1162 priv->can.can_stats.error_passive++;
1163 break;
1164 default:
1165 break;
1166 }
1167 priv->can.state = new_state;
1168
1169 if (intf & CANINTF_ERRIF) {
1170 /* Handle overflow counters */
1171 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
1172 if (eflag & EFLG_RX0OVR) {
1173 net->stats.rx_over_errors++;
1174 net->stats.rx_errors++;
1175 }
1176 if (eflag & EFLG_RX1OVR) {
1177 net->stats.rx_over_errors++;
1178 net->stats.rx_errors++;
1179 }
1180 can_id |= CAN_ERR_CRTL;
1181 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
1182 }
1183 mcp251x_error_skb(net, can_id, data1);
1184 }
1185
1186 if (priv->can.state == CAN_STATE_BUS_OFF) {
1187 if (priv->can.restart_ms == 0) {
1188 priv->force_quit = 1;
1189 priv->can.can_stats.bus_off++;
1190 can_bus_off(net);
1191 mcp251x_hw_sleep(spi);
1192 break;
1193 }
1194 }
1195
1196 if (intf == 0)
1197 break;
1198
1199 if (intf & CANINTF_TX) {
1200 if (priv->tx_busy) {
1201 net->stats.tx_packets++;
1202 net->stats.tx_bytes += can_get_echo_skb(net, 0,
1203 NULL);
1204 priv->tx_busy = false;
1205 }
1206 netif_wake_queue(net);
1207 }
1208 }
1209 mutex_unlock(&priv->mcp_lock);
1210 return IRQ_HANDLED;
1211 }
1212
mcp251x_open(struct net_device * net)1213 static int mcp251x_open(struct net_device *net)
1214 {
1215 struct mcp251x_priv *priv = netdev_priv(net);
1216 struct spi_device *spi = priv->spi;
1217 unsigned long flags = 0;
1218 int ret;
1219
1220 ret = open_candev(net);
1221 if (ret) {
1222 dev_err(&spi->dev, "unable to set initial baudrate!\n");
1223 return ret;
1224 }
1225
1226 mutex_lock(&priv->mcp_lock);
1227 mcp251x_power_enable(priv->transceiver, 1);
1228
1229 priv->force_quit = 0;
1230 priv->tx_skb = NULL;
1231 priv->tx_busy = false;
1232
1233 if (!dev_fwnode(&spi->dev))
1234 flags = IRQF_TRIGGER_FALLING;
1235
1236 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
1237 flags | IRQF_ONESHOT, dev_name(&spi->dev),
1238 priv);
1239 if (ret) {
1240 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
1241 goto out_close;
1242 }
1243
1244 ret = mcp251x_hw_wake(spi);
1245 if (ret)
1246 goto out_free_irq;
1247 ret = mcp251x_setup(net, spi);
1248 if (ret)
1249 goto out_free_irq;
1250 ret = mcp251x_set_normal_mode(spi);
1251 if (ret)
1252 goto out_free_irq;
1253
1254 netif_wake_queue(net);
1255 mutex_unlock(&priv->mcp_lock);
1256
1257 return 0;
1258
1259 out_free_irq:
1260 free_irq(spi->irq, priv);
1261 mcp251x_hw_sleep(spi);
1262 out_close:
1263 mcp251x_power_enable(priv->transceiver, 0);
1264 close_candev(net);
1265 mutex_unlock(&priv->mcp_lock);
1266 return ret;
1267 }
1268
1269 static const struct net_device_ops mcp251x_netdev_ops = {
1270 .ndo_open = mcp251x_open,
1271 .ndo_stop = mcp251x_stop,
1272 .ndo_start_xmit = mcp251x_hard_start_xmit,
1273 .ndo_change_mtu = can_change_mtu,
1274 };
1275
1276 static const struct ethtool_ops mcp251x_ethtool_ops = {
1277 .get_ts_info = ethtool_op_get_ts_info,
1278 };
1279
1280 static const struct of_device_id mcp251x_of_match[] = {
1281 {
1282 .compatible = "microchip,mcp2510",
1283 .data = (void *)CAN_MCP251X_MCP2510,
1284 },
1285 {
1286 .compatible = "microchip,mcp2515",
1287 .data = (void *)CAN_MCP251X_MCP2515,
1288 },
1289 {
1290 .compatible = "microchip,mcp25625",
1291 .data = (void *)CAN_MCP251X_MCP25625,
1292 },
1293 { }
1294 };
1295 MODULE_DEVICE_TABLE(of, mcp251x_of_match);
1296
1297 static const struct spi_device_id mcp251x_id_table[] = {
1298 {
1299 .name = "mcp2510",
1300 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510,
1301 },
1302 {
1303 .name = "mcp2515",
1304 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515,
1305 },
1306 {
1307 .name = "mcp25625",
1308 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP25625,
1309 },
1310 { }
1311 };
1312 MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1313
mcp251x_can_probe(struct spi_device * spi)1314 static int mcp251x_can_probe(struct spi_device *spi)
1315 {
1316 struct net_device *net;
1317 struct mcp251x_priv *priv;
1318 struct clk *clk;
1319 u32 freq;
1320 int ret;
1321
1322 clk = devm_clk_get_optional(&spi->dev, NULL);
1323 if (IS_ERR(clk))
1324 return PTR_ERR(clk);
1325
1326 freq = clk_get_rate(clk);
1327 if (freq == 0)
1328 device_property_read_u32(&spi->dev, "clock-frequency", &freq);
1329
1330 /* Sanity check */
1331 if (freq < 1000000 || freq > 25000000)
1332 return -ERANGE;
1333
1334 /* Allocate can/net device */
1335 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
1336 if (!net)
1337 return -ENOMEM;
1338
1339 ret = clk_prepare_enable(clk);
1340 if (ret)
1341 goto out_free;
1342
1343 net->netdev_ops = &mcp251x_netdev_ops;
1344 net->ethtool_ops = &mcp251x_ethtool_ops;
1345 net->flags |= IFF_ECHO;
1346
1347 priv = netdev_priv(net);
1348 priv->can.bittiming_const = &mcp251x_bittiming_const;
1349 priv->can.do_set_mode = mcp251x_do_set_mode;
1350 priv->can.clock.freq = freq / 2;
1351 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1352 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
1353 priv->model = (enum mcp251x_model)(uintptr_t)spi_get_device_match_data(spi);
1354 priv->net = net;
1355 priv->clk = clk;
1356
1357 spi_set_drvdata(spi, priv);
1358
1359 /* Configure the SPI bus */
1360 spi->bits_per_word = 8;
1361 if (mcp251x_is_2510(spi))
1362 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
1363 else
1364 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
1365 ret = spi_setup(spi);
1366 if (ret)
1367 goto out_clk;
1368
1369 priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
1370 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
1371 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
1372 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
1373 ret = -EPROBE_DEFER;
1374 goto out_clk;
1375 }
1376
1377 ret = mcp251x_power_enable(priv->power, 1);
1378 if (ret)
1379 goto out_clk;
1380
1381 priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
1382 0);
1383 if (!priv->wq) {
1384 ret = -ENOMEM;
1385 goto out_clk;
1386 }
1387 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
1388 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
1389
1390 priv->spi = spi;
1391 mutex_init(&priv->mcp_lock);
1392
1393 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1394 GFP_KERNEL);
1395 if (!priv->spi_tx_buf) {
1396 ret = -ENOMEM;
1397 goto error_probe;
1398 }
1399
1400 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1401 GFP_KERNEL);
1402 if (!priv->spi_rx_buf) {
1403 ret = -ENOMEM;
1404 goto error_probe;
1405 }
1406
1407 SET_NETDEV_DEV(net, &spi->dev);
1408
1409 /* Here is OK to not lock the MCP, no one knows about it yet */
1410 ret = mcp251x_hw_probe(spi);
1411 if (ret) {
1412 if (ret == -ENODEV)
1413 dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n",
1414 priv->model);
1415 goto error_probe;
1416 }
1417
1418 mcp251x_hw_sleep(spi);
1419
1420 ret = register_candev(net);
1421 if (ret)
1422 goto error_probe;
1423
1424 ret = mcp251x_gpio_setup(priv);
1425 if (ret)
1426 goto out_unregister_candev;
1427
1428 netdev_info(net, "MCP%x successfully initialized.\n", priv->model);
1429 return 0;
1430
1431 out_unregister_candev:
1432 unregister_candev(net);
1433
1434 error_probe:
1435 destroy_workqueue(priv->wq);
1436 priv->wq = NULL;
1437 mcp251x_power_enable(priv->power, 0);
1438
1439 out_clk:
1440 clk_disable_unprepare(clk);
1441
1442 out_free:
1443 free_candev(net);
1444
1445 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
1446 return ret;
1447 }
1448
mcp251x_can_remove(struct spi_device * spi)1449 static void mcp251x_can_remove(struct spi_device *spi)
1450 {
1451 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1452 struct net_device *net = priv->net;
1453
1454 unregister_candev(net);
1455
1456 mcp251x_power_enable(priv->power, 0);
1457
1458 destroy_workqueue(priv->wq);
1459 priv->wq = NULL;
1460
1461 clk_disable_unprepare(priv->clk);
1462
1463 free_candev(net);
1464 }
1465
mcp251x_can_suspend(struct device * dev)1466 static int __maybe_unused mcp251x_can_suspend(struct device *dev)
1467 {
1468 struct spi_device *spi = to_spi_device(dev);
1469 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1470 struct net_device *net = priv->net;
1471
1472 priv->force_quit = 1;
1473 disable_irq(spi->irq);
1474 /* Note: at this point neither IST nor workqueues are running.
1475 * open/stop cannot be called anyway so locking is not needed
1476 */
1477 if (netif_running(net)) {
1478 netif_device_detach(net);
1479
1480 mcp251x_hw_sleep(spi);
1481 mcp251x_power_enable(priv->transceiver, 0);
1482 priv->after_suspend = AFTER_SUSPEND_UP;
1483 } else {
1484 priv->after_suspend = AFTER_SUSPEND_DOWN;
1485 }
1486
1487 mcp251x_power_enable(priv->power, 0);
1488 priv->after_suspend |= AFTER_SUSPEND_POWER;
1489
1490 return 0;
1491 }
1492
mcp251x_can_resume(struct device * dev)1493 static int __maybe_unused mcp251x_can_resume(struct device *dev)
1494 {
1495 struct spi_device *spi = to_spi_device(dev);
1496 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1497
1498 if (priv->after_suspend & AFTER_SUSPEND_POWER)
1499 mcp251x_power_enable(priv->power, 1);
1500 if (priv->after_suspend & AFTER_SUSPEND_UP)
1501 mcp251x_power_enable(priv->transceiver, 1);
1502
1503 if (priv->after_suspend & (AFTER_SUSPEND_POWER | AFTER_SUSPEND_UP))
1504 queue_work(priv->wq, &priv->restart_work);
1505 else
1506 priv->after_suspend = 0;
1507
1508 priv->force_quit = 0;
1509 enable_irq(spi->irq);
1510 return 0;
1511 }
1512
1513 static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
1514 mcp251x_can_resume);
1515
1516 static struct spi_driver mcp251x_can_driver = {
1517 .driver = {
1518 .name = DEVICE_NAME,
1519 .of_match_table = mcp251x_of_match,
1520 .pm = &mcp251x_can_pm_ops,
1521 },
1522 .id_table = mcp251x_id_table,
1523 .probe = mcp251x_can_probe,
1524 .remove = mcp251x_can_remove,
1525 };
1526 module_spi_driver(mcp251x_can_driver);
1527
1528 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1529 "Christian Pellegrin <chripell@evolware.org>");
1530 MODULE_DESCRIPTION("Microchip 251x/25625 CAN driver");
1531 MODULE_LICENSE("GPL v2");
1532