1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd
4 * Caesar Wang <wxt@rock-chips.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/nvmem-consumer.h>
13 #include <linux/of.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/platform_device.h>
17 #include <linux/regmap.h>
18 #include <linux/reset.h>
19 #include <linux/thermal.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/pinctrl/consumer.h>
22
23 /*
24 * If the temperature over a period of time High,
25 * the resulting TSHUT gave CRU module,let it reset the entire chip,
26 * or via GPIO give PMIC.
27 */
28 enum tshut_mode {
29 TSHUT_MODE_CRU = 0,
30 TSHUT_MODE_GPIO,
31 };
32
33 /*
34 * The system Temperature Sensors tshut(tshut) polarity
35 * the bit 8 is tshut polarity.
36 * 0: low active, 1: high active
37 */
38 enum tshut_polarity {
39 TSHUT_LOW_ACTIVE = 0,
40 TSHUT_HIGH_ACTIVE,
41 };
42
43 /*
44 * The conversion table has the adc value and temperature.
45 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
46 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
47 */
48 enum adc_sort_mode {
49 ADC_DECREMENT = 0,
50 ADC_INCREMENT,
51 };
52
53 #include "thermal_hwmon.h"
54
55 /**
56 * struct chip_tsadc_table - hold information about chip-specific differences
57 * @id: conversion table
58 * @length: size of conversion table
59 * @data_mask: mask to apply on data inputs
60 * @mode: sort mode of this adc variant (incrementing or decrementing)
61 */
62 struct chip_tsadc_table {
63 const struct tsadc_table *id;
64 unsigned int length;
65 u32 data_mask;
66 enum adc_sort_mode mode;
67 };
68
69 /**
70 * struct rockchip_tsadc_chip - hold the private data of tsadc chip
71 * @chn_offset: the channel offset of the first channel
72 * @chn_num: the channel number of tsadc chip
73 * @trim_slope: used to convert the trim code to a temperature in millicelsius
74 * @tshut_temp: the hardware-controlled shutdown temperature value, with no trim
75 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
76 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
77 * @initialize: SoC special initialize tsadc controller method
78 * @irq_ack: clear the interrupt
79 * @control: enable/disable method for the tsadc controller
80 * @get_temp: get the raw temperature, unadjusted by trim
81 * @set_alarm_temp: set the high temperature interrupt
82 * @set_tshut_temp: set the hardware-controlled shutdown temperature
83 * @set_tshut_mode: set the hardware-controlled shutdown mode
84 * @get_trim_code: convert a hardware temperature code to one adjusted for by trim
85 * @table: the chip-specific conversion table
86 */
87 struct rockchip_tsadc_chip {
88 /* The sensor id of chip correspond to the ADC channel */
89 int chn_offset;
90 int chn_num;
91
92 /* Used to convert trim code to trim temp */
93 int trim_slope;
94
95 /* The hardware-controlled tshut property */
96 int tshut_temp;
97 enum tshut_mode tshut_mode;
98 enum tshut_polarity tshut_polarity;
99
100 /* Chip-wide methods */
101 void (*initialize)(struct regmap *grf,
102 void __iomem *reg, enum tshut_polarity p);
103 void (*irq_ack)(void __iomem *reg);
104 void (*control)(void __iomem *reg, bool on);
105
106 /* Per-sensor methods */
107 int (*get_temp)(const struct chip_tsadc_table *table,
108 int chn, void __iomem *reg, int *temp);
109 int (*set_alarm_temp)(const struct chip_tsadc_table *table,
110 int chn, void __iomem *reg, int temp);
111 int (*set_tshut_temp)(const struct chip_tsadc_table *table,
112 int chn, void __iomem *reg, int temp);
113 void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m);
114 int (*get_trim_code)(const struct chip_tsadc_table *table,
115 int code, int trim_base, int trim_base_frac);
116
117 /* Per-table methods */
118 struct chip_tsadc_table table;
119 };
120
121 /**
122 * struct rockchip_thermal_sensor - hold the information of thermal sensor
123 * @thermal: pointer to the platform/configuration data
124 * @tzd: pointer to a thermal zone
125 * @of_node: pointer to the device_node representing this sensor, if any
126 * @id: identifier of the thermal sensor
127 * @trim_temp: per-sensor trim temperature value
128 */
129 struct rockchip_thermal_sensor {
130 struct rockchip_thermal_data *thermal;
131 struct thermal_zone_device *tzd;
132 struct device_node *of_node;
133 int id;
134 int trim_temp;
135 };
136
137 /**
138 * struct rockchip_thermal_data - hold the private data of thermal driver
139 * @chip: pointer to the platform/configuration data
140 * @pdev: platform device of thermal
141 * @reset: the reset controller of tsadc
142 * @sensors: array of thermal sensors
143 * @clk: the controller clock is divided by the exteral 24MHz
144 * @pclk: the advanced peripherals bus clock
145 * @grf: the general register file will be used to do static set by software
146 * @regs: the base address of tsadc controller
147 * @trim_base: major component of sensor trim value, in Celsius
148 * @trim_base_frac: minor component of sensor trim value, in Decicelsius
149 * @trim: fallback thermal trim value for each channel
150 * @tshut_temp: the hardware-controlled shutdown temperature value, with no trim
151 * @trim_temp: the fallback trim temperature for the whole sensor
152 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
153 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
154 */
155 struct rockchip_thermal_data {
156 const struct rockchip_tsadc_chip *chip;
157 struct platform_device *pdev;
158 struct reset_control *reset;
159
160 struct rockchip_thermal_sensor *sensors;
161
162 struct clk *clk;
163 struct clk *pclk;
164
165 struct regmap *grf;
166 void __iomem *regs;
167
168 int trim_base;
169 int trim_base_frac;
170 int trim;
171
172 int tshut_temp;
173 int trim_temp;
174 enum tshut_mode tshut_mode;
175 enum tshut_polarity tshut_polarity;
176 };
177
178 /*
179 * TSADC Sensor Register description:
180 *
181 * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it.
182 * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399)
183 *
184 */
185 #define TSADCV2_USER_CON 0x00
186 #define TSADCV2_AUTO_CON 0x04
187 #define TSADCV2_INT_EN 0x08
188 #define TSADCV2_INT_PD 0x0c
189 #define TSADCV3_AUTO_SRC_CON 0x0c
190 #define TSADCV3_HT_INT_EN 0x14
191 #define TSADCV3_HSHUT_GPIO_INT_EN 0x18
192 #define TSADCV3_HSHUT_CRU_INT_EN 0x1c
193 #define TSADCV3_INT_PD 0x24
194 #define TSADCV3_HSHUT_PD 0x28
195 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
196 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04)
197 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
198 #define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04)
199 #define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04)
200 #define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04)
201 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
202 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
203 #define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c
204 #define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150
205 #define TSADCV2_AUTO_PERIOD 0x68
206 #define TSADCV2_AUTO_PERIOD_HT 0x6c
207 #define TSADCV3_AUTO_PERIOD 0x154
208 #define TSADCV3_AUTO_PERIOD_HT 0x158
209
210 #define TSADCV2_AUTO_EN BIT(0)
211 #define TSADCV2_AUTO_EN_MASK BIT(16)
212 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
213 #define TSADCV3_AUTO_SRC_EN(chn) BIT(chn)
214 #define TSADCV3_AUTO_SRC_EN_MASK(chn) BIT(16 + chn)
215 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
216 #define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24)
217
218 #define TSADCV3_AUTO_Q_SEL_EN BIT(1)
219
220 #define TSADCV2_INT_SRC_EN(chn) BIT(chn)
221 #define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn))
222 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
223 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
224
225 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
226 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
227 #define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff
228
229 #define TSADCV2_DATA_MASK 0xfff
230 #define TSADCV3_DATA_MASK 0x3ff
231 #define TSADCV4_DATA_MASK 0x1ff
232
233 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
234 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
235 #define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */
236 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */
237 #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */
238 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */
239
240 #define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */
241 #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */
242 #define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */
243 #define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */
244
245 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
246 #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
247
248 #define GRF_SARADC_TESTBIT 0x0e644
249 #define GRF_TSADC_TESTBIT_L 0x0e648
250 #define GRF_TSADC_TESTBIT_H 0x0e64c
251
252 #define PX30_GRF_SOC_CON2 0x0408
253
254 #define RK3568_GRF_TSADC_CON 0x0600
255 #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0)
256 #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1)
257 #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2)
258 #define RK3568_GRF_TSADC_TSEN (0x10001 << 8)
259
260 #define RK3588_GRF0_TSADC_CON 0x0100
261
262 #define RK3588_GRF0_TSADC_TRM (0xff0077 << 0)
263 #define RK3588_GRF0_TSADC_SHUT_2CRU (0x30003 << 10)
264 #define RK3588_GRF0_TSADC_SHUT_2GPIO (0x70007 << 12)
265
266 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
267 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
268 #define GRF_TSADC_VCM_EN_L (0x10001 << 7)
269 #define GRF_TSADC_VCM_EN_H (0x10001 << 7)
270
271 #define GRF_CON_TSADC_CH_INV (0x10001 << 1)
272
273
274 #define RK_MAX_TEMP (180000)
275
276 /**
277 * struct tsadc_table - code to temperature conversion table
278 * @code: the value of adc channel
279 * @temp: the temperature
280 * Note:
281 * code to temperature mapping of the temperature sensor is a piece wise linear
282 * curve.Any temperature, code faling between to 2 give temperatures can be
283 * linearly interpolated.
284 * Code to Temperature mapping should be updated based on manufacturer results.
285 */
286 struct tsadc_table {
287 u32 code;
288 int temp;
289 };
290
291 static const struct tsadc_table rv1108_table[] = {
292 {0, -40000},
293 {374, -40000},
294 {382, -35000},
295 {389, -30000},
296 {397, -25000},
297 {405, -20000},
298 {413, -15000},
299 {421, -10000},
300 {429, -5000},
301 {436, 0},
302 {444, 5000},
303 {452, 10000},
304 {460, 15000},
305 {468, 20000},
306 {476, 25000},
307 {483, 30000},
308 {491, 35000},
309 {499, 40000},
310 {507, 45000},
311 {515, 50000},
312 {523, 55000},
313 {531, 60000},
314 {539, 65000},
315 {547, 70000},
316 {555, 75000},
317 {562, 80000},
318 {570, 85000},
319 {578, 90000},
320 {586, 95000},
321 {594, 100000},
322 {602, 105000},
323 {610, 110000},
324 {618, 115000},
325 {626, 120000},
326 {634, 125000},
327 {TSADCV2_DATA_MASK, 125000},
328 };
329
330 static const struct tsadc_table rk3228_code_table[] = {
331 {0, -40000},
332 {588, -40000},
333 {593, -35000},
334 {598, -30000},
335 {603, -25000},
336 {608, -20000},
337 {613, -15000},
338 {618, -10000},
339 {623, -5000},
340 {629, 0},
341 {634, 5000},
342 {639, 10000},
343 {644, 15000},
344 {649, 20000},
345 {654, 25000},
346 {660, 30000},
347 {665, 35000},
348 {670, 40000},
349 {675, 45000},
350 {681, 50000},
351 {686, 55000},
352 {691, 60000},
353 {696, 65000},
354 {702, 70000},
355 {707, 75000},
356 {712, 80000},
357 {717, 85000},
358 {723, 90000},
359 {728, 95000},
360 {733, 100000},
361 {738, 105000},
362 {744, 110000},
363 {749, 115000},
364 {754, 120000},
365 {760, 125000},
366 {TSADCV2_DATA_MASK, 125000},
367 };
368
369 static const struct tsadc_table rk3288_code_table[] = {
370 {TSADCV2_DATA_MASK, -40000},
371 {3800, -40000},
372 {3792, -35000},
373 {3783, -30000},
374 {3774, -25000},
375 {3765, -20000},
376 {3756, -15000},
377 {3747, -10000},
378 {3737, -5000},
379 {3728, 0},
380 {3718, 5000},
381 {3708, 10000},
382 {3698, 15000},
383 {3688, 20000},
384 {3678, 25000},
385 {3667, 30000},
386 {3656, 35000},
387 {3645, 40000},
388 {3634, 45000},
389 {3623, 50000},
390 {3611, 55000},
391 {3600, 60000},
392 {3588, 65000},
393 {3575, 70000},
394 {3563, 75000},
395 {3550, 80000},
396 {3537, 85000},
397 {3524, 90000},
398 {3510, 95000},
399 {3496, 100000},
400 {3482, 105000},
401 {3467, 110000},
402 {3452, 115000},
403 {3437, 120000},
404 {3421, 125000},
405 {0, 125000},
406 };
407
408 static const struct tsadc_table rk3328_code_table[] = {
409 {0, -40000},
410 {296, -40000},
411 {304, -35000},
412 {313, -30000},
413 {322, -25000},
414 {331, -20000},
415 {340, -15000},
416 {349, -10000},
417 {359, -5000},
418 {368, 0},
419 {378, 5000},
420 {388, 10000},
421 {398, 15000},
422 {408, 20000},
423 {418, 25000},
424 {429, 30000},
425 {440, 35000},
426 {451, 40000},
427 {462, 45000},
428 {473, 50000},
429 {485, 55000},
430 {496, 60000},
431 {508, 65000},
432 {521, 70000},
433 {533, 75000},
434 {546, 80000},
435 {559, 85000},
436 {572, 90000},
437 {586, 95000},
438 {600, 100000},
439 {614, 105000},
440 {629, 110000},
441 {644, 115000},
442 {659, 120000},
443 {675, 125000},
444 {TSADCV2_DATA_MASK, 125000},
445 };
446
447 static const struct tsadc_table rk3368_code_table[] = {
448 {0, -40000},
449 {106, -40000},
450 {108, -35000},
451 {110, -30000},
452 {112, -25000},
453 {114, -20000},
454 {116, -15000},
455 {118, -10000},
456 {120, -5000},
457 {122, 0},
458 {124, 5000},
459 {126, 10000},
460 {128, 15000},
461 {130, 20000},
462 {132, 25000},
463 {134, 30000},
464 {136, 35000},
465 {138, 40000},
466 {140, 45000},
467 {142, 50000},
468 {144, 55000},
469 {146, 60000},
470 {148, 65000},
471 {150, 70000},
472 {152, 75000},
473 {154, 80000},
474 {156, 85000},
475 {158, 90000},
476 {160, 95000},
477 {162, 100000},
478 {163, 105000},
479 {165, 110000},
480 {167, 115000},
481 {169, 120000},
482 {171, 125000},
483 {TSADCV3_DATA_MASK, 125000},
484 };
485
486 static const struct tsadc_table rk3399_code_table[] = {
487 {0, -40000},
488 {402, -40000},
489 {410, -35000},
490 {419, -30000},
491 {427, -25000},
492 {436, -20000},
493 {444, -15000},
494 {453, -10000},
495 {461, -5000},
496 {470, 0},
497 {478, 5000},
498 {487, 10000},
499 {496, 15000},
500 {504, 20000},
501 {513, 25000},
502 {521, 30000},
503 {530, 35000},
504 {538, 40000},
505 {547, 45000},
506 {555, 50000},
507 {564, 55000},
508 {573, 60000},
509 {581, 65000},
510 {590, 70000},
511 {599, 75000},
512 {607, 80000},
513 {616, 85000},
514 {624, 90000},
515 {633, 95000},
516 {642, 100000},
517 {650, 105000},
518 {659, 110000},
519 {668, 115000},
520 {677, 120000},
521 {685, 125000},
522 {TSADCV3_DATA_MASK, 125000},
523 };
524
525 static const struct tsadc_table rk3568_code_table[] = {
526 {0, -40000},
527 {1584, -40000},
528 {1620, -35000},
529 {1652, -30000},
530 {1688, -25000},
531 {1720, -20000},
532 {1756, -15000},
533 {1788, -10000},
534 {1824, -5000},
535 {1856, 0},
536 {1892, 5000},
537 {1924, 10000},
538 {1956, 15000},
539 {1992, 20000},
540 {2024, 25000},
541 {2060, 30000},
542 {2092, 35000},
543 {2128, 40000},
544 {2160, 45000},
545 {2196, 50000},
546 {2228, 55000},
547 {2264, 60000},
548 {2300, 65000},
549 {2332, 70000},
550 {2368, 75000},
551 {2400, 80000},
552 {2436, 85000},
553 {2468, 90000},
554 {2500, 95000},
555 {2536, 100000},
556 {2572, 105000},
557 {2604, 110000},
558 {2636, 115000},
559 {2672, 120000},
560 {2704, 125000},
561 {TSADCV2_DATA_MASK, 125000},
562 };
563
564 static const struct tsadc_table rk3588_code_table[] = {
565 {0, -40000},
566 {215, -40000},
567 {285, 25000},
568 {350, 85000},
569 {395, 125000},
570 {TSADCV4_DATA_MASK, 125000},
571 };
572
rk_tsadcv2_temp_to_code(const struct chip_tsadc_table * table,int temp)573 static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
574 int temp)
575 {
576 int high, low, mid;
577 unsigned long num;
578 unsigned int denom;
579 u32 error = table->data_mask;
580
581 low = 0;
582 high = (table->length - 1) - 1; /* ignore the last check for table */
583 mid = (high + low) / 2;
584
585 /* Return mask code data when the temp is over table range */
586 if (temp < table->id[low].temp || temp > table->id[high].temp)
587 goto exit;
588
589 while (low <= high) {
590 if (temp == table->id[mid].temp)
591 return table->id[mid].code;
592 else if (temp < table->id[mid].temp)
593 high = mid - 1;
594 else
595 low = mid + 1;
596 mid = (low + high) / 2;
597 }
598
599 /*
600 * The conversion code granularity provided by the table. Let's
601 * assume that the relationship between temperature and
602 * analog value between 2 table entries is linear and interpolate
603 * to produce less granular result.
604 */
605 num = abs(table->id[mid + 1].code - table->id[mid].code);
606 num *= temp - table->id[mid].temp;
607 denom = table->id[mid + 1].temp - table->id[mid].temp;
608
609 switch (table->mode) {
610 case ADC_DECREMENT:
611 return table->id[mid].code - (num / denom);
612 case ADC_INCREMENT:
613 return table->id[mid].code + (num / denom);
614 default:
615 pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
616 return error;
617 }
618
619 exit:
620 pr_err("%s: invalid temperature, temp=%d error=%d\n",
621 __func__, temp, error);
622 return error;
623 }
624
rk_tsadcv2_code_to_temp(const struct chip_tsadc_table * table,u32 code,int * temp)625 static int rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table,
626 u32 code, int *temp)
627 {
628 unsigned int low = 1;
629 unsigned int high = table->length - 1;
630 unsigned int mid = (low + high) / 2;
631 unsigned int num;
632 unsigned long denom;
633
634 WARN_ON(table->length < 2);
635
636 switch (table->mode) {
637 case ADC_DECREMENT:
638 code &= table->data_mask;
639 if (code <= table->id[high].code)
640 return -EAGAIN; /* Incorrect reading */
641
642 while (low <= high) {
643 if (code >= table->id[mid].code &&
644 code < table->id[mid - 1].code)
645 break;
646 else if (code < table->id[mid].code)
647 low = mid + 1;
648 else
649 high = mid - 1;
650
651 mid = (low + high) / 2;
652 }
653 break;
654 case ADC_INCREMENT:
655 code &= table->data_mask;
656 if (code < table->id[low].code)
657 return -EAGAIN; /* Incorrect reading */
658
659 while (low <= high) {
660 if (code <= table->id[mid].code &&
661 code > table->id[mid - 1].code)
662 break;
663 else if (code > table->id[mid].code)
664 low = mid + 1;
665 else
666 high = mid - 1;
667
668 mid = (low + high) / 2;
669 }
670 break;
671 default:
672 pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
673 return -EINVAL;
674 }
675
676 /*
677 * The 5C granularity provided by the table is too much. Let's
678 * assume that the relationship between sensor readings and
679 * temperature between 2 table entries is linear and interpolate
680 * to produce less granular result.
681 */
682 num = table->id[mid].temp - table->id[mid - 1].temp;
683 num *= abs(table->id[mid - 1].code - code);
684 denom = abs(table->id[mid - 1].code - table->id[mid].code);
685 *temp = table->id[mid - 1].temp + (num / denom);
686
687 return 0;
688 }
689
690 /**
691 * rk_tsadcv2_initialize - initialize TASDC Controller.
692 * @grf: the general register file will be used to do static set by software
693 * @regs: the base address of tsadc controller
694 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
695 *
696 * (1) Set TSADC_V2_AUTO_PERIOD:
697 * Configure the interleave between every two accessing of
698 * TSADC in normal operation.
699 *
700 * (2) Set TSADCV2_AUTO_PERIOD_HT:
701 * Configure the interleave between every two accessing of
702 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
703 *
704 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
705 * If the temperature is higher than COMP_INT or COMP_SHUT for
706 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
707 */
rk_tsadcv2_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)708 static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs,
709 enum tshut_polarity tshut_polarity)
710 {
711 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
712 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
713 regs + TSADCV2_AUTO_CON);
714 else
715 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
716 regs + TSADCV2_AUTO_CON);
717
718 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
719 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
720 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
721 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
722 regs + TSADCV2_AUTO_PERIOD_HT);
723 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
724 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
725 }
726
727 /**
728 * rk_tsadcv3_initialize - initialize TASDC Controller.
729 * @grf: the general register file will be used to do static set by software
730 * @regs: the base address of tsadc controller
731 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
732 *
733 * (1) The tsadc control power sequence.
734 *
735 * (2) Set TSADC_V2_AUTO_PERIOD:
736 * Configure the interleave between every two accessing of
737 * TSADC in normal operation.
738 *
739 * (2) Set TSADCV2_AUTO_PERIOD_HT:
740 * Configure the interleave between every two accessing of
741 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
742 *
743 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
744 * If the temperature is higher than COMP_INT or COMP_SHUT for
745 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
746 */
rk_tsadcv3_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)747 static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs,
748 enum tshut_polarity tshut_polarity)
749 {
750 /* The tsadc control power sequence */
751 if (IS_ERR(grf)) {
752 /* Set interleave value to workround ic time sync issue */
753 writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs +
754 TSADCV2_USER_CON);
755
756 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
757 regs + TSADCV2_AUTO_PERIOD);
758 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
759 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
760 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
761 regs + TSADCV2_AUTO_PERIOD_HT);
762 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
763 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
764
765 } else {
766 /* Enable the voltage common mode feature */
767 regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L);
768 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H);
769
770 usleep_range(15, 100); /* The spec note says at least 15 us */
771 regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON);
772 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON);
773 usleep_range(90, 200); /* The spec note says at least 90 us */
774
775 writel_relaxed(TSADCV3_AUTO_PERIOD_TIME,
776 regs + TSADCV2_AUTO_PERIOD);
777 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
778 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
779 writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME,
780 regs + TSADCV2_AUTO_PERIOD_HT);
781 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
782 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
783 }
784
785 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
786 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
787 regs + TSADCV2_AUTO_CON);
788 else
789 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
790 regs + TSADCV2_AUTO_CON);
791 }
792
rk_tsadcv4_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)793 static void rk_tsadcv4_initialize(struct regmap *grf, void __iomem *regs,
794 enum tshut_polarity tshut_polarity)
795 {
796 rk_tsadcv2_initialize(grf, regs, tshut_polarity);
797 regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV);
798 }
799
rk_tsadcv7_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)800 static void rk_tsadcv7_initialize(struct regmap *grf, void __iomem *regs,
801 enum tshut_polarity tshut_polarity)
802 {
803 writel_relaxed(TSADCV5_USER_INTER_PD_SOC, regs + TSADCV2_USER_CON);
804 writel_relaxed(TSADCV5_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
805 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
806 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
807 writel_relaxed(TSADCV5_AUTO_PERIOD_HT_TIME,
808 regs + TSADCV2_AUTO_PERIOD_HT);
809 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
810 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
811
812 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
813 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
814 regs + TSADCV2_AUTO_CON);
815 else
816 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
817 regs + TSADCV2_AUTO_CON);
818
819 /*
820 * The general register file will is optional
821 * and might not be available.
822 */
823 if (!IS_ERR(grf)) {
824 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
825 /*
826 * RK3568 TRM, section 18.5. requires a delay no less
827 * than 10us between the rising edge of tsadc_tsen_en
828 * and the rising edge of tsadc_ana_reg_0/1/2.
829 */
830 udelay(15);
831 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
832 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
833 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
834
835 /*
836 * RK3568 TRM, section 18.5. requires a delay no less
837 * than 90us after the rising edge of tsadc_ana_reg_0/1/2.
838 */
839 usleep_range(100, 200);
840 }
841 }
842
rk_tsadcv8_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)843 static void rk_tsadcv8_initialize(struct regmap *grf, void __iomem *regs,
844 enum tshut_polarity tshut_polarity)
845 {
846 writel_relaxed(TSADCV6_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
847 writel_relaxed(TSADCV6_AUTO_PERIOD_HT_TIME,
848 regs + TSADCV3_AUTO_PERIOD_HT);
849 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
850 regs + TSADCV3_HIGHT_INT_DEBOUNCE);
851 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
852 regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
853 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
854 writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
855 TSADCV2_AUTO_TSHUT_POLARITY_MASK,
856 regs + TSADCV2_AUTO_CON);
857 else
858 writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
859 regs + TSADCV2_AUTO_CON);
860 }
861
rk_tsadcv2_irq_ack(void __iomem * regs)862 static void rk_tsadcv2_irq_ack(void __iomem *regs)
863 {
864 u32 val;
865
866 val = readl_relaxed(regs + TSADCV2_INT_PD);
867 writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
868 }
869
rk_tsadcv3_irq_ack(void __iomem * regs)870 static void rk_tsadcv3_irq_ack(void __iomem *regs)
871 {
872 u32 val;
873
874 val = readl_relaxed(regs + TSADCV2_INT_PD);
875 writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
876 }
877
rk_tsadcv4_irq_ack(void __iomem * regs)878 static void rk_tsadcv4_irq_ack(void __iomem *regs)
879 {
880 u32 val;
881
882 val = readl_relaxed(regs + TSADCV3_INT_PD);
883 writel_relaxed(val & TSADCV4_INT_PD_CLEAR_MASK, regs + TSADCV3_INT_PD);
884 val = readl_relaxed(regs + TSADCV3_HSHUT_PD);
885 writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK,
886 regs + TSADCV3_HSHUT_PD);
887 }
888
rk_tsadcv2_control(void __iomem * regs,bool enable)889 static void rk_tsadcv2_control(void __iomem *regs, bool enable)
890 {
891 u32 val;
892
893 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
894 if (enable)
895 val |= TSADCV2_AUTO_EN;
896 else
897 val &= ~TSADCV2_AUTO_EN;
898
899 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
900 }
901
902 /**
903 * rk_tsadcv3_control - the tsadc controller is enabled or disabled.
904 * @regs: the base address of tsadc controller
905 * @enable: boolean flag to enable the controller
906 *
907 * NOTE: TSADC controller works at auto mode, and some SoCs need set the
908 * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output
909 * adc value if setting this bit to enable.
910 */
rk_tsadcv3_control(void __iomem * regs,bool enable)911 static void rk_tsadcv3_control(void __iomem *regs, bool enable)
912 {
913 u32 val;
914
915 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
916 if (enable)
917 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN;
918 else
919 val &= ~TSADCV2_AUTO_EN;
920
921 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
922 }
923
rk_tsadcv4_control(void __iomem * regs,bool enable)924 static void rk_tsadcv4_control(void __iomem *regs, bool enable)
925 {
926 u32 val;
927
928 if (enable)
929 val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK;
930 else
931 val = TSADCV2_AUTO_EN_MASK;
932
933 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
934 }
935
rk_tsadcv2_get_temp(const struct chip_tsadc_table * table,int chn,void __iomem * regs,int * temp)936 static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
937 int chn, void __iomem *regs, int *temp)
938 {
939 u32 val;
940
941 val = readl_relaxed(regs + TSADCV2_DATA(chn));
942
943 return rk_tsadcv2_code_to_temp(table, val, temp);
944 }
945
rk_tsadcv4_get_temp(const struct chip_tsadc_table * table,int chn,void __iomem * regs,int * temp)946 static int rk_tsadcv4_get_temp(const struct chip_tsadc_table *table,
947 int chn, void __iomem *regs, int *temp)
948 {
949 u32 val;
950
951 val = readl_relaxed(regs + TSADCV3_DATA(chn));
952
953 return rk_tsadcv2_code_to_temp(table, val, temp);
954 }
955
rk_tsadcv2_alarm_temp(const struct chip_tsadc_table * table,int chn,void __iomem * regs,int temp)956 static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
957 int chn, void __iomem *regs, int temp)
958 {
959 u32 alarm_value;
960 u32 int_en, int_clr;
961
962 /*
963 * In some cases, some sensors didn't need the trip points, the
964 * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
965 * in the end, ignore this case and disable the high temperature
966 * interrupt.
967 */
968 if (temp == INT_MAX) {
969 int_clr = readl_relaxed(regs + TSADCV2_INT_EN);
970 int_clr &= ~TSADCV2_INT_SRC_EN(chn);
971 writel_relaxed(int_clr, regs + TSADCV2_INT_EN);
972 return 0;
973 }
974
975 /* Make sure the value is valid */
976 alarm_value = rk_tsadcv2_temp_to_code(table, temp);
977 if (alarm_value == table->data_mask)
978 return -ERANGE;
979
980 writel_relaxed(alarm_value & table->data_mask,
981 regs + TSADCV2_COMP_INT(chn));
982
983 int_en = readl_relaxed(regs + TSADCV2_INT_EN);
984 int_en |= TSADCV2_INT_SRC_EN(chn);
985 writel_relaxed(int_en, regs + TSADCV2_INT_EN);
986
987 return 0;
988 }
989
rk_tsadcv3_alarm_temp(const struct chip_tsadc_table * table,int chn,void __iomem * regs,int temp)990 static int rk_tsadcv3_alarm_temp(const struct chip_tsadc_table *table,
991 int chn, void __iomem *regs, int temp)
992 {
993 u32 alarm_value;
994
995 /*
996 * In some cases, some sensors didn't need the trip points, the
997 * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
998 * in the end, ignore this case and disable the high temperature
999 * interrupt.
1000 */
1001 if (temp == INT_MAX) {
1002 writel_relaxed(TSADCV2_INT_SRC_EN_MASK(chn),
1003 regs + TSADCV3_HT_INT_EN);
1004 return 0;
1005 }
1006 /* Make sure the value is valid */
1007 alarm_value = rk_tsadcv2_temp_to_code(table, temp);
1008 if (alarm_value == table->data_mask)
1009 return -ERANGE;
1010 writel_relaxed(alarm_value & table->data_mask,
1011 regs + TSADCV3_COMP_INT(chn));
1012 writel_relaxed(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn),
1013 regs + TSADCV3_HT_INT_EN);
1014 return 0;
1015 }
1016
rk_tsadcv2_tshut_temp(const struct chip_tsadc_table * table,int chn,void __iomem * regs,int temp)1017 static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
1018 int chn, void __iomem *regs, int temp)
1019 {
1020 u32 tshut_value, val;
1021
1022 /* Make sure the value is valid */
1023 tshut_value = rk_tsadcv2_temp_to_code(table, temp);
1024 if (tshut_value == table->data_mask)
1025 return -ERANGE;
1026
1027 writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
1028
1029 /* TSHUT will be valid */
1030 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
1031 writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
1032
1033 return 0;
1034 }
1035
rk_tsadcv3_tshut_temp(const struct chip_tsadc_table * table,int chn,void __iomem * regs,int temp)1036 static int rk_tsadcv3_tshut_temp(const struct chip_tsadc_table *table,
1037 int chn, void __iomem *regs, int temp)
1038 {
1039 u32 tshut_value;
1040
1041 /* Make sure the value is valid */
1042 tshut_value = rk_tsadcv2_temp_to_code(table, temp);
1043 if (tshut_value == table->data_mask)
1044 return -ERANGE;
1045
1046 writel_relaxed(tshut_value, regs + TSADCV3_COMP_SHUT(chn));
1047
1048 /* TSHUT will be valid */
1049 writel_relaxed(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn),
1050 regs + TSADCV3_AUTO_SRC_CON);
1051
1052 return 0;
1053 }
1054
rk_tsadcv2_tshut_mode(int chn,void __iomem * regs,enum tshut_mode mode)1055 static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
1056 enum tshut_mode mode)
1057 {
1058 u32 val;
1059
1060 val = readl_relaxed(regs + TSADCV2_INT_EN);
1061 if (mode == TSHUT_MODE_GPIO) {
1062 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
1063 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
1064 } else {
1065 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
1066 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
1067 }
1068
1069 writel_relaxed(val, regs + TSADCV2_INT_EN);
1070 }
1071
rk_tsadcv4_tshut_mode(int chn,void __iomem * regs,enum tshut_mode mode)1072 static void rk_tsadcv4_tshut_mode(int chn, void __iomem *regs,
1073 enum tshut_mode mode)
1074 {
1075 u32 val_gpio, val_cru;
1076
1077 if (mode == TSHUT_MODE_GPIO) {
1078 val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
1079 val_cru = TSADCV2_INT_SRC_EN_MASK(chn);
1080 } else {
1081 val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
1082 val_gpio = TSADCV2_INT_SRC_EN_MASK(chn);
1083 }
1084 writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN);
1085 writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN);
1086 }
1087
rk_tsadcv2_get_trim_code(const struct chip_tsadc_table * table,int code,int trim_base,int trim_base_frac)1088 static int rk_tsadcv2_get_trim_code(const struct chip_tsadc_table *table,
1089 int code, int trim_base, int trim_base_frac)
1090 {
1091 int temp = trim_base * 1000 + trim_base_frac * 100;
1092 u32 base_code = rk_tsadcv2_temp_to_code(table, temp);
1093
1094 return code - base_code;
1095 }
1096
1097 static const struct rockchip_tsadc_chip px30_tsadc_data = {
1098 /* cpu, gpu */
1099 .chn_offset = 0,
1100 .chn_num = 2, /* 2 channels for tsadc */
1101
1102 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1103 .tshut_temp = 95000,
1104
1105 .initialize = rk_tsadcv4_initialize,
1106 .irq_ack = rk_tsadcv3_irq_ack,
1107 .control = rk_tsadcv3_control,
1108 .get_temp = rk_tsadcv2_get_temp,
1109 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1110 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1111 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1112
1113 .table = {
1114 .id = rk3328_code_table,
1115 .length = ARRAY_SIZE(rk3328_code_table),
1116 .data_mask = TSADCV2_DATA_MASK,
1117 .mode = ADC_INCREMENT,
1118 },
1119 };
1120
1121 static const struct rockchip_tsadc_chip rv1108_tsadc_data = {
1122 /* cpu */
1123 .chn_offset = 0,
1124 .chn_num = 1, /* one channel for tsadc */
1125
1126 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1127 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1128 .tshut_temp = 95000,
1129
1130 .initialize = rk_tsadcv2_initialize,
1131 .irq_ack = rk_tsadcv3_irq_ack,
1132 .control = rk_tsadcv3_control,
1133 .get_temp = rk_tsadcv2_get_temp,
1134 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1135 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1136 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1137
1138 .table = {
1139 .id = rv1108_table,
1140 .length = ARRAY_SIZE(rv1108_table),
1141 .data_mask = TSADCV2_DATA_MASK,
1142 .mode = ADC_INCREMENT,
1143 },
1144 };
1145
1146 static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
1147 /* cpu */
1148 .chn_offset = 0,
1149 .chn_num = 1, /* one channel for tsadc */
1150
1151 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1152 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1153 .tshut_temp = 95000,
1154
1155 .initialize = rk_tsadcv2_initialize,
1156 .irq_ack = rk_tsadcv3_irq_ack,
1157 .control = rk_tsadcv3_control,
1158 .get_temp = rk_tsadcv2_get_temp,
1159 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1160 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1161 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1162
1163 .table = {
1164 .id = rk3228_code_table,
1165 .length = ARRAY_SIZE(rk3228_code_table),
1166 .data_mask = TSADCV3_DATA_MASK,
1167 .mode = ADC_INCREMENT,
1168 },
1169 };
1170
1171 static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
1172 /* cpu, gpu */
1173 .chn_offset = 1,
1174 .chn_num = 2, /* two channels for tsadc */
1175
1176 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1177 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1178 .tshut_temp = 95000,
1179
1180 .initialize = rk_tsadcv2_initialize,
1181 .irq_ack = rk_tsadcv2_irq_ack,
1182 .control = rk_tsadcv2_control,
1183 .get_temp = rk_tsadcv2_get_temp,
1184 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1185 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1186 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1187
1188 .table = {
1189 .id = rk3288_code_table,
1190 .length = ARRAY_SIZE(rk3288_code_table),
1191 .data_mask = TSADCV2_DATA_MASK,
1192 .mode = ADC_DECREMENT,
1193 },
1194 };
1195
1196 static const struct rockchip_tsadc_chip rk3328_tsadc_data = {
1197 /* cpu */
1198 .chn_offset = 0,
1199 .chn_num = 1, /* one channels for tsadc */
1200
1201 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1202 .tshut_temp = 95000,
1203
1204 .initialize = rk_tsadcv2_initialize,
1205 .irq_ack = rk_tsadcv3_irq_ack,
1206 .control = rk_tsadcv3_control,
1207 .get_temp = rk_tsadcv2_get_temp,
1208 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1209 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1210 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1211
1212 .table = {
1213 .id = rk3328_code_table,
1214 .length = ARRAY_SIZE(rk3328_code_table),
1215 .data_mask = TSADCV2_DATA_MASK,
1216 .mode = ADC_INCREMENT,
1217 },
1218 };
1219
1220 static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
1221 /* cpu, gpu */
1222 .chn_offset = 0,
1223 .chn_num = 2, /* two channels for tsadc */
1224
1225 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1226 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1227 .tshut_temp = 95000,
1228
1229 .initialize = rk_tsadcv3_initialize,
1230 .irq_ack = rk_tsadcv3_irq_ack,
1231 .control = rk_tsadcv3_control,
1232 .get_temp = rk_tsadcv2_get_temp,
1233 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1234 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1235 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1236
1237 .table = {
1238 .id = rk3228_code_table,
1239 .length = ARRAY_SIZE(rk3228_code_table),
1240 .data_mask = TSADCV3_DATA_MASK,
1241 .mode = ADC_INCREMENT,
1242 },
1243 };
1244
1245 static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
1246 /* cpu, gpu */
1247 .chn_offset = 0,
1248 .chn_num = 2, /* two channels for tsadc */
1249
1250 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1251 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1252 .tshut_temp = 95000,
1253
1254 .initialize = rk_tsadcv2_initialize,
1255 .irq_ack = rk_tsadcv2_irq_ack,
1256 .control = rk_tsadcv2_control,
1257 .get_temp = rk_tsadcv2_get_temp,
1258 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1259 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1260 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1261
1262 .table = {
1263 .id = rk3368_code_table,
1264 .length = ARRAY_SIZE(rk3368_code_table),
1265 .data_mask = TSADCV3_DATA_MASK,
1266 .mode = ADC_INCREMENT,
1267 },
1268 };
1269
1270 static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
1271 /* cpu, gpu */
1272 .chn_offset = 0,
1273 .chn_num = 2, /* two channels for tsadc */
1274
1275 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1276 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1277 .tshut_temp = 95000,
1278
1279 .initialize = rk_tsadcv3_initialize,
1280 .irq_ack = rk_tsadcv3_irq_ack,
1281 .control = rk_tsadcv3_control,
1282 .get_temp = rk_tsadcv2_get_temp,
1283 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1284 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1285 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1286
1287 .table = {
1288 .id = rk3399_code_table,
1289 .length = ARRAY_SIZE(rk3399_code_table),
1290 .data_mask = TSADCV3_DATA_MASK,
1291 .mode = ADC_INCREMENT,
1292 },
1293 };
1294
1295 static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
1296 /* cpu, gpu */
1297 .chn_offset = 0,
1298 .chn_num = 2, /* two channels for tsadc */
1299
1300 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1301 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1302 .tshut_temp = 95000,
1303
1304 .initialize = rk_tsadcv7_initialize,
1305 .irq_ack = rk_tsadcv3_irq_ack,
1306 .control = rk_tsadcv3_control,
1307 .get_temp = rk_tsadcv2_get_temp,
1308 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1309 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1310 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1311
1312 .table = {
1313 .id = rk3568_code_table,
1314 .length = ARRAY_SIZE(rk3568_code_table),
1315 .data_mask = TSADCV2_DATA_MASK,
1316 .mode = ADC_INCREMENT,
1317 },
1318 };
1319
1320 static const struct rockchip_tsadc_chip rk3576_tsadc_data = {
1321 /* top, big_core, little_core, ddr, npu, gpu */
1322 .chn_offset = 0,
1323 .chn_num = 6, /* six channels for tsadc */
1324 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1325 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1326 .tshut_temp = 95000,
1327 .initialize = rk_tsadcv8_initialize,
1328 .irq_ack = rk_tsadcv4_irq_ack,
1329 .control = rk_tsadcv4_control,
1330 .get_temp = rk_tsadcv4_get_temp,
1331 .set_alarm_temp = rk_tsadcv3_alarm_temp,
1332 .set_tshut_temp = rk_tsadcv3_tshut_temp,
1333 .set_tshut_mode = rk_tsadcv4_tshut_mode,
1334 .get_trim_code = rk_tsadcv2_get_trim_code,
1335 .trim_slope = 923,
1336 .table = {
1337 .id = rk3588_code_table,
1338 .length = ARRAY_SIZE(rk3588_code_table),
1339 .data_mask = TSADCV4_DATA_MASK,
1340 .mode = ADC_INCREMENT,
1341 },
1342 };
1343
1344 static const struct rockchip_tsadc_chip rk3588_tsadc_data = {
1345 /* top, big_core0, big_core1, little_core, center, gpu, npu */
1346 .chn_offset = 0,
1347 .chn_num = 7, /* seven channels for tsadc */
1348 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1349 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1350 .tshut_temp = 95000,
1351 .initialize = rk_tsadcv8_initialize,
1352 .irq_ack = rk_tsadcv4_irq_ack,
1353 .control = rk_tsadcv4_control,
1354 .get_temp = rk_tsadcv4_get_temp,
1355 .set_alarm_temp = rk_tsadcv3_alarm_temp,
1356 .set_tshut_temp = rk_tsadcv3_tshut_temp,
1357 .set_tshut_mode = rk_tsadcv4_tshut_mode,
1358 .table = {
1359 .id = rk3588_code_table,
1360 .length = ARRAY_SIZE(rk3588_code_table),
1361 .data_mask = TSADCV4_DATA_MASK,
1362 .mode = ADC_INCREMENT,
1363 },
1364 };
1365
1366 static const struct of_device_id of_rockchip_thermal_match[] = {
1367 { .compatible = "rockchip,px30-tsadc",
1368 .data = (void *)&px30_tsadc_data,
1369 },
1370 {
1371 .compatible = "rockchip,rv1108-tsadc",
1372 .data = (void *)&rv1108_tsadc_data,
1373 },
1374 {
1375 .compatible = "rockchip,rk3228-tsadc",
1376 .data = (void *)&rk3228_tsadc_data,
1377 },
1378 {
1379 .compatible = "rockchip,rk3288-tsadc",
1380 .data = (void *)&rk3288_tsadc_data,
1381 },
1382 {
1383 .compatible = "rockchip,rk3328-tsadc",
1384 .data = (void *)&rk3328_tsadc_data,
1385 },
1386 {
1387 .compatible = "rockchip,rk3366-tsadc",
1388 .data = (void *)&rk3366_tsadc_data,
1389 },
1390 {
1391 .compatible = "rockchip,rk3368-tsadc",
1392 .data = (void *)&rk3368_tsadc_data,
1393 },
1394 {
1395 .compatible = "rockchip,rk3399-tsadc",
1396 .data = (void *)&rk3399_tsadc_data,
1397 },
1398 {
1399 .compatible = "rockchip,rk3568-tsadc",
1400 .data = (void *)&rk3568_tsadc_data,
1401 },
1402 {
1403 .compatible = "rockchip,rk3576-tsadc",
1404 .data = (void *)&rk3576_tsadc_data,
1405 },
1406 {
1407 .compatible = "rockchip,rk3588-tsadc",
1408 .data = (void *)&rk3588_tsadc_data,
1409 },
1410 { /* end */ },
1411 };
1412 MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
1413
1414 static void
rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor * sensor,bool on)1415 rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)
1416 {
1417 struct thermal_zone_device *tzd = sensor->tzd;
1418
1419 if (on)
1420 thermal_zone_device_enable(tzd);
1421 else
1422 thermal_zone_device_disable(tzd);
1423 }
1424
rockchip_thermal_alarm_irq_thread(int irq,void * dev)1425 static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
1426 {
1427 struct rockchip_thermal_data *thermal = dev;
1428 int i;
1429
1430 dev_dbg(&thermal->pdev->dev, "thermal alarm\n");
1431
1432 thermal->chip->irq_ack(thermal->regs);
1433
1434 for (i = 0; i < thermal->chip->chn_num; i++)
1435 thermal_zone_device_update(thermal->sensors[i].tzd,
1436 THERMAL_EVENT_UNSPECIFIED);
1437
1438 return IRQ_HANDLED;
1439 }
1440
rockchip_thermal_set_trips(struct thermal_zone_device * tz,int low,int high)1441 static int rockchip_thermal_set_trips(struct thermal_zone_device *tz, int low, int high)
1442 {
1443 struct rockchip_thermal_sensor *sensor = thermal_zone_device_priv(tz);
1444 struct rockchip_thermal_data *thermal = sensor->thermal;
1445 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1446
1447 dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n",
1448 __func__, sensor->id, low, high);
1449
1450 return tsadc->set_alarm_temp(&tsadc->table,
1451 sensor->id, thermal->regs, high + sensor->trim_temp);
1452 }
1453
rockchip_thermal_get_temp(struct thermal_zone_device * tz,int * out_temp)1454 static int rockchip_thermal_get_temp(struct thermal_zone_device *tz, int *out_temp)
1455 {
1456 struct rockchip_thermal_sensor *sensor = thermal_zone_device_priv(tz);
1457 struct rockchip_thermal_data *thermal = sensor->thermal;
1458 const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
1459 int retval;
1460
1461 retval = tsadc->get_temp(&tsadc->table,
1462 sensor->id, thermal->regs, out_temp);
1463 *out_temp -= sensor->trim_temp;
1464
1465 return retval;
1466 }
1467
1468 static const struct thermal_zone_device_ops rockchip_of_thermal_ops = {
1469 .get_temp = rockchip_thermal_get_temp,
1470 .set_trips = rockchip_thermal_set_trips,
1471 };
1472
1473 /**
1474 * rockchip_get_efuse_value - read an OTP cell from a device node
1475 * @np: pointer to the device node with the nvmem-cells property
1476 * @cell_name: name of cell that should be read
1477 * @value: pointer to where the read value will be placed
1478 *
1479 * Return: Negative errno on failure, during which *value will not be touched,
1480 * or 0 on success.
1481 */
rockchip_get_efuse_value(struct device_node * np,const char * cell_name,int * value)1482 static int rockchip_get_efuse_value(struct device_node *np, const char *cell_name,
1483 int *value)
1484 {
1485 struct nvmem_cell *cell;
1486 int ret = 0;
1487 size_t len;
1488 u8 *buf;
1489 int i;
1490
1491 cell = of_nvmem_cell_get(np, cell_name);
1492 if (IS_ERR(cell))
1493 return PTR_ERR(cell);
1494
1495 buf = nvmem_cell_read(cell, &len);
1496
1497 nvmem_cell_put(cell);
1498
1499 if (IS_ERR(buf))
1500 return PTR_ERR(buf);
1501
1502 if (len > sizeof(*value)) {
1503 ret = -ERANGE;
1504 goto exit;
1505 }
1506
1507 /* Copy with implicit endian conversion */
1508 *value = 0;
1509 for (i = 0; i < len; i++)
1510 *value |= (int) buf[i] << (8 * i);
1511
1512 exit:
1513 kfree(buf);
1514 return ret;
1515 }
1516
rockchip_get_trim_configuration(struct device * dev,struct device_node * np,struct rockchip_thermal_data * thermal)1517 static int rockchip_get_trim_configuration(struct device *dev, struct device_node *np,
1518 struct rockchip_thermal_data *thermal)
1519 {
1520 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1521 int trim_base = 0, trim_base_frac = 0, trim = 0;
1522 int trim_code;
1523 int ret;
1524
1525 thermal->trim_base = 0;
1526 thermal->trim_base_frac = 0;
1527 thermal->trim = 0;
1528
1529 if (!tsadc->get_trim_code)
1530 return 0;
1531
1532 ret = rockchip_get_efuse_value(np, "trim_base", &trim_base);
1533 if (ret < 0) {
1534 if (ret == -ENOENT) {
1535 trim_base = 30;
1536 dev_dbg(dev, "trim_base is absent, defaulting to 30\n");
1537 } else {
1538 dev_err(dev, "failed reading nvmem value of trim_base: %pe\n",
1539 ERR_PTR(ret));
1540 return ret;
1541 }
1542 }
1543 ret = rockchip_get_efuse_value(np, "trim_base_frac", &trim_base_frac);
1544 if (ret < 0) {
1545 if (ret == -ENOENT) {
1546 dev_dbg(dev, "trim_base_frac is absent, defaulting to 0\n");
1547 } else {
1548 dev_err(dev, "failed reading nvmem value of trim_base_frac: %pe\n",
1549 ERR_PTR(ret));
1550 return ret;
1551 }
1552 }
1553 thermal->trim_base = trim_base;
1554 thermal->trim_base_frac = trim_base_frac;
1555
1556 /*
1557 * If the tsadc node contains the trim property, then it is used in the
1558 * absence of per-channel trim values
1559 */
1560 if (!rockchip_get_efuse_value(np, "trim", &trim))
1561 thermal->trim = trim;
1562 if (trim) {
1563 trim_code = tsadc->get_trim_code(&tsadc->table, trim,
1564 trim_base, trim_base_frac);
1565 thermal->trim_temp = thermal->chip->trim_slope * trim_code;
1566 }
1567
1568 return 0;
1569 }
1570
rockchip_configure_from_dt(struct device * dev,struct device_node * np,struct rockchip_thermal_data * thermal)1571 static int rockchip_configure_from_dt(struct device *dev,
1572 struct device_node *np,
1573 struct rockchip_thermal_data *thermal)
1574 {
1575 u32 shut_temp, tshut_mode, tshut_polarity;
1576
1577 if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) {
1578 dev_warn(dev,
1579 "Missing tshut temp property, using default %d\n",
1580 thermal->chip->tshut_temp);
1581 thermal->tshut_temp = thermal->chip->tshut_temp;
1582 } else {
1583 if (shut_temp > INT_MAX) {
1584 dev_err(dev, "Invalid tshut temperature specified: %d\n",
1585 shut_temp);
1586 return -ERANGE;
1587 }
1588 thermal->tshut_temp = shut_temp;
1589 }
1590
1591 if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) {
1592 dev_warn(dev,
1593 "Missing tshut mode property, using default (%s)\n",
1594 thermal->chip->tshut_mode == TSHUT_MODE_GPIO ?
1595 "gpio" : "cru");
1596 thermal->tshut_mode = thermal->chip->tshut_mode;
1597 } else {
1598 thermal->tshut_mode = tshut_mode;
1599 }
1600
1601 if (thermal->tshut_mode > 1) {
1602 dev_err(dev, "Invalid tshut mode specified: %d\n",
1603 thermal->tshut_mode);
1604 return -EINVAL;
1605 }
1606
1607 if (of_property_read_u32(np, "rockchip,hw-tshut-polarity",
1608 &tshut_polarity)) {
1609 dev_warn(dev,
1610 "Missing tshut-polarity property, using default (%s)\n",
1611 thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ?
1612 "low" : "high");
1613 thermal->tshut_polarity = thermal->chip->tshut_polarity;
1614 } else {
1615 thermal->tshut_polarity = tshut_polarity;
1616 }
1617
1618 if (thermal->tshut_polarity > 1) {
1619 dev_err(dev, "Invalid tshut-polarity specified: %d\n",
1620 thermal->tshut_polarity);
1621 return -EINVAL;
1622 }
1623
1624 /* The tsadc wont to handle the error in here since some SoCs didn't
1625 * need this property.
1626 */
1627 thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1628 if (IS_ERR(thermal->grf))
1629 dev_warn(dev, "Missing rockchip,grf property\n");
1630
1631 rockchip_get_trim_configuration(dev, np, thermal);
1632
1633 return 0;
1634 }
1635
1636 static int
rockchip_thermal_register_sensor(struct platform_device * pdev,struct rockchip_thermal_data * thermal,struct rockchip_thermal_sensor * sensor,int id)1637 rockchip_thermal_register_sensor(struct platform_device *pdev,
1638 struct rockchip_thermal_data *thermal,
1639 struct rockchip_thermal_sensor *sensor,
1640 int id)
1641 {
1642 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1643 struct device *dev = &pdev->dev;
1644 int trim = thermal->trim;
1645 int trim_code, tshut_temp;
1646 int trim_temp = 0;
1647 int error;
1648
1649 if (thermal->trim_temp)
1650 trim_temp = thermal->trim_temp;
1651
1652 if (tsadc->get_trim_code && sensor->of_node) {
1653 error = rockchip_get_efuse_value(sensor->of_node, "trim", &trim);
1654 if (error < 0 && error != -ENOENT) {
1655 dev_err(dev, "failed reading trim of sensor %d: %pe\n",
1656 id, ERR_PTR(error));
1657 return error;
1658 }
1659 if (trim) {
1660 trim_code = tsadc->get_trim_code(&tsadc->table, trim,
1661 thermal->trim_base,
1662 thermal->trim_base_frac);
1663 trim_temp = thermal->chip->trim_slope * trim_code;
1664 }
1665 }
1666
1667 sensor->trim_temp = trim_temp;
1668
1669 dev_dbg(dev, "trim of sensor %d is %d\n", id, sensor->trim_temp);
1670
1671 tshut_temp = min(thermal->tshut_temp + sensor->trim_temp, RK_MAX_TEMP);
1672
1673 tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode);
1674
1675 error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs, tshut_temp);
1676 if (error)
1677 dev_err(dev, "%s: invalid tshut=%d, error=%d\n",
1678 __func__, tshut_temp, error);
1679
1680 sensor->thermal = thermal;
1681 sensor->id = id;
1682 sensor->tzd = devm_thermal_of_zone_register(dev, id, sensor,
1683 &rockchip_of_thermal_ops);
1684 if (IS_ERR(sensor->tzd)) {
1685 error = PTR_ERR(sensor->tzd);
1686 dev_err(dev, "failed to register sensor %d: %d\n",
1687 id, error);
1688 return error;
1689 }
1690
1691 return 0;
1692 }
1693
1694 /**
1695 * rockchip_thermal_reset_controller - Reset TSADC Controller, reset all tsadc registers.
1696 * @reset: the reset controller of tsadc
1697 */
rockchip_thermal_reset_controller(struct reset_control * reset)1698 static void rockchip_thermal_reset_controller(struct reset_control *reset)
1699 {
1700 reset_control_assert(reset);
1701 usleep_range(10, 20);
1702 reset_control_deassert(reset);
1703 }
1704
rockchip_thermal_probe(struct platform_device * pdev)1705 static int rockchip_thermal_probe(struct platform_device *pdev)
1706 {
1707 struct device_node *np = pdev->dev.of_node;
1708 struct rockchip_thermal_data *thermal;
1709 struct device_node *child;
1710 int irq;
1711 int i;
1712 int error;
1713 u32 chn;
1714
1715 irq = platform_get_irq(pdev, 0);
1716 if (irq < 0)
1717 return -EINVAL;
1718
1719 thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
1720 GFP_KERNEL);
1721 if (!thermal)
1722 return -ENOMEM;
1723
1724 thermal->pdev = pdev;
1725
1726 thermal->chip = device_get_match_data(&pdev->dev);
1727 if (!thermal->chip)
1728 return -EINVAL;
1729
1730 thermal->sensors = devm_kcalloc(&pdev->dev, thermal->chip->chn_num,
1731 sizeof(*thermal->sensors), GFP_KERNEL);
1732 if (!thermal->sensors)
1733 return -ENOMEM;
1734
1735 thermal->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1736 if (IS_ERR(thermal->regs))
1737 return PTR_ERR(thermal->regs);
1738
1739 thermal->reset = devm_reset_control_array_get_exclusive(&pdev->dev);
1740 if (IS_ERR(thermal->reset))
1741 return dev_err_probe(&pdev->dev, PTR_ERR(thermal->reset),
1742 "failed to get tsadc reset.\n");
1743
1744 thermal->clk = devm_clk_get_enabled(&pdev->dev, "tsadc");
1745 if (IS_ERR(thermal->clk))
1746 return dev_err_probe(&pdev->dev, PTR_ERR(thermal->clk),
1747 "failed to get tsadc clock.\n");
1748
1749 thermal->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
1750 if (IS_ERR(thermal->pclk))
1751 return dev_err_probe(&pdev->dev, PTR_ERR(thermal->pclk),
1752 "failed to get apb_pclk clock.\n");
1753
1754 rockchip_thermal_reset_controller(thermal->reset);
1755
1756 error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
1757 if (error)
1758 return dev_err_probe(&pdev->dev, error,
1759 "failed to parse device tree data\n");
1760
1761 thermal->chip->initialize(thermal->grf, thermal->regs,
1762 thermal->tshut_polarity);
1763
1764 for_each_available_child_of_node(np, child) {
1765 if (!of_property_read_u32(child, "reg", &chn)) {
1766 if (chn < thermal->chip->chn_num)
1767 thermal->sensors[chn].of_node = child;
1768 else
1769 dev_warn(&pdev->dev,
1770 "sensor address (%d) too large, ignoring its trim\n",
1771 chn);
1772 }
1773
1774 }
1775
1776 for (i = 0; i < thermal->chip->chn_num; i++) {
1777 error = rockchip_thermal_register_sensor(pdev, thermal,
1778 &thermal->sensors[i],
1779 thermal->chip->chn_offset + i);
1780 if (error)
1781 return dev_err_probe(&pdev->dev, error,
1782 "failed to register sensor[%d].\n", i);
1783 }
1784
1785 error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1786 &rockchip_thermal_alarm_irq_thread,
1787 IRQF_ONESHOT,
1788 "rockchip_thermal", thermal);
1789 if (error)
1790 return dev_err_probe(&pdev->dev, error,
1791 "failed to request tsadc irq.\n");
1792
1793 thermal->chip->control(thermal->regs, true);
1794
1795 for (i = 0; i < thermal->chip->chn_num; i++) {
1796 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1797 error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd);
1798 if (error)
1799 dev_warn(&pdev->dev,
1800 "failed to register sensor %d with hwmon: %d\n",
1801 i, error);
1802 }
1803
1804 platform_set_drvdata(pdev, thermal);
1805
1806 return 0;
1807 }
1808
rockchip_thermal_remove(struct platform_device * pdev)1809 static void rockchip_thermal_remove(struct platform_device *pdev)
1810 {
1811 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1812 int i;
1813
1814 for (i = 0; i < thermal->chip->chn_num; i++) {
1815 struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
1816
1817 thermal_remove_hwmon_sysfs(sensor->tzd);
1818 rockchip_thermal_toggle_sensor(sensor, false);
1819 }
1820
1821 thermal->chip->control(thermal->regs, false);
1822 }
1823
rockchip_thermal_suspend(struct device * dev)1824 static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
1825 {
1826 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
1827 int i;
1828
1829 for (i = 0; i < thermal->chip->chn_num; i++)
1830 rockchip_thermal_toggle_sensor(&thermal->sensors[i], false);
1831
1832 thermal->chip->control(thermal->regs, false);
1833
1834 clk_disable(thermal->pclk);
1835 clk_disable(thermal->clk);
1836
1837 pinctrl_pm_select_sleep_state(dev);
1838
1839 return 0;
1840 }
1841
rockchip_thermal_resume(struct device * dev)1842 static int __maybe_unused rockchip_thermal_resume(struct device *dev)
1843 {
1844 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
1845 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1846 struct rockchip_thermal_sensor *sensor;
1847 int tshut_temp;
1848 int error;
1849 int i;
1850
1851 error = clk_enable(thermal->clk);
1852 if (error)
1853 return error;
1854
1855 error = clk_enable(thermal->pclk);
1856 if (error) {
1857 clk_disable(thermal->clk);
1858 return error;
1859 }
1860
1861 rockchip_thermal_reset_controller(thermal->reset);
1862
1863 tsadc->initialize(thermal->grf, thermal->regs, thermal->tshut_polarity);
1864
1865 for (i = 0; i < thermal->chip->chn_num; i++) {
1866 sensor = &thermal->sensors[i];
1867
1868 tshut_temp = min(thermal->tshut_temp + sensor->trim_temp,
1869 RK_MAX_TEMP);
1870
1871 tsadc->set_tshut_mode(sensor->id, thermal->regs,
1872 thermal->tshut_mode);
1873
1874 error = tsadc->set_tshut_temp(&thermal->chip->table,
1875 sensor->id, thermal->regs,
1876 tshut_temp);
1877 if (error)
1878 dev_err(dev, "%s: invalid tshut=%d, error=%d\n",
1879 __func__, tshut_temp, error);
1880 }
1881
1882 thermal->chip->control(thermal->regs, true);
1883
1884 for (i = 0; i < thermal->chip->chn_num; i++)
1885 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1886
1887 pinctrl_pm_select_default_state(dev);
1888
1889 return 0;
1890 }
1891
1892 static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops,
1893 rockchip_thermal_suspend, rockchip_thermal_resume);
1894
1895 static struct platform_driver rockchip_thermal_driver = {
1896 .driver = {
1897 .name = "rockchip-thermal",
1898 .pm = &rockchip_thermal_pm_ops,
1899 .of_match_table = of_rockchip_thermal_match,
1900 },
1901 .probe = rockchip_thermal_probe,
1902 .remove = rockchip_thermal_remove,
1903 };
1904
1905 module_platform_driver(rockchip_thermal_driver);
1906
1907 MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
1908 MODULE_AUTHOR("Rockchip, Inc.");
1909 MODULE_LICENSE("GPL v2");
1910 MODULE_ALIAS("platform:rockchip-thermal");
1911