xref: /linux/drivers/gpu/drm/i915/gvt/reg.h (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  */
23 
24 #ifndef _GVT_REG_H
25 #define _GVT_REG_H
26 
27 #define INTEL_GVT_PCI_CLASS_VGA_OTHER   0x80
28 
29 #define INTEL_GVT_PCI_GMCH_CONTROL	0x50
30 #define   BDW_GMCH_GMS_SHIFT		8
31 #define   BDW_GMCH_GMS_MASK		0xff
32 
33 #define INTEL_GVT_PCI_SWSCI		0xe8
34 #define   SWSCI_SCI_SELECT		(1 << 15)
35 #define   SWSCI_SCI_TRIGGER		1
36 
37 #define INTEL_GVT_PCI_OPREGION		0xfc
38 
39 #define INTEL_GVT_OPREGION_CLID		0x1AC
40 #define INTEL_GVT_OPREGION_SCIC		0x200
41 #define   OPREGION_SCIC_FUNC_MASK	0x1E
42 #define   OPREGION_SCIC_FUNC_SHIFT	1
43 #define   OPREGION_SCIC_SUBFUNC_MASK	0xFF00
44 #define   OPREGION_SCIC_SUBFUNC_SHIFT	8
45 #define   OPREGION_SCIC_EXIT_MASK	0xE0
46 #define INTEL_GVT_OPREGION_SCIC_F_GETBIOSDATA         4
47 #define INTEL_GVT_OPREGION_SCIC_F_GETBIOSCALLBACKS    6
48 #define INTEL_GVT_OPREGION_SCIC_SF_SUPPRTEDCALLS      0
49 #define INTEL_GVT_OPREGION_SCIC_SF_REQEUSTEDCALLBACKS 1
50 #define INTEL_GVT_OPREGION_PARM                   0x204
51 
52 #define INTEL_GVT_OPREGION_PAGES	2
53 #define INTEL_GVT_OPREGION_SIZE		(INTEL_GVT_OPREGION_PAGES * PAGE_SIZE)
54 #define INTEL_GVT_OPREGION_VBT_OFFSET	0x400
55 #define INTEL_GVT_OPREGION_VBT_SIZE	\
56 		(INTEL_GVT_OPREGION_SIZE - INTEL_GVT_OPREGION_VBT_OFFSET)
57 
58 #define VGT_SPRSTRIDE(pipe)	_PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
59 
60 #define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe))
61 
62 #define REG50080_FLIP_TYPE_MASK	0x3
63 #define REG50080_FLIP_TYPE_ASYNC	0x1
64 
65 #define REG_50080(_pipe, _plane) ({ \
66 	typeof(_pipe) (p) = (_pipe); \
67 	typeof(_plane) (q) = (_plane); \
68 	(((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
69 		(_MMIO(0x50090))) : \
70 	(((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
71 		(_MMIO(0x50098))) : \
72 	(((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \
73 		(_MMIO(0x5009C))) : \
74 		(_MMIO(0x50080))))); })
75 
76 #define REG_50080_TO_PIPE(_reg) ({ \
77 	typeof(_reg) (reg) = (_reg); \
78 	(((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \
79 	(((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \
80 	(((reg) == 0x5008C || (reg) == 0x5009C) ? (PIPE_C) : \
81 	(INVALID_PIPE)))); })
82 
83 #define REG_50080_TO_PLANE(_reg) ({ \
84 	typeof(_reg) (reg) = (_reg); \
85 	(((reg) == 0x50080 || (reg) == 0x50088 || (reg) == 0x5008C) ? \
86 		(PLANE_PRIMARY) : \
87 	(((reg) == 0x50090 || (reg) == 0x50098 || (reg) == 0x5009C) ? \
88 		(PLANE_SPRITE0) : (I915_MAX_PLANES))); })
89 
90 #define GFX_MODE_BIT_SET_IN_MASK(val, bit) \
91 		((((bit) & 0xffff0000) == 0) && !!((val) & (((bit) << 16))))
92 
93 #define IS_MASKED_BITS_ENABLED(_val, _b) \
94 		(((_val) & _MASKED_BIT_ENABLE(_b)) == _MASKED_BIT_ENABLE(_b))
95 #define IS_MASKED_BITS_DISABLED(_val, _b) \
96 		((_val) & _MASKED_BIT_DISABLE(_b))
97 
98 #define FORCEWAKE_RENDER_GEN9_REG 0xa278
99 #define FORCEWAKE_ACK_RENDER_GEN9_REG 0x0D84
100 #define FORCEWAKE_GT_GEN9_REG 0xa188
101 #define FORCEWAKE_ACK_GT_GEN9_REG 0x130044
102 #define FORCEWAKE_MEDIA_GEN9_REG 0xa270
103 #define FORCEWAKE_ACK_MEDIA_GEN9_REG 0x0D88
104 #define FORCEWAKE_ACK_HSW_REG 0x130044
105 
106 #define RB_HEAD_WRAP_CNT_MAX	((1 << 11) - 1)
107 #define RB_HEAD_WRAP_CNT_OFF	21
108 #define RB_HEAD_OFF_MASK	((1U << 21) - (1U << 2))
109 #define RB_TAIL_OFF_MASK	((1U << 21) - (1U << 3))
110 #define RB_TAIL_SIZE_MASK	((1U << 21) - (1U << 12))
111 #define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + \
112 		I915_GTT_PAGE_SIZE)
113 
114 #define PCH_GPIO_BASE	_MMIO(0xc5010)
115 
116 #define PCH_GMBUS0	_MMIO(0xc5100)
117 #define PCH_GMBUS1	_MMIO(0xc5104)
118 #define PCH_GMBUS2	_MMIO(0xc5108)
119 #define PCH_GMBUS3	_MMIO(0xc510c)
120 #define PCH_GMBUS4	_MMIO(0xc5110)
121 #define PCH_GMBUS5	_MMIO(0xc5120)
122 
123 #define TRVATTL3PTRDW(i)	_MMIO(0x4de0 + (i) * 4)
124 #define TRNULLDETCT		_MMIO(0x4de8)
125 #define TRINVTILEDETCT		_MMIO(0x4dec)
126 #define TRVADR			_MMIO(0x4df0)
127 #define TRTTE			_MMIO(0x4df4)
128 #define RING_EXCC(base)		_MMIO((base) + 0x28)
129 #define RING_GFX_MODE(base)	_MMIO((base) + 0x29c)
130 #define VF_GUARDBAND		_MMIO(0x83a4)
131 
132 #define BCS_TILE_REGISTER_VAL_OFFSET (0x43*4)
133 
134 /* XXX FIXME i915 has changed PP_XXX definition */
135 #define PCH_PP_STATUS  _MMIO(0xc7200)
136 #define PCH_PP_CONTROL _MMIO(0xc7204)
137 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
138 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
139 #define PCH_PP_DIVISOR _MMIO(0xc7210)
140 
141 #endif
142