1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /*- 13 * Copyright (c) 2017 Chelsio Communications, Inc. 14 * All rights reserved. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 */ 37 38 #ifndef __CUDBG_ENTITY_H__ 39 #define __CUDBG_ENTITY_H__ 40 41 #include "common.h" 42 43 #ifdef __GNUC__ 44 #define ATTRIBUTE_UNUSED __attribute__ ((unused)) 45 #else 46 #define ATTRIBUTE_UNUSED 47 #endif 48 49 #define MC0_FLAG 1 50 #define MC1_FLAG 2 51 #define EDC0_FLAG 3 52 #define EDC1_FLAG 4 53 54 #define NUM_PCIE_CONFIG_REGS 0x61 55 #define CUDBG_CTXT_SIZE_BYTES 24 56 #define CUDBG_MAX_INGRESS_QIDS 65536 57 #define CUDBG_MAX_FL_QIDS 2048 58 #define CUDBG_MAX_CNM_QIDS 1024 59 #define CUDBG_LOWMEM_MAX_CTXT_QIDS 256 60 #define ETH_ALEN 6 61 #define CUDBG_MAX_RPLC_SIZE 128 62 #define CUDBG_NUM_REQ_REGS 17 63 #define CUDBG_MAX_TCAM_TID 0x800 64 #define CUDBG_NUM_ULPTX 11 65 66 #define SN_REG_ADDR 0x183f 67 #define BN_REG_ADDR 0x1819 68 #define NA_REG_ADDR 0x185a 69 #define MN_REG_ADDR 0x1803 70 71 #define A_MPS_VF_RPLCT_MAP0 0x1111c 72 #define A_MPS_VF_RPLCT_MAP1 0x11120 73 #define A_MPS_VF_RPLCT_MAP2 0x11124 74 #define A_MPS_VF_RPLCT_MAP3 0x11128 75 #define A_MPS_VF_RPLCT_MAP4 0x11300 76 #define A_MPS_VF_RPLCT_MAP5 0x11304 77 #define A_MPS_VF_RPLCT_MAP6 0x11308 78 #define A_MPS_VF_RPLCT_MAP7 0x1130c 79 80 #define PORT_TYPE_ADDR 0x1869 81 #define PORT_TYPE_LEN 8 82 83 /* For T6 */ 84 #define SN_T6_ADDR 0x83f 85 #define BN_T6_ADDR 0x819 86 #define NA_T6_ADDR 0x85a 87 #define MN_T6_ADDR 0x803 88 89 #define SN_MAX_LEN 24 90 #define BN_MAX_LEN 16 91 #define NA_MAX_LEN 12 92 #define MN_MAX_LEN 16 93 #define MAX_VPD_DATA_LEN 32 94 95 #define VPD_VER_ADDR 0x18c7 96 #define VPD_VER_LEN 2 97 #define SCFG_VER_ADDR 0x06 98 #define SCFG_VER_LEN 4 99 100 #define CUDBG_CIM_BUSY_BIT (1 << 17) 101 102 #define CUDBG_CHAC_PBT_ADDR 0x2800 103 #define CUDBG_CHAC_PBT_LRF 0x3000 104 #define CUDBG_CHAC_PBT_DATA 0x3800 105 #define CUDBG_PBT_DYNAMIC_ENTRIES 8 106 #define CUDBG_PBT_STATIC_ENTRIES 16 107 #define CUDBG_LRF_ENTRIES 8 108 #define CUDBG_PBT_DATA_ENTRIES 512 109 110 #define CUDBG_ENTITY_SIGNATURE 0xCCEDB001 111 #define CUDBG_TID_INFO_REV 1 112 #define CUDBG_MAC_STATS_REV 1 113 #define CUDBG_ULPTX_LA_REV 1 114 #define CUDBG_MEMINFO_REV 1 115 116 #define CUDBG_ULPTX_LA_REV 1 117 118 #define CUDBG_T6_CLIP 1536 119 #define CUDBG_MAX_TID_COMP_EN 6144 120 #define CUDBG_MAX_TID_COMP_DIS 3072 121 #define CUDBG_NUM_ULPTX_READ 512 122 #define CUDBG_NUM_ULPTX_ASIC 6 123 #define CUDBG_NUM_ULPTX_ASIC_READ 128 124 125 #ifndef ARRAY_SIZE 126 #define ARRAY_SIZE(_a) (sizeof((_a)) / sizeof((_a)[0])) 127 #endif 128 129 enum cudbg_qdesc_qtype { 130 CUDBG_QTYPE_UNKNOWN = 0, 131 CUDBG_QTYPE_NIC_TXQ, 132 CUDBG_QTYPE_NIC_RXQ, 133 CUDBG_QTYPE_NIC_FLQ, 134 CUDBG_QTYPE_CTRLQ, 135 CUDBG_QTYPE_FWEVTQ, 136 CUDBG_QTYPE_INTRQ, 137 CUDBG_QTYPE_PTP_TXQ, 138 CUDBG_QTYPE_OFLD_TXQ, 139 CUDBG_QTYPE_RDMA_RXQ, 140 CUDBG_QTYPE_RDMA_FLQ, 141 CUDBG_QTYPE_RDMA_CIQ, 142 CUDBG_QTYPE_ISCSI_RXQ, 143 CUDBG_QTYPE_ISCSI_FLQ, 144 CUDBG_QTYPE_ISCSIT_RXQ, 145 CUDBG_QTYPE_ISCSIT_FLQ, 146 CUDBG_QTYPE_CRYPTO_TXQ, 147 CUDBG_QTYPE_CRYPTO_RXQ, 148 CUDBG_QTYPE_CRYPTO_FLQ, 149 CUDBG_QTYPE_TLS_RXQ, 150 CUDBG_QTYPE_TLS_FLQ, 151 CUDBG_QTYPE_MAX, 152 }; 153 154 struct cudbg_pbt_tables { 155 u32 pbt_dynamic[CUDBG_PBT_DYNAMIC_ENTRIES]; 156 u32 pbt_static[CUDBG_PBT_STATIC_ENTRIES]; 157 u32 lrf_table[CUDBG_LRF_ENTRIES]; 158 u32 pbt_data[CUDBG_PBT_DATA_ENTRIES]; 159 }; 160 161 struct card_mem { 162 u16 size_mc0; 163 u16 size_mc1; 164 u16 size_edc0; 165 u16 size_edc1; 166 u16 mem_flag; 167 u16 res; 168 }; 169 170 struct rss_pf_conf { 171 u32 rss_pf_map; 172 u32 rss_pf_mask; 173 u32 rss_pf_config; 174 }; 175 176 struct cudbg_ch_cntxt { 177 uint32_t cntxt_type; 178 uint32_t cntxt_id; 179 uint32_t data[SGE_CTXT_SIZE / 4]; 180 }; 181 182 struct cudbg_tcam { 183 u32 filter_start; 184 u32 server_start; 185 u32 clip_start; 186 u32 routing_start; 187 u32 tid_hash_base; 188 u32 max_tid; 189 }; 190 191 struct cudbg_mbox_log { 192 struct mbox_cmd entry; 193 u32 hi[MBOX_LEN / 8]; 194 u32 lo[MBOX_LEN / 8]; 195 }; 196 197 struct cudbg_tid_data { 198 u32 tid; 199 u32 dbig_cmd; 200 u32 dbig_conf; 201 u32 dbig_rsp_stat; 202 u32 data[CUDBG_NUM_REQ_REGS]; 203 }; 204 205 struct cudbg_cntxt_field { 206 char *name; 207 u32 start_bit; 208 u32 end_bit; 209 u32 shift; 210 u32 islog2; 211 }; 212 213 struct cudbg_mps_tcam { 214 u64 mask; 215 u32 rplc[8]; 216 u32 idx; 217 u32 cls_lo; 218 u32 cls_hi; 219 u32 rplc_size; 220 u32 vniy; 221 u32 vnix; 222 u32 dip_hit; 223 u32 vlan_vld; 224 u32 repli; 225 u16 ivlan; 226 u8 addr[ETH_ALEN]; 227 u8 lookup_type; 228 u8 port_num; 229 u8 reserved[2]; 230 }; 231 232 struct rss_vf_conf { 233 u32 rss_vf_vfl; 234 u32 rss_vf_vfh; 235 }; 236 237 struct rss_config { 238 u32 tp_rssconf; /* A_TP_RSS_CONFIG */ 239 u32 tp_rssconf_tnl; /* A_TP_RSS_CONFIG_TNL */ 240 u32 tp_rssconf_ofd; /* A_TP_RSS_CONFIG_OFD */ 241 u32 tp_rssconf_syn; /* A_TP_RSS_CONFIG_SYN */ 242 u32 tp_rssconf_vrt; /* A_TP_RSS_CONFIG_VRT */ 243 u32 tp_rssconf_cng; /* A_TP_RSS_CONFIG_CNG */ 244 u32 chip; 245 }; 246 247 struct struct_pm_stats { 248 u32 tx_cnt[T6_PM_NSTATS]; 249 u32 rx_cnt[T6_PM_NSTATS]; 250 u64 tx_cyc[T6_PM_NSTATS]; 251 u64 rx_cyc[T6_PM_NSTATS]; 252 }; 253 254 struct struct_hw_sched { 255 u32 kbps[NTX_SCHED]; 256 u32 ipg[NTX_SCHED]; 257 u32 pace_tab[NTX_SCHED]; 258 u32 mode; 259 u32 map; 260 }; 261 262 struct struct_tcp_stats { 263 struct tp_tcp_stats v4, v6; 264 }; 265 266 struct struct_tp_err_stats { 267 struct tp_err_stats stats; 268 u32 nchan; 269 }; 270 271 struct struct_tp_fcoe_stats { 272 struct tp_fcoe_stats stats[4]; 273 u32 nchan; 274 }; 275 276 struct struct_mac_stats { 277 u32 port_count; 278 struct port_stats stats[4]; 279 }; 280 281 struct struct_mac_stats_rev1 { 282 struct cudbg_ver_hdr ver_hdr; 283 u32 port_count; 284 u32 reserved; 285 struct port_stats stats[4]; 286 }; 287 288 struct struct_tp_cpl_stats { 289 struct tp_cpl_stats stats; 290 u32 nchan; 291 }; 292 293 struct struct_wc_stats { 294 u32 wr_cl_success; 295 u32 wr_cl_fail; 296 }; 297 298 struct struct_ulptx_la { 299 u32 rdptr[CUDBG_NUM_ULPTX]; 300 u32 wrptr[CUDBG_NUM_ULPTX]; 301 u32 rddata[CUDBG_NUM_ULPTX]; 302 u32 rd_data[CUDBG_NUM_ULPTX][CUDBG_NUM_ULPTX_READ]; 303 u32 rdptr_asic[CUDBG_NUM_ULPTX_ASIC_READ]; 304 u32 rddata_asic[CUDBG_NUM_ULPTX_ASIC_READ][CUDBG_NUM_ULPTX_ASIC]; 305 }; 306 307 struct struct_ulprx_la { 308 u32 data[ULPRX_LA_SIZE * 8]; 309 u32 size; 310 }; 311 312 struct struct_cim_qcfg { 313 u8 chip; 314 u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 315 u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 316 u16 thres[CIM_NUM_IBQ]; 317 u32 obq_wr[2 * CIM_NUM_OBQ_T5]; 318 u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)]; 319 }; 320 321 enum region_index { 322 REGN_DBQ_CONTEXS_IDX, 323 REGN_IMSG_CONTEXTS_IDX, 324 REGN_FLM_CACHE_IDX, 325 REGN_TCBS_IDX, 326 REGN_PSTRUCT_IDX, 327 REGN_TIMERS_IDX, 328 REGN_RX_FL_IDX, 329 REGN_TX_FL_IDX, 330 REGN_PSTRUCT_FL_IDX, 331 REGN_TX_PAYLOAD_IDX, 332 REGN_RX_PAYLOAD_IDX, 333 REGN_LE_HASH_IDX, 334 REGN_ISCSI_IDX, 335 REGN_TDDP_IDX, 336 REGN_TPT_IDX, 337 REGN_STAG_IDX, 338 REGN_RQ_IDX, 339 REGN_RQUDP_IDX, 340 REGN_PBL_IDX, 341 REGN_TXPBL_IDX, 342 REGN_DBVFIFO_IDX, 343 REGN_ULPRX_STATE_IDX, 344 REGN_ULPTX_STATE_IDX, 345 #ifndef __NO_DRIVER_OCQ_SUPPORT__ 346 REGN_ON_CHIP_Q_IDX, 347 #endif 348 }; 349 350 struct cudbg_qdesc_info { 351 u32 qdesc_entry_size; 352 u32 num_queues; 353 u8 data[0]; /* Must be last */ 354 }; 355 356 static const char * const region[] = { 357 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 358 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 359 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 360 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 361 "RQUDP region:", "PBL region:", "TXPBL region:", 362 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 363 #ifndef __NO_DRIVER_OCQ_SUPPORT__ 364 "On-chip queues:" 365 #endif 366 }; 367 368 /* Info relative to memory region (i.e. wrt 0). */ 369 struct struct_region_info { 370 bool exist; /* Does region exists in current memory region? */ 371 u32 start; /* Start wrt 0 */ 372 u32 end; /* End wrt 0 */ 373 }; 374 375 struct struct_port_usage { 376 u32 id; 377 u32 used; 378 u32 alloc; 379 }; 380 381 struct struct_lpbk_usage { 382 u32 id; 383 u32 used; 384 u32 alloc; 385 }; 386 387 struct struct_mem_desc { 388 u32 base; 389 u32 limit; 390 u32 idx; 391 }; 392 393 enum string_size_units { 394 STRING_UNITS_10, /* use powers of 10^3 (standard SI) */ 395 STRING_UNITS_2, /* use binary powers of 2^10 */ 396 }; 397 398 struct struct_meminfo { 399 struct struct_mem_desc avail[4]; 400 struct struct_mem_desc mem[ARRAY_SIZE(region) + 3]; 401 u32 avail_c; 402 u32 mem_c; 403 u32 up_ram_lo; 404 u32 up_ram_hi; 405 u32 up_extmem2_lo; 406 u32 up_extmem2_hi; 407 u32 rx_pages_data[3]; 408 u32 tx_pages_data[4]; 409 u32 p_structs; 410 struct struct_port_usage port_data[4]; 411 u32 port_used[4]; 412 u32 port_alloc[4]; 413 u32 loopback_used[NCHAN]; 414 u32 loopback_alloc[NCHAN]; 415 u32 pstructs_free_cnt; 416 u32 free_rx_cnt; 417 u32 free_tx_cnt; 418 }; 419 420 #ifndef __GNUC__ 421 #pragma warning(disable : 4200) 422 #endif 423 424 struct struct_lb_stats { 425 int nchan; 426 struct lb_port_stats s[0]; 427 }; 428 429 struct struct_clk_info { 430 u64 retransmit_min; 431 u64 retransmit_max; 432 u64 persist_timer_min; 433 u64 persist_timer_max; 434 u64 keepalive_idle_timer; 435 u64 keepalive_interval; 436 u64 initial_srtt; 437 u64 finwait2_timer; 438 u32 dack_timer; 439 u32 res; 440 u32 cclk_ps; 441 u32 tre; 442 u32 dack_re; 443 char core_clk_period[32]; 444 char tp_timer_tick[32]; 445 char tcp_tstamp_tick[32]; 446 char dack_tick[32]; 447 }; 448 449 struct cim_pif_la { 450 int size; 451 u8 data[0]; 452 }; 453 454 struct struct_tp_la { 455 u32 size; 456 u32 mode; 457 u8 data[0]; 458 }; 459 460 struct field_desc { 461 const char *name; 462 u32 start; 463 u32 width; 464 }; 465 466 struct tp_mib_type { 467 char *key; 468 u32 addr; 469 u32 value; 470 }; 471 472 struct wtp_type_0 { 473 u32 sop; 474 u32 eop; 475 }; 476 477 struct wtp_type_1 { 478 u32 sop[2]; 479 u32 eop[2]; 480 }; 481 482 struct wtp_type_2 { 483 u32 sop[4]; 484 u32 eop[4]; 485 }; 486 487 struct wtp_type_3 { 488 u32 sop[4]; 489 u32 eop[4]; 490 u32 drops; 491 }; 492 493 struct wtp_data { 494 /*TX path, Request Work request sub-path:*/ 495 496 struct wtp_type_1 sge_pcie_cmd_req; /*SGE_DEBUG PC_Req_xOPn*/ 497 struct wtp_type_1 pcie_core_cmd_req; /*PCIE_CMDR_REQ_CNT*/ 498 499 500 /*TX path, Work request to uP sub-path*/ 501 struct wtp_type_1 core_pcie_cmd_rsp; /*PCIE_CMDR_RSP_CNT*/ 502 struct wtp_type_1 pcie_sge_cmd_rsp; /*SGE_DEBUG PC_Rsp_xOPn*/ 503 struct wtp_type_1 sge_cim; /*SGE_DEBUG CIM_xOPn*/ 504 505 /*TX path, Data request path from ULP_TX to core*/ 506 struct wtp_type_2 utx_sge_dma_req; /*SGE UD_Rx_xOPn*/ 507 struct wtp_type_2 sge_pcie_dma_req; /*SGE PD_Req_Rdn (no eops)*/ 508 struct wtp_type_2 pcie_core_dma_req; /*PCIE_DMAR_REQ_CNT (no eops)*/ 509 510 /*Main TX path, from core to wire*/ 511 struct wtp_type_2 core_pcie_dma_rsp; /*PCIE_DMAR_RSP_SOP_CNT/ 512 PCIE_DMAR_EOP_CNT*/ 513 struct wtp_type_2 pcie_sge_dma_rsp; /*SGE_DEBUG PD_Rsp_xOPn*/ 514 struct wtp_type_2 sge_utx; /*SGE_DEBUG U_Tx_xOPn*/ 515 struct wtp_type_2 utx_tp; /*ULP_TX_SE_CNT_CHn[xOP_CNT_ULP2TP]*/ 516 struct wtp_type_2 utx_tpcside; /*TP_DBG_CSIDE_RXn[RxXoPCnt]*/ 517 518 struct wtp_type_2 tpcside_rxpld; 519 struct wtp_type_2 tpcside_rxarb; /*TP_DBG_CSIDE_RXn[RxArbXopCnt]*/ 520 struct wtp_type_2 tpcside_rxcpl; 521 522 struct wtp_type_2 tpeside_mps; /*TP_DBG_ESDIE_PKT0[TxXoPCnt]*/ 523 struct wtp_type_2 tpeside_pm; 524 struct wtp_type_2 tpeside_pld; 525 526 /*Tx path, PCIE t5 DMA stat*/ 527 struct wtp_type_2 pcie_t5_dma_stat3; 528 529 /*Tx path, SGE debug data high index 6*/ 530 struct wtp_type_2 sge_debug_data_high_index_6; 531 532 /*Tx path, SGE debug data high index 3*/ 533 struct wtp_type_2 sge_debug_data_high_index_3; 534 535 /*Tx path, ULP SE CNT CHx*/ 536 struct wtp_type_2 ulp_se_cnt_chx; 537 538 /*pcie cmd stat 2*/ 539 struct wtp_type_2 pcie_cmd_stat2; 540 541 /*pcie cmd stat 3*/ 542 struct wtp_type_2 pcie_cmd_stat3; 543 544 struct wtp_type_2 pcie_dma1_stat2_core; 545 546 struct wtp_type_1 sge_work_req_pkt; 547 548 struct wtp_type_2 sge_debug_data_high_indx5; 549 550 /*Tx path, mac portx pkt count*/ 551 struct wtp_type_2 mac_portx_pkt_count; 552 553 /*Rx path, mac porrx pkt count*/ 554 struct wtp_type_2 mac_porrx_pkt_count; 555 556 /*Rx path, PCIE T5 dma1 stat 2*/ 557 struct wtp_type_2 pcie_dma1_stat2; 558 559 /*Rx path, sge debug data high index 7*/ 560 struct wtp_type_2 sge_debug_data_high_indx7; 561 562 /*Rx path, sge debug data high index 1*/ 563 struct wtp_type_1 sge_debug_data_high_indx1; 564 565 /*Rx path, TP debug CSIDE Tx register*/ 566 struct wtp_type_1 utx_tpcside_tx; 567 568 /*Rx path, LE DB response count*/ 569 struct wtp_type_0 le_db_rsp_cnt; 570 571 /*Rx path, TP debug Eside PKTx*/ 572 struct wtp_type_2 tp_dbg_eside_pktx; 573 574 /*Rx path, sge debug data high index 9*/ 575 struct wtp_type_1 sge_debug_data_high_indx9; 576 577 /*Tx path, mac portx aFramesTransmittesok*/ 578 struct wtp_type_2 mac_portx_aframestra_ok; 579 580 /*Rx path, mac portx aFramesTransmittesok*/ 581 struct wtp_type_2 mac_porrx_aframestra_ok; 582 583 /*Tx path, MAC_PORT_MTIP_1G10G_RX_etherStatsPkts*/ 584 struct wtp_type_1 mac_portx_etherstatspkts; 585 586 /*Rx path, MAC_PORT_MTIP_1G10G_RX_etherStatsPkts*/ 587 struct wtp_type_1 mac_porrx_etherstatspkts; 588 589 struct wtp_type_3 tp_mps; /*MPS_TX_SE_CNT_TP01 and 590 MPS_TX_SE_CNT_TP34*/ 591 struct wtp_type_3 mps_xgm; /*MPS_TX_SE_CNT_MAC01 and 592 MPS_TX_SE_CNT_MAC34*/ 593 struct wtp_type_2 tx_xgm_xgm; /*XGMAC_PORT_PKT_CNT_PORT_n*/ 594 struct wtp_type_2 xgm_wire; /*XGMAC_PORT_XGM_STAT_TX_FRAME_LOW_PORT_N 595 (clear on read)*/ 596 597 /*RX path, from wire to core.*/ 598 struct wtp_type_2 wire_xgm; /*XGMAC_PORT_XGM_STAT_RX_FRAMES_LOW_PORT_N 599 (clear on read)*/ 600 struct wtp_type_2 rx_xgm_xgm; /*XGMAC_PORT_PKT_CNT_PORT_n*/ 601 struct _xgm_mps { /*MPS_RX_SE_CNT_INn*/ 602 u32 sop[8]; /* => undef,*/ 603 u32 eop[8]; /* => undef,*/ 604 u32 drop; /* => undef,*/ 605 u32 cls_drop; /* => undef,*/ 606 u32 err; /* => undef,*/ 607 u32 bp; /* => undef,*/ 608 } xgm_mps; 609 610 struct wtp_type_3 mps_tp; /*MPS_RX_SE_CNT_OUT01 and 611 MPS_RX_SE_CNT_OUT23*/ 612 struct wtp_type_2 mps_tpeside; /*TP_DBG_ESIDE_PKTn*/ 613 struct wtp_type_1 tpeside_pmrx; /*???*/ 614 struct wtp_type_2 pmrx_ulprx; /*ULP_RX_SE_CNT_CHn[xOP_CNT_INn]*/ 615 struct wtp_type_2 ulprx_tpcside; /*ULP_RX_SE_CNT_CHn[xOP_CNT_OUTn]*/ 616 struct wtp_type_2 tpcside_csw; /*TP_DBG_CSIDE_TXn[TxSopCnt]*/ 617 struct wtp_type_2 tpcside_pm; 618 struct wtp_type_2 tpcside_uturn; 619 struct wtp_type_2 tpcside_txcpl; 620 struct wtp_type_1 tp_csw; /*SGE_DEBUG CPLSW_TP_Rx_xOPn*/ 621 struct wtp_type_1 csw_sge; /*SGE_DEBUG T_Rx_xOPn*/ 622 struct wtp_type_2 sge_pcie; /*SGE_DEBUG PD_Req_SopN - 623 PD_Req_RdN - PD_ReqIntN*/ 624 struct wtp_type_2 sge_pcie_ints; /*SGE_DEBUG PD_Req_IntN*/ 625 struct wtp_type_2 pcie_core_dmaw; /*PCIE_DMAW_SOP_CNT and 626 PCIE_DMAW_EOP_CNT*/ 627 struct wtp_type_2 pcie_core_dmai; /*PCIE_DMAI_CNT*/ 628 629 }; 630 631 struct tp_mib_data { 632 struct tp_mib_type TP_MIB_MAC_IN_ERR_0; 633 struct tp_mib_type TP_MIB_MAC_IN_ERR_1; 634 struct tp_mib_type TP_MIB_MAC_IN_ERR_2; 635 struct tp_mib_type TP_MIB_MAC_IN_ERR_3; 636 struct tp_mib_type TP_MIB_HDR_IN_ERR_0; 637 struct tp_mib_type TP_MIB_HDR_IN_ERR_1; 638 struct tp_mib_type TP_MIB_HDR_IN_ERR_2; 639 struct tp_mib_type TP_MIB_HDR_IN_ERR_3; 640 struct tp_mib_type TP_MIB_TCP_IN_ERR_0; 641 struct tp_mib_type TP_MIB_TCP_IN_ERR_1; 642 struct tp_mib_type TP_MIB_TCP_IN_ERR_2; 643 struct tp_mib_type TP_MIB_TCP_IN_ERR_3; 644 struct tp_mib_type TP_MIB_TCP_OUT_RST; 645 struct tp_mib_type TP_MIB_TCP_IN_SEG_HI; 646 struct tp_mib_type TP_MIB_TCP_IN_SEG_LO; 647 struct tp_mib_type TP_MIB_TCP_OUT_SEG_HI; 648 struct tp_mib_type TP_MIB_TCP_OUT_SEG_LO; 649 struct tp_mib_type TP_MIB_TCP_RXT_SEG_HI; 650 struct tp_mib_type TP_MIB_TCP_RXT_SEG_LO; 651 struct tp_mib_type TP_MIB_TNL_CNG_DROP_0; 652 struct tp_mib_type TP_MIB_TNL_CNG_DROP_1; 653 struct tp_mib_type TP_MIB_TNL_CNG_DROP_2; 654 struct tp_mib_type TP_MIB_TNL_CNG_DROP_3; 655 struct tp_mib_type TP_MIB_OFD_CHN_DROP_0; 656 struct tp_mib_type TP_MIB_OFD_CHN_DROP_1; 657 struct tp_mib_type TP_MIB_OFD_CHN_DROP_2; 658 struct tp_mib_type TP_MIB_OFD_CHN_DROP_3; 659 struct tp_mib_type TP_MIB_TNL_OUT_PKT_0; 660 struct tp_mib_type TP_MIB_TNL_OUT_PKT_1; 661 struct tp_mib_type TP_MIB_TNL_OUT_PKT_2; 662 struct tp_mib_type TP_MIB_TNL_OUT_PKT_3; 663 struct tp_mib_type TP_MIB_TNL_IN_PKT_0; 664 struct tp_mib_type TP_MIB_TNL_IN_PKT_1; 665 struct tp_mib_type TP_MIB_TNL_IN_PKT_2; 666 struct tp_mib_type TP_MIB_TNL_IN_PKT_3; 667 struct tp_mib_type TP_MIB_TCP_V6IN_ERR_0; 668 struct tp_mib_type TP_MIB_TCP_V6IN_ERR_1; 669 struct tp_mib_type TP_MIB_TCP_V6IN_ERR_2; 670 struct tp_mib_type TP_MIB_TCP_V6IN_ERR_3; 671 struct tp_mib_type TP_MIB_TCP_V6OUT_RST; 672 struct tp_mib_type TP_MIB_TCP_V6IN_SEG_HI; 673 struct tp_mib_type TP_MIB_TCP_V6IN_SEG_LO; 674 struct tp_mib_type TP_MIB_TCP_V6OUT_SEG_HI; 675 struct tp_mib_type TP_MIB_TCP_V6OUT_SEG_LO; 676 struct tp_mib_type TP_MIB_TCP_V6RXT_SEG_HI; 677 struct tp_mib_type TP_MIB_TCP_V6RXT_SEG_LO; 678 struct tp_mib_type TP_MIB_OFD_ARP_DROP; 679 struct tp_mib_type TP_MIB_OFD_DFR_DROP; 680 struct tp_mib_type TP_MIB_CPL_IN_REQ_0; 681 struct tp_mib_type TP_MIB_CPL_IN_REQ_1; 682 struct tp_mib_type TP_MIB_CPL_IN_REQ_2; 683 struct tp_mib_type TP_MIB_CPL_IN_REQ_3; 684 struct tp_mib_type TP_MIB_CPL_OUT_RSP_0; 685 struct tp_mib_type TP_MIB_CPL_OUT_RSP_1; 686 struct tp_mib_type TP_MIB_CPL_OUT_RSP_2; 687 struct tp_mib_type TP_MIB_CPL_OUT_RSP_3; 688 struct tp_mib_type TP_MIB_TNL_LPBK_0; 689 struct tp_mib_type TP_MIB_TNL_LPBK_1; 690 struct tp_mib_type TP_MIB_TNL_LPBK_2; 691 struct tp_mib_type TP_MIB_TNL_LPBK_3; 692 struct tp_mib_type TP_MIB_TNL_DROP_0; 693 struct tp_mib_type TP_MIB_TNL_DROP_1; 694 struct tp_mib_type TP_MIB_TNL_DROP_2; 695 struct tp_mib_type TP_MIB_TNL_DROP_3; 696 struct tp_mib_type TP_MIB_FCOE_DDP_0; 697 struct tp_mib_type TP_MIB_FCOE_DDP_1; 698 struct tp_mib_type TP_MIB_FCOE_DDP_2; 699 struct tp_mib_type TP_MIB_FCOE_DDP_3; 700 struct tp_mib_type TP_MIB_FCOE_DROP_0; 701 struct tp_mib_type TP_MIB_FCOE_DROP_1; 702 struct tp_mib_type TP_MIB_FCOE_DROP_2; 703 struct tp_mib_type TP_MIB_FCOE_DROP_3; 704 struct tp_mib_type TP_MIB_FCOE_BYTE_0_HI; 705 struct tp_mib_type TP_MIB_FCOE_BYTE_0_LO; 706 struct tp_mib_type TP_MIB_FCOE_BYTE_1_HI; 707 struct tp_mib_type TP_MIB_FCOE_BYTE_1_LO; 708 struct tp_mib_type TP_MIB_FCOE_BYTE_2_HI; 709 struct tp_mib_type TP_MIB_FCOE_BYTE_2_LO; 710 struct tp_mib_type TP_MIB_FCOE_BYTE_3_HI; 711 struct tp_mib_type TP_MIB_FCOE_BYTE_3_LO; 712 struct tp_mib_type TP_MIB_OFD_VLN_DROP_0; 713 struct tp_mib_type TP_MIB_OFD_VLN_DROP_1; 714 struct tp_mib_type TP_MIB_OFD_VLN_DROP_2; 715 struct tp_mib_type TP_MIB_OFD_VLN_DROP_3; 716 struct tp_mib_type TP_MIB_USM_PKTS; 717 struct tp_mib_type TP_MIB_USM_DROP; 718 struct tp_mib_type TP_MIB_USM_BYTES_HI; 719 struct tp_mib_type TP_MIB_USM_BYTES_LO; 720 struct tp_mib_type TP_MIB_TID_DEL; 721 struct tp_mib_type TP_MIB_TID_INV; 722 struct tp_mib_type TP_MIB_TID_ACT; 723 struct tp_mib_type TP_MIB_TID_PAS; 724 struct tp_mib_type TP_MIB_RQE_DFR_MOD; 725 struct tp_mib_type TP_MIB_RQE_DFR_PKT; 726 }; 727 728 struct cudbg_reg_info { 729 const char *name; 730 unsigned int addr; 731 unsigned int len; 732 }; 733 734 struct tp1_reg_info { 735 char addr[10]; 736 char name[40]; 737 }; 738 739 struct ireg_field { 740 u32 ireg_addr; 741 u32 ireg_data; 742 u32 ireg_local_offset; 743 u32 ireg_offset_range; 744 }; 745 746 struct ireg_buf { 747 struct ireg_field tp_pio; 748 u32 outbuf[32]; 749 }; 750 751 struct tx_rate { 752 u64 nrate[NCHAN]; 753 u64 orate[NCHAN]; 754 u32 nchan; 755 }; 756 757 struct tid_info_region { 758 u32 ntids; 759 u32 nstids; 760 u32 stid_base; 761 u32 hash_base; 762 763 u32 natids; 764 u32 nftids; 765 u32 ftid_base; 766 u32 aftid_base; 767 u32 aftid_end; 768 769 /* Server filter region */ 770 u32 sftid_base; 771 u32 nsftids; 772 773 /* UO context range */ 774 u32 uotid_base; 775 u32 nuotids; 776 777 u32 sb; 778 u32 flags; 779 u32 le_db_conf; 780 u32 IP_users; 781 u32 IPv6_users; 782 783 u32 hpftid_base; 784 u32 nhpftids; 785 }; 786 787 struct tid_info_region_rev1 { 788 struct cudbg_ver_hdr ver_hdr; 789 struct tid_info_region tid; 790 u32 tid_start; 791 u32 reserved[16]; 792 }; 793 794 struct struct_vpd_data { 795 u8 sn[SN_MAX_LEN + 1]; 796 u8 bn[BN_MAX_LEN + 1]; 797 u8 na[NA_MAX_LEN + 1]; 798 u8 mn[MN_MAX_LEN + 1]; 799 u16 fw_major; 800 u16 fw_minor; 801 u16 fw_micro; 802 u16 fw_build; 803 u32 scfg_vers; 804 u32 vpd_vers; 805 }; 806 807 struct sw_state { 808 u32 fw_state; 809 u8 caller_string[100]; 810 u8 os_type; 811 u8 reserved[3]; 812 u32 reserved1[16]; 813 }; 814 815 struct sge_qbase_reg_field { 816 u32 reg_addr; 817 u32 reg_data[4]; 818 u32 pf_data_value[8][4]; /* [max pf][4 data reg SGE_QBASE_MAP[0-3] */ 819 u32 vf_data_value[256][4]; /* [max vf][4 data reg SGE_QBASE_MAP[0-3] */ 820 u32 vfcount; 821 }; 822 823 struct cudbg_qdesc_entry { 824 u32 data_size; 825 u32 qtype; 826 u32 qid; 827 u32 desc_size; 828 u32 num_desc; 829 u8 data[0]; /* Must be last */ 830 }; 831 832 static u32 ATTRIBUTE_UNUSED t6_tp_pio_array[][4] = { 833 {0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */ 834 {0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */ 835 {0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */ 836 {0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */ 837 {0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */ 838 {0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */ 839 {0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */ 840 {0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */ 841 {0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */ 842 {0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */ 843 {0x7e40, 0x7e44, 0x24a, 3}, /* t6_tp_pio_regs_24c */ 844 {0x7e40, 0x7e44, 0x8C0, 1} /* t6_tp_pio_regs_8c0 */ 845 }; 846 847 static u32 ATTRIBUTE_UNUSED t5_tp_pio_array[][4] = { 848 {0x7e40, 0x7e44, 0x020, 28}, /* t5_tp_pio_regs_20_to_3b */ 849 {0x7e40, 0x7e44, 0x040, 19}, /* t5_tp_pio_regs_40_to_52 */ 850 {0x7e40, 0x7e44, 0x054, 2}, /* t5_tp_pio_regs_54_to_55 */ 851 {0x7e40, 0x7e44, 0x060, 13}, /* t5_tp_pio_regs_60_to_6c */ 852 {0x7e40, 0x7e44, 0x06F, 1}, /* t5_tp_pio_regs_6f */ 853 {0x7e40, 0x7e44, 0x120, 4}, /* t5_tp_pio_regs_120_to_123 */ 854 {0x7e40, 0x7e44, 0x12b, 2}, /* t5_tp_pio_regs_12b_to_12c */ 855 {0x7e40, 0x7e44, 0x12f, 21}, /* t5_tp_pio_regs_12f_to_143 */ 856 {0x7e40, 0x7e44, 0x145, 19}, /* t5_tp_pio_regs_145_to_157 */ 857 {0x7e40, 0x7e44, 0x230, 25}, /* t5_tp_pio_regs_230_to_248 */ 858 {0x7e40, 0x7e44, 0x8C0, 1} /* t5_tp_pio_regs_8c0 */ 859 }; 860 861 static u32 ATTRIBUTE_UNUSED t6_ma_ireg_array[][4] = { 862 {0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */ 863 {0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */ 864 {0x78f8, 0x78fc, 0xa800, 20} /* t6_ma_regs_a800_to_a813 */ 865 }; 866 867 static u32 ATTRIBUTE_UNUSED t6_ma_ireg_array2[][4] = { 868 {0x78f8, 0x78fc, 0xe400, 17}, /* t6_ma_regs_e400_to_e600 */ 869 {0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */ 870 }; 871 872 static u32 ATTRIBUTE_UNUSED t6_hma_ireg_array[][4] = { 873 {0x51320, 0x51324, 0xa000, 32} /* t6_hma_regs_a000_to_a01f */ 874 }; 875 static u32 ATTRIBUTE_UNUSED t5_pcie_pdbg_array[][4] = { 876 {0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */ 877 {0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */ 878 {0x5a04, 0x5a0c, 0x41, 0x10}, /* t5_pcie_pdbg_regs_41_to_50 */ 879 }; 880 881 static u32 ATTRIBUTE_UNUSED t5_pcie_config_array[][2] = { 882 {0x0, 0x34}, 883 {0x3c, 0x40}, 884 {0x50, 0x64}, 885 {0x70, 0x80}, 886 {0x94, 0xa0}, 887 {0xb0, 0xb8}, 888 {0xd0, 0xd4}, 889 {0x100, 0x128}, 890 {0x140, 0x148}, 891 {0x150, 0x164}, 892 {0x170, 0x178}, 893 {0x180, 0x194}, 894 {0x1a0, 0x1b8}, 895 {0x1c0, 0x208}, 896 }; 897 898 static u32 ATTRIBUTE_UNUSED t5_pcie_cdbg_array[][4] = { 899 {0x5a10, 0x5a18, 0x00, 0x20}, /* t5_pcie_cdbg_regs_00_to_20 */ 900 {0x5a10, 0x5a18, 0x21, 0x18}, /* t5_pcie_cdbg_regs_21_to_37 */ 901 }; 902 903 static u32 ATTRIBUTE_UNUSED t6_tp_tm_pio_array[1][4] = { 904 {0x7e18, 0x7e1c, 0x0, 12} 905 }; 906 907 static u32 ATTRIBUTE_UNUSED t5_tp_tm_pio_array[1][4] = { 908 {0x7e18, 0x7e1c, 0x0, 12} 909 }; 910 911 static u32 ATTRIBUTE_UNUSED t5_pm_rx_array[][4] = { 912 {0x8FD0, 0x8FD4, 0x10000, 0x20}, /* t5_pm_rx_regs_10000_to_10020 */ 913 {0x8FD0, 0x8FD4, 0x10021, 0x0D}, /* t5_pm_rx_regs_10021_to_1002c */ 914 }; 915 916 static u32 ATTRIBUTE_UNUSED t5_pm_tx_array[][4] = { 917 {0x8FF0, 0x8FF4, 0x10000, 0x20}, /* t5_pm_tx_regs_10000_to_10020 */ 918 {0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */ 919 }; 920 921 static u32 ATTRIBUTE_UNUSED t6_tp_mib_index_array[6][4] = { 922 {0x7e50, 0x7e54, 0x0, 13}, 923 {0x7e50, 0x7e54, 0x10, 6}, 924 {0x7e50, 0x7e54, 0x18, 21}, 925 {0x7e50, 0x7e54, 0x30, 32}, 926 {0x7e50, 0x7e54, 0x50, 22}, 927 {0x7e50, 0x7e54, 0x68, 12} 928 }; 929 930 static u32 ATTRIBUTE_UNUSED t5_tp_mib_index_array[9][4] = { 931 {0x7e50, 0x7e54, 0x0, 13}, 932 {0x7e50, 0x7e54, 0x10, 6}, 933 {0x7e50, 0x7e54, 0x18, 8}, 934 {0x7e50, 0x7e54, 0x20, 13}, 935 {0x7e50, 0x7e54, 0x30, 16}, 936 {0x7e50, 0x7e54, 0x40, 16}, 937 {0x7e50, 0x7e54, 0x50, 16}, 938 {0x7e50, 0x7e54, 0x60, 6}, 939 {0x7e50, 0x7e54, 0x68, 4} 940 }; 941 942 static u32 ATTRIBUTE_UNUSED t5_sge_dbg_index_array[9][4] = { 943 {0x10cc, 0x10d0, 0x0, 16}, 944 {0x10cc, 0x10d4, 0x0, 16}, 945 }; 946 947 static u32 ATTRIBUTE_UNUSED t6_up_cim_reg_array[][4] = { 948 {0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */ 949 {0x7b50, 0x7b54, 0x2080, 0x1d}, /* up_cim_2080_to_20fc */ 950 {0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */ 951 {0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */ 952 {0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */ 953 {0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */ 954 {0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */ 955 {0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */ 956 {0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */ 957 {0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */ 958 {0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */ 959 {0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */ 960 {0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */ 961 962 }; 963 964 static u32 ATTRIBUTE_UNUSED t5_up_cim_reg_array[][4] = { 965 {0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */ 966 {0x7b50, 0x7b54, 0x2080, 0x19}, /* up_cim_2080_to_20ec */ 967 {0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */ 968 {0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */ 969 {0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */ 970 {0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */ 971 {0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */ 972 {0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */ 973 {0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */ 974 {0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */ 975 {0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */ 976 {0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */ 977 {0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */ 978 }; 979 980 #endif 981