| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1509 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine() local
1525 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 623 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedBits() local
639 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedBits() local
654 TargetLoweringOpt &TLO, in SimplifyDemandedBits()
955 TargetLowering::TargetLoweringOpt &TLO, in combineShiftToAVG()
1103 const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, in SimplifyDemandedBits()
2979 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedVectorElts() local
3043 APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth, in SimplifyDemandedVectorElts()
3781 TargetLoweringOpt &TLO, unsigned Depth) const { in SimplifyDemandedVectorEltsForTargetNode()
3793 KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const { in SimplifyDemandedBitsForTargetNode()
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| H A D | DAGCombiner.cpp | 930 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { in CommitTargetLoweringOpt()
1360 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { in CommitTargetLoweringOpt()
1381 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); in SimplifyDemandedBits() local
1400 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); in SimplifyDemandedVectorElts() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 3979 TargetLoweringOpt &TLO) const { in targetShrinkDemandedConstant()
4076 const TargetLoweringOpt &TLO) const { in shouldSimplifyDemandedVectorElts()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 5230 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 2169 TargetLowering::TargetLoweringOpt &TLO, in optimizeLogicalImm()
22547 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in performTBISimplification() local
28388 const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, in SimplifyDemandedBitsForTargetNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 41817 TargetLowering::TargetLoweringOpt &TLO, unsigned Depth) const { in SimplifyDemandedVectorEltsForTargetShuffle()
41884 TargetLoweringOpt &TLO, unsigned Depth) const { in SimplifyDemandedVectorEltsForTargetNode()
42651 const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, in SimplifyDemandedBitsForTargetNode()
45729 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in combineVSelectToBLENDV() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 20279 const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, in SimplifyDemandedBitsForTargetNode()
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