1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
5 * Copyright (c) 2014 Luiz Otavio O Souza <loos@freebsd.org>.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /**
31 * Driver for the I2C module on the TI SoC.
32 *
33 * This driver is heavily based on the TWI driver for the AT91 (at91_twi.c).
34 *
35 * CAUTION: The I2Ci registers are limited to 16 bit and 8 bit data accesses,
36 * 32 bit data access is not allowed and can corrupt register content.
37 *
38 * This driver currently doesn't use DMA for the transfer, although I hope to
39 * incorporate that sometime in the future. The idea being that for transaction
40 * larger than a certain size the DMA engine is used, for anything less the
41 * normal interrupt/fifo driven option is used.
42 */
43
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/bus.h>
47 #include <sys/conf.h>
48 #include <sys/kernel.h>
49 #include <sys/lock.h>
50 #include <sys/mbuf.h>
51 #include <sys/malloc.h>
52 #include <sys/module.h>
53 #include <sys/mutex.h>
54 #include <sys/rman.h>
55 #include <sys/sysctl.h>
56 #include <machine/bus.h>
57
58 #include <dev/ofw/openfirm.h>
59 #include <dev/ofw/ofw_bus.h>
60 #include <dev/ofw/ofw_bus_subr.h>
61
62 #include <arm/ti/ti_cpuid.h>
63 #include <arm/ti/ti_sysc.h>
64 #include <arm/ti/ti_i2c.h>
65
66 #include <dev/iicbus/iiconf.h>
67 #include <dev/iicbus/iicbus.h>
68
69 #include "iicbus_if.h"
70
71 /**
72 * I2C device driver context, a pointer to this is stored in the device
73 * driver structure.
74 */
75 struct ti_i2c_softc
76 {
77 device_t sc_dev;
78 struct resource* sc_irq_res;
79 struct resource* sc_mem_res;
80 device_t sc_iicbus;
81
82 void* sc_irq_h;
83
84 struct mtx sc_mtx;
85
86 struct iic_msg* sc_buffer;
87 int sc_bus_inuse;
88 int sc_buffer_pos;
89 int sc_error;
90 int sc_fifo_trsh;
91 int sc_timeout;
92
93 uint16_t sc_con_reg;
94 uint16_t sc_rev;
95 };
96
97 struct ti_i2c_clock_config
98 {
99 u_int frequency; /* Bus frequency in Hz */
100 uint8_t psc; /* Fast/Standard mode prescale divider */
101 uint8_t scll; /* Fast/Standard mode SCL low time */
102 uint8_t sclh; /* Fast/Standard mode SCL high time */
103 uint8_t hsscll; /* High Speed mode SCL low time */
104 uint8_t hssclh; /* High Speed mode SCL high time */
105 };
106
107 #if defined(SOC_OMAP4)
108 /*
109 * OMAP4 i2c bus clock is 96MHz / ((psc + 1) * (scll + 7 + sclh + 5)).
110 * The prescaler values for 100KHz and 400KHz modes come from the table in the
111 * OMAP4 TRM. The table doesn't list 1MHz; these values should give that speed.
112 */
113 static struct ti_i2c_clock_config ti_omap4_i2c_clock_configs[] = {
114 { 100000, 23, 13, 15, 0, 0},
115 { 400000, 9, 5, 7, 0, 0},
116 { 1000000, 3, 5, 7, 0, 0},
117 /* { 3200000, 1, 113, 115, 7, 10}, - HS mode */
118 { 0 /* Table terminator */ }
119 };
120 #endif
121
122 #if defined(SOC_TI_AM335X)
123 /*
124 * AM335x i2c bus clock is 48MHZ / ((psc + 1) * (scll + 7 + sclh + 5))
125 * In all cases we prescale the clock to 24MHz as recommended in the manual.
126 */
127 static struct ti_i2c_clock_config ti_am335x_i2c_clock_configs[] = {
128 { 100000, 1, 111, 117, 0, 0},
129 { 400000, 1, 23, 25, 0, 0},
130 { 1000000, 1, 5, 7, 0, 0},
131 { 0 /* Table terminator */ }
132 };
133 #endif
134
135 /**
136 * Locking macros used throughout the driver
137 */
138 #define TI_I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
139 #define TI_I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
140 #define TI_I2C_LOCK_INIT(_sc) \
141 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
142 "ti_i2c", MTX_DEF)
143 #define TI_I2C_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx)
144 #define TI_I2C_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
145 #define TI_I2C_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED)
146
147 #ifdef DEBUG
148 #define ti_i2c_dbg(_sc, fmt, args...) \
149 device_printf((_sc)->sc_dev, fmt, ##args)
150 #else
151 #define ti_i2c_dbg(_sc, fmt, args...)
152 #endif
153
154 /**
155 * ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers
156 * @sc: I2C device context
157 * @off: the byte offset within the register bank to read from.
158 *
159 *
160 * LOCKING:
161 * No locking required
162 *
163 * RETURNS:
164 * 16-bit value read from the register.
165 */
166 static inline uint16_t
ti_i2c_read_2(struct ti_i2c_softc * sc,bus_size_t off)167 ti_i2c_read_2(struct ti_i2c_softc *sc, bus_size_t off)
168 {
169
170 return (bus_read_2(sc->sc_mem_res, off));
171 }
172
173 /**
174 * ti_i2c_write_2 - writes a 16-bit value to one of the I2C registers
175 * @sc: I2C device context
176 * @off: the byte offset within the register bank to read from.
177 * @val: the value to write into the register
178 *
179 * LOCKING:
180 * No locking required
181 *
182 * RETURNS:
183 * 16-bit value read from the register.
184 */
185 static inline void
ti_i2c_write_2(struct ti_i2c_softc * sc,bus_size_t off,uint16_t val)186 ti_i2c_write_2(struct ti_i2c_softc *sc, bus_size_t off, uint16_t val)
187 {
188
189 bus_write_2(sc->sc_mem_res, off, val);
190 }
191
192 static int
ti_i2c_transfer_intr(struct ti_i2c_softc * sc,uint16_t status)193 ti_i2c_transfer_intr(struct ti_i2c_softc* sc, uint16_t status)
194 {
195 int amount, done, i;
196
197 done = 0;
198 amount = 0;
199 /* Check for the error conditions. */
200 if (status & I2C_STAT_NACK) {
201 /* No ACK from slave. */
202 ti_i2c_dbg(sc, "NACK\n");
203 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_NACK);
204 sc->sc_error = ENXIO;
205 } else if (status & I2C_STAT_AL) {
206 /* Arbitration lost. */
207 ti_i2c_dbg(sc, "Arbitration lost\n");
208 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_AL);
209 sc->sc_error = ENXIO;
210 }
211
212 /* Check if we have finished. */
213 if (status & I2C_STAT_ARDY) {
214 /* Register access ready - transaction complete basically. */
215 ti_i2c_dbg(sc, "ARDY transaction complete\n");
216 if (sc->sc_error != 0 && sc->sc_buffer->flags & IIC_M_NOSTOP) {
217 ti_i2c_write_2(sc, I2C_REG_CON,
218 sc->sc_con_reg | I2C_CON_STP);
219 }
220 ti_i2c_write_2(sc, I2C_REG_STATUS,
221 I2C_STAT_ARDY | I2C_STAT_RDR | I2C_STAT_RRDY |
222 I2C_STAT_XDR | I2C_STAT_XRDY);
223 return (1);
224 }
225
226 if (sc->sc_buffer->flags & IIC_M_RD) {
227 /* Read some data. */
228 if (status & I2C_STAT_RDR) {
229 /*
230 * Receive draining interrupt - last data received.
231 * The set FIFO threshold won't be reached to trigger
232 * RRDY.
233 */
234 ti_i2c_dbg(sc, "Receive draining interrupt\n");
235
236 /*
237 * Drain the FIFO. Read the pending data in the FIFO.
238 */
239 amount = sc->sc_buffer->len - sc->sc_buffer_pos;
240 } else if (status & I2C_STAT_RRDY) {
241 /*
242 * Receive data ready interrupt - FIFO has reached the
243 * set threshold.
244 */
245 ti_i2c_dbg(sc, "Receive data ready interrupt\n");
246
247 amount = min(sc->sc_fifo_trsh,
248 sc->sc_buffer->len - sc->sc_buffer_pos);
249 }
250
251 /* Read the bytes from the fifo. */
252 for (i = 0; i < amount; i++)
253 sc->sc_buffer->buf[sc->sc_buffer_pos++] =
254 (uint8_t)(ti_i2c_read_2(sc, I2C_REG_DATA) & 0xff);
255
256 if (status & I2C_STAT_RDR)
257 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RDR);
258 if (status & I2C_STAT_RRDY)
259 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RRDY);
260
261 } else {
262 /* Write some data. */
263 if (status & I2C_STAT_XDR) {
264 /*
265 * Transmit draining interrupt - FIFO level is below
266 * the set threshold and the amount of data still to
267 * be transferred won't reach the set FIFO threshold.
268 */
269 ti_i2c_dbg(sc, "Transmit draining interrupt\n");
270
271 /*
272 * Drain the TX data. Write the pending data in the
273 * FIFO.
274 */
275 amount = sc->sc_buffer->len - sc->sc_buffer_pos;
276 } else if (status & I2C_STAT_XRDY) {
277 /*
278 * Transmit data ready interrupt - the FIFO level
279 * is below the set threshold.
280 */
281 ti_i2c_dbg(sc, "Transmit data ready interrupt\n");
282
283 amount = min(sc->sc_fifo_trsh,
284 sc->sc_buffer->len - sc->sc_buffer_pos);
285 }
286
287 /* Write the bytes from the fifo. */
288 for (i = 0; i < amount; i++)
289 ti_i2c_write_2(sc, I2C_REG_DATA,
290 sc->sc_buffer->buf[sc->sc_buffer_pos++]);
291
292 if (status & I2C_STAT_XDR)
293 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XDR);
294 if (status & I2C_STAT_XRDY)
295 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XRDY);
296 }
297
298 return (done);
299 }
300
301 /**
302 * ti_i2c_intr - interrupt handler for the I2C module
303 * @dev: i2c device handle
304 *
305 *
306 *
307 * LOCKING:
308 * Called from timer context
309 *
310 * RETURNS:
311 * EH_HANDLED or EH_NOT_HANDLED
312 */
313 static void
ti_i2c_intr(void * arg)314 ti_i2c_intr(void *arg)
315 {
316 int done;
317 struct ti_i2c_softc *sc;
318 uint16_t events, status;
319
320 sc = (struct ti_i2c_softc *)arg;
321
322 TI_I2C_LOCK(sc);
323
324 status = ti_i2c_read_2(sc, I2C_REG_STATUS);
325 if (status == 0) {
326 TI_I2C_UNLOCK(sc);
327 return;
328 }
329
330 /* Save enabled interrupts. */
331 events = ti_i2c_read_2(sc, I2C_REG_IRQENABLE_SET);
332
333 /* We only care about enabled interrupts. */
334 status &= events;
335
336 done = 0;
337
338 if (sc->sc_buffer != NULL)
339 done = ti_i2c_transfer_intr(sc, status);
340 else {
341 ti_i2c_dbg(sc, "Transfer interrupt without buffer\n");
342 sc->sc_error = EINVAL;
343 done = 1;
344 }
345
346 if (done)
347 /* Wakeup the process that started the transaction. */
348 wakeup(sc);
349
350 TI_I2C_UNLOCK(sc);
351 }
352
353 /**
354 * ti_i2c_transfer - called to perform the transfer
355 * @dev: i2c device handle
356 * @msgs: the messages to send/receive
357 * @nmsgs: the number of messages in the msgs array
358 *
359 *
360 * LOCKING:
361 * Internally locked
362 *
363 * RETURNS:
364 * 0 on function succeeded
365 * EINVAL if invalid message is passed as an arg
366 */
367 static int
ti_i2c_transfer(device_t dev,struct iic_msg * msgs,uint32_t nmsgs)368 ti_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
369 {
370 int err, i, repstart, timeout;
371 struct ti_i2c_softc *sc;
372 uint16_t reg;
373
374 sc = device_get_softc(dev);
375 TI_I2C_LOCK(sc);
376
377 /* If the controller is busy wait until it is available. */
378 while (sc->sc_bus_inuse == 1)
379 mtx_sleep(sc, &sc->sc_mtx, 0, "i2cbuswait", 0);
380
381 /* Now we have control over the I2C controller. */
382 sc->sc_bus_inuse = 1;
383
384 err = 0;
385 repstart = 0;
386 for (i = 0; i < nmsgs; i++) {
387 sc->sc_buffer = &msgs[i];
388 sc->sc_buffer_pos = 0;
389 sc->sc_error = 0;
390
391 /* Zero byte transfers aren't allowed. */
392 if (sc->sc_buffer == NULL || sc->sc_buffer->buf == NULL ||
393 sc->sc_buffer->len == 0) {
394 err = EINVAL;
395 break;
396 }
397
398 /* Check if the i2c bus is free. */
399 if (repstart == 0) {
400 /*
401 * On repeated start we send the START condition while
402 * the bus _is_ busy.
403 */
404 timeout = 0;
405 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) {
406 if (timeout++ > 100) {
407 err = EBUSY;
408 goto out;
409 }
410 DELAY(1000);
411 }
412 timeout = 0;
413 } else
414 repstart = 0;
415
416 if (sc->sc_buffer->flags & IIC_M_NOSTOP)
417 repstart = 1;
418
419 /* Set the slave address. */
420 ti_i2c_write_2(sc, I2C_REG_SA, msgs[i].slave >> 1);
421
422 /* Write the data length. */
423 ti_i2c_write_2(sc, I2C_REG_CNT, sc->sc_buffer->len);
424
425 /* Clear the RX and the TX FIFO. */
426 reg = ti_i2c_read_2(sc, I2C_REG_BUF);
427 reg |= I2C_BUF_RXFIFO_CLR | I2C_BUF_TXFIFO_CLR;
428 ti_i2c_write_2(sc, I2C_REG_BUF, reg);
429
430 reg = sc->sc_con_reg | I2C_CON_STT;
431 if (repstart == 0)
432 reg |= I2C_CON_STP;
433 if ((sc->sc_buffer->flags & IIC_M_RD) == 0)
434 reg |= I2C_CON_TRX;
435 ti_i2c_write_2(sc, I2C_REG_CON, reg);
436
437 /* Wait for an event. */
438 err = mtx_sleep(sc, &sc->sc_mtx, 0, "i2ciowait", sc->sc_timeout);
439 if (err == 0)
440 err = sc->sc_error;
441
442 if (err)
443 break;
444 }
445
446 out:
447 if (timeout == 0) {
448 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) {
449 if (timeout++ > 100)
450 break;
451 DELAY(1000);
452 }
453 }
454 /* Put the controller in master mode again. */
455 if ((ti_i2c_read_2(sc, I2C_REG_CON) & I2C_CON_MST) == 0)
456 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
457
458 sc->sc_buffer = NULL;
459 sc->sc_bus_inuse = 0;
460
461 /* Wake up the processes that are waiting for the bus. */
462 wakeup(sc);
463
464 TI_I2C_UNLOCK(sc);
465
466 return (err);
467 }
468
469 static int
ti_i2c_reset(struct ti_i2c_softc * sc,u_char speed)470 ti_i2c_reset(struct ti_i2c_softc *sc, u_char speed)
471 {
472 int timeout;
473 struct ti_i2c_clock_config *clkcfg;
474 u_int busfreq;
475 uint16_t fifo_trsh, reg, scll, sclh;
476
477 switch (ti_chip()) {
478 #ifdef SOC_OMAP4
479 case CHIP_OMAP_4:
480 clkcfg = ti_omap4_i2c_clock_configs;
481 break;
482 #endif
483 #ifdef SOC_TI_AM335X
484 case CHIP_AM335X:
485 clkcfg = ti_am335x_i2c_clock_configs;
486 break;
487 #endif
488 default:
489 panic("Unknown TI SoC, unable to reset the i2c");
490 }
491
492 /*
493 * If we haven't attached the bus yet, just init at the default slow
494 * speed. This lets us get the hardware initialized enough to attach
495 * the bus which is where the real speed configuration is handled. After
496 * the bus is attached, get the configured speed from it. Search the
497 * configuration table for the best speed we can do that doesn't exceed
498 * the requested speed.
499 */
500 if (sc->sc_iicbus == NULL)
501 busfreq = 100000;
502 else
503 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
504 for (;;) {
505 if (clkcfg[1].frequency == 0 || clkcfg[1].frequency > busfreq)
506 break;
507 clkcfg++;
508 }
509
510 /*
511 * 23.1.4.3 - HS I2C Software Reset
512 * From OMAP4 TRM at page 4068.
513 *
514 * 1. Ensure that the module is disabled.
515 */
516 sc->sc_con_reg = 0;
517 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
518
519 /* 2. Issue a softreset to the controller. */
520 bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST);
521
522 /*
523 * 3. Enable the module.
524 * The I2Ci.I2C_SYSS[0] RDONE bit is asserted only after the module
525 * is enabled by setting the I2Ci.I2C_CON[15] I2C_EN bit to 1.
526 */
527 ti_i2c_write_2(sc, I2C_REG_CON, I2C_CON_I2C_EN);
528
529 /* 4. Wait for the software reset to complete. */
530 timeout = 0;
531 while ((ti_i2c_read_2(sc, I2C_REG_SYSS) & I2C_SYSS_RDONE) == 0) {
532 if (timeout++ > 100)
533 return (EBUSY);
534 DELAY(100);
535 }
536
537 /*
538 * Disable the I2C controller once again, now that the reset has
539 * finished.
540 */
541 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
542
543 /*
544 * The following sequence is taken from the OMAP4 TRM at page 4077.
545 *
546 * 1. Enable the functional and interface clocks (see Section
547 * 23.1.5.1.1.1.1). Done at ti_i2c_activate().
548 *
549 * 2. Program the prescaler to obtain an approximately 12MHz internal
550 * sampling clock (I2Ci_INTERNAL_CLK) by programming the
551 * corresponding value in the I2Ci.I2C_PSC[3:0] PSC field.
552 * This value depends on the frequency of the functional clock
553 * (I2Ci_FCLK). Because this frequency is 96MHz, the
554 * I2Ci.I2C_PSC[7:0] PSC field value is 0x7.
555 */
556 ti_i2c_write_2(sc, I2C_REG_PSC, clkcfg->psc);
557
558 /*
559 * 3. Program the I2Ci.I2C_SCLL[7:0] SCLL and I2Ci.I2C_SCLH[7:0] SCLH
560 * bit fields to obtain a bit rate of 100 Kbps, 400 Kbps or 1Mbps.
561 * These values depend on the internal sampling clock frequency
562 * (see Table 23-8).
563 */
564 scll = clkcfg->scll & I2C_SCLL_MASK;
565 sclh = clkcfg->sclh & I2C_SCLH_MASK;
566
567 /*
568 * 4. (Optional) Program the I2Ci.I2C_SCLL[15:8] HSSCLL and
569 * I2Ci.I2C_SCLH[15:8] HSSCLH fields to obtain a bit rate of
570 * 400K bps or 3.4M bps (for the second phase of HS mode). These
571 * values depend on the internal sampling clock frequency (see
572 * Table 23-8).
573 *
574 * 5. (Optional) If a bit rate of 3.4M bps is used and the bus line
575 * capacitance exceeds 45 pF, (see Section 18.4.8, PAD Functional
576 * Multiplexing and Configuration).
577 */
578 switch (ti_chip()) {
579 #ifdef SOC_OMAP4
580 case CHIP_OMAP_4:
581 if ((clkcfg->hsscll + clkcfg->hssclh) > 0) {
582 scll |= clkcfg->hsscll << I2C_HSSCLL_SHIFT;
583 sclh |= clkcfg->hssclh << I2C_HSSCLH_SHIFT;
584 sc->sc_con_reg |= I2C_CON_OPMODE_HS;
585 }
586 break;
587 #endif
588 }
589
590 /* Write the selected bit rate. */
591 ti_i2c_write_2(sc, I2C_REG_SCLL, scll);
592 ti_i2c_write_2(sc, I2C_REG_SCLH, sclh);
593
594 /*
595 * 6. Configure the Own Address of the I2C controller by storing it in
596 * the I2Ci.I2C_OA0 register. Up to four Own Addresses can be
597 * programmed in the I2Ci.I2C_OAi registers (where i = 0, 1, 2, 3)
598 * for each I2C controller.
599 *
600 * Note: For a 10-bit address, set the corresponding expand Own Address
601 * bit in the I2Ci.I2C_CON register.
602 *
603 * Driver currently always in single master mode so ignore this step.
604 */
605
606 /*
607 * 7. Set the TX threshold (in transmitter mode) and the RX threshold
608 * (in receiver mode) by setting the I2Ci.I2C_BUF[5:0]XTRSH field to
609 * (TX threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX
610 * threshold - 1), where the TX and RX thresholds are greater than
611 * or equal to 1.
612 *
613 * The threshold is set to 5 for now.
614 */
615 fifo_trsh = (sc->sc_fifo_trsh - 1) & I2C_BUF_TRSH_MASK;
616 reg = fifo_trsh | (fifo_trsh << I2C_BUF_RXTRSH_SHIFT);
617 ti_i2c_write_2(sc, I2C_REG_BUF, reg);
618
619 /*
620 * 8. Take the I2C controller out of reset by setting the
621 * I2Ci.I2C_CON[15] I2C_EN bit to 1.
622 *
623 * 23.1.5.1.1.1.2 - Initialize the I2C Controller
624 *
625 * To initialize the I2C controller, perform the following steps:
626 *
627 * 1. Configure the I2Ci.I2C_CON register:
628 * . For master or slave mode, set the I2Ci.I2C_CON[10] MST bit
629 * (0: slave, 1: master).
630 * . For transmitter or receiver mode, set the I2Ci.I2C_CON[9] TRX
631 * bit (0: receiver, 1: transmitter).
632 */
633
634 /* Enable the I2C controller in master mode. */
635 sc->sc_con_reg |= I2C_CON_I2C_EN | I2C_CON_MST;
636 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
637
638 /*
639 * 2. If using an interrupt to transmit/receive data, set the
640 * corresponding bit in the I2Ci.I2C_IE register (the I2Ci.I2C_IE[4]
641 * XRDY_IE bit for the transmit interrupt, the I2Ci.I2C_IE[3] RRDY
642 * bit for the receive interrupt).
643 */
644
645 /* Set the interrupts we want to be notified. */
646 reg = I2C_IE_XDR | /* Transmit draining interrupt. */
647 I2C_IE_XRDY | /* Transmit Data Ready interrupt. */
648 I2C_IE_RDR | /* Receive draining interrupt. */
649 I2C_IE_RRDY | /* Receive Data Ready interrupt. */
650 I2C_IE_ARDY | /* Register Access Ready interrupt. */
651 I2C_IE_NACK | /* No Acknowledgment interrupt. */
652 I2C_IE_AL; /* Arbitration lost interrupt. */
653
654 /* Enable the interrupts. */
655 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_SET, reg);
656
657 /*
658 * 3. If using DMA to receive/transmit data, set to 1 the corresponding
659 * bit in the I2Ci.I2C_BUF register (the I2Ci.I2C_BUF[15] RDMA_EN
660 * bit for the receive DMA channel, the I2Ci.I2C_BUF[7] XDMA_EN bit
661 * for the transmit DMA channel).
662 *
663 * Not using DMA for now, so ignore this.
664 */
665
666 return (0);
667 }
668
669 static int
ti_i2c_iicbus_reset(device_t dev,u_char speed,u_char addr,u_char * oldaddr)670 ti_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
671 {
672 struct ti_i2c_softc *sc;
673 int err;
674
675 sc = device_get_softc(dev);
676 TI_I2C_LOCK(sc);
677 err = ti_i2c_reset(sc, speed);
678 TI_I2C_UNLOCK(sc);
679 if (err)
680 return (err);
681
682 return (IIC_ENOADDR);
683 }
684
685 static int
ti_i2c_activate(device_t dev)686 ti_i2c_activate(device_t dev)
687 {
688 int err;
689 struct ti_i2c_softc *sc;
690
691 sc = (struct ti_i2c_softc*)device_get_softc(dev);
692
693 /*
694 * 1. Enable the functional and interface clocks (see Section
695 * 23.1.5.1.1.1.1).
696 */
697 err = ti_sysc_clock_enable(device_get_parent(dev));
698 if (err)
699 return (err);
700
701 return (ti_i2c_reset(sc, IIC_UNKNOWN));
702 }
703
704 /**
705 * ti_i2c_deactivate - deactivates the controller and releases resources
706 * @dev: i2c device handle
707 *
708 *
709 *
710 * LOCKING:
711 * Assumed called in an atomic context.
712 *
713 * RETURNS:
714 * nothing
715 */
716 static void
ti_i2c_deactivate(device_t dev)717 ti_i2c_deactivate(device_t dev)
718 {
719 struct ti_i2c_softc *sc = device_get_softc(dev);
720
721 /* Disable the controller - cancel all transactions. */
722 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_CLR, 0xffff);
723 ti_i2c_write_2(sc, I2C_REG_STATUS, 0xffff);
724 ti_i2c_write_2(sc, I2C_REG_CON, 0);
725
726 /* Release the interrupt handler. */
727 if (sc->sc_irq_h != NULL) {
728 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h);
729 sc->sc_irq_h = NULL;
730 }
731
732 /* Unmap the I2C controller registers. */
733 if (sc->sc_mem_res != NULL) {
734 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
735 sc->sc_mem_res = NULL;
736 }
737
738 /* Release the IRQ resource. */
739 if (sc->sc_irq_res != NULL) {
740 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
741 sc->sc_irq_res = NULL;
742 }
743
744 /* Finally disable the functional and interface clocks. */
745 ti_sysc_clock_disable(device_get_parent(dev));
746 }
747
748 static int
ti_i2c_sysctl_clk(SYSCTL_HANDLER_ARGS)749 ti_i2c_sysctl_clk(SYSCTL_HANDLER_ARGS)
750 {
751 int clk, psc, sclh, scll;
752 struct ti_i2c_softc *sc;
753
754 sc = arg1;
755
756 TI_I2C_LOCK(sc);
757 /* Get the system prescaler value. */
758 psc = (int)ti_i2c_read_2(sc, I2C_REG_PSC) + 1;
759
760 /* Get the bitrate. */
761 scll = (int)ti_i2c_read_2(sc, I2C_REG_SCLL) & I2C_SCLL_MASK;
762 sclh = (int)ti_i2c_read_2(sc, I2C_REG_SCLH) & I2C_SCLH_MASK;
763
764 clk = I2C_CLK / psc / (scll + 7 + sclh + 5);
765 TI_I2C_UNLOCK(sc);
766
767 return (sysctl_handle_int(oidp, &clk, 0, req));
768 }
769
770 static int
ti_i2c_sysctl_timeout(SYSCTL_HANDLER_ARGS)771 ti_i2c_sysctl_timeout(SYSCTL_HANDLER_ARGS)
772 {
773 struct ti_i2c_softc *sc;
774 unsigned int val;
775 int err;
776
777 sc = arg1;
778
779 /*
780 * MTX_DEF lock can't be held while doing uimove in
781 * sysctl_handle_int
782 */
783 TI_I2C_LOCK(sc);
784 val = sc->sc_timeout;
785 TI_I2C_UNLOCK(sc);
786
787 err = sysctl_handle_int(oidp, &val, 0, req);
788 /* Write request? */
789 if ((err == 0) && (req->newptr != NULL)) {
790 TI_I2C_LOCK(sc);
791 sc->sc_timeout = val;
792 TI_I2C_UNLOCK(sc);
793 }
794
795 return (err);
796 }
797
798 static int
ti_i2c_probe(device_t dev)799 ti_i2c_probe(device_t dev)
800 {
801
802 if (!ofw_bus_status_okay(dev))
803 return (ENXIO);
804 if (!ofw_bus_is_compatible(dev, "ti,omap4-i2c"))
805 return (ENXIO);
806 device_set_desc(dev, "TI I2C Controller");
807
808 return (0);
809 }
810
811 static int
ti_i2c_attach(device_t dev)812 ti_i2c_attach(device_t dev)
813 {
814 int err, rid;
815 struct ti_i2c_softc *sc;
816 struct sysctl_ctx_list *ctx;
817 struct sysctl_oid_list *tree;
818 uint16_t fifosz;
819
820 sc = device_get_softc(dev);
821 sc->sc_dev = dev;
822
823 /* Get the memory resource for the register mapping. */
824 rid = 0;
825 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
826 RF_ACTIVE);
827 if (sc->sc_mem_res == NULL) {
828 device_printf(dev, "Cannot map registers.\n");
829 return (ENXIO);
830 }
831
832 /* Allocate our IRQ resource. */
833 rid = 0;
834 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
835 RF_ACTIVE | RF_SHAREABLE);
836 if (sc->sc_irq_res == NULL) {
837 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
838 device_printf(dev, "Cannot allocate interrupt.\n");
839 return (ENXIO);
840 }
841
842 TI_I2C_LOCK_INIT(sc);
843
844 /* First of all, we _must_ activate the H/W. */
845 err = ti_i2c_activate(dev);
846 if (err) {
847 device_printf(dev, "ti_i2c_activate failed\n");
848 goto out;
849 }
850
851 /* Read the version number of the I2C module */
852 sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff;
853
854 /* Get the fifo size. */
855 fifosz = ti_i2c_read_2(sc, I2C_REG_BUFSTAT);
856 fifosz >>= I2C_BUFSTAT_FIFODEPTH_SHIFT;
857 fifosz &= I2C_BUFSTAT_FIFODEPTH_MASK;
858
859 device_printf(dev, "I2C revision %d.%d FIFO size: %d bytes\n",
860 sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz);
861
862 /* Set the FIFO threshold to 5 for now. */
863 sc->sc_fifo_trsh = 5;
864
865 /* Set I2C bus timeout */
866 sc->sc_timeout = 5*hz;
867
868 ctx = device_get_sysctl_ctx(dev);
869 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
870 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_clock",
871 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0,
872 ti_i2c_sysctl_clk, "IU", "I2C bus clock");
873
874 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_timeout",
875 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0,
876 ti_i2c_sysctl_timeout, "IU", "I2C bus timeout (in ticks)");
877
878 /* Activate the interrupt. */
879 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
880 NULL, ti_i2c_intr, sc, &sc->sc_irq_h);
881 if (err)
882 goto out;
883
884 /* Attach the iicbus. */
885 if ((sc->sc_iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
886 device_printf(dev, "could not allocate iicbus instance\n");
887 err = ENXIO;
888 goto out;
889 }
890
891 /* Probe and attach the iicbus when interrupts are available. */
892 bus_delayed_attach_children(dev);
893
894 out:
895 if (err) {
896 ti_i2c_deactivate(dev);
897 TI_I2C_LOCK_DESTROY(sc);
898 }
899
900 return (err);
901 }
902
903 static int
ti_i2c_detach(device_t dev)904 ti_i2c_detach(device_t dev)
905 {
906 struct ti_i2c_softc *sc;
907 int rv;
908
909 sc = device_get_softc(dev);
910
911 if ((rv = bus_generic_detach(dev)) != 0) {
912 device_printf(dev, "cannot detach child devices\n");
913 return (rv);
914 }
915
916 if (sc->sc_iicbus &&
917 (rv = device_delete_child(dev, sc->sc_iicbus)) != 0)
918 return (rv);
919
920 ti_i2c_deactivate(dev);
921 TI_I2C_LOCK_DESTROY(sc);
922
923 return (0);
924 }
925
926 static phandle_t
ti_i2c_get_node(device_t bus,device_t dev)927 ti_i2c_get_node(device_t bus, device_t dev)
928 {
929
930 /* Share controller node with iibus device. */
931 return (ofw_bus_get_node(bus));
932 }
933
934 static device_method_t ti_i2c_methods[] = {
935 /* Device interface */
936 DEVMETHOD(device_probe, ti_i2c_probe),
937 DEVMETHOD(device_attach, ti_i2c_attach),
938 DEVMETHOD(device_detach, ti_i2c_detach),
939
940 /* Bus interface */
941 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
942 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
943 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
944 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
945 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
946 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
947 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
948 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
949 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
950
951 /* OFW methods */
952 DEVMETHOD(ofw_bus_get_node, ti_i2c_get_node),
953
954 /* iicbus interface */
955 DEVMETHOD(iicbus_callback, iicbus_null_callback),
956 DEVMETHOD(iicbus_reset, ti_i2c_iicbus_reset),
957 DEVMETHOD(iicbus_transfer, ti_i2c_transfer),
958
959 DEVMETHOD_END
960 };
961
962 static driver_t ti_i2c_driver = {
963 "iichb",
964 ti_i2c_methods,
965 sizeof(struct ti_i2c_softc),
966 };
967
968 DRIVER_MODULE(ti_iic, simplebus, ti_i2c_driver, 0, 0);
969 DRIVER_MODULE(iicbus, ti_iic, iicbus_driver, 0, 0);
970
971 MODULE_DEPEND(ti_iic, ti_sysc, 1, 1, 1);
972 MODULE_DEPEND(ti_iic, iicbus, 1, 1, 1);
973