1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2014 - 2018, NVIDIA CORPORATION. All rights reserved.
4 *
5 * Author:
6 * Mikko Perttunen <mperttunen@nvidia.com>
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19 #include <linux/debugfs.h>
20 #include <linux/bitops.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/err.h>
24 #include <linux/interrupt.h>
25 #include <linux/io.h>
26 #include <linux/irq.h>
27 #include <linux/irqdomain.h>
28 #include <linux/module.h>
29 #include <linux/of.h>
30 #include <linux/platform_device.h>
31 #include <linux/reset.h>
32 #include <linux/thermal.h>
33
34 #include <dt-bindings/thermal/tegra124-soctherm.h>
35
36 #include "../thermal_core.h"
37 #include "soctherm.h"
38
39 #define SENSOR_CONFIG0 0
40 #define SENSOR_CONFIG0_STOP BIT(0)
41 #define SENSOR_CONFIG0_CPTR_OVER BIT(2)
42 #define SENSOR_CONFIG0_OVER BIT(3)
43 #define SENSOR_CONFIG0_TCALC_OVER BIT(4)
44 #define SENSOR_CONFIG0_TALL_MASK (0xfffff << 8)
45 #define SENSOR_CONFIG0_TALL_SHIFT 8
46
47 #define SENSOR_CONFIG1 4
48 #define SENSOR_CONFIG1_TSAMPLE_MASK 0x3ff
49 #define SENSOR_CONFIG1_TSAMPLE_SHIFT 0
50 #define SENSOR_CONFIG1_TIDDQ_EN_MASK (0x3f << 15)
51 #define SENSOR_CONFIG1_TIDDQ_EN_SHIFT 15
52 #define SENSOR_CONFIG1_TEN_COUNT_MASK (0x3f << 24)
53 #define SENSOR_CONFIG1_TEN_COUNT_SHIFT 24
54 #define SENSOR_CONFIG1_TEMP_ENABLE BIT(31)
55
56 /*
57 * SENSOR_CONFIG2 is defined in soctherm.h
58 * because, it will be used by tegra_soctherm_fuse.c
59 */
60
61 #define SENSOR_STATUS0 0xc
62 #define SENSOR_STATUS0_VALID_MASK BIT(31)
63 #define SENSOR_STATUS0_CAPTURE_MASK 0xffff
64
65 #define SENSOR_STATUS1 0x10
66 #define SENSOR_STATUS1_TEMP_VALID_MASK BIT(31)
67 #define SENSOR_STATUS1_TEMP_MASK 0xffff
68
69 #define READBACK_VALUE_MASK 0xff00
70 #define READBACK_VALUE_SHIFT 8
71 #define READBACK_ADD_HALF BIT(7)
72 #define READBACK_NEGATE BIT(0)
73
74 /*
75 * THERMCTL_LEVEL0_GROUP_CPU is defined in soctherm.h
76 * because it will be used by tegraxxx_soctherm.c
77 */
78 #define THERMCTL_LVL0_CPU0_EN_MASK BIT(8)
79 #define THERMCTL_LVL0_CPU0_CPU_THROT_MASK (0x3 << 5)
80 #define THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT 0x1
81 #define THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY 0x2
82 #define THERMCTL_LVL0_CPU0_GPU_THROT_MASK (0x3 << 3)
83 #define THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT 0x1
84 #define THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY 0x2
85 #define THERMCTL_LVL0_CPU0_MEM_THROT_MASK BIT(2)
86 #define THERMCTL_LVL0_CPU0_STATUS_MASK 0x3
87
88 #define THERMCTL_LVL0_UP_STATS 0x10
89 #define THERMCTL_LVL0_DN_STATS 0x14
90
91 #define THERMCTL_INTR_STATUS 0x84
92
93 #define TH_INTR_MD0_MASK BIT(25)
94 #define TH_INTR_MU0_MASK BIT(24)
95 #define TH_INTR_GD0_MASK BIT(17)
96 #define TH_INTR_GU0_MASK BIT(16)
97 #define TH_INTR_CD0_MASK BIT(9)
98 #define TH_INTR_CU0_MASK BIT(8)
99 #define TH_INTR_PD0_MASK BIT(1)
100 #define TH_INTR_PU0_MASK BIT(0)
101 #define TH_INTR_IGNORE_MASK 0xFCFCFCFC
102
103 #define THERMCTL_STATS_CTL 0x94
104 #define STATS_CTL_CLR_DN 0x8
105 #define STATS_CTL_EN_DN 0x4
106 #define STATS_CTL_CLR_UP 0x2
107 #define STATS_CTL_EN_UP 0x1
108
109 #define OC1_CFG 0x310
110 #define OC1_CFG_LONG_LATENCY_MASK BIT(6)
111 #define OC1_CFG_HW_RESTORE_MASK BIT(5)
112 #define OC1_CFG_PWR_GOOD_MASK_MASK BIT(4)
113 #define OC1_CFG_THROTTLE_MODE_MASK (0x3 << 2)
114 #define OC1_CFG_ALARM_POLARITY_MASK BIT(1)
115 #define OC1_CFG_EN_THROTTLE_MASK BIT(0)
116
117 #define OC1_CNT_THRESHOLD 0x314
118 #define OC1_THROTTLE_PERIOD 0x318
119 #define OC1_ALARM_COUNT 0x31c
120 #define OC1_FILTER 0x320
121 #define OC1_STATS 0x3a8
122
123 #define OC_INTR_STATUS 0x39c
124 #define OC_INTR_ENABLE 0x3a0
125 #define OC_INTR_DISABLE 0x3a4
126 #define OC_STATS_CTL 0x3c4
127 #define OC_STATS_CTL_CLR_ALL 0x2
128 #define OC_STATS_CTL_EN_ALL 0x1
129
130 #define OC_INTR_OC1_MASK BIT(0)
131 #define OC_INTR_OC2_MASK BIT(1)
132 #define OC_INTR_OC3_MASK BIT(2)
133 #define OC_INTR_OC4_MASK BIT(3)
134 #define OC_INTR_OC5_MASK BIT(4)
135
136 #define THROT_GLOBAL_CFG 0x400
137 #define THROT_GLOBAL_ENB_MASK BIT(0)
138
139 #define CPU_PSKIP_STATUS 0x418
140 #define XPU_PSKIP_STATUS_M_MASK (0xff << 12)
141 #define XPU_PSKIP_STATUS_N_MASK (0xff << 4)
142 #define XPU_PSKIP_STATUS_SW_OVERRIDE_MASK BIT(1)
143 #define XPU_PSKIP_STATUS_ENABLED_MASK BIT(0)
144
145 #define THROT_PRIORITY_LOCK 0x424
146 #define THROT_PRIORITY_LOCK_PRIORITY_MASK 0xff
147
148 #define THROT_STATUS 0x428
149 #define THROT_STATUS_BREACH_MASK BIT(12)
150 #define THROT_STATUS_STATE_MASK (0xff << 4)
151 #define THROT_STATUS_ENABLED_MASK BIT(0)
152
153 #define THROT_PSKIP_CTRL_LITE_CPU 0x430
154 #define THROT_PSKIP_CTRL_ENABLE_MASK BIT(31)
155 #define THROT_PSKIP_CTRL_DIVIDEND_MASK (0xff << 8)
156 #define THROT_PSKIP_CTRL_DIVISOR_MASK 0xff
157 #define THROT_PSKIP_CTRL_VECT_GPU_MASK (0x7 << 16)
158 #define THROT_PSKIP_CTRL_VECT_CPU_MASK (0x7 << 8)
159 #define THROT_PSKIP_CTRL_VECT2_CPU_MASK 0x7
160
161 #define THROT_VECT_NONE 0x0 /* 3'b000 */
162 #define THROT_VECT_LOW 0x1 /* 3'b001 */
163 #define THROT_VECT_MED 0x3 /* 3'b011 */
164 #define THROT_VECT_HIGH 0x7 /* 3'b111 */
165
166 #define THROT_PSKIP_RAMP_LITE_CPU 0x434
167 #define THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK BIT(31)
168 #define THROT_PSKIP_RAMP_DURATION_MASK (0xffff << 8)
169 #define THROT_PSKIP_RAMP_STEP_MASK 0xff
170
171 #define THROT_PRIORITY_LITE 0x444
172 #define THROT_PRIORITY_LITE_PRIO_MASK 0xff
173
174 #define THROT_DELAY_LITE 0x448
175 #define THROT_DELAY_LITE_DELAY_MASK 0xff
176
177 /* car register offsets needed for enabling HW throttling */
178 #define CAR_SUPER_CCLKG_DIVIDER 0x36c
179 #define CDIVG_USE_THERM_CONTROLS_MASK BIT(30)
180
181 /* ccroc register offsets needed for enabling HW throttling for Tegra132 */
182 #define CCROC_SUPER_CCLKG_DIVIDER 0x024
183
184 #define CCROC_GLOBAL_CFG 0x148
185
186 #define CCROC_THROT_PSKIP_RAMP_CPU 0x150
187 #define CCROC_THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK BIT(31)
188 #define CCROC_THROT_PSKIP_RAMP_DURATION_MASK (0xffff << 8)
189 #define CCROC_THROT_PSKIP_RAMP_STEP_MASK 0xff
190
191 #define CCROC_THROT_PSKIP_CTRL_CPU 0x154
192 #define CCROC_THROT_PSKIP_CTRL_ENB_MASK BIT(31)
193 #define CCROC_THROT_PSKIP_CTRL_DIVIDEND_MASK (0xff << 8)
194 #define CCROC_THROT_PSKIP_CTRL_DIVISOR_MASK 0xff
195
196 /* get val from register(r) mask bits(m) */
197 #define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
198 /* set val(v) to mask bits(m) of register(r) */
199 #define REG_SET_MASK(r, m, v) (((r) & ~(m)) | \
200 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
201
202 /* get dividend from the depth */
203 #define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1)
204
205 /* gk20a nv_therm interface N:3 Mapping. Levels defined in tegra124-soctherm.h
206 * level vector
207 * NONE 3'b000
208 * LOW 3'b001
209 * MED 3'b011
210 * HIGH 3'b111
211 */
212 #define THROT_LEVEL_TO_DEPTH(level) ((0x1 << (level)) - 1)
213
214 /* get THROT_PSKIP_xxx offset per LIGHT/HEAVY throt and CPU/GPU dev */
215 #define THROT_OFFSET 0x30
216 #define THROT_PSKIP_CTRL(throt, dev) (THROT_PSKIP_CTRL_LITE_CPU + \
217 (THROT_OFFSET * throt) + (8 * dev))
218 #define THROT_PSKIP_RAMP(throt, dev) (THROT_PSKIP_RAMP_LITE_CPU + \
219 (THROT_OFFSET * throt) + (8 * dev))
220
221 /* get THROT_xxx_CTRL offset per LIGHT/HEAVY throt */
222 #define THROT_PRIORITY_CTRL(throt) (THROT_PRIORITY_LITE + \
223 (THROT_OFFSET * throt))
224 #define THROT_DELAY_CTRL(throt) (THROT_DELAY_LITE + \
225 (THROT_OFFSET * throt))
226
227 #define ALARM_OFFSET 0x14
228 #define ALARM_CFG(throt) (OC1_CFG + \
229 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
230
231 #define ALARM_CNT_THRESHOLD(throt) (OC1_CNT_THRESHOLD + \
232 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
233
234 #define ALARM_THROTTLE_PERIOD(throt) (OC1_THROTTLE_PERIOD + \
235 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
236
237 #define ALARM_ALARM_COUNT(throt) (OC1_ALARM_COUNT + \
238 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
239
240 #define ALARM_FILTER(throt) (OC1_FILTER + \
241 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
242
243 #define ALARM_STATS(throt) (OC1_STATS + \
244 (4 * (throt - THROTTLE_OC1)))
245
246 /* get CCROC_THROT_PSKIP_xxx offset per HIGH/MED/LOW vect*/
247 #define CCROC_THROT_OFFSET 0x0c
248 #define CCROC_THROT_PSKIP_CTRL_CPU_REG(vect) (CCROC_THROT_PSKIP_CTRL_CPU + \
249 (CCROC_THROT_OFFSET * vect))
250 #define CCROC_THROT_PSKIP_RAMP_CPU_REG(vect) (CCROC_THROT_PSKIP_RAMP_CPU + \
251 (CCROC_THROT_OFFSET * vect))
252
253 /* get THERMCTL_LEVELx offset per CPU/GPU/MEM/TSENSE rg and LEVEL0~3 lv */
254 #define THERMCTL_LVL_REGS_SIZE 0x20
255 #define THERMCTL_LVL_REG(rg, lv) ((rg) + ((lv) * THERMCTL_LVL_REGS_SIZE))
256
257 #define OC_THROTTLE_MODE_DISABLED 0
258 #define OC_THROTTLE_MODE_BRIEF 2
259
260 static const int min_low_temp = -127000;
261 static const int max_high_temp = 127000;
262
263 enum soctherm_throttle_id {
264 THROTTLE_LIGHT = 0,
265 THROTTLE_HEAVY,
266 THROTTLE_OC1,
267 THROTTLE_OC2,
268 THROTTLE_OC3,
269 THROTTLE_OC4,
270 THROTTLE_OC5, /* OC5 is reserved */
271 THROTTLE_SIZE,
272 };
273
274 enum soctherm_oc_irq_id {
275 TEGRA_SOC_OC_IRQ_1,
276 TEGRA_SOC_OC_IRQ_2,
277 TEGRA_SOC_OC_IRQ_3,
278 TEGRA_SOC_OC_IRQ_4,
279 TEGRA_SOC_OC_IRQ_5,
280 TEGRA_SOC_OC_IRQ_MAX,
281 };
282
283 enum soctherm_throttle_dev_id {
284 THROTTLE_DEV_CPU = 0,
285 THROTTLE_DEV_GPU,
286 THROTTLE_DEV_SIZE,
287 };
288
289 static const char *const throt_names[] = {
290 [THROTTLE_LIGHT] = "light",
291 [THROTTLE_HEAVY] = "heavy",
292 [THROTTLE_OC1] = "oc1",
293 [THROTTLE_OC2] = "oc2",
294 [THROTTLE_OC3] = "oc3",
295 [THROTTLE_OC4] = "oc4",
296 [THROTTLE_OC5] = "oc5",
297 };
298
299 struct tegra_soctherm;
300 struct tegra_thermctl_zone {
301 void __iomem *reg;
302 struct device *dev;
303 struct tegra_soctherm *ts;
304 struct thermal_zone_device *tz;
305 const struct tegra_tsensor_group *sg;
306 };
307
308 struct soctherm_oc_cfg {
309 u32 active_low;
310 u32 throt_period;
311 u32 alarm_cnt_thresh;
312 u32 alarm_filter;
313 u32 mode;
314 bool intr_en;
315 };
316
317 struct soctherm_throt_cfg {
318 const char *name;
319 unsigned int id;
320 u8 priority;
321 u8 cpu_throt_level;
322 u32 cpu_throt_depth;
323 u32 gpu_throt_level;
324 struct soctherm_oc_cfg oc_cfg;
325 struct thermal_cooling_device *cdev;
326 bool init;
327 };
328
329 struct tegra_soctherm {
330 struct reset_control *reset;
331 struct clk *clock_tsensor;
332 struct clk *clock_soctherm;
333 void __iomem *regs;
334 void __iomem *clk_regs;
335 void __iomem *ccroc_regs;
336
337 int thermal_irq;
338 int edp_irq;
339
340 u32 *calib;
341 struct thermal_zone_device **thermctl_tzs;
342 struct tegra_soctherm_soc *soc;
343
344 struct soctherm_throt_cfg throt_cfgs[THROTTLE_SIZE];
345
346 struct dentry *debugfs_dir;
347
348 struct mutex thermctl_lock;
349 };
350
351 struct soctherm_oc_irq_chip_data {
352 struct mutex irq_lock; /* serialize OC IRQs */
353 struct irq_chip irq_chip;
354 struct irq_domain *domain;
355 int irq_enable;
356 };
357
358 static struct soctherm_oc_irq_chip_data soc_irq_cdata;
359
360 /**
361 * ccroc_writel() - writes a value to a CCROC register
362 * @ts: pointer to a struct tegra_soctherm
363 * @value: the value to write
364 * @reg: the register offset
365 *
366 * Writes @v to @reg. No return value.
367 */
ccroc_writel(struct tegra_soctherm * ts,u32 value,u32 reg)368 static inline void ccroc_writel(struct tegra_soctherm *ts, u32 value, u32 reg)
369 {
370 writel(value, (ts->ccroc_regs + reg));
371 }
372
373 /**
374 * ccroc_readl() - reads specified register from CCROC IP block
375 * @ts: pointer to a struct tegra_soctherm
376 * @reg: register address to be read
377 *
378 * Return: the value of the register
379 */
ccroc_readl(struct tegra_soctherm * ts,u32 reg)380 static inline u32 ccroc_readl(struct tegra_soctherm *ts, u32 reg)
381 {
382 return readl(ts->ccroc_regs + reg);
383 }
384
enable_tsensor(struct tegra_soctherm * tegra,unsigned int i)385 static void enable_tsensor(struct tegra_soctherm *tegra, unsigned int i)
386 {
387 const struct tegra_tsensor *sensor = &tegra->soc->tsensors[i];
388 void __iomem *base = tegra->regs + sensor->base;
389 unsigned int val;
390
391 val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT;
392 writel(val, base + SENSOR_CONFIG0);
393
394 val = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT;
395 val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
396 val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
397 val |= SENSOR_CONFIG1_TEMP_ENABLE;
398 writel(val, base + SENSOR_CONFIG1);
399
400 writel(tegra->calib[i], base + SENSOR_CONFIG2);
401 }
402
403 /*
404 * Translate from soctherm readback format to millicelsius.
405 * The soctherm readback format in bits is as follows:
406 * TTTTTTTT H______N
407 * where T's contain the temperature in Celsius,
408 * H denotes an addition of 0.5 Celsius and N denotes negation
409 * of the final value.
410 */
translate_temp(u16 val)411 static int translate_temp(u16 val)
412 {
413 int t;
414
415 t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
416 if (val & READBACK_ADD_HALF)
417 t += 500;
418 if (val & READBACK_NEGATE)
419 t *= -1;
420
421 return t;
422 }
423
tegra_thermctl_get_temp(struct thermal_zone_device * tz,int * out_temp)424 static int tegra_thermctl_get_temp(struct thermal_zone_device *tz, int *out_temp)
425 {
426 struct tegra_thermctl_zone *zone = thermal_zone_device_priv(tz);
427 u32 val;
428
429 val = readl(zone->reg);
430 val = REG_GET_MASK(val, zone->sg->sensor_temp_mask);
431 *out_temp = translate_temp(val);
432
433 return 0;
434 }
435
436 /**
437 * enforce_temp_range() - check and enforce temperature range [min, max]
438 * @dev: struct device * of the SOC_THERM instance
439 * @trip_temp: the trip temperature to check
440 *
441 * Checks and enforces the permitted temperature range that SOC_THERM
442 * HW can support This is
443 * done while taking care of precision.
444 *
445 * Return: The precision adjusted capped temperature in millicelsius.
446 */
enforce_temp_range(struct device * dev,int trip_temp)447 static int enforce_temp_range(struct device *dev, int trip_temp)
448 {
449 int temp;
450
451 temp = clamp_val(trip_temp, min_low_temp, max_high_temp);
452 if (temp != trip_temp)
453 dev_dbg(dev, "soctherm: trip temperature %d forced to %d\n",
454 trip_temp, temp);
455 return temp;
456 }
457
458 /**
459 * thermtrip_program() - Configures the hardware to shut down the
460 * system if a given sensor group reaches a given temperature
461 * @dev: ptr to the struct device for the SOC_THERM IP block
462 * @sg: pointer to the sensor group to set the thermtrip temperature for
463 * @trip_temp: the temperature in millicelsius to trigger the thermal trip at
464 *
465 * Sets the thermal trip threshold of the given sensor group to be the
466 * @trip_temp. If this threshold is crossed, the hardware will shut
467 * down.
468 *
469 * Note that, although @trip_temp is specified in millicelsius, the
470 * hardware is programmed in degrees Celsius.
471 *
472 * Return: 0 upon success, or %-EINVAL upon failure.
473 */
thermtrip_program(struct device * dev,const struct tegra_tsensor_group * sg,int trip_temp)474 static int thermtrip_program(struct device *dev,
475 const struct tegra_tsensor_group *sg,
476 int trip_temp)
477 {
478 struct tegra_soctherm *ts = dev_get_drvdata(dev);
479 int temp;
480 u32 r;
481
482 if (!sg || !sg->thermtrip_threshold_mask)
483 return -EINVAL;
484
485 temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain;
486
487 r = readl(ts->regs + THERMCTL_THERMTRIP_CTL);
488 r = REG_SET_MASK(r, sg->thermtrip_threshold_mask, temp);
489 r = REG_SET_MASK(r, sg->thermtrip_enable_mask, 1);
490 r = REG_SET_MASK(r, sg->thermtrip_any_en_mask, 0);
491 writel(r, ts->regs + THERMCTL_THERMTRIP_CTL);
492
493 return 0;
494 }
495
496 /**
497 * throttrip_program() - Configures the hardware to throttle the
498 * pulse if a given sensor group reaches a given temperature
499 * @dev: ptr to the struct device for the SOC_THERM IP block
500 * @sg: pointer to the sensor group to set the thermtrip temperature for
501 * @stc: pointer to the throttle need to be triggered
502 * @trip_temp: the temperature in millicelsius to trigger the thermal trip at
503 *
504 * Sets the thermal trip threshold and throttle event of the given sensor
505 * group. If this threshold is crossed, the hardware will trigger the
506 * throttle.
507 *
508 * Note that, although @trip_temp is specified in millicelsius, the
509 * hardware is programmed in degrees Celsius.
510 *
511 * Return: 0 upon success, or %-EINVAL upon failure.
512 */
throttrip_program(struct device * dev,const struct tegra_tsensor_group * sg,struct soctherm_throt_cfg * stc,int trip_temp)513 static int throttrip_program(struct device *dev,
514 const struct tegra_tsensor_group *sg,
515 struct soctherm_throt_cfg *stc,
516 int trip_temp)
517 {
518 struct tegra_soctherm *ts = dev_get_drvdata(dev);
519 int temp, cpu_throt, gpu_throt;
520 unsigned int throt;
521 u32 r, reg_off;
522
523 if (!sg || !stc || !stc->init)
524 return -EINVAL;
525
526 temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain;
527
528 /* Hardcode LIGHT on LEVEL1 and HEAVY on LEVEL2 */
529 throt = stc->id;
530 reg_off = THERMCTL_LVL_REG(sg->thermctl_lvl0_offset, throt + 1);
531
532 if (throt == THROTTLE_LIGHT) {
533 cpu_throt = THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT;
534 gpu_throt = THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT;
535 } else {
536 cpu_throt = THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY;
537 gpu_throt = THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY;
538 if (throt != THROTTLE_HEAVY)
539 dev_warn(dev,
540 "invalid throt id %d - assuming HEAVY",
541 throt);
542 }
543
544 r = readl(ts->regs + reg_off);
545 r = REG_SET_MASK(r, sg->thermctl_lvl0_up_thresh_mask, temp);
546 r = REG_SET_MASK(r, sg->thermctl_lvl0_dn_thresh_mask, temp);
547 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_CPU_THROT_MASK, cpu_throt);
548 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_GPU_THROT_MASK, gpu_throt);
549 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1);
550 writel(r, ts->regs + reg_off);
551
552 return 0;
553 }
554
555 static struct soctherm_throt_cfg *
find_throttle_cfg_by_name(struct tegra_soctherm * ts,const char * name)556 find_throttle_cfg_by_name(struct tegra_soctherm *ts, const char *name)
557 {
558 unsigned int i;
559
560 for (i = 0; ts->throt_cfgs[i].name; i++)
561 if (!strcmp(ts->throt_cfgs[i].name, name))
562 return &ts->throt_cfgs[i];
563
564 return NULL;
565 }
566
tsensor_group_thermtrip_get(struct tegra_soctherm * ts,int id)567 static int tsensor_group_thermtrip_get(struct tegra_soctherm *ts, int id)
568 {
569 int i, temp = min_low_temp;
570 struct tsensor_group_thermtrips *tt = ts->soc->thermtrips;
571
572 if (id >= TEGRA124_SOCTHERM_SENSOR_NUM)
573 return temp;
574
575 if (tt) {
576 for (i = 0; i < ts->soc->num_ttgs; i++) {
577 if (tt[i].id == id)
578 return tt[i].temp;
579 }
580 }
581
582 return temp;
583 }
584
tegra_thermctl_set_trip_temp(struct thermal_zone_device * tz,const struct thermal_trip * trip,int temp)585 static int tegra_thermctl_set_trip_temp(struct thermal_zone_device *tz,
586 const struct thermal_trip *trip, int temp)
587 {
588 struct tegra_thermctl_zone *zone = thermal_zone_device_priv(tz);
589 struct tegra_soctherm *ts = zone->ts;
590 const struct tegra_tsensor_group *sg = zone->sg;
591 struct device *dev = zone->dev;
592
593 if (!tz)
594 return -EINVAL;
595
596 if (trip->type == THERMAL_TRIP_CRITICAL) {
597 /*
598 * If thermtrips property is set in DT,
599 * doesn't need to program critical type trip to HW,
600 * if not, program critical trip to HW.
601 */
602 if (min_low_temp == tsensor_group_thermtrip_get(ts, sg->id))
603 return thermtrip_program(dev, sg, temp);
604 else
605 return 0;
606
607 } else if (trip->type == THERMAL_TRIP_HOT) {
608 int i;
609
610 for (i = 0; i < THROTTLE_SIZE; i++) {
611 struct thermal_cooling_device *cdev;
612 struct soctherm_throt_cfg *stc;
613
614 if (!ts->throt_cfgs[i].init)
615 continue;
616
617 cdev = ts->throt_cfgs[i].cdev;
618 if (thermal_trip_is_bound_to_cdev(tz, trip, cdev))
619 stc = find_throttle_cfg_by_name(ts, cdev->type);
620 else
621 continue;
622
623 return throttrip_program(dev, sg, stc, temp);
624 }
625 }
626
627 return 0;
628 }
629
thermal_irq_enable(struct tegra_thermctl_zone * zn)630 static void thermal_irq_enable(struct tegra_thermctl_zone *zn)
631 {
632 u32 r;
633
634 /* multiple zones could be handling and setting trips at once */
635 mutex_lock(&zn->ts->thermctl_lock);
636 r = readl(zn->ts->regs + THERMCTL_INTR_ENABLE);
637 r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, TH_INTR_UP_DN_EN);
638 writel(r, zn->ts->regs + THERMCTL_INTR_ENABLE);
639 mutex_unlock(&zn->ts->thermctl_lock);
640 }
641
thermal_irq_disable(struct tegra_thermctl_zone * zn)642 static void thermal_irq_disable(struct tegra_thermctl_zone *zn)
643 {
644 u32 r;
645
646 /* multiple zones could be handling and setting trips at once */
647 mutex_lock(&zn->ts->thermctl_lock);
648 r = readl(zn->ts->regs + THERMCTL_INTR_DISABLE);
649 r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, 0);
650 writel(r, zn->ts->regs + THERMCTL_INTR_DISABLE);
651 mutex_unlock(&zn->ts->thermctl_lock);
652 }
653
tegra_thermctl_set_trips(struct thermal_zone_device * tz,int lo,int hi)654 static int tegra_thermctl_set_trips(struct thermal_zone_device *tz, int lo, int hi)
655 {
656 struct tegra_thermctl_zone *zone = thermal_zone_device_priv(tz);
657 u32 r;
658
659 thermal_irq_disable(zone);
660
661 r = readl(zone->ts->regs + zone->sg->thermctl_lvl0_offset);
662 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 0);
663 writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset);
664
665 lo = enforce_temp_range(zone->dev, lo) / zone->ts->soc->thresh_grain;
666 hi = enforce_temp_range(zone->dev, hi) / zone->ts->soc->thresh_grain;
667 dev_dbg(zone->dev, "%s hi:%d, lo:%d\n", __func__, hi, lo);
668
669 r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_up_thresh_mask, hi);
670 r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_dn_thresh_mask, lo);
671 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1);
672 writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset);
673
674 thermal_irq_enable(zone);
675
676 return 0;
677 }
678
679 static const struct thermal_zone_device_ops tegra_of_thermal_ops = {
680 .get_temp = tegra_thermctl_get_temp,
681 .set_trip_temp = tegra_thermctl_set_trip_temp,
682 .set_trips = tegra_thermctl_set_trips,
683 };
684
get_hot_trip_cb(struct thermal_trip * trip,void * arg)685 static int get_hot_trip_cb(struct thermal_trip *trip, void *arg)
686 {
687 const struct thermal_trip **trip_ret = arg;
688
689 if (trip->type != THERMAL_TRIP_HOT)
690 return 0;
691
692 *trip_ret = trip;
693 /* Return nonzero to terminate the search. */
694 return 1;
695 }
696
get_hot_trip(struct thermal_zone_device * tz)697 static const struct thermal_trip *get_hot_trip(struct thermal_zone_device *tz)
698 {
699 const struct thermal_trip *trip = NULL;
700
701 thermal_zone_for_each_trip(tz, get_hot_trip_cb, &trip);
702
703 return trip;
704 }
705
706 /**
707 * tegra_soctherm_set_hwtrips() - set HW trip point from DT data
708 * @dev: struct device * of the SOC_THERM instance
709 * @sg: pointer to the sensor group to set the thermtrip temperature for
710 * @tz: struct thermal_zone_device *
711 *
712 * Configure the SOC_THERM HW trip points, setting "THERMTRIP"
713 * "THROTTLE" trip points , using "thermtrips", "critical" or "hot"
714 * type trip_temp
715 * from thermal zone.
716 * After they have been configured, THERMTRIP or THROTTLE will take
717 * action when the configured SoC thermal sensor group reaches a
718 * certain temperature.
719 *
720 * Return: 0 upon success, or a negative error code on failure.
721 * "Success" does not mean that trips was enabled; it could also
722 * mean that no node was found in DT.
723 * THERMTRIP has been enabled successfully when a message similar to
724 * this one appears on the serial console:
725 * "thermtrip: will shut down when sensor group XXX reaches YYYYYY mC"
726 * THROTTLE has been enabled successfully when a message similar to
727 * this one appears on the serial console:
728 * ""throttrip: will throttle when sensor group XXX reaches YYYYYY mC"
729 */
tegra_soctherm_set_hwtrips(struct device * dev,const struct tegra_tsensor_group * sg,struct thermal_zone_device * tz)730 static int tegra_soctherm_set_hwtrips(struct device *dev,
731 const struct tegra_tsensor_group *sg,
732 struct thermal_zone_device *tz)
733 {
734 struct tegra_soctherm *ts = dev_get_drvdata(dev);
735 const struct thermal_trip *hot_trip;
736 struct soctherm_throt_cfg *stc;
737 int i, temperature, ret;
738
739 /* Get thermtrips. If missing, try to get critical trips. */
740 temperature = tsensor_group_thermtrip_get(ts, sg->id);
741 if (min_low_temp == temperature)
742 if (thermal_zone_get_crit_temp(tz, &temperature))
743 temperature = max_high_temp;
744
745 ret = thermtrip_program(dev, sg, temperature);
746 if (ret) {
747 dev_err(dev, "thermtrip: %s: error during enable\n", sg->name);
748 return ret;
749 }
750
751 dev_info(dev, "thermtrip: will shut down when %s reaches %d mC\n",
752 sg->name, temperature);
753
754 hot_trip = get_hot_trip(tz);
755 if (!hot_trip) {
756 dev_info(dev, "throttrip: %s: missing hot temperature\n",
757 sg->name);
758 return 0;
759 }
760
761 for (i = 0; i < THROTTLE_OC1; i++) {
762 struct thermal_cooling_device *cdev;
763
764 if (!ts->throt_cfgs[i].init)
765 continue;
766
767 cdev = ts->throt_cfgs[i].cdev;
768 if (thermal_trip_is_bound_to_cdev(tz, hot_trip, cdev))
769 stc = find_throttle_cfg_by_name(ts, cdev->type);
770 else
771 continue;
772
773 ret = throttrip_program(dev, sg, stc, temperature);
774 if (ret) {
775 dev_err(dev, "throttrip: %s: error during enable\n",
776 sg->name);
777 return ret;
778 }
779
780 dev_info(dev,
781 "throttrip: will throttle when %s reaches %d mC\n",
782 sg->name, temperature);
783 break;
784 }
785
786 if (i == THROTTLE_SIZE)
787 dev_info(dev, "throttrip: %s: missing throttle cdev\n",
788 sg->name);
789
790 return 0;
791 }
792
soctherm_thermal_isr(int irq,void * dev_id)793 static irqreturn_t soctherm_thermal_isr(int irq, void *dev_id)
794 {
795 struct tegra_soctherm *ts = dev_id;
796 u32 r;
797
798 /* Case for no lock:
799 * Although interrupts are enabled in set_trips, there is still no need
800 * to lock here because the interrupts are disabled before programming
801 * new trip points. Hence there cant be a interrupt on the same sensor.
802 * An interrupt can however occur on a sensor while trips are being
803 * programmed on a different one. This beign a LEVEL interrupt won't
804 * cause a new interrupt but this is taken care of by the re-reading of
805 * the STATUS register in the thread function.
806 */
807 r = readl(ts->regs + THERMCTL_INTR_STATUS);
808 writel(r, ts->regs + THERMCTL_INTR_DISABLE);
809
810 return IRQ_WAKE_THREAD;
811 }
812
813 /**
814 * soctherm_thermal_isr_thread() - Handles a thermal interrupt request
815 * @irq: The interrupt number being requested; not used
816 * @dev_id: Opaque pointer to tegra_soctherm;
817 *
818 * Clears the interrupt status register if there are expected
819 * interrupt bits set.
820 * The interrupt(s) are then handled by updating the corresponding
821 * thermal zones.
822 *
823 * An error is logged if any unexpected interrupt bits are set.
824 *
825 * Disabled interrupts are re-enabled.
826 *
827 * Return: %IRQ_HANDLED. Interrupt was handled and no further processing
828 * is needed.
829 */
soctherm_thermal_isr_thread(int irq,void * dev_id)830 static irqreturn_t soctherm_thermal_isr_thread(int irq, void *dev_id)
831 {
832 struct tegra_soctherm *ts = dev_id;
833 struct thermal_zone_device *tz;
834 u32 st, ex = 0, cp = 0, gp = 0, pl = 0, me = 0;
835
836 st = readl(ts->regs + THERMCTL_INTR_STATUS);
837
838 /* deliberately clear expected interrupts handled in SW */
839 cp |= st & TH_INTR_CD0_MASK;
840 cp |= st & TH_INTR_CU0_MASK;
841
842 gp |= st & TH_INTR_GD0_MASK;
843 gp |= st & TH_INTR_GU0_MASK;
844
845 pl |= st & TH_INTR_PD0_MASK;
846 pl |= st & TH_INTR_PU0_MASK;
847
848 me |= st & TH_INTR_MD0_MASK;
849 me |= st & TH_INTR_MU0_MASK;
850
851 ex |= cp | gp | pl | me;
852 if (ex) {
853 writel(ex, ts->regs + THERMCTL_INTR_STATUS);
854 st &= ~ex;
855
856 if (cp) {
857 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_CPU];
858 thermal_zone_device_update(tz,
859 THERMAL_EVENT_UNSPECIFIED);
860 }
861
862 if (gp) {
863 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_GPU];
864 thermal_zone_device_update(tz,
865 THERMAL_EVENT_UNSPECIFIED);
866 }
867
868 if (pl) {
869 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_PLLX];
870 thermal_zone_device_update(tz,
871 THERMAL_EVENT_UNSPECIFIED);
872 }
873
874 if (me) {
875 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_MEM];
876 thermal_zone_device_update(tz,
877 THERMAL_EVENT_UNSPECIFIED);
878 }
879 }
880
881 /* deliberately ignore expected interrupts NOT handled in SW */
882 ex |= TH_INTR_IGNORE_MASK;
883 st &= ~ex;
884
885 if (st) {
886 /* Whine about any other unexpected INTR bits still set */
887 pr_err("soctherm: Ignored unexpected INTRs 0x%08x\n", st);
888 writel(st, ts->regs + THERMCTL_INTR_STATUS);
889 }
890
891 return IRQ_HANDLED;
892 }
893
894 /**
895 * soctherm_oc_intr_enable() - Enables the soctherm over-current interrupt
896 * @ts: pointer to a struct tegra_soctherm
897 * @alarm: The soctherm throttle id
898 * @enable: Flag indicating enable the soctherm over-current
899 * interrupt or disable it
900 *
901 * Enables a specific over-current pins @alarm to raise an interrupt if the flag
902 * is set and the alarm corresponds to OC1, OC2, OC3, or OC4.
903 */
soctherm_oc_intr_enable(struct tegra_soctherm * ts,enum soctherm_throttle_id alarm,bool enable)904 static void soctherm_oc_intr_enable(struct tegra_soctherm *ts,
905 enum soctherm_throttle_id alarm,
906 bool enable)
907 {
908 u32 r;
909
910 if (!enable)
911 return;
912
913 r = readl(ts->regs + OC_INTR_ENABLE);
914 switch (alarm) {
915 case THROTTLE_OC1:
916 r = REG_SET_MASK(r, OC_INTR_OC1_MASK, 1);
917 break;
918 case THROTTLE_OC2:
919 r = REG_SET_MASK(r, OC_INTR_OC2_MASK, 1);
920 break;
921 case THROTTLE_OC3:
922 r = REG_SET_MASK(r, OC_INTR_OC3_MASK, 1);
923 break;
924 case THROTTLE_OC4:
925 r = REG_SET_MASK(r, OC_INTR_OC4_MASK, 1);
926 break;
927 default:
928 r = 0;
929 break;
930 }
931 writel(r, ts->regs + OC_INTR_ENABLE);
932 }
933
934 /**
935 * soctherm_handle_alarm() - Handles soctherm alarms
936 * @alarm: The soctherm throttle id
937 *
938 * "Handles" over-current alarms (OC1, OC2, OC3, and OC4) by printing
939 * a warning or informative message.
940 *
941 * Return: -EINVAL for @alarm = THROTTLE_OC3, otherwise 0 (success).
942 */
soctherm_handle_alarm(enum soctherm_throttle_id alarm)943 static int soctherm_handle_alarm(enum soctherm_throttle_id alarm)
944 {
945 int rv = -EINVAL;
946
947 switch (alarm) {
948 case THROTTLE_OC1:
949 pr_debug("soctherm: Successfully handled OC1 alarm\n");
950 rv = 0;
951 break;
952
953 case THROTTLE_OC2:
954 pr_debug("soctherm: Successfully handled OC2 alarm\n");
955 rv = 0;
956 break;
957
958 case THROTTLE_OC3:
959 pr_debug("soctherm: Successfully handled OC3 alarm\n");
960 rv = 0;
961 break;
962
963 case THROTTLE_OC4:
964 pr_debug("soctherm: Successfully handled OC4 alarm\n");
965 rv = 0;
966 break;
967
968 default:
969 break;
970 }
971
972 if (rv)
973 pr_err("soctherm: ERROR in handling %s alarm\n",
974 throt_names[alarm]);
975
976 return rv;
977 }
978
979 /**
980 * soctherm_edp_isr_thread() - log an over-current interrupt request
981 * @irq: OC irq number. Currently not being used. See description
982 * @arg: a void pointer for callback, currently not being used
983 *
984 * Over-current events are handled in hardware. This function is called to log
985 * and handle any OC events that happened. Additionally, it checks every
986 * over-current interrupt registers for registers are set but
987 * was not expected (i.e. any discrepancy in interrupt status) by the function,
988 * the discrepancy will logged.
989 *
990 * Return: %IRQ_HANDLED
991 */
soctherm_edp_isr_thread(int irq,void * arg)992 static irqreturn_t soctherm_edp_isr_thread(int irq, void *arg)
993 {
994 struct tegra_soctherm *ts = arg;
995 u32 st, ex, oc1, oc2, oc3, oc4;
996
997 st = readl(ts->regs + OC_INTR_STATUS);
998
999 /* deliberately clear expected interrupts handled in SW */
1000 oc1 = st & OC_INTR_OC1_MASK;
1001 oc2 = st & OC_INTR_OC2_MASK;
1002 oc3 = st & OC_INTR_OC3_MASK;
1003 oc4 = st & OC_INTR_OC4_MASK;
1004 ex = oc1 | oc2 | oc3 | oc4;
1005
1006 pr_err("soctherm: OC ALARM 0x%08x\n", ex);
1007 if (ex) {
1008 writel(st, ts->regs + OC_INTR_STATUS);
1009 st &= ~ex;
1010
1011 if (oc1 && !soctherm_handle_alarm(THROTTLE_OC1))
1012 soctherm_oc_intr_enable(ts, THROTTLE_OC1, true);
1013
1014 if (oc2 && !soctherm_handle_alarm(THROTTLE_OC2))
1015 soctherm_oc_intr_enable(ts, THROTTLE_OC2, true);
1016
1017 if (oc3 && !soctherm_handle_alarm(THROTTLE_OC3))
1018 soctherm_oc_intr_enable(ts, THROTTLE_OC3, true);
1019
1020 if (oc4 && !soctherm_handle_alarm(THROTTLE_OC4))
1021 soctherm_oc_intr_enable(ts, THROTTLE_OC4, true);
1022
1023 if (oc1 && soc_irq_cdata.irq_enable & BIT(0))
1024 handle_nested_irq(
1025 irq_find_mapping(soc_irq_cdata.domain, 0));
1026
1027 if (oc2 && soc_irq_cdata.irq_enable & BIT(1))
1028 handle_nested_irq(
1029 irq_find_mapping(soc_irq_cdata.domain, 1));
1030
1031 if (oc3 && soc_irq_cdata.irq_enable & BIT(2))
1032 handle_nested_irq(
1033 irq_find_mapping(soc_irq_cdata.domain, 2));
1034
1035 if (oc4 && soc_irq_cdata.irq_enable & BIT(3))
1036 handle_nested_irq(
1037 irq_find_mapping(soc_irq_cdata.domain, 3));
1038 }
1039
1040 if (st) {
1041 pr_err("soctherm: Ignored unexpected OC ALARM 0x%08x\n", st);
1042 writel(st, ts->regs + OC_INTR_STATUS);
1043 }
1044
1045 return IRQ_HANDLED;
1046 }
1047
1048 /**
1049 * soctherm_edp_isr() - Disables any active interrupts
1050 * @irq: The interrupt request number
1051 * @arg: Opaque pointer to an argument
1052 *
1053 * Writes to the OC_INTR_DISABLE register the over current interrupt status,
1054 * masking any asserted interrupts. Doing this prevents the same interrupts
1055 * from triggering this isr repeatedly. The thread woken by this isr will
1056 * handle asserted interrupts and subsequently unmask/re-enable them.
1057 *
1058 * The OC_INTR_DISABLE register indicates which OC interrupts
1059 * have been disabled.
1060 *
1061 * Return: %IRQ_WAKE_THREAD, handler requests to wake the handler thread
1062 */
soctherm_edp_isr(int irq,void * arg)1063 static irqreturn_t soctherm_edp_isr(int irq, void *arg)
1064 {
1065 struct tegra_soctherm *ts = arg;
1066 u32 r;
1067
1068 if (!ts)
1069 return IRQ_NONE;
1070
1071 r = readl(ts->regs + OC_INTR_STATUS);
1072 writel(r, ts->regs + OC_INTR_DISABLE);
1073
1074 return IRQ_WAKE_THREAD;
1075 }
1076
1077 /**
1078 * soctherm_oc_irq_lock() - locks the over-current interrupt request
1079 * @data: Interrupt request data
1080 *
1081 * Looks up the chip data from @data and locks the mutex associated with
1082 * a particular over-current interrupt request.
1083 */
soctherm_oc_irq_lock(struct irq_data * data)1084 static void soctherm_oc_irq_lock(struct irq_data *data)
1085 {
1086 struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
1087
1088 mutex_lock(&d->irq_lock);
1089 }
1090
1091 /**
1092 * soctherm_oc_irq_sync_unlock() - Unlocks the OC interrupt request
1093 * @data: Interrupt request data
1094 *
1095 * Looks up the interrupt request data @data and unlocks the mutex associated
1096 * with a particular over-current interrupt request.
1097 */
soctherm_oc_irq_sync_unlock(struct irq_data * data)1098 static void soctherm_oc_irq_sync_unlock(struct irq_data *data)
1099 {
1100 struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
1101
1102 mutex_unlock(&d->irq_lock);
1103 }
1104
1105 /**
1106 * soctherm_oc_irq_enable() - Enables the SOC_THERM over-current interrupt queue
1107 * @data: irq_data structure of the chip
1108 *
1109 * Sets the irq_enable bit of SOC_THERM allowing SOC_THERM
1110 * to respond to over-current interrupts.
1111 *
1112 */
soctherm_oc_irq_enable(struct irq_data * data)1113 static void soctherm_oc_irq_enable(struct irq_data *data)
1114 {
1115 struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
1116
1117 d->irq_enable |= BIT(data->hwirq);
1118 }
1119
1120 /**
1121 * soctherm_oc_irq_disable() - Disables overcurrent interrupt requests
1122 * @data: The interrupt request information
1123 *
1124 * Clears the interrupt request enable bit of the overcurrent
1125 * interrupt request chip data.
1126 *
1127 * Return: Nothing is returned (void)
1128 */
soctherm_oc_irq_disable(struct irq_data * data)1129 static void soctherm_oc_irq_disable(struct irq_data *data)
1130 {
1131 struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
1132
1133 d->irq_enable &= ~BIT(data->hwirq);
1134 }
1135
soctherm_oc_irq_set_type(struct irq_data * data,unsigned int type)1136 static int soctherm_oc_irq_set_type(struct irq_data *data, unsigned int type)
1137 {
1138 return 0;
1139 }
1140
1141 /**
1142 * soctherm_oc_irq_map() - SOC_THERM interrupt request domain mapper
1143 * @h: Interrupt request domain
1144 * @virq: Virtual interrupt request number
1145 * @hw: Hardware interrupt request number
1146 *
1147 * Mapping callback function for SOC_THERM's irq_domain. When a SOC_THERM
1148 * interrupt request is called, the irq_domain takes the request's virtual
1149 * request number (much like a virtual memory address) and maps it to a
1150 * physical hardware request number.
1151 *
1152 * When a mapping doesn't already exist for a virtual request number, the
1153 * irq_domain calls this function to associate the virtual request number with
1154 * a hardware request number.
1155 *
1156 * Return: 0
1157 */
soctherm_oc_irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)1158 static int soctherm_oc_irq_map(struct irq_domain *h, unsigned int virq,
1159 irq_hw_number_t hw)
1160 {
1161 struct soctherm_oc_irq_chip_data *data = h->host_data;
1162
1163 irq_set_chip_data(virq, data);
1164 irq_set_chip(virq, &data->irq_chip);
1165 irq_set_nested_thread(virq, 1);
1166 return 0;
1167 }
1168
1169 /**
1170 * soctherm_irq_domain_xlate_twocell() - xlate for soctherm interrupts
1171 * @d: Interrupt request domain
1172 * @ctrlr: Controller device tree node
1173 * @intspec: Array of u32s from DTs "interrupt" property
1174 * @intsize: Number of values inside the intspec array
1175 * @out_hwirq: HW IRQ value associated with this interrupt
1176 * @out_type: The IRQ SENSE type for this interrupt.
1177 *
1178 * This Device Tree IRQ specifier translation function will translate a
1179 * specific "interrupt" as defined by 2 DT values where the cell values map
1180 * the hwirq number + 1 and linux irq flags. Since the output is the hwirq
1181 * number, this function will subtract 1 from the value listed in DT.
1182 *
1183 * Return: 0
1184 */
soctherm_irq_domain_xlate_twocell(struct irq_domain * d,struct device_node * ctrlr,const u32 * intspec,unsigned int intsize,irq_hw_number_t * out_hwirq,unsigned int * out_type)1185 static int soctherm_irq_domain_xlate_twocell(struct irq_domain *d,
1186 struct device_node *ctrlr, const u32 *intspec, unsigned int intsize,
1187 irq_hw_number_t *out_hwirq, unsigned int *out_type)
1188 {
1189 if (WARN_ON(intsize < 2))
1190 return -EINVAL;
1191
1192 /*
1193 * The HW value is 1 index less than the DT IRQ values.
1194 * i.e. OC4 goes to HW index 3.
1195 */
1196 *out_hwirq = intspec[0] - 1;
1197 *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
1198 return 0;
1199 }
1200
1201 static const struct irq_domain_ops soctherm_oc_domain_ops = {
1202 .map = soctherm_oc_irq_map,
1203 .xlate = soctherm_irq_domain_xlate_twocell,
1204 };
1205
1206 /**
1207 * soctherm_oc_int_init() - Initial enabling of the over
1208 * current interrupts
1209 * @fwnode: The devicetree node for soctherm
1210 * @num_irqs: The number of new interrupt requests
1211 *
1212 * Sets the over current interrupt request chip data
1213 *
1214 * Return: 0 on success or if overcurrent interrupts are not enabled,
1215 * -ENOMEM (out of memory), or irq_base if the function failed to
1216 * allocate the irqs
1217 */
soctherm_oc_int_init(struct fwnode_handle * fwnode,int num_irqs)1218 static int soctherm_oc_int_init(struct fwnode_handle *fwnode, int num_irqs)
1219 {
1220 if (!num_irqs) {
1221 pr_info("%s(): OC interrupts are not enabled\n", __func__);
1222 return 0;
1223 }
1224
1225 mutex_init(&soc_irq_cdata.irq_lock);
1226 soc_irq_cdata.irq_enable = 0;
1227
1228 soc_irq_cdata.irq_chip.name = "soc_therm_oc";
1229 soc_irq_cdata.irq_chip.irq_bus_lock = soctherm_oc_irq_lock;
1230 soc_irq_cdata.irq_chip.irq_bus_sync_unlock =
1231 soctherm_oc_irq_sync_unlock;
1232 soc_irq_cdata.irq_chip.irq_disable = soctherm_oc_irq_disable;
1233 soc_irq_cdata.irq_chip.irq_enable = soctherm_oc_irq_enable;
1234 soc_irq_cdata.irq_chip.irq_set_type = soctherm_oc_irq_set_type;
1235 soc_irq_cdata.irq_chip.irq_set_wake = NULL;
1236
1237 soc_irq_cdata.domain = irq_domain_create_linear(fwnode, num_irqs, &soctherm_oc_domain_ops,
1238 &soc_irq_cdata);
1239 if (!soc_irq_cdata.domain) {
1240 pr_err("%s: Failed to create IRQ domain\n", __func__);
1241 return -ENOMEM;
1242 }
1243
1244 pr_debug("%s(): OC interrupts enabled successful\n", __func__);
1245 return 0;
1246 }
1247
1248 #ifdef CONFIG_DEBUG_FS
regs_show(struct seq_file * s,void * data)1249 static int regs_show(struct seq_file *s, void *data)
1250 {
1251 struct platform_device *pdev = s->private;
1252 struct tegra_soctherm *ts = platform_get_drvdata(pdev);
1253 const struct tegra_tsensor *tsensors = ts->soc->tsensors;
1254 const struct tegra_tsensor_group **ttgs = ts->soc->ttgs;
1255 u32 r, state;
1256 int i, level;
1257
1258 seq_puts(s, "-----TSENSE (convert HW)-----\n");
1259
1260 for (i = 0; i < ts->soc->num_tsensors; i++) {
1261 r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG1);
1262 state = REG_GET_MASK(r, SENSOR_CONFIG1_TEMP_ENABLE);
1263
1264 seq_printf(s, "%s: ", tsensors[i].name);
1265 seq_printf(s, "En(%d) ", state);
1266
1267 if (!state) {
1268 seq_puts(s, "\n");
1269 continue;
1270 }
1271
1272 state = REG_GET_MASK(r, SENSOR_CONFIG1_TIDDQ_EN_MASK);
1273 seq_printf(s, "tiddq(%d) ", state);
1274 state = REG_GET_MASK(r, SENSOR_CONFIG1_TEN_COUNT_MASK);
1275 seq_printf(s, "ten_count(%d) ", state);
1276 state = REG_GET_MASK(r, SENSOR_CONFIG1_TSAMPLE_MASK);
1277 seq_printf(s, "tsample(%d) ", state + 1);
1278
1279 r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS1);
1280 state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_VALID_MASK);
1281 seq_printf(s, "Temp(%d/", state);
1282 state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_MASK);
1283 seq_printf(s, "%d) ", translate_temp(state));
1284
1285 r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS0);
1286 state = REG_GET_MASK(r, SENSOR_STATUS0_VALID_MASK);
1287 seq_printf(s, "Capture(%d/", state);
1288 state = REG_GET_MASK(r, SENSOR_STATUS0_CAPTURE_MASK);
1289 seq_printf(s, "%d) ", state);
1290
1291 r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG0);
1292 state = REG_GET_MASK(r, SENSOR_CONFIG0_STOP);
1293 seq_printf(s, "Stop(%d) ", state);
1294 state = REG_GET_MASK(r, SENSOR_CONFIG0_TALL_MASK);
1295 seq_printf(s, "Tall(%d) ", state);
1296 state = REG_GET_MASK(r, SENSOR_CONFIG0_TCALC_OVER);
1297 seq_printf(s, "Over(%d/", state);
1298 state = REG_GET_MASK(r, SENSOR_CONFIG0_OVER);
1299 seq_printf(s, "%d/", state);
1300 state = REG_GET_MASK(r, SENSOR_CONFIG0_CPTR_OVER);
1301 seq_printf(s, "%d) ", state);
1302
1303 r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG2);
1304 state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMA_MASK);
1305 seq_printf(s, "Therm_A/B(%d/", state);
1306 state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMB_MASK);
1307 seq_printf(s, "%d)\n", (s16)state);
1308 }
1309
1310 r = readl(ts->regs + SENSOR_PDIV);
1311 seq_printf(s, "PDIV: 0x%x\n", r);
1312
1313 r = readl(ts->regs + SENSOR_HOTSPOT_OFF);
1314 seq_printf(s, "HOTSPOT: 0x%x\n", r);
1315
1316 seq_puts(s, "\n");
1317 seq_puts(s, "-----SOC_THERM-----\n");
1318
1319 r = readl(ts->regs + SENSOR_TEMP1);
1320 state = REG_GET_MASK(r, SENSOR_TEMP1_CPU_TEMP_MASK);
1321 seq_printf(s, "Temperatures: CPU(%d) ", translate_temp(state));
1322 state = REG_GET_MASK(r, SENSOR_TEMP1_GPU_TEMP_MASK);
1323 seq_printf(s, " GPU(%d) ", translate_temp(state));
1324 r = readl(ts->regs + SENSOR_TEMP2);
1325 state = REG_GET_MASK(r, SENSOR_TEMP2_PLLX_TEMP_MASK);
1326 seq_printf(s, " PLLX(%d) ", translate_temp(state));
1327 state = REG_GET_MASK(r, SENSOR_TEMP2_MEM_TEMP_MASK);
1328 seq_printf(s, " MEM(%d)\n", translate_temp(state));
1329
1330 for (i = 0; i < ts->soc->num_ttgs; i++) {
1331 seq_printf(s, "%s:\n", ttgs[i]->name);
1332 for (level = 0; level < 4; level++) {
1333 s32 v;
1334 u32 mask;
1335 u16 off = ttgs[i]->thermctl_lvl0_offset;
1336
1337 r = readl(ts->regs + THERMCTL_LVL_REG(off, level));
1338
1339 mask = ttgs[i]->thermctl_lvl0_up_thresh_mask;
1340 state = REG_GET_MASK(r, mask);
1341 v = sign_extend32(state, ts->soc->bptt - 1);
1342 v *= ts->soc->thresh_grain;
1343 seq_printf(s, " %d: Up/Dn(%d /", level, v);
1344
1345 mask = ttgs[i]->thermctl_lvl0_dn_thresh_mask;
1346 state = REG_GET_MASK(r, mask);
1347 v = sign_extend32(state, ts->soc->bptt - 1);
1348 v *= ts->soc->thresh_grain;
1349 seq_printf(s, "%d ) ", v);
1350
1351 mask = THERMCTL_LVL0_CPU0_EN_MASK;
1352 state = REG_GET_MASK(r, mask);
1353 seq_printf(s, "En(%d) ", state);
1354
1355 mask = THERMCTL_LVL0_CPU0_CPU_THROT_MASK;
1356 state = REG_GET_MASK(r, mask);
1357 seq_puts(s, "CPU Throt");
1358 if (!state)
1359 seq_printf(s, "(%s) ", "none");
1360 else if (state == THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT)
1361 seq_printf(s, "(%s) ", "L");
1362 else if (state == THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY)
1363 seq_printf(s, "(%s) ", "H");
1364 else
1365 seq_printf(s, "(%s) ", "H+L");
1366
1367 mask = THERMCTL_LVL0_CPU0_GPU_THROT_MASK;
1368 state = REG_GET_MASK(r, mask);
1369 seq_puts(s, "GPU Throt");
1370 if (!state)
1371 seq_printf(s, "(%s) ", "none");
1372 else if (state == THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT)
1373 seq_printf(s, "(%s) ", "L");
1374 else if (state == THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY)
1375 seq_printf(s, "(%s) ", "H");
1376 else
1377 seq_printf(s, "(%s) ", "H+L");
1378
1379 mask = THERMCTL_LVL0_CPU0_STATUS_MASK;
1380 state = REG_GET_MASK(r, mask);
1381 seq_printf(s, "Status(%s)\n",
1382 state == 0 ? "LO" :
1383 state == 1 ? "In" :
1384 state == 2 ? "Res" : "HI");
1385 }
1386 }
1387
1388 r = readl(ts->regs + THERMCTL_STATS_CTL);
1389 seq_printf(s, "STATS: Up(%s) Dn(%s)\n",
1390 r & STATS_CTL_EN_UP ? "En" : "--",
1391 r & STATS_CTL_EN_DN ? "En" : "--");
1392
1393 for (level = 0; level < 4; level++) {
1394 u16 off;
1395
1396 off = THERMCTL_LVL0_UP_STATS;
1397 r = readl(ts->regs + THERMCTL_LVL_REG(off, level));
1398 seq_printf(s, " Level_%d Up(%d) ", level, r);
1399
1400 off = THERMCTL_LVL0_DN_STATS;
1401 r = readl(ts->regs + THERMCTL_LVL_REG(off, level));
1402 seq_printf(s, "Dn(%d)\n", r);
1403 }
1404
1405 r = readl(ts->regs + THERMCTL_THERMTRIP_CTL);
1406 state = REG_GET_MASK(r, ttgs[0]->thermtrip_any_en_mask);
1407 seq_printf(s, "Thermtrip Any En(%d)\n", state);
1408 for (i = 0; i < ts->soc->num_ttgs; i++) {
1409 state = REG_GET_MASK(r, ttgs[i]->thermtrip_enable_mask);
1410 seq_printf(s, " %s En(%d) ", ttgs[i]->name, state);
1411 state = REG_GET_MASK(r, ttgs[i]->thermtrip_threshold_mask);
1412 state *= ts->soc->thresh_grain;
1413 seq_printf(s, "Thresh(%d)\n", state);
1414 }
1415
1416 r = readl(ts->regs + THROT_GLOBAL_CFG);
1417 seq_puts(s, "\n");
1418 seq_printf(s, "GLOBAL THROTTLE CONFIG: 0x%08x\n", r);
1419
1420 seq_puts(s, "---------------------------------------------------\n");
1421 r = readl(ts->regs + THROT_STATUS);
1422 state = REG_GET_MASK(r, THROT_STATUS_BREACH_MASK);
1423 seq_printf(s, "THROT STATUS: breach(%d) ", state);
1424 state = REG_GET_MASK(r, THROT_STATUS_STATE_MASK);
1425 seq_printf(s, "state(%d) ", state);
1426 state = REG_GET_MASK(r, THROT_STATUS_ENABLED_MASK);
1427 seq_printf(s, "enabled(%d)\n", state);
1428
1429 r = readl(ts->regs + CPU_PSKIP_STATUS);
1430 if (ts->soc->use_ccroc) {
1431 state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK);
1432 seq_printf(s, "CPU PSKIP STATUS: enabled(%d)\n", state);
1433 } else {
1434 state = REG_GET_MASK(r, XPU_PSKIP_STATUS_M_MASK);
1435 seq_printf(s, "CPU PSKIP STATUS: M(%d) ", state);
1436 state = REG_GET_MASK(r, XPU_PSKIP_STATUS_N_MASK);
1437 seq_printf(s, "N(%d) ", state);
1438 state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK);
1439 seq_printf(s, "enabled(%d)\n", state);
1440 }
1441
1442 return 0;
1443 }
1444
1445 DEFINE_SHOW_ATTRIBUTE(regs);
1446
soctherm_debug_init(struct platform_device * pdev)1447 static void soctherm_debug_init(struct platform_device *pdev)
1448 {
1449 struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
1450 struct dentry *root;
1451
1452 root = debugfs_create_dir("soctherm", NULL);
1453
1454 tegra->debugfs_dir = root;
1455
1456 debugfs_create_file("reg_contents", 0644, root, pdev, ®s_fops);
1457 }
1458 #else
soctherm_debug_init(struct platform_device * pdev)1459 static inline void soctherm_debug_init(struct platform_device *pdev) {}
1460 #endif
1461
soctherm_clk_enable(struct platform_device * pdev,bool enable)1462 static int soctherm_clk_enable(struct platform_device *pdev, bool enable)
1463 {
1464 struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
1465 int err;
1466
1467 if (!tegra->clock_soctherm || !tegra->clock_tsensor)
1468 return -EINVAL;
1469
1470 reset_control_assert(tegra->reset);
1471
1472 if (enable) {
1473 err = clk_prepare_enable(tegra->clock_soctherm);
1474 if (err) {
1475 reset_control_deassert(tegra->reset);
1476 return err;
1477 }
1478
1479 err = clk_prepare_enable(tegra->clock_tsensor);
1480 if (err) {
1481 clk_disable_unprepare(tegra->clock_soctherm);
1482 reset_control_deassert(tegra->reset);
1483 return err;
1484 }
1485 } else {
1486 clk_disable_unprepare(tegra->clock_tsensor);
1487 clk_disable_unprepare(tegra->clock_soctherm);
1488 }
1489
1490 reset_control_deassert(tegra->reset);
1491
1492 return 0;
1493 }
1494
throt_get_cdev_max_state(struct thermal_cooling_device * cdev,unsigned long * max_state)1495 static int throt_get_cdev_max_state(struct thermal_cooling_device *cdev,
1496 unsigned long *max_state)
1497 {
1498 *max_state = 1;
1499 return 0;
1500 }
1501
throt_get_cdev_cur_state(struct thermal_cooling_device * cdev,unsigned long * cur_state)1502 static int throt_get_cdev_cur_state(struct thermal_cooling_device *cdev,
1503 unsigned long *cur_state)
1504 {
1505 struct tegra_soctherm *ts = cdev->devdata;
1506 u32 r;
1507
1508 r = readl(ts->regs + THROT_STATUS);
1509 if (REG_GET_MASK(r, THROT_STATUS_STATE_MASK))
1510 *cur_state = 1;
1511 else
1512 *cur_state = 0;
1513
1514 return 0;
1515 }
1516
throt_set_cdev_state(struct thermal_cooling_device * cdev,unsigned long cur_state)1517 static int throt_set_cdev_state(struct thermal_cooling_device *cdev,
1518 unsigned long cur_state)
1519 {
1520 return 0;
1521 }
1522
1523 static const struct thermal_cooling_device_ops throt_cooling_ops = {
1524 .get_max_state = throt_get_cdev_max_state,
1525 .get_cur_state = throt_get_cdev_cur_state,
1526 .set_cur_state = throt_set_cdev_state,
1527 };
1528
soctherm_thermtrips_parse(struct platform_device * pdev)1529 static int soctherm_thermtrips_parse(struct platform_device *pdev)
1530 {
1531 struct device *dev = &pdev->dev;
1532 struct tegra_soctherm *ts = dev_get_drvdata(dev);
1533 struct tsensor_group_thermtrips *tt = ts->soc->thermtrips;
1534 const int max_num_prop = ts->soc->num_ttgs * 2;
1535 u32 *tlb;
1536 int i, j, n, ret;
1537
1538 if (!tt)
1539 return -ENOMEM;
1540
1541 n = of_property_count_u32_elems(dev->of_node, "nvidia,thermtrips");
1542 if (n <= 0) {
1543 dev_info(dev,
1544 "missing thermtrips, will use critical trips as shut down temp\n");
1545 return n;
1546 }
1547
1548 n = min(max_num_prop, n);
1549
1550 tlb = devm_kcalloc(&pdev->dev, max_num_prop, sizeof(u32), GFP_KERNEL);
1551 if (!tlb)
1552 return -ENOMEM;
1553 ret = of_property_read_u32_array(dev->of_node, "nvidia,thermtrips",
1554 tlb, n);
1555 if (ret) {
1556 dev_err(dev, "invalid num ele: thermtrips:%d\n", ret);
1557 return ret;
1558 }
1559
1560 i = 0;
1561 for (j = 0; j < n; j = j + 2) {
1562 if (tlb[j] >= TEGRA124_SOCTHERM_SENSOR_NUM)
1563 continue;
1564
1565 tt[i].id = tlb[j];
1566 tt[i].temp = tlb[j + 1];
1567 i++;
1568 }
1569
1570 return 0;
1571 }
1572
soctherm_oc_cfg_parse(struct device * dev,struct device_node * np_oc,struct soctherm_throt_cfg * stc)1573 static void soctherm_oc_cfg_parse(struct device *dev,
1574 struct device_node *np_oc,
1575 struct soctherm_throt_cfg *stc)
1576 {
1577 u32 val;
1578
1579 if (of_property_read_bool(np_oc, "nvidia,polarity-active-low"))
1580 stc->oc_cfg.active_low = 1;
1581 else
1582 stc->oc_cfg.active_low = 0;
1583
1584 if (!of_property_read_u32(np_oc, "nvidia,count-threshold", &val)) {
1585 stc->oc_cfg.intr_en = 1;
1586 stc->oc_cfg.alarm_cnt_thresh = val;
1587 }
1588
1589 if (!of_property_read_u32(np_oc, "nvidia,throttle-period-us", &val))
1590 stc->oc_cfg.throt_period = val;
1591
1592 if (!of_property_read_u32(np_oc, "nvidia,alarm-filter", &val))
1593 stc->oc_cfg.alarm_filter = val;
1594
1595 /* BRIEF throttling by default, do not support STICKY */
1596 stc->oc_cfg.mode = OC_THROTTLE_MODE_BRIEF;
1597 }
1598
soctherm_throt_cfg_parse(struct device * dev,struct device_node * np,struct soctherm_throt_cfg * stc)1599 static int soctherm_throt_cfg_parse(struct device *dev,
1600 struct device_node *np,
1601 struct soctherm_throt_cfg *stc)
1602 {
1603 struct tegra_soctherm *ts = dev_get_drvdata(dev);
1604 int ret;
1605 u32 val;
1606
1607 ret = of_property_read_u32(np, "nvidia,priority", &val);
1608 if (ret) {
1609 dev_err(dev, "throttle-cfg: %s: invalid priority\n", stc->name);
1610 return -EINVAL;
1611 }
1612 stc->priority = val;
1613
1614 ret = of_property_read_u32(np, ts->soc->use_ccroc ?
1615 "nvidia,cpu-throt-level" :
1616 "nvidia,cpu-throt-percent", &val);
1617 if (!ret) {
1618 if (ts->soc->use_ccroc &&
1619 val <= TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
1620 stc->cpu_throt_level = val;
1621 else if (!ts->soc->use_ccroc && val <= 100)
1622 stc->cpu_throt_depth = val;
1623 else
1624 goto err;
1625 } else {
1626 goto err;
1627 }
1628
1629 ret = of_property_read_u32(np, "nvidia,gpu-throt-level", &val);
1630 if (!ret && val <= TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
1631 stc->gpu_throt_level = val;
1632 else
1633 goto err;
1634
1635 return 0;
1636
1637 err:
1638 dev_err(dev, "throttle-cfg: %s: no throt prop or invalid prop\n",
1639 stc->name);
1640 return -EINVAL;
1641 }
1642
1643 /**
1644 * soctherm_init_hw_throt_cdev() - Parse the HW throttle configurations
1645 * and register them as cooling devices.
1646 * @pdev: Pointer to platform_device struct
1647 */
soctherm_init_hw_throt_cdev(struct platform_device * pdev)1648 static void soctherm_init_hw_throt_cdev(struct platform_device *pdev)
1649 {
1650 struct device *dev = &pdev->dev;
1651 struct tegra_soctherm *ts = dev_get_drvdata(dev);
1652 struct device_node *np_stc;
1653 const char *name;
1654 int i;
1655
1656 for (i = 0; i < THROTTLE_SIZE; i++) {
1657 ts->throt_cfgs[i].name = throt_names[i];
1658 ts->throt_cfgs[i].id = i;
1659 ts->throt_cfgs[i].init = false;
1660 }
1661
1662 np_stc = of_get_child_by_name(dev->of_node, "throttle-cfgs");
1663 if (!np_stc) {
1664 dev_info(dev,
1665 "throttle-cfg: no throttle-cfgs - not enabling\n");
1666 return;
1667 }
1668
1669 for_each_child_of_node_scoped(np_stc, np_stcc) {
1670 struct soctherm_throt_cfg *stc;
1671 struct thermal_cooling_device *tcd;
1672 int err;
1673
1674 name = np_stcc->name;
1675 stc = find_throttle_cfg_by_name(ts, name);
1676 if (!stc) {
1677 dev_err(dev,
1678 "throttle-cfg: could not find %s\n", name);
1679 continue;
1680 }
1681
1682 if (stc->init) {
1683 dev_err(dev, "throttle-cfg: %s: redefined!\n", name);
1684 break;
1685 }
1686
1687 err = soctherm_throt_cfg_parse(dev, np_stcc, stc);
1688 if (err)
1689 continue;
1690
1691 if (stc->id >= THROTTLE_OC1) {
1692 soctherm_oc_cfg_parse(dev, np_stcc, stc);
1693 stc->init = true;
1694 } else {
1695
1696 tcd = thermal_of_cooling_device_register(np_stcc,
1697 (char *)name, ts,
1698 &throt_cooling_ops);
1699 if (IS_ERR_OR_NULL(tcd)) {
1700 dev_err(dev,
1701 "throttle-cfg: %s: failed to register cooling device\n",
1702 name);
1703 continue;
1704 }
1705 stc->cdev = tcd;
1706 stc->init = true;
1707 }
1708
1709 }
1710
1711 of_node_put(np_stc);
1712 }
1713
1714 /**
1715 * throttlectl_cpu_level_cfg() - programs CCROC NV_THERM level config
1716 * @ts: pointer to a struct tegra_soctherm
1717 * @level: describing the level LOW/MED/HIGH of throttling
1718 *
1719 * It's necessary to set up the CPU-local CCROC NV_THERM instance with
1720 * the M/N values desired for each level. This function does this.
1721 *
1722 * This function pre-programs the CCROC NV_THERM levels in terms of
1723 * pre-configured "Low", "Medium" or "Heavy" throttle levels which are
1724 * mapped to THROT_LEVEL_LOW, THROT_LEVEL_MED and THROT_LEVEL_HVY.
1725 */
throttlectl_cpu_level_cfg(struct tegra_soctherm * ts,int level)1726 static void throttlectl_cpu_level_cfg(struct tegra_soctherm *ts, int level)
1727 {
1728 u8 depth, dividend;
1729 u32 r;
1730
1731 switch (level) {
1732 case TEGRA_SOCTHERM_THROT_LEVEL_LOW:
1733 depth = 50;
1734 break;
1735 case TEGRA_SOCTHERM_THROT_LEVEL_MED:
1736 depth = 75;
1737 break;
1738 case TEGRA_SOCTHERM_THROT_LEVEL_HIGH:
1739 depth = 80;
1740 break;
1741 case TEGRA_SOCTHERM_THROT_LEVEL_NONE:
1742 return;
1743 default:
1744 return;
1745 }
1746
1747 dividend = THROT_DEPTH_DIVIDEND(depth);
1748
1749 /* setup PSKIP in ccroc nv_therm registers */
1750 r = ccroc_readl(ts, CCROC_THROT_PSKIP_RAMP_CPU_REG(level));
1751 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_DURATION_MASK, 0xff);
1752 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_STEP_MASK, 0xf);
1753 ccroc_writel(ts, r, CCROC_THROT_PSKIP_RAMP_CPU_REG(level));
1754
1755 r = ccroc_readl(ts, CCROC_THROT_PSKIP_CTRL_CPU_REG(level));
1756 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_ENB_MASK, 1);
1757 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend);
1758 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff);
1759 ccroc_writel(ts, r, CCROC_THROT_PSKIP_CTRL_CPU_REG(level));
1760 }
1761
1762 /**
1763 * throttlectl_cpu_level_select() - program CPU pulse skipper config
1764 * @ts: pointer to a struct tegra_soctherm
1765 * @throt: the LIGHT/HEAVY of throttle event id
1766 *
1767 * Pulse skippers are used to throttle clock frequencies. This
1768 * function programs the pulse skippers based on @throt and platform
1769 * data. This function is used on SoCs which have CPU-local pulse
1770 * skipper control, such as T13x. It programs soctherm's interface to
1771 * Denver:CCROC NV_THERM in terms of Low, Medium and HIGH throttling
1772 * vectors. PSKIP_BYPASS mode is set as required per HW spec.
1773 */
throttlectl_cpu_level_select(struct tegra_soctherm * ts,enum soctherm_throttle_id throt)1774 static void throttlectl_cpu_level_select(struct tegra_soctherm *ts,
1775 enum soctherm_throttle_id throt)
1776 {
1777 u32 r, throt_vect;
1778
1779 /* Denver:CCROC NV_THERM interface N:3 Mapping */
1780 switch (ts->throt_cfgs[throt].cpu_throt_level) {
1781 case TEGRA_SOCTHERM_THROT_LEVEL_LOW:
1782 throt_vect = THROT_VECT_LOW;
1783 break;
1784 case TEGRA_SOCTHERM_THROT_LEVEL_MED:
1785 throt_vect = THROT_VECT_MED;
1786 break;
1787 case TEGRA_SOCTHERM_THROT_LEVEL_HIGH:
1788 throt_vect = THROT_VECT_HIGH;
1789 break;
1790 default:
1791 throt_vect = THROT_VECT_NONE;
1792 break;
1793 }
1794
1795 r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
1796 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
1797 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_CPU_MASK, throt_vect);
1798 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT2_CPU_MASK, throt_vect);
1799 writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
1800
1801 /* bypass sequencer in soc_therm as it is programmed in ccroc */
1802 r = REG_SET_MASK(0, THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK, 1);
1803 writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
1804 }
1805
1806 /**
1807 * throttlectl_cpu_mn() - program CPU pulse skipper configuration
1808 * @ts: pointer to a struct tegra_soctherm
1809 * @throt: the LIGHT/HEAVY of throttle event id
1810 *
1811 * Pulse skippers are used to throttle clock frequencies. This
1812 * function programs the pulse skippers based on @throt and platform
1813 * data. This function is used for CPUs that have "remote" pulse
1814 * skipper control, e.g., the CPU pulse skipper is controlled by the
1815 * SOC_THERM IP block. (SOC_THERM is located outside the CPU
1816 * complex.)
1817 */
throttlectl_cpu_mn(struct tegra_soctherm * ts,enum soctherm_throttle_id throt)1818 static void throttlectl_cpu_mn(struct tegra_soctherm *ts,
1819 enum soctherm_throttle_id throt)
1820 {
1821 u32 r;
1822 int depth;
1823 u8 dividend;
1824
1825 depth = ts->throt_cfgs[throt].cpu_throt_depth;
1826 dividend = THROT_DEPTH_DIVIDEND(depth);
1827
1828 r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
1829 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
1830 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend);
1831 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff);
1832 writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
1833
1834 r = readl(ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
1835 r = REG_SET_MASK(r, THROT_PSKIP_RAMP_DURATION_MASK, 0xff);
1836 r = REG_SET_MASK(r, THROT_PSKIP_RAMP_STEP_MASK, 0xf);
1837 writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
1838 }
1839
1840 /**
1841 * throttlectl_gpu_level_select() - selects throttling level for GPU
1842 * @ts: pointer to a struct tegra_soctherm
1843 * @throt: the LIGHT/HEAVY of throttle event id
1844 *
1845 * This function programs soctherm's interface to GK20a NV_THERM to select
1846 * pre-configured "Low", "Medium" or "Heavy" throttle levels.
1847 *
1848 * Return: boolean true if HW was programmed
1849 */
throttlectl_gpu_level_select(struct tegra_soctherm * ts,enum soctherm_throttle_id throt)1850 static void throttlectl_gpu_level_select(struct tegra_soctherm *ts,
1851 enum soctherm_throttle_id throt)
1852 {
1853 u32 r, level, throt_vect;
1854
1855 level = ts->throt_cfgs[throt].gpu_throt_level;
1856 throt_vect = THROT_LEVEL_TO_DEPTH(level);
1857 r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));
1858 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
1859 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_GPU_MASK, throt_vect);
1860 writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));
1861 }
1862
soctherm_oc_cfg_program(struct tegra_soctherm * ts,enum soctherm_throttle_id throt)1863 static int soctherm_oc_cfg_program(struct tegra_soctherm *ts,
1864 enum soctherm_throttle_id throt)
1865 {
1866 u32 r;
1867 struct soctherm_oc_cfg *oc = &ts->throt_cfgs[throt].oc_cfg;
1868
1869 if (oc->mode == OC_THROTTLE_MODE_DISABLED)
1870 return -EINVAL;
1871
1872 r = REG_SET_MASK(0, OC1_CFG_HW_RESTORE_MASK, 1);
1873 r = REG_SET_MASK(r, OC1_CFG_THROTTLE_MODE_MASK, oc->mode);
1874 r = REG_SET_MASK(r, OC1_CFG_ALARM_POLARITY_MASK, oc->active_low);
1875 r = REG_SET_MASK(r, OC1_CFG_EN_THROTTLE_MASK, 1);
1876 writel(r, ts->regs + ALARM_CFG(throt));
1877 writel(oc->throt_period, ts->regs + ALARM_THROTTLE_PERIOD(throt));
1878 writel(oc->alarm_cnt_thresh, ts->regs + ALARM_CNT_THRESHOLD(throt));
1879 writel(oc->alarm_filter, ts->regs + ALARM_FILTER(throt));
1880 soctherm_oc_intr_enable(ts, throt, oc->intr_en);
1881
1882 return 0;
1883 }
1884
1885 /**
1886 * soctherm_throttle_program() - programs pulse skippers' configuration
1887 * @ts: pointer to a struct tegra_soctherm
1888 * @throt: the LIGHT/HEAVY of the throttle event id.
1889 *
1890 * Pulse skippers are used to throttle clock frequencies.
1891 * This function programs the pulse skippers.
1892 */
soctherm_throttle_program(struct tegra_soctherm * ts,enum soctherm_throttle_id throt)1893 static void soctherm_throttle_program(struct tegra_soctherm *ts,
1894 enum soctherm_throttle_id throt)
1895 {
1896 u32 r;
1897 struct soctherm_throt_cfg stc = ts->throt_cfgs[throt];
1898
1899 if (!stc.init)
1900 return;
1901
1902 if ((throt >= THROTTLE_OC1) && (soctherm_oc_cfg_program(ts, throt)))
1903 return;
1904
1905 /* Setup PSKIP parameters */
1906 if (ts->soc->use_ccroc)
1907 throttlectl_cpu_level_select(ts, throt);
1908 else
1909 throttlectl_cpu_mn(ts, throt);
1910
1911 throttlectl_gpu_level_select(ts, throt);
1912
1913 r = REG_SET_MASK(0, THROT_PRIORITY_LITE_PRIO_MASK, stc.priority);
1914 writel(r, ts->regs + THROT_PRIORITY_CTRL(throt));
1915
1916 r = REG_SET_MASK(0, THROT_DELAY_LITE_DELAY_MASK, 0);
1917 writel(r, ts->regs + THROT_DELAY_CTRL(throt));
1918
1919 r = readl(ts->regs + THROT_PRIORITY_LOCK);
1920 r = REG_GET_MASK(r, THROT_PRIORITY_LOCK_PRIORITY_MASK);
1921 if (r >= stc.priority)
1922 return;
1923 r = REG_SET_MASK(0, THROT_PRIORITY_LOCK_PRIORITY_MASK,
1924 stc.priority);
1925 writel(r, ts->regs + THROT_PRIORITY_LOCK);
1926 }
1927
tegra_soctherm_throttle(struct device * dev)1928 static void tegra_soctherm_throttle(struct device *dev)
1929 {
1930 struct tegra_soctherm *ts = dev_get_drvdata(dev);
1931 u32 v;
1932 int i;
1933
1934 /* configure LOW, MED and HIGH levels for CCROC NV_THERM */
1935 if (ts->soc->use_ccroc) {
1936 throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_LOW);
1937 throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_MED);
1938 throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_HIGH);
1939 }
1940
1941 /* Thermal HW throttle programming */
1942 for (i = 0; i < THROTTLE_SIZE; i++)
1943 soctherm_throttle_program(ts, i);
1944
1945 v = REG_SET_MASK(0, THROT_GLOBAL_ENB_MASK, 1);
1946 if (ts->soc->use_ccroc) {
1947 ccroc_writel(ts, v, CCROC_GLOBAL_CFG);
1948
1949 v = ccroc_readl(ts, CCROC_SUPER_CCLKG_DIVIDER);
1950 v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1);
1951 ccroc_writel(ts, v, CCROC_SUPER_CCLKG_DIVIDER);
1952 } else {
1953 writel(v, ts->regs + THROT_GLOBAL_CFG);
1954
1955 v = readl(ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER);
1956 v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1);
1957 writel(v, ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER);
1958 }
1959
1960 /* initialize stats collection */
1961 v = STATS_CTL_CLR_DN | STATS_CTL_EN_DN |
1962 STATS_CTL_CLR_UP | STATS_CTL_EN_UP;
1963 writel(v, ts->regs + THERMCTL_STATS_CTL);
1964 }
1965
soctherm_interrupts_init(struct platform_device * pdev,struct tegra_soctherm * tegra)1966 static int soctherm_interrupts_init(struct platform_device *pdev,
1967 struct tegra_soctherm *tegra)
1968 {
1969 int ret;
1970
1971 ret = soctherm_oc_int_init(dev_fwnode(&pdev->dev), TEGRA_SOC_OC_IRQ_MAX);
1972 if (ret < 0) {
1973 dev_err(&pdev->dev, "soctherm_oc_int_init failed\n");
1974 return ret;
1975 }
1976
1977 tegra->thermal_irq = platform_get_irq(pdev, 0);
1978 if (tegra->thermal_irq < 0) {
1979 dev_dbg(&pdev->dev, "get 'thermal_irq' failed.\n");
1980 return 0;
1981 }
1982
1983 tegra->edp_irq = platform_get_irq(pdev, 1);
1984 if (tegra->edp_irq < 0) {
1985 dev_dbg(&pdev->dev, "get 'edp_irq' failed.\n");
1986 return 0;
1987 }
1988
1989 ret = devm_request_threaded_irq(&pdev->dev,
1990 tegra->thermal_irq,
1991 soctherm_thermal_isr,
1992 soctherm_thermal_isr_thread,
1993 IRQF_ONESHOT,
1994 dev_name(&pdev->dev),
1995 tegra);
1996 if (ret < 0) {
1997 dev_err(&pdev->dev, "request_irq 'thermal_irq' failed.\n");
1998 return ret;
1999 }
2000
2001 ret = devm_request_threaded_irq(&pdev->dev,
2002 tegra->edp_irq,
2003 soctherm_edp_isr,
2004 soctherm_edp_isr_thread,
2005 IRQF_ONESHOT,
2006 "soctherm_edp",
2007 tegra);
2008 if (ret < 0) {
2009 dev_err(&pdev->dev, "request_irq 'edp_irq' failed.\n");
2010 return ret;
2011 }
2012
2013 return 0;
2014 }
2015
soctherm_init(struct platform_device * pdev)2016 static void soctherm_init(struct platform_device *pdev)
2017 {
2018 struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
2019 const struct tegra_tsensor_group **ttgs = tegra->soc->ttgs;
2020 int i;
2021 u32 pdiv, hotspot;
2022
2023 /* Initialize raw sensors */
2024 for (i = 0; i < tegra->soc->num_tsensors; ++i)
2025 enable_tsensor(tegra, i);
2026
2027 /* program pdiv and hotspot offsets per THERM */
2028 pdiv = readl(tegra->regs + SENSOR_PDIV);
2029 hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
2030 for (i = 0; i < tegra->soc->num_ttgs; ++i) {
2031 pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask,
2032 ttgs[i]->pdiv);
2033 /* hotspot offset from PLLX, doesn't need to configure PLLX */
2034 if (ttgs[i]->id == TEGRA124_SOCTHERM_SENSOR_PLLX)
2035 continue;
2036 hotspot = REG_SET_MASK(hotspot,
2037 ttgs[i]->pllx_hotspot_mask,
2038 ttgs[i]->pllx_hotspot_diff);
2039 }
2040 writel(pdiv, tegra->regs + SENSOR_PDIV);
2041 writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
2042
2043 /* Configure hw throttle */
2044 tegra_soctherm_throttle(&pdev->dev);
2045 }
2046
2047 static const struct of_device_id tegra_soctherm_of_match[] = {
2048 #ifdef CONFIG_ARCH_TEGRA_124_SOC
2049 {
2050 .compatible = "nvidia,tegra124-soctherm",
2051 .data = &tegra124_soctherm,
2052 },
2053 #endif
2054 #ifdef CONFIG_ARCH_TEGRA_132_SOC
2055 {
2056 .compatible = "nvidia,tegra132-soctherm",
2057 .data = &tegra132_soctherm,
2058 },
2059 #endif
2060 #ifdef CONFIG_ARCH_TEGRA_210_SOC
2061 {
2062 .compatible = "nvidia,tegra210-soctherm",
2063 .data = &tegra210_soctherm,
2064 },
2065 #endif
2066 { },
2067 };
2068 MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
2069
tegra_soctherm_probe(struct platform_device * pdev)2070 static int tegra_soctherm_probe(struct platform_device *pdev)
2071 {
2072 const struct of_device_id *match;
2073 struct tegra_soctherm *tegra;
2074 struct thermal_zone_device *z;
2075 struct tsensor_shared_calib shared_calib;
2076 struct tegra_soctherm_soc *soc;
2077 unsigned int i;
2078 int err;
2079
2080 match = of_match_node(tegra_soctherm_of_match, pdev->dev.of_node);
2081 if (!match)
2082 return -ENODEV;
2083
2084 soc = (struct tegra_soctherm_soc *)match->data;
2085 if (soc->num_ttgs > TEGRA124_SOCTHERM_SENSOR_NUM)
2086 return -EINVAL;
2087
2088 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
2089 if (!tegra)
2090 return -ENOMEM;
2091
2092 mutex_init(&tegra->thermctl_lock);
2093 dev_set_drvdata(&pdev->dev, tegra);
2094
2095 tegra->soc = soc;
2096
2097 tegra->regs = devm_platform_ioremap_resource_byname(pdev, "soctherm-reg");
2098 if (IS_ERR(tegra->regs)) {
2099 dev_err(&pdev->dev, "can't get soctherm registers");
2100 return PTR_ERR(tegra->regs);
2101 }
2102
2103 if (!tegra->soc->use_ccroc) {
2104 tegra->clk_regs = devm_platform_ioremap_resource_byname(pdev, "car-reg");
2105 if (IS_ERR(tegra->clk_regs)) {
2106 dev_err(&pdev->dev, "can't get car clk registers");
2107 return PTR_ERR(tegra->clk_regs);
2108 }
2109 } else {
2110 tegra->ccroc_regs = devm_platform_ioremap_resource_byname(pdev, "ccroc-reg");
2111 if (IS_ERR(tegra->ccroc_regs)) {
2112 dev_err(&pdev->dev, "can't get ccroc registers");
2113 return PTR_ERR(tegra->ccroc_regs);
2114 }
2115 }
2116
2117 tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");
2118 if (IS_ERR(tegra->reset)) {
2119 dev_err(&pdev->dev, "can't get soctherm reset\n");
2120 return PTR_ERR(tegra->reset);
2121 }
2122
2123 tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor");
2124 if (IS_ERR(tegra->clock_tsensor)) {
2125 dev_err(&pdev->dev, "can't get tsensor clock\n");
2126 return PTR_ERR(tegra->clock_tsensor);
2127 }
2128
2129 tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm");
2130 if (IS_ERR(tegra->clock_soctherm)) {
2131 dev_err(&pdev->dev, "can't get soctherm clock\n");
2132 return PTR_ERR(tegra->clock_soctherm);
2133 }
2134
2135 tegra->calib = devm_kcalloc(&pdev->dev,
2136 soc->num_tsensors, sizeof(u32),
2137 GFP_KERNEL);
2138 if (!tegra->calib)
2139 return -ENOMEM;
2140
2141 /* calculate shared calibration data */
2142 err = tegra_calc_shared_calib(soc->tfuse, &shared_calib);
2143 if (err)
2144 return err;
2145
2146 /* calculate tsensor calibration data */
2147 for (i = 0; i < soc->num_tsensors; ++i) {
2148 err = tegra_calc_tsensor_calib(&soc->tsensors[i],
2149 &shared_calib,
2150 &tegra->calib[i]);
2151 if (err)
2152 return err;
2153 }
2154
2155 tegra->thermctl_tzs = devm_kcalloc(&pdev->dev,
2156 soc->num_ttgs, sizeof(z),
2157 GFP_KERNEL);
2158 if (!tegra->thermctl_tzs)
2159 return -ENOMEM;
2160
2161 err = soctherm_clk_enable(pdev, true);
2162 if (err)
2163 return err;
2164
2165 soctherm_thermtrips_parse(pdev);
2166
2167 soctherm_init_hw_throt_cdev(pdev);
2168
2169 soctherm_init(pdev);
2170
2171 for (i = 0; i < soc->num_ttgs; ++i) {
2172 struct tegra_thermctl_zone *zone =
2173 devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
2174 if (!zone) {
2175 err = -ENOMEM;
2176 goto disable_clocks;
2177 }
2178
2179 zone->reg = tegra->regs + soc->ttgs[i]->sensor_temp_offset;
2180 zone->dev = &pdev->dev;
2181 zone->sg = soc->ttgs[i];
2182 zone->ts = tegra;
2183
2184 z = devm_thermal_of_zone_register(&pdev->dev,
2185 soc->ttgs[i]->id, zone,
2186 &tegra_of_thermal_ops);
2187 if (IS_ERR(z)) {
2188 err = PTR_ERR(z);
2189 dev_err(&pdev->dev, "failed to register sensor: %d\n",
2190 err);
2191 goto disable_clocks;
2192 }
2193
2194 zone->tz = z;
2195 tegra->thermctl_tzs[soc->ttgs[i]->id] = z;
2196
2197 /* Configure hw trip points */
2198 err = tegra_soctherm_set_hwtrips(&pdev->dev, soc->ttgs[i], z);
2199 if (err)
2200 goto disable_clocks;
2201 }
2202
2203 err = soctherm_interrupts_init(pdev, tegra);
2204
2205 soctherm_debug_init(pdev);
2206
2207 return 0;
2208
2209 disable_clocks:
2210 soctherm_clk_enable(pdev, false);
2211
2212 return err;
2213 }
2214
tegra_soctherm_remove(struct platform_device * pdev)2215 static void tegra_soctherm_remove(struct platform_device *pdev)
2216 {
2217 struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
2218
2219 debugfs_remove_recursive(tegra->debugfs_dir);
2220
2221 soctherm_clk_enable(pdev, false);
2222 }
2223
soctherm_suspend(struct device * dev)2224 static int __maybe_unused soctherm_suspend(struct device *dev)
2225 {
2226 struct platform_device *pdev = to_platform_device(dev);
2227
2228 soctherm_clk_enable(pdev, false);
2229
2230 return 0;
2231 }
2232
soctherm_resume(struct device * dev)2233 static int __maybe_unused soctherm_resume(struct device *dev)
2234 {
2235 struct platform_device *pdev = to_platform_device(dev);
2236 struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
2237 struct tegra_soctherm_soc *soc = tegra->soc;
2238 int err, i;
2239
2240 err = soctherm_clk_enable(pdev, true);
2241 if (err) {
2242 dev_err(&pdev->dev,
2243 "Resume failed: enable clocks failed\n");
2244 return err;
2245 }
2246
2247 soctherm_init(pdev);
2248
2249 for (i = 0; i < soc->num_ttgs; ++i) {
2250 struct thermal_zone_device *tz;
2251
2252 tz = tegra->thermctl_tzs[soc->ttgs[i]->id];
2253 err = tegra_soctherm_set_hwtrips(dev, soc->ttgs[i], tz);
2254 if (err) {
2255 dev_err(&pdev->dev,
2256 "Resume failed: set hwtrips failed\n");
2257 return err;
2258 }
2259 }
2260
2261 return 0;
2262 }
2263
2264 static SIMPLE_DEV_PM_OPS(tegra_soctherm_pm, soctherm_suspend, soctherm_resume);
2265
2266 static struct platform_driver tegra_soctherm_driver = {
2267 .probe = tegra_soctherm_probe,
2268 .remove = tegra_soctherm_remove,
2269 .driver = {
2270 .name = "tegra_soctherm",
2271 .pm = &tegra_soctherm_pm,
2272 .of_match_table = tegra_soctherm_of_match,
2273 },
2274 };
2275 module_platform_driver(tegra_soctherm_driver);
2276
2277 MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
2278 MODULE_DESCRIPTION("NVIDIA Tegra SOCTHERM thermal management driver");
2279 MODULE_LICENSE("GPL v2");
2280