1 /*-
2 * Copyright (c) 2015 The FreeBSD Foundation
3 *
4 * This software was developed by Semihalf under
5 * the sponsorship of the FreeBSD Foundation.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /* Common PCIe functions for Cavium Thunder SOC */
30
31 #include <sys/cdefs.h>
32 #include "opt_platform.h"
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/bus.h>
39 #include <sys/rman.h>
40
41 #include <machine/bus.h>
42 #include <machine/cpu.h>
43 #include <machine/intr.h>
44
45 #ifdef FDT
46 #include <dev/ofw/openfirm.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
49 #include <dev/ofw/ofw_pci.h>
50 #endif
51
52 #include <sys/pciio.h>
53 #include <dev/pci/pcireg.h>
54 #include <dev/pci/pcivar.h>
55 #include <dev/pci/pci_private.h>
56 #include <dev/pci/pcib_private.h>
57 #include <dev/pci/pci_host_generic.h>
58 #ifdef FDT
59 #include <dev/pci/pci_host_generic_fdt.h>
60 #endif
61
62 #include "thunder_pcie_common.h"
63
64 MALLOC_DEFINE(M_THUNDER_PCIE, "Thunder PCIe driver", "Thunder PCIe driver memory");
65
66 #define THUNDER_CFG_BASE_TO_ECAM(x) ((((x) >> 36UL) & 0x3) | (((x) >> 42UL) & 0x4))
67
68 uint32_t
range_addr_is_pci(struct pcie_range * ranges,uint64_t addr,uint64_t size)69 range_addr_is_pci(struct pcie_range *ranges, uint64_t addr, uint64_t size)
70 {
71 struct pcie_range *r;
72 int tuple;
73
74 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
75 r = &ranges[tuple];
76 if (addr >= r->pci_base &&
77 addr < (r->pci_base + r->size) &&
78 size < r->size) {
79 /* Address is within PCI range */
80 return (1);
81 }
82 }
83
84 /* Address is outside PCI range */
85 return (0);
86 }
87
88 uint32_t
range_addr_is_phys(struct pcie_range * ranges,uint64_t addr,uint64_t size)89 range_addr_is_phys(struct pcie_range *ranges, uint64_t addr, uint64_t size)
90 {
91 struct pcie_range *r;
92 int tuple;
93
94 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
95 r = &ranges[tuple];
96 if (addr >= r->phys_base &&
97 addr < (r->phys_base + r->size) &&
98 size < r->size) {
99 /* Address is within Physical range */
100 return (1);
101 }
102 }
103
104 /* Address is outside Physical range */
105 return (0);
106 }
107
108 uint64_t
range_addr_phys_to_pci(struct pcie_range * ranges,uint64_t phys_addr)109 range_addr_phys_to_pci(struct pcie_range *ranges, uint64_t phys_addr)
110 {
111 struct pcie_range *r;
112 uint64_t offset;
113 int tuple;
114
115 /* Find physical address corresponding to given bus address */
116 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
117 r = &ranges[tuple];
118 if (phys_addr >= r->phys_base &&
119 phys_addr < (r->phys_base + r->size)) {
120 /* Given phys addr is in this range.
121 * Translate phys addr to bus addr.
122 */
123 offset = phys_addr - r->phys_base;
124 return (r->pci_base + offset);
125 }
126 }
127 return (0);
128 }
129
130 uint64_t
range_addr_pci_to_phys(struct pcie_range * ranges,uint64_t pci_addr)131 range_addr_pci_to_phys(struct pcie_range *ranges, uint64_t pci_addr)
132 {
133 struct pcie_range *r;
134 uint64_t offset;
135 int tuple;
136
137 /* Find physical address corresponding to given bus address */
138 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
139 r = &ranges[tuple];
140 if (pci_addr >= r->pci_base &&
141 pci_addr < (r->pci_base + r->size)) {
142 /* Given pci addr is in this range.
143 * Translate bus addr to phys addr.
144 */
145 offset = pci_addr - r->pci_base;
146 return (r->phys_base + offset);
147 }
148 }
149 return (0);
150 }
151
152 int
thunder_pcie_identify_ecam(device_t dev,int * ecam)153 thunder_pcie_identify_ecam(device_t dev, int *ecam)
154 {
155 rman_res_t start;
156
157 /* Check if we're running on Cavium ThunderX */
158 if (!CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
159 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, 0))
160 return (EINVAL);
161
162 start = bus_get_resource_start(dev, SYS_RES_MEMORY, 0);
163 *ecam = THUNDER_CFG_BASE_TO_ECAM(start);
164
165 device_printf(dev, "ThunderX quirk, setting ECAM to %d\n", *ecam);
166
167 return (0);
168 }
169
170 #ifdef THUNDERX_PASS_1_1_ERRATA
171 struct resource *
thunder_pcie_alloc_resource(device_t dev,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)172 thunder_pcie_alloc_resource(device_t dev, device_t child, int type, int *rid,
173 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
174 {
175 pci_addr_t map, testval;
176
177 /*
178 * If Enhanced Allocation is not used, we can't allocate any random
179 * range. All internal devices have hardcoded place where they can
180 * be located within PCI address space. Fortunately, we can read
181 * this value from BAR.
182 */
183 if (((type == SYS_RES_IOPORT) || (type == SYS_RES_MEMORY)) &&
184 RMAN_IS_DEFAULT_RANGE(start, end)) {
185 /* Read BAR manually to get resource address and size */
186 pci_read_bar(child, *rid, &map, &testval, NULL);
187
188 /* Mask the information bits */
189 if (PCI_BAR_MEM(map))
190 map &= PCIM_BAR_MEM_BASE;
191 else
192 map &= PCIM_BAR_IO_BASE;
193
194 if (PCI_BAR_MEM(testval))
195 testval &= PCIM_BAR_MEM_BASE;
196 else
197 testval &= PCIM_BAR_IO_BASE;
198
199 start = map;
200 end = start + count - 1;
201 }
202
203 return (pci_host_generic_core_alloc_resource(dev, child, type, rid,
204 start, end, count, flags));
205 }
206 #endif
207