xref: /illumos-gate/usr/src/uts/common/io/cxgbe/common/t4_extra_regs.h (revision c990198d76d849d7844c4637a3158c1432cce551)
1 /*
2  * This file and its contents are supplied under the terms of the
3  * Common Development and Distribution License ("CDDL"), version 1.0.
4  * You may only use this file in accordance with the terms of version
5  * 1.0 of the CDDL.
6  *
7  * A full copy of the text of the CDDL should have accompanied this
8  * source.  A copy of the CDDL is also available via the Internet at
9  * http://www.illumos.org/license/CDDL.
10  */
11 
12 /*
13  * Copyright 2023 Oxide Computer Company
14  */
15 
16 #ifndef _T4_EXTRA_REGS_H
17 #define	_T4_EXTRA_REGS_H
18 
19 /*
20  * Additional registers not present in the current auto-generated t4_regs.h.
21  */
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 /*
28  * RS FEC error count registers. These are 16-bit counters. The low register
29  * must be read first. These are clear on read registers.
30  */
31 #define	T6_RS_FEC_CCW_LO	0x2208
32 #define	T6_RS_FEC_CCW_HI	0x220c
33 #define	T6_RS_FEC_NCCW_LO	0x2210
34 #define	T6_RS_FEC_NCCW_HI	0x2214
35 
36 #define	T6_RS_FEC_SYMERR0_LO	0x2228
37 #define	T6_RS_FEC_SYMERR0_HI	0x222c
38 #define	T6_RS_FEC_SYMERR1_LO	0x2230
39 #define	T6_RS_FEC_SYMERR1_HI	0x2234
40 #define	T6_RS_FEC_SYMERR2_LO	0x2238
41 #define	T6_RS_FEC_SYMERR2_HI	0x223c
42 #define	T6_RS_FEC_SYMERR3_LO	0x2240
43 #define	T6_RS_FEC_SYMERR3_HI	0x2244
44 
45 /*
46  * Firecode / BASE-R FEC registers. These only exist per-lane. There is a pair
47  * of registers for both correctable and uncorrectable errors. These are also
48  * clear on read registers.
49  */
50 #define	T6_FC_FEC_L0_CERR_LO	0x2624
51 #define	T6_FC_FEC_L0_CERR_HI	0x2628
52 #define	T6_FC_FEC_L0_NCERR_LO	0x262c
53 #define	T6_FC_FEC_L0_NCERR_HI	0x2630
54 
55 #define	T6_FC_FEC_L1_CERR_LO	0x2668
56 #define	T6_FC_FEC_L1_CERR_HI	0x266c
57 #define	T6_FC_FEC_L1_NCERR_LO	0x2670
58 #define	T6_FC_FEC_L1_NCERR_HI	0x2674
59 
60 #define	T6_FC_FEC_L2_CERR_LO	0x26ac
61 #define	T6_FC_FEC_L2_CERR_HI	0x26b0
62 #define	T6_FC_FEC_L2_NCERR_LO	0x26b4
63 #define	T6_FC_FEC_L2_NCERR_HI	0x26b8
64 
65 #define	T6_FC_FEC_L3_CERR_LO	0x26f0
66 #define	T6_FC_FEC_L3_CERR_HI	0x26f4
67 #define	T6_FC_FEC_L3_NCERR_LO	0x26f8
68 #define	T6_FC_FEC_L3_NCERR_HI	0x26fc
69 
70 #ifdef __cplusplus
71 }
72 #endif
73 
74 #endif /* _T4_EXTRA_REGS_H */
75