| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenInstAlias.cpp | 234 for (unsigned SubOp = 0; SubOp != NumSubOps; ++SubOp) { in CodeGenInstAlias() local
254 for (unsigned SubOp = 0; SubOp != NumSubOps; ++SubOp) { in CodeGenInstAlias() local
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| H A D | CodeGenInstruction.cpp | 249 if (auto SubOp = findSubOperandAlias(OpName)) { in ParseOperandName() local
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CompressInstEmitter.cpp | 237 for (unsigned SubOp = 0; SubOp != Opnd.MINumOperands; ++SubOp, ++OpNo) { in addDagOperandMapping() local
408 for (unsigned SubOp = 0; SubOp != Operand.MINumOperands; ++SubOp, ++OpNo) { in createInstOperandMapping() local
761 for (unsigned SubOp = 0; SubOp != SourceOperand.MINumOperands; ++SubOp) { in emitCompressInstEmitter() local
793 for (unsigned SubOp = 0; SubOp != DestOperand.MINumOperands; ++SubOp) { in emitCompressInstEmitter() local
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| H A D | CodeEmitterGen.cpp | 126 if (auto SubOp = CGI.Operands.findSubOperandAlias(VarName)) { in addCodeToMergeInOperand() local
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| /freebsd/contrib/llvm-project/llvm/lib/TableGen/ |
| H A D | SetTheory.cpp | 47 struct SubOp : public SetTheory::Operator { struct
48 void apply(SetTheory &ST, const DagInit *Expr, RecSet &Elts, in apply()
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| /freebsd/sys/contrib/dev/acpica/compiler/ |
| H A D | aslerror.c | 1515 ACPI_PARSE_OBJECT *SubOp, in AslDualParseOpError()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 1226 unsigned SubOp = AMDGPU::V_SUB_CO_U32_e32; in SelectDS1Addr1Offset() local
1411 unsigned SubOp = AMDGPU::V_SUB_CO_U32_e32; in SelectDSReadWrite2() local
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| H A D | SIInstrInfo.cpp | 8128 unsigned SubOp = ST.hasAddNoCarry() ? in lowerScalarAbs() local
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSelect.cpp | 2087 Instruction *AddOp = nullptr, *SubOp = nullptr; in foldAddSubSelect() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 1562 SDValue SubOp = Node->getOperand(I); in ExpandConcatVectors() local
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| H A D | TargetLowering.cpp | 3418 SDValue SubOp = Op.getOperand(i); in SimplifyDemandedVectorElts() local
3433 SDValue SubOp = Op.getOperand(i); in SimplifyDemandedVectorElts() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 2051 SDValue SubOp = Node->getOperand(i); in LowerCONCAT_VECTORS() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4203 unsigned SubOp; in expandDivRem() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 58359 for (SDValue SubOp : SubOps) in combineConcatVectorOps() local
58382 if (isa<LoadSDNode>(BC0) && all_of(SubOps, [&](SDValue SubOp) { in combineConcatVectorOps()
58401 for (SDValue SubOp : SubOps) { in combineConcatVectorOps() local
58417 for (SDValue SubOp : Ops) in combineConcatVectorOps() local
59354 if (all_of(SubVectorOps, [](SDValue SubOp) { in combineINSERT_SUBVECTOR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 9207 SDValue SubOp = DAG.getNode(ISD::SUB, DL, VT, RegV, ConstVal); in lowerSELECT() local
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