| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | DetectDeadLanes.cpp | 158 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
162 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
182 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
232 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
238 unsigned SubIdx = MI.getOperand(3).getImm(); in transferDefinedLanes() local
250 unsigned SubIdx = MI.getOperand(2).getImm(); in transferDefinedLanes() local
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| H A D | ExpandPostRAPseudos.cpp | 69 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
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| H A D | LiveRangeEdit.cpp | 186 bool Late, unsigned SubIdx, in rematerializeAt()
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| H A D | RegisterCoalescer.cpp | 1817 unsigned SubIdx) { in updateRegDefsUses()
2415 const unsigned SubIdx; member in __anonf9586a8a0311::JoinVals
2589 JoinVals(LiveRange &LR, Register Reg, unsigned SubIdx, LaneBitmask LaneMask, in JoinVals()
3110 bool JoinVals::usesLanes(const MachineInstr &MI, Register Reg, unsigned SubIdx, in usesLanes()
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| H A D | TwoAddressInstructionPass.cpp | 1920 unsigned SubIdx = mi->getOperand(3).getImm(); in run() local
2006 unsigned SubIdx = MI.getOperand(i+1).getImm(); in eliminateRegSequence() local
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| H A D | TargetRegisterInfo.cpp | 109 unsigned SubIdx, const MachineRegisterInfo *MRI) { in printReg()
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| H A D | TargetInstrInfo.cpp | 389 unsigned SubIdx, unsigned &Size, in getStackSlotRange()
420 Register DestReg, unsigned SubIdx, in reMaterialize()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ThumbRegisterInfo.cpp | 64 unsigned SubIdx, int Val, in emitThumb1LoadConstPool() argument
84 unsigned SubIdx, int Val, in emitThumb2LoadConstPool() argument
105 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
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| H A D | ARMBaseRegisterInfo.cpp | 498 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, in emitLoadConstPool()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | GlobalISelEmitter.cpp | 1311 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(ChildRec); in importExplicitUseRenderer() local
1445 auto SubIdx = inferSubRegIndexForNode(Dst.getChild(1)); in createAndImportSubInstructionRenderer() local
1490 auto SubIdx = inferSubRegIndexForNode(SubRegChild); in createAndImportSubInstructionRenderer() local
1587 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); in importExplicitUseRenderers() local
1654 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); in importExplicitUseRenderers() local
1879 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); in inferSuperRegisterClass() local
2135 auto SubIdx = inferSubRegIndexForNode(Dst.getChild(1)); in runOnPattern() local
2205 auto SubIdx = inferSubRegIndexForNode(SubRegChild); in runOnPattern() local
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| H A D | RegisterBankEmitter.cpp | 203 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) { in visitRegisterBankClasses() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TileConfig.cpp | 183 unsigned SubIdx = IsRow ? X86::sub_8bit : X86::sub_16bit; in INITIALIZE_PASS_DEPENDENCY() local
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| H A D | X86InstructionSelector.cpp | |
| H A D | X86LegalizerInfo.cpp | |
| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.h | 407 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg()
425 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg()
436 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass()
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| H A D | CodeGenRegisters.cpp | 139 CodeGenSubRegIndex *SubIdx = *I; in computeConcatTransitiveClosure() local
547 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SubReg.second); in computeSecondarySubRegs() local
1142 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, in getSuperRegClasses()
1965 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); SubIdx != EndIdx; in pruneUnitSets() local
2313 for (const auto &SubIdx : SubRegIndices) { in inferSubClassWithSubReg() local
2347 for (auto &SubIdx : SubRegIndices) { in inferMatchingSuperRegClass() local
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| H A D | CodeGenTarget.cpp | 181 const CodeGenSubRegIndex *SubIdx, bool MustBeAllocatable) const { in getSuperRegForSubReg() argument
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 476 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx, in ConstrainForSubReg()
525 unsigned SubIdx = Node->getConstantOperandVal(1); in EmitSubregNode() local
581 unsigned SubIdx = N2->getAsZExtVal(); in EmitSubregNode() local
680 unsigned SubIdx = Op->getAsZExtVal(); in EmitRegSequence() local
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| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 108 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 218 unsigned SubIdx = X86::NoSubRegister; in getSubRegIndex() local
826 unsigned SubIdx; in selectTruncOrPtrToInt() local
1286 unsigned SubIdx = X86::NoSubRegister; in emitExtractSubreg() local
1324 unsigned SubIdx = X86::NoSubRegister; in emitInsertSubreg() local
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| H A D | X86LegalizerInfo.cpp | 516 unsigned SubIdx = Query.Opcode == G_EXTRACT ? 0 : 1; in X86LegalizerInfo() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 388 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName()
408 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask()
640 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPrepareFunctions.cpp | 224 for (std::size_t SubIdx = 1; SubIdx < MatchStr.size(); ++SubIdx) in parseAnnotation() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 761 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; in expandExtractElementF64() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 744 SDValue SubIdx = DAG.getNode(ISD::AND, dl, MVT::i32, {Idx, Mask}); in getIndexInWord32() local
1386 return DAG.getTargetInsertSubreg(SubIdx, dl, VecTy, VecV, SubV); in insertHvxSubvectorReg() local
1169 SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG); extractHvxElementReg() local
1230 SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG); insertHvxElementReg() local
1595 extractSubvector(SDValue Vec,MVT SubTy,unsigned SubIdx,SelectionDAG & DAG) const extractSubvector() argument
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