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Searched defs:Sub2 (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DExpandFp.cpp383 Value *Sub2 = Builder.CreateSub(Builder.getIntN(BitWidthNew, BitWidth - 1), in expandIToFP() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp1579 unsigned Sub2 = DI->getOperand(2).getImm(); in checkForImmediate() local
H A DHexagonConstPropagation.cpp1948 unsigned Sub2 = MI.getOperand(4).getImm(); in evaluate() local
H A DHexagonBitSimplify.cpp444 unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm(); in parseRegSequence() local
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp1414 const CodeGenSubRegIndex *Sub2) { in computeComposites()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp7851 GSub *Sub2 = cast<GSub>(MRI.getVRegDef(Sub1->getLHSReg())); in matchFoldAMinusC1MinusC2() local
7874 GSub *Sub2 = cast<GSub>(MRI.getVRegDef(Sub1->getLHSReg())); in matchFoldC1Minus2MinusC2() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2210 SDValue Sub2 = DAG.getBitcast(VT, in LowerUDIVREM64() local
H A DAMDGPULegalizerInfo.cpp4688 auto Sub2 = B.buildMergeLikeInstr(S64, {Sub2_Lo, Sub2_Hi}); in legalizeUnsignedDIV_REM64Impl() local