xref: /titanic_41/usr/src/uts/common/io/mwl/mwl_reg.h (revision d8d810637042c2a73a269f125dee75e8ed1421d1)
1 /*
2  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
3  * Use is subject to license terms.
4  */
5 
6 /*
7  * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
8  * Copyright (c) 2007-2009 Marvell Semiconductor, Inc.
9  * All rights reserved.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer,
16  *    without modification.
17  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
18  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
19  *    redistribution must be conditioned upon including a substantially
20  *    similar Disclaimer requirement for further binary redistribution.
21  *
22  * NO WARRANTY
23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
26  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
27  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
28  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
31  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33  * THE POSSIBILITY OF SUCH DAMAGES.
34  */
35 
36 /*
37  * Definitions for the Marvell Wireless LAN controller Hardware Access Layer.
38  */
39 
40 #ifndef _MWL_REG_H
41 #define	_MWL_REG_H
42 
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46 
47 #define	MWL_MBSS_SUPPORT		/* enable multi-bss support */
48 
49 /*
50  * Host/Firmware Interface definitions.
51  */
52 
53 /*
54  * Define total number of TX queues in the shared memory.
55  * This count includes the EDCA queues, Block Ack queues, and HCCA queues
56  * In addition to this, there could be a management packet queue some
57  * time in the future
58  */
59 #define	NUM_EDCA_QUEUES		4
60 #define	NUM_HCCA_QUEUES		0
61 #define	NUM_BA_QUEUES		0
62 #define	NUM_MGMT_QUEUES		0
63 #define	NUM_ACK_EVENT_QUEUE	1
64 #define	TOTAL_TX_QUEUES		\
65 	(NUM_EDCA_QUEUES +	\
66 	NUM_HCCA_QUEUES +	\
67 	NUM_BA_QUEUES +		\
68 	NUM_MGMT_QUEUES +	\
69 	NUM_ACK_EVENT_QUEUE)
70 #define	MAX_TXWCB_QUEUES	TOTAL_TX_QUEUES - NUM_ACK_EVENT_QUEUE
71 #define	MAX_RXWCB_QUEUES	1
72 
73 /*
74  * Firmware download support.
75  */
76 #define	FW_DOWNLOAD_BLOCK_SIZE	256
77 #define	FW_CHECK_USECS		(5*1000) /* 5ms */
78 #define	FW_MAX_NUM_CHECKS	200
79 
80 #define	MWL_ANT_INFO_SUPPORT /* per-antenna data in rx descriptor */
81 
82 #define	MACREG_REG_TSF_LOW	0xa600 /* TSF lo */
83 #define	MACREG_REG_TSF_HIGH	0xa604 /* TSF hi */
84 #define	MACREG_REG_CHIP_REV	0xa814 /* chip rev */
85 
86 /*
87  * Map to 0x80000000 (Bus control) on BAR0
88  */
89 /* From host to ARM */
90 #define	MACREG_REG_H2A_INTERRUPT_EVENTS		0x00000C18
91 #define	MACREG_REG_H2A_INTERRUPT_CAUSE		0x00000C1C
92 #define	MACREG_REG_H2A_INTERRUPT_MASK		0x00000C20
93 #define	MACREG_REG_H2A_INTERRUPT_CLEAR_SEL	0x00000C24
94 #define	MACREG_REG_H2A_INTERRUPT_STATUS_MASK	0x00000C28
95 /* From ARM to host */
96 #define	MACREG_REG_A2H_INTERRUPT_EVENTS		0x00000C2C
97 #define	MACREG_REG_A2H_INTERRUPT_CAUSE		0x00000C30
98 #define	MACREG_REG_A2H_INTERRUPT_MASK		0x00000C34
99 #define	MACREG_REG_A2H_INTERRUPT_CLEAR_SEL	0x00000C38
100 #define	MACREG_REG_A2H_INTERRUPT_STATUS_MASK	0x00000C3C
101 
102 
103 /* Map to 0x80000000 on BAR1 */
104 #define	MACREG_REG_GEN_PTR		0x00000C10
105 #define	MACREG_REG_INT_CODE		0x00000C14
106 #define	MACREG_REG_SCRATCH		0x00000C40
107 #define	MACREG_REG_FW_PRESENT		0x0000BFFC
108 
109 #define	MACREG_REG_PROMISCUOUS		0xA300
110 /* Bit definitio for MACREG_REG_A2H_INTERRUPT_CAUSE (A2HRIC) */
111 #define	MACREG_A2HRIC_BIT_TX_DONE	0x00000001 /* bit 0 */
112 #define	MACREG_A2HRIC_BIT_RX_RDY	0x00000002 /* bit 1 */
113 #define	MACREG_A2HRIC_BIT_OPC_DONE	0x00000004 /* bit 2 */
114 #define	MACREG_A2HRIC_BIT_MAC_EVENT	0x00000008 /* bit 3 */
115 #define	MACREG_A2HRIC_BIT_RX_PROBLEM	0x00000010 /* bit 4 */
116 
117 #define	MACREG_A2HRIC_BIT_RADIO_OFF	0x00000020 /* bit 5 */
118 #define	MACREG_A2HRIC_BIT_RADIO_ON	0x00000040 /* bit 6 */
119 
120 #define	MACREG_A2HRIC_BIT_RADAR_DETECT	0x00000080 /* bit 7 */
121 
122 #define	MACREG_A2HRIC_BIT_ICV_ERROR	0x00000100 /* bit 8 */
123 #define	MACREG_A2HRIC_BIT_MIC_ERROR	0x00000200 /* bit 9 */
124 #define	MACREG_A2HRIC_BIT_QUEUE_EMPTY	0x00004000
125 #define	MACREG_A2HRIC_BIT_QUEUE_FULL	0x00000800
126 #define	MACREG_A2HRIC_BIT_CHAN_SWITCH	0x00001000
127 #define	MACREG_A2HRIC_BIT_TX_WATCHDOG	0x00002000
128 #define	MACREG_A2HRIC_BIT_BA_WATCHDOG	0x00000400
129 #define	MACREQ_A2HRIC_BIT_TX_ACK	0x00008000
130 #define	ISR_SRC_BITS	((MACREG_A2HRIC_BIT_RX_RDY)	| \
131 			(MACREG_A2HRIC_BIT_TX_DONE)	| \
132 			(MACREG_A2HRIC_BIT_OPC_DONE)	| \
133 			(MACREG_A2HRIC_BIT_MAC_EVENT)	| \
134 			(MACREG_A2HRIC_BIT_MIC_ERROR)	| \
135 			(MACREG_A2HRIC_BIT_ICV_ERROR)	| \
136 			(MACREG_A2HRIC_BIT_RADAR_DETECT)| \
137 			(MACREG_A2HRIC_BIT_CHAN_SWITCH)	| \
138 			(MACREG_A2HRIC_BIT_TX_WATCHDOG)	| \
139 			(MACREG_A2HRIC_BIT_QUEUE_EMPTY)	| \
140 			(MACREG_A2HRIC_BIT_BA_WATCHDOG)	| \
141 			(MACREQ_A2HRIC_BIT_TX_ACK))
142 
143 #define	MACREG_A2HRIC_BIT_MASK	ISR_SRC_BITS
144 
145 /* Bit definitio for MACREG_REG_H2A_INTERRUPT_CAUSE (H2ARIC) */
146 #define	MACREG_H2ARIC_BIT_PPA_READY	0x00000001 /* bit 0 */
147 #define	MACREG_H2ARIC_BIT_DOOR_BELL	0x00000002 /* bit 1 */
148 #define	ISR_RESET			(1<<15)
149 
150 /* INT code register event definition */
151 #define	MACREG_INT_CODE_CMD_FINISHED	0x00000005
152 
153 /*
154  * Define OpMode for SoftAP/Station mode
155  */
156 
157 /*
158  * The following mode signature has to be written to PCI scratch register#0
159  * right after successfully downloading the last block of firmware and
160  * before waiting for firmware ready signature
161  */
162 #define	HostCmd_STA_MODE		0x5A
163 #define	HostCmd_SOFTAP_MODE		0xA5
164 
165 #define	HostCmd_STA_FWRDY_SIGNATURE	0xF0F1F2F4
166 #define	HostCmd_SOFTAP_FWRDY_SIGNATURE	0xF1F2F4A5
167 
168 #define	HostCmd_CMD_CODE_DNLD			0x0001
169 #define	HostCmd_CMD_GET_HW_SPEC			0x0003
170 #define	HostCmd_CMD_SET_HW_SPEC			0x0004
171 #define	HostCmd_CMD_MAC_MULTICAST_ADR		0x0010
172 #define	HostCmd_CMD_802_11_GET_STAT		0x0014
173 #define	HostCmd_CMD_MAC_REG_ACCESS		0x0019
174 #define	HostCmd_CMD_BBP_REG_ACCESS		0x001a
175 #define	HostCmd_CMD_RF_REG_ACCESS		0x001b
176 #define	HostCmd_CMD_802_11_RADIO_CONTROL	0x001c
177 #define	HostCmd_CMD_802_11_RF_TX_POWER		0x001e
178 #define	HostCmd_CMD_802_11_RF_ANTENNA		0x0020
179 #define	HostCmd_CMD_SET_BEACON			0x0100
180 #define	HostCmd_CMD_SET_AID			0x010d
181 #define	HostCmd_CMD_SET_RF_CHANNEL		0x010a
182 #define	HostCmd_CMD_SET_INFRA_MODE		0x010e
183 #define	HostCmd_CMD_SET_G_PROTECT_FLAG		0x010f
184 #define	HostCmd_CMD_802_11_RTS_THSD		0x0113
185 #define	HostCmd_CMD_802_11_SET_SLOT		0x0114
186 
187 #define	HostCmd_CMD_802_11H_DETECT_RADAR	0x0120
188 #define	HostCmd_CMD_SET_WMM_MODE		0x0123
189 #define	HostCmd_CMD_HT_GUARD_INTERVAL		0x0124
190 #define	HostCmd_CMD_SET_FIXED_RATE		0x0126
191 #define	HostCmd_CMD_SET_LINKADAPT_CS_MODE	0x0129
192 #define	HostCmd_CMD_SET_MAC_ADDR		0x0202
193 #define	HostCmd_CMD_SET_RATE_ADAPT_MODE		0x0203
194 #define	HostCmd_CMD_GET_WATCHDOG_BITMAP		0x0205
195 
196 /* SoftAP command code */
197 #define	HostCmd_CMD_BSS_START			0x1100
198 #define	HostCmd_CMD_SET_NEW_STN			0x1111
199 #define	HostCmd_CMD_SET_KEEP_ALIVE		0x1112
200 #define	HostCmd_CMD_SET_APMODE			0x1114
201 #define	HostCmd_CMD_SET_SWITCH_CHANNEL		0x1121
202 
203 /*
204  * @HWENCR@
205  * Command to update firmware encryption keys.
206  */
207 #define	HostCmd_CMD_UPDATE_ENCRYPTION		0x1122
208 /*
209  * @11E-BA@
210  * Command to create/destroy block ACK
211  */
212 #define	HostCmd_CMD_BASTREAM			0x1125
213 #define	HostCmd_CMD_SET_RIFS			0x1126
214 #define	HostCmd_CMD_SET_N_PROTECT_FLAG		0x1131
215 #define	HostCmd_CMD_SET_N_PROTECT_OPMODE	0x1132
216 #define	HostCmd_CMD_SET_OPTIMIZATION_LEVEL	0x1133
217 #define	HostCmd_CMD_GET_CALTABLE		0x1134
218 #define	HostCmd_CMD_SET_MIMOPSHT		0x1135
219 #define	HostCmd_CMD_GET_BEACON			0x1138
220 #define	HostCmd_CMD_SET_REGION_CODE		0x1139
221 #define	HostCmd_CMD_SET_POWERSAVESTATION	0x1140
222 #define	HostCmd_CMD_SET_TIM			0x1141
223 #define	HostCmd_CMD_GET_TIM			0x1142
224 #define	HostCmd_CMD_GET_SEQNO			0x1143
225 #define	HostCmd_CMD_DWDS_ENABLE			0x1144
226 #define	HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE	0x1145
227 #define	HostCmd_CMD_CFEND_ENABLE		0x1146
228 
229 /*
230  * Define general result code for each command
231  */
232 /* RESULT OK */
233 #define	HostCmd_RESULT_OK		0x0000
234 /* Genenral error */
235 #define	HostCmd_RESULT_ERROR		0x0001
236 /* Command is not valid */
237 #define	HostCmd_RESULT_NOT_SUPPORT	0x0002
238 /* Command is pending (will be processed) */
239 #define	HostCmd_RESULT_PENDING		0x0003
240 /* System is busy (command ignored) */
241 #define	HostCmd_RESULT_BUSY		0x0004
242 /* Data buffer is not big enough */
243 #define	HostCmd_RESULT_PARTIAL_DATA	0x0005
244 
245 #define	HostCmd_CMD_SET_EDCA_PARAMS	0x0115
246 
247 /*
248  * Definition of action or option for each command
249  */
250 
251 /*
252  * Define general purpose action
253  */
254 #define	HostCmd_ACT_GEN_READ	0x0000
255 #define	HostCmd_ACT_GEN_WRITE	0x0001
256 #define	HostCmd_ACT_GEN_GET	0x0000
257 #define	HostCmd_ACT_GEN_SET	0x0001
258 #define	HostCmd_ACT_GEN_OFF	0x0000
259 #define	HostCmd_ACT_GEN_ON	0x0001
260 
261 #define	HostCmd_ACT_DIFF_CHANNEL	0x0002
262 #define	HostCmd_ACT_GEN_SET_LIST	0x0002
263 
264 /* Define action or option for HostCmd_FW_USE_FIXED_RATE */
265 #define	HostCmd_ACT_USE_FIXED_RATE	0x0001
266 #define	HostCmd_ACT_NOT_USE_FIXED_RATE	0x0002
267 
268 /* Define action or option for HostCmd_CMD_802_11_SET_WEP */
269 #define	HostCmd_ACT_ADD		0x0002
270 #define	HostCmd_ACT_REMOVE	0x0004
271 #define	HostCmd_ACT_USE_DEFAULT	0x0008
272 
273 /*
274  * PUBLIC DEFINITIONS
275  */
276 #define	RATE_INDEX_MAX_ARRAY	14
277 #define	WOW_MAX_STATION		32
278 
279 
280 #pragma pack(1)
281 
282 struct mwl_ant_info {
283 	uint8_t		rssi_a;	/* RSSI for antenna A */
284 	uint8_t		rssi_b;	/* RSSI for antenna B */
285 	uint8_t		rssi_c;	/* RSSI for antenna C */
286 	uint8_t		rsvd1;	/* Reserved */
287 	uint8_t		nf_a;	/* Noise floor for antenna A */
288 	uint8_t		nf_b;	/* Noise floor for antenna B */
289 	uint8_t		nf_c;	/* Noise floor for antenna C */
290 	uint8_t		rsvd2;	/* Reserved */
291 	uint8_t		nf;	/* Noise floor */
292 	uint8_t		rsvd3[3]; /* Reserved - To make word aligned */
293 };
294 
295 /*
296  * Hardware tx/rx descriptors.
297  *
298  * NB: tx descriptor size must match f/w expected size
299  * because f/w prefetch's the next descriptor linearly
300  * and doesn't chase the next pointer.
301  */
302 struct mwl_txdesc {
303 	uint32_t	Status;
304 #define	EAGLE_TXD_STATUS_IDLE		0x00000000
305 #define	EAGLE_TXD_STATUS_USED		0x00000001
306 #define	EAGLE_TXD_STATUS_OK		0x00000001
307 #define	EAGLE_TXD_STATUS_OK_RETRY	0x00000002
308 #define	EAGLE_TXD_STATUS_OK_MORE_RETRY	0x00000004
309 #define	EAGLE_TXD_STATUS_MULTICAST_TX	0x00000008
310 #define	EAGLE_TXD_STATUS_BROADCAST_TX	0x00000010
311 #define	EAGLE_TXD_STATUS_FAILED_LINK_ERROR		0x00000020
312 #define	EAGLE_TXD_STATUS_FAILED_EXCEED_LIMIT		0x00000040
313 #define	EAGLE_TXD_STATUS_FAILED_XRETRY	EAGLE_TXD_STATUS_FAILED_EXCEED_LIMIT
314 #define	EAGLE_TXD_STATUS_FAILED_AGING	0x00000080
315 #define	EAGLE_TXD_STATUS_FW_OWNED	0x80000000
316 	uint8_t		DataRate;
317 	uint8_t		TxPriority;
318 	uint16_t	QosCtrl;
319 	uint32_t	PktPtr;
320 	uint16_t	PktLen;
321 	uint8_t		DestAddr[6];
322 	uint32_t	pPhysNext;
323 	uint32_t	SapPktInfo;
324 #define	EAGLE_TXD_MODE_BONLY	1
325 #define	EAGLE_TXD_MODE_GONLY	2
326 #define	EAGLE_TXD_MODE_BG	3
327 #define	EAGLE_TXD_MODE_NONLY	4
328 #define	EAGLE_TXD_MODE_BN	5
329 #define	EAGLE_TXD_MODE_GN	6
330 #define	EAGLE_TXD_MODE_BGN	7
331 #define	EAGLE_TXD_MODE_AONLY	8
332 #define	EAGLE_TXD_MODE_AG	10
333 #define	EAGLE_TXD_MODE_AN	12
334 	uint16_t	Format;
335 #define	EAGLE_TXD_FORMAT	0x0001	/* frame format/rate */
336 #define	EAGLE_TXD_FORMAT_LEGACY	0x0000	/* legacy rate frame */
337 #define	EAGLE_TXD_FORMAT_HT	0x0001	/* HT rate frame */
338 #define	EAGLE_TXD_GI		0x0002	/* guard interval */
339 #define	EAGLE_TXD_GI_SHORT	0x0002	/* short guard interval */
340 #define	EAGLE_TXD_GI_LONG	0x0000	/* long guard interval */
341 #define	EAGLE_TXD_CHW		0x0004	/* channel width */
342 #define	EAGLE_TXD_CHW_20	0x0000	/* 20MHz channel width */
343 #define	EAGLE_TXD_CHW_40	0x0004	/* 40MHz channel width */
344 #define	EAGLE_TXD_RATE		0x01f8	/* tx rate (legacy)/ MCS */
345 #define	EAGLE_TXD_RATE_S	3
346 #define	EAGLE_TXD_ADV		0x0600	/* advanced coding */
347 #define	EAGLE_TXD_ADV_S		9
348 #define	EAGLE_TXD_ADV_NONE	0x0000
349 #define	EAGLE_TXD_ADV_LDPC	0x0200
350 #define	EAGLE_TXD_ADV_RS	0x0400
351 /* NB: 3 is reserved */
352 #define	EAGLE_TXD_ANTENNA	0x1800	/* antenna select */
353 #define	EAGLE_TXD_ANTENNA_S	11
354 #define	EAGLE_TXD_EXTCHAN	0x6000	/* extension channel */
355 #define	EAGLE_TXD_EXTCHAN_S	13
356 #define	EAGLE_TXD_EXTCHAN_HI	0x0000	/* above */
357 #define	EAGLE_TXD_EXTCHAN_LO	0x2000	/* below */
358 #define	EAGLE_TXD_PREAMBLE	0x8000
359 #define	EAGLE_TXD_PREAMBLE_SHORT 0x8000	/* short preamble */
360 #define	EAGLE_TXD_PREAMBLE_LONG 0x0000	/* long preamble */
361 	uint16_t	pad;		/* align to 4-byte boundary */
362 #define	EAGLE_TXD_FIXED_RATE	0x0100	/* get tx rate from Format */
363 #define	EAGLE_TXD_DONT_AGGR	0x0200	/* don't aggregate frame */
364 	uint32_t	ack_wcb_addr;
365 };
366 
367 struct mwl_rxdesc {
368 	/* control element */
369 	uint8_t		RxControl;
370 #define	EAGLE_RXD_CTRL_DRIVER_OWN	0x00
371 #define	EAGLE_RXD_CTRL_OS_OWN		0x04
372 #define	EAGLE_RXD_CTRL_DMA_OWN		0x80
373 	/* received signal strengt indication */
374 	uint8_t		RSSI;
375 	/* status field w/ USED bit */
376 	uint8_t		Status;
377 #define	EAGLE_RXD_STATUS_IDLE		0x00
378 #define	EAGLE_RXD_STATUS_OK		0x01
379 #define	EAGLE_RXD_STATUS_MULTICAST_RX	0x02
380 #define	EAGLE_RXD_STATUS_BROADCAST_RX	0x04
381 #define	EAGLE_RXD_STATUS_FRAGMENT_RX	0x08
382 #define	EAGLE_RXD_STATUS_GENERAL_DECRYPT_ERR	0xff
383 #define	EAGLE_RXD_STATUS_DECRYPT_ERR_MASK	0x80
384 #define	EAGLE_RXD_STATUS_TKIP_MIC_DECRYPT_ERR	0x02
385 #define	EAGLE_RXD_STATUS_WEP_ICV_DECRYPT_ERR	0x04
386 #define	EAGLE_RXD_STATUS_TKIP_ICV_DECRYPT_ERR	0x08
387 	/* channel # pkt received on */
388 	uint8_t		Channel;
389 	/* total length of received data */
390 	uint16_t	PktLen;
391 	/* not used */
392 	uint8_t		SQ2;
393 	/* received data rate */
394 	uint8_t		Rate;
395 	/* physical address of payload data */
396 	uint32_t	pPhysBuffData;
397 	/* physical address of next RX desc */
398 	uint32_t	pPhysNext;
399 	/* received QosCtrl field variable */
400 	uint16_t	QosCtrl;
401 	/* like name states */
402 	uint16_t	HtSig2;
403 #ifdef MWL_ANT_INFO_SUPPORT
404 	/* antenna info */
405 	struct mwl_ant_info ai;
406 #endif
407 };
408 #pragma pack()
409 
410 
411 
412 // =============================================================================
413 //			HOST COMMAND DEFINITIONS
414 // =============================================================================
415 
416 //
417 // Definition of data structure for each command
418 //
419 // Define general data structure
420 #pragma pack(1)
421 typedef struct {
422 	uint16_t	Cmd;
423 	uint16_t	Length;
424 #ifdef MWL_MBSS_SUPPORT
425 	uint8_t		SeqNum;
426 	uint8_t		MacId;
427 #else
428 	uint16_t	SeqNum;
429 #endif
430 	uint16_t	Result;
431 } FWCmdHdr;
432 
433 typedef struct {
434 	FWCmdHdr	CmdHdr;
435 	uint8_t		annex;
436 	uint8_t		index;
437 	uint8_t		len;
438 	uint8_t		Reserverd;
439 #define	CAL_TBL_SIZE	160
440 	uint8_t	calTbl[CAL_TBL_SIZE];
441 } HostCmd_FW_GET_CALTABLE;
442 
443 typedef struct {
444 	FWCmdHdr	CmdHdr;
445 	/* version of the HW */
446 	uint8_t		Version;
447 	/* host interface */
448 	uint8_t		HostIf;
449 	/* Max. number of WCB FW can handle */
450 	uint16_t	NumOfWCB;
451 	/* MaxNbr of MC addresses FW can handle */
452 	uint16_t	NumOfMCastAddr;
453 	/* MAC address programmed in HW */
454 	uint8_t		PermanentAddr[6];
455 	uint16_t	RegionCode;
456 	/* Number of antenna used */
457 	uint16_t	NumberOfAntenna;
458 	/* 4 byte of FW release number */
459 	uint32_t	FWReleaseNumber;
460 	uint32_t	WcbBase0;
461 	uint32_t	RxPdWrPtr;
462 	uint32_t	RxPdRdPtr;
463 	uint32_t	ulFwAwakeCookie;
464 	uint32_t	WcbBase1[3];
465 } HostCmd_DS_GET_HW_SPEC;
466 
467 typedef struct {
468 	FWCmdHdr	CmdHdr;
469 	/* HW revision */
470 	uint8_t		Version;
471 	/* Host interface */
472 	uint8_t		HostIf;
473 	/* Max. number of Multicast address FW can handle */
474 	uint16_t	NumOfMCastAdr;
475 	/* MAC address */
476 	uint8_t		PermanentAddr[6];
477 	/* Region Code */
478 	uint16_t	RegionCode;
479 	/* 4 byte of FW release number */
480 	uint32_t	FWReleaseNumber;
481 	/* Firmware awake cookie */
482 	uint32_t	ulFwAwakeCookie;
483 	/* Device capabilities (see above) */
484 	uint32_t	DeviceCaps;
485 	/* Rx shared memory queue */
486 	uint32_t	RxPdWrPtr;
487 	/* TX queues in WcbBase array */
488 	uint32_t	NumTxQueues;
489 	/* TX WCB Rings */
490 	uint32_t	WcbBase[MAX_TXWCB_QUEUES];
491 	uint32_t	Flags;
492 #define	SET_HW_SPEC_DISABLEMBSS		0x08
493 #define	SET_HW_SPEC_HOSTFORM_BEACON	0x10
494 #define	SET_HW_SPEC_HOSTFORM_PROBERESP	0x20
495 #define	SET_HW_SPEC_HOST_POWERSAVE	0x40
496 #define	SET_HW_SPEC_HOSTENCRDECR_MGMT	0x80
497 	uint32_t	TxWcbNumPerQueue;
498 	uint32_t	TotalRxWcb;
499 }HostCmd_DS_SET_HW_SPEC;
500 
501 // used for stand alone bssid sets/clears
502 typedef struct {
503 	FWCmdHdr	CmdHdr;
504 #ifdef MWL_MBSS_SUPPORT
505 	uint16_t	MacType;
506 #define	WL_MAC_TYPE_PRIMARY_CLIENT	0
507 #define	WL_MAC_TYPE_SECONDARY_CLIENT	1
508 #define	WL_MAC_TYPE_PRIMARY_AP		2
509 #define	WL_MAC_TYPE_SECONDARY_AP	3
510 #endif
511 	uint8_t		MacAddr[6];
512 } HostCmd_DS_SET_MAC,
513 	HostCmd_FW_SET_BSSID,
514 	HostCmd_FW_SET_MAC;
515 
516 typedef struct {
517 	uint32_t	LegacyRateBitMap;
518 	uint32_t	HTRateBitMap;
519 	uint16_t	CapInfo;
520 	uint16_t	HTCapabilitiesInfo;
521 	uint8_t		MacHTParamInfo;
522 	uint8_t		Rev;
523 	struct {
524 		uint8_t		ControlChan;
525 		uint8_t		AddChan;
526 		uint16_t	OpMode;
527 		uint16_t	stbc;
528 	} AddHtInfo;
529 } PeerInfo_t;
530 
531 typedef struct {
532 	FWCmdHdr	CmdHdr;
533 	uint16_t	AID;
534 	uint8_t		MacAddr[6];
535 	uint16_t	StnId;
536 	uint16_t	Action;
537 	uint16_t	Reserved;
538 	PeerInfo_t	PeerInfo;
539 	uint8_t		Qosinfo;
540 	uint8_t		isQosSta;
541 	uint32_t	FwStaPtr;
542 } HostCmd_FW_SET_NEW_STN;
543 
544 /* Define data structure for HostCmd_CMD_802_11_RF_ANTENNA */
545 typedef struct _HostCmd_DS_802_11_RF_ANTENNA {
546 	FWCmdHdr	CmdHdr;
547 	uint16_t	Action;
548 	/* Number of antennas or 0xffff(diversity) */
549 	uint16_t	AntennaMode;
550 } HostCmd_DS_802_11_RF_ANTENNA;
551 
552 /* Define data structure for HostCmd_CMD_802_11_RADIO_CONTROL */
553 typedef struct {
554 	FWCmdHdr	CmdHdr;
555 	uint16_t	Action;
556 	/*
557 	 *  @bit0: 1/0, on/off
558 	 *  @bit1: 1/0, long/short
559 	 *  @bit2: 1/0,auto/fix
560 	 */
561 	uint16_t	Control;
562 	uint16_t	RadioOn;
563 } HostCmd_DS_802_11_RADIO_CONTROL;
564 
565 /* for HostCmd_CMD_SET_WMM_MODE */
566 typedef struct {
567 	FWCmdHdr	CmdHdr;
568 	/* 0->unset, 1->set */
569 	uint16_t	Action;
570 } HostCmd_FW_SetWMMMode;
571 
572 /* bits 0-5 specify frequency band */
573 #define	FREQ_BAND_2DOT4GHZ	0x0001
574 #define	FREQ_BAND_4DOT9GHZ	0x0002	/* XXX not implemented */
575 #define	FREQ_BAND_5GHZ		0x0004
576 #define	FREQ_BAND_5DOT2GHZ	0x0008	/* XXX not implemented */
577 /* bits 6-10 specify channel width */
578 #define	CH_AUTO_WIDTH		0x0000	/* XXX not used? */
579 #define	CH_10_MHz_WIDTH		0x0040
580 #define	CH_20_MHz_WIDTH		0x0080
581 #define	CH_40_MHz_WIDTH		0x0100
582 /* bits 11-12 specify extension channel */
583 #define	EXT_CH_NONE		0x0000	/* no extension channel */
584 #define	EXT_CH_ABOVE_CTRL_CH	0x0800	/* extension channel above */
585 #define	EXT_CH_AUTO		0x1000	/* XXX not used? */
586 #define	EXT_CH_BELOW_CTRL_CH	0x1800	/* extension channel below */
587 /* bits 13-31 are reserved */
588 
589 #define	FIXED_RATE_WITH_AUTO_RATE_DROP		0
590 #define	FIXED_RATE_WITHOUT_AUTORATE_DROP	1
591 
592 #define	LEGACY_RATE_TYPE			0
593 #define	HT_RATE_TYPE				1
594 
595 #define	RETRY_COUNT_VALID			0
596 #define	RETRY_COUNT_INVALID			1
597 
598 // Define data structure for HostCmd_CMD_802_11_RF_CHANNEL
599 typedef struct {
600 	FWCmdHdr	CmdHdr;
601 	uint16_t	Action;
602 	uint8_t		CurrentChannel;	/* channel # */
603 	uint32_t	ChannelFlags;	/* see below */
604 } HostCmd_FW_SET_RF_CHANNEL;
605 
606 #define	TX_POWER_LEVEL_TOTAL	8
607 
608 /* Define data structure for HostCmd_CMD_802_11_RF_TX_POWER */
609 typedef struct {
610 	FWCmdHdr	CmdHdr;
611 	uint16_t	Action;
612 	uint16_t	SupportTxPowerLevel;
613 	uint16_t	CurrentTxPowerLevel;
614 	uint16_t	Reserved;
615 	uint16_t	PowerLevelList[TX_POWER_LEVEL_TOTAL];
616 } HostCmd_DS_802_11_RF_TX_POWER;
617 
618 typedef struct {
619 	/*
620 	 * lower rate after the retry count
621 	 * 0: legacy, 1: HT
622 	 */
623 	uint32_t	FixRateType;
624 	/*
625 	 *  0: retry count is not valid
626 	 *  1: use retry count specified
627 	 */
628 	uint32_t	RetryCountValid;
629 } FIX_RATE_FLAG;
630 
631 typedef  struct {
632 	FIX_RATE_FLAG	FixRateTypeFlags;
633 	/* legacy rate(not index) or an MCS code */
634 	uint32_t	FixedRate;
635 	uint32_t	RetryCount;
636 } FIXED_RATE_ENTRY;
637 
638 typedef  struct {
639 	FWCmdHdr	CmdHdr;
640 	/*
641 	 * HostCmd_ACT_GEN_GET			0x0000
642 	 * HostCmd_ACT_GEN_SET 			0x0001
643 	 * HostCmd_ACT_NOT_USE_FIXED_RATE	0x0002
644 	 */
645 	uint32_t	Action;
646 	/* use fixed rate specified but firmware can drop */
647 	uint32_t	AllowRateDrop;
648 	uint32_t	EntryCount;
649 	FIXED_RATE_ENTRY FixedRateTable[4];
650 	uint8_t		MulticastRate;
651 	uint8_t		MultiRateTxType;
652 	uint8_t		ManagementRate;
653 } HostCmd_FW_USE_FIXED_RATE;
654 
655 /* Define data structure for HostCmd_CMD_SET_RATE_ADAPT_MODE */
656 typedef struct {
657 	FWCmdHdr	CmdHdr;
658 	uint16_t	Action;
659 	uint16_t	RateAdaptMode;
660 } HostCmd_DS_SET_RATE_ADAPT_MODE;
661 
662 typedef struct {
663 	FWCmdHdr	CmdHdr;
664 	uint8_t	OptLevel;
665 } HostCmd_FW_SET_OPTIMIZATION_LEVEL;
666 
667 typedef struct {
668 	FWCmdHdr	CmdHdr;
669 	uint16_t	regionCode;
670 } HostCmd_SET_REGIONCODE_INFO;
671 
672 typedef struct {
673 	FWCmdHdr	CmdHdr;
674 	uint16_t	Action;	/* 0: Get. 1:Set */
675 	uint32_t	Option;	/* 0: default. 1:Aggressive */
676 	uint32_t	Threshold;	/* Range 0-200, default 8 */
677 } HostCmd_FW_AMPDU_RETRY_RATEDROP_MODE;
678 
679 typedef struct {
680 	FWCmdHdr	CmdHdr;
681 	uint32_t	Enable;	/* 0 -- Disable. or 1 -- Enable */
682 } HostCmd_CFEND_ENABLE;
683 
684 typedef struct {
685 	FWCmdHdr	CmdHdr;
686 	uint32_t	Enable;	/* FALSE: Disable or TRUE: Enable */
687 } HostCmd_DS_BSS_START;
688 
689 typedef struct {
690 	FWCmdHdr	CmdHdr;
691 } HostCmd_FW_SET_INFRA_MODE;
692 
693 /* used for AID sets/clears */
694 typedef struct {
695 	FWCmdHdr	CmdHdr;
696 	uint16_t	AssocID;
697 	uint8_t		MacAddr[6]; /* AP's Mac Address(BSSID) */
698 	uint32_t	GProtection;
699 	uint8_t		ApRates[RATE_INDEX_MAX_ARRAY];
700 } HostCmd_FW_SET_AID;
701 
702 typedef struct {
703 	FWCmdHdr	CmdHdr;
704 	uint16_t	Action;
705 	uint16_t	Threshold;
706 } HostCmd_DS_802_11_RTS_THSD;
707 
708 /* Define data structure for HostCmd_CMD_SET_LINKADAPT_CS_MODE */
709 typedef struct {
710 	FWCmdHdr	CmdHdr;
711 	uint16_t	Action;
712 	uint16_t	CSMode;
713 } HostCmd_DS_SET_LINKADAPT_CS_MODE;
714 
715 typedef struct {
716 	FWCmdHdr	CmdHdr;
717 	uint32_t	ActionType; /* ENCR_ACTION_TYPE */
718 	uint32_t	DataLength; /* size of the data buffer attached */
719 #ifdef MWL_MBSS_SUPPORT
720 	uint8_t	macaddr[6];
721 #endif
722 	uint8_t	ActionData[1];
723 } HostCmd_FW_UPDATE_ENCRYPTION;
724 
725 /*
726  * @HWENCR@
727  * Hardware Encryption related data structures and constant definitions.
728  * Note that all related changes are marked with the @HWENCR@ tag.
729  */
730 
731 #define	MAX_ENCR_KEY_LENGTH	16	/* max 128 bits - depends on type */
732 #define	MIC_KEY_LENGTH		8	/* size of Tx/Rx MIC key - 8 bytes */
733 
734 #define	ENCR_KEY_TYPE_ID_WEP	0x00	/* Key type is WEP */
735 #define	ENCR_KEY_TYPE_ID_TKIP	0x01	/* Key type is TKIP */
736 #define	ENCR_KEY_TYPE_ID_AES	0x02	/* Key type is AES-CCMP	*/
737 
738 /*
739  * flags used in structure - same as driver EKF_XXX flags
740  */
741 /* indicate key is in use */
742 #define	ENCR_KEY_FLAG_INUSE		0x00000001
743 /* Group key for RX only */
744 #define	ENCR_KEY_FLAG_RXGROUPKEY	0x00000002
745 /* Group key for TX */
746 #define	ENCR_KEY_FLAG_TXGROUPKEY	0x00000004
747 /* pairwise */
748 #define	ENCR_KEY_FLAG_PAIRWISE		0x00000008
749 /* only used for RX */
750 #define	ENCR_KEY_FLAG_RXONLY		0x00000010
751 /*
752  * These flags are new additions - for hardware encryption commands only
753  */
754 /* Key is for Authenticator */
755 #define	ENCR_KEY_FLAG_AUTHENTICATOR	0x00000020
756 /* Sequence counters valid */
757 #define	ENCR_KEY_FLAG_TSC_VALID		0x00000040
758 /* Tx key for WEP */
759 #define	ENCR_KEY_FLAG_WEP_TXKEY		0x01000000
760 /* Tx/Rx MIC keys are valid */
761 #define	ENCR_KEY_FLAG_MICKEY_VALID	0x02000000
762 
763 /*
764  * Key material definitions (for WEP, TKIP, & AES-CCMP)
765  */
766 
767 /*
768  * WEP Key material definition
769  * ----------------------------
770  * WEPKey	--> An array of 'MAX_ENCR_KEY_LENGTH' bytes.
771  * Note that we do not support 152bit WEP keys
772  */
773 typedef struct {
774 	/* WEP key material (max 128bit) */
775 	uint8_t	KeyMaterial[MAX_ENCR_KEY_LENGTH];
776 } WEP_TYPE_KEY;
777 
778 /*
779  * TKIP Key material definition
780  * ----------------------------
781  * This structure defines TKIP key material. Note that
782  * the TxMicKey and RxMicKey may or may not be valid.
783  */
784 /*
785  * TKIP Sequence counter - 24 bits
786  * Incremented on each fragment MPDU
787  */
788 typedef struct {
789 	uint16_t	low;
790 	uint32_t	high;
791 } ENCR_TKIPSEQCNT;
792 
793 /*
794  * TKIP Key material. Key type (group or pairwise key) is
795  * determined by flags in KEY_PARAM_SET structure
796  */
797 typedef struct {
798 	uint8_t		KeyMaterial[MAX_ENCR_KEY_LENGTH];
799 	uint8_t		TkipTxMicKey[MIC_KEY_LENGTH];
800 	uint8_t		TkipRxMicKey[MIC_KEY_LENGTH];
801 	ENCR_TKIPSEQCNT	TkipRsc;
802 	ENCR_TKIPSEQCNT	TkipTsc;
803 } TKIP_TYPE_KEY;
804 
805 /*
806  * AES-CCMP Key material definition
807  * --------------------------------
808  * This structure defines AES-CCMP key material.
809  */
810 typedef struct {
811 	/* AES Key material */
812 	uint8_t	KeyMaterial[MAX_ENCR_KEY_LENGTH];
813 } AES_TYPE_KEY;
814 
815 /*
816  * UPDATE_ENCRYPTION command action type.
817  */
818 typedef enum {
819 	/* request to enable/disable HW encryption */
820 	EncrActionEnableHWEncryption,
821 	/* request to set encryption key */
822 	EncrActionTypeSetKey,
823 	/* request to remove one or more keys */
824 	EncrActionTypeRemoveKey,
825 	EncrActionTypeSetGroupKey
826 } ENCR_ACTION_TYPE;
827 
828 /*
829  * Encryption key definition.
830  * --------------------------
831  * This structure provides all required/essential
832  * information about the key being set/removed.
833  */
834 typedef struct {
835 	uint16_t	Length;		/* Total length of this structure */
836 	uint16_t	KeyTypeId;	/* Key type - WEP, TKIP or AES-CCMP */
837 	uint32_t	KeyInfo;	/* key flags */
838 	uint32_t	KeyIndex; 	/* For WEP only - actual key index */
839 	uint16_t	KeyLen;		/* Size of the key */
840 	union {				/* Key material (variable size array) */
841 		WEP_TYPE_KEY	WepKey;
842 		TKIP_TYPE_KEY	TkipKey;
843 		AES_TYPE_KEY	AesKey;
844 	} Key;
845 #ifdef MWL_MBSS_SUPPORT
846 	uint8_t	Macaddr[6];
847 #endif
848 } KEY_PARAM_SET;
849 
850 
851 typedef struct {
852 	FWCmdHdr	CmdHdr;
853 	uint32_t	ActionType;	/* ENCR_ACTION_TYPE */
854 	uint32_t	DataLength;	/* size of the data buffer attached */
855 	KEY_PARAM_SET	KeyParam;
856 #ifndef MWL_MBSS_SUPPORT
857 	uint8_t		Macaddr[8];
858 #endif
859 } HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY;
860 #pragma pack()
861 
862 #ifdef __cplusplus
863 }
864 #endif
865 
866 #endif /* _MWL_REG_H */
867