Searched defs:Srl (Results 1 – 9 of 9) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 68 SDValue Srl = In.getOperand(0); in isExtractHiElt() local
2310 const SDValue &Srl = N->getOperand(0); in SelectS_BFE() local
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| H A D | SIISelLowering.cpp | 13471 SDValue Srl = DAG.getNode(ISD::SRL, SL, MVT::i32, Elt, in performExtractVectorEltCombine() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 2060 SDValue Srl = DAG.getNode(ISD::SRL, DL, XVT, X, Eight); in foldMaskAndShiftToExtract() local
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| H A D | X86ISelLowering.cpp | 30247 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, R, in LowerRotate() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 470 SDValue Srl = N1.getOperand(0); in PreprocessISelDAG() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 13678 SDValue Srl = DAG.getNode(ISD::SRL, DL, MVT::i64, Op0, Op1); performTRUNCATECombine() local
13706 SDValue Srl = DAG.getNode(ISD::SRL, DL, MVT::i64, Op0, Op1); performANDCombine() local
14028 SDValue Srl = And.getOperand(0); combineVectorMulToSraBitcast() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 7086 auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub); in lowerFPTOSI() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 18179 SDValue Srl = And.getOperand(0); in performMulVectorCmpZeroCombine() local
22119 static SDValue trySimplifySrlAddToRshrnb(SDValue Srl, SelectionDAG &DAG, in trySimplifySrlAddToRshrnb()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 4814 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); in visitSDIVLike() local
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