| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600OptimizeVectorRegisters.cpp | 187 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() local
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| H A D | SIISelLowering.cpp | 4749 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in emitIndirectDst() local
8705 SDValue SrcVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, in LowerINTRINSIC_WO_CHAIN() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 480 Register SrcVec = Left; in matchINS() local
498 Register DstVec, SrcVec; in applyINS() local
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | Verifier.cpp | 3304 bool SrcVec = SrcTy->isVectorTy(); in visitUIToFPInst() local
3327 bool SrcVec = SrcTy->isVectorTy(); in visitSIToFPInst() local
3350 bool SrcVec = SrcTy->isVectorTy(); in visitFPToUIInst() local
3372 bool SrcVec = SrcTy->isVectorTy(); in visitFPToSIInst() local
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CodeGenFunction.cpp | 3053 llvm::Value *CodeGenFunction::emitBoolVecConversion(llvm::Value *SrcVec, in emitBoolVecConversion()
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| /freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/ |
| H A D | Execution.cpp | 1513 GenericValue TempDst, TempSrc, SrcVec; in executeBitCastInst() local
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineVectorOps.cpp | 399 Value *SrcVec = EI.getVectorOperand(); in visitExtractElementInst() local
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VectorCombine.cpp | 643 Value *SrcVec; in foldInsExtFNeg() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 1992 unsigned &Index) -> bool { in LowerConvertLow()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 7529 Register SrcVec = MI.getOperand(1).getReg(); in lowerExtractInsertVectorElt() local
7621 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; in lowerShuffleVector() local
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| H A D | CombinerHelper.cpp | 4125 Register SrcVec = MI.getOperand(1).getReg(); in matchExtractVecEltBuildVec() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 863 __anona938eeb30302(SDValue &SrcVec, SmallVectorImpl<int> &SrcIdx) buildHvxVectorReg() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 6054 SDValue SrcVec = SrcExtract.getOperand(0); in getFauxShuffleMask() local
8459 static SDValue createVariablePermute(MVT VT, SDValue SrcVec, SDValue IndicesVec, in createVariablePermute()
8731 SDValue SrcVec, IndicesVec; in LowerBUILD_VECTORAsVariablePermute() local
39770 SDValue SrcVec = Op.getOperand(0); in combineX86ShufflesRecursively() local
44646 combineExtractFromVectorLoad(SDNode *N, EVT VecVT, SDValue SrcVec, uint64_t Idx, in combineExtractFromVectorLoad()
50076 SDValue SrcVec = N0.getOperand(0); in combineAnd() local
56127 SDValue SrcVec = Op0.getOperand(0); in combineConcatVectorOps() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 5064 SDValue SrcVec = (unsigned)SrcVecIdx >= VRegsPerSrc ? V2 : V1; lowerShuffleViaVRegSplitting() local
12987 SDValue SrcVec = RHS.getOperand(0); combineBinOpOfExtractToReduceTree() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 13269 SDValue SrcVec = V1; in LowerVECTOR_SHUFFLE() local
20223 SDValue SrcVec = Elt0->getOperand(0)->getOperand(0); in performBuildVectorCombine() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 15110 SDValue SrcVec = Ext1.getOperand(0); in DAGCombineBuildVector() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 26466 SDValue SrcVec = Scalar.getOperand(0); in visitSCALAR_TO_VECTOR() local
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