| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 179 Register &SrcReg2, int64_t &CmpMask, in analyzeCompare()
207 unsigned SrcReg2, int64_t ImmValue, in isRedundantFlagInstr()
285 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, in optimizeCompareInstr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PreLegalizerCombiner.cpp | 562 Register DstReg, Register SrcReg1, Register SrcReg2) { in matchPushAddSubExt()
588 Register SrcReg1, Register SrcReg2) { in applyPushAddSubExt()
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| H A D | AArch64LegalizerInfo.cpp | 1410 Register SrcReg2 = MI.getOperand(3).getReg(); in legalizeICMP() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMCCodeEmitter.cpp | 250 MCRegister SrcReg2 = MI.getOperand(1).getReg(); in expandLongCondBr() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SIMDInstrOpt.cpp | 441 Register SrcReg2 = MI.getOperand(3).getReg(); optimizeVectElement() local
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| H A D | AArch64InstrInfo.cpp | 1175 Register &SrcReg2, int64_t &CmpMask, in analyzeCompare()
1536 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, in optimizeCompareInstr()
6673 Register SrcReg2; in genFusedMultiply() local
6735 Register SrcReg2 = MAD->getOperand(3).getReg(); in genFNegatedMAD() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZElimCompare.cpp | 613 Register SrcReg2 = in fuseCompareOperations() local
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| H A D | SystemZInstrInfo.cpp | 534 Register &SrcReg2, int64_t &Mask, in analyzeCompare()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 854 unsigned SrcReg2 = 0; in PPCEmitCmp() local
1358 Register SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
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| H A D | PPCInstrInfo.cpp | 2348 Register &SrcReg2, int64_t &Mask, in analyzeCompare()
2378 Register SrcReg2, int64_t Mask, in optimizeCompareInstr()
2767 Register SrcReg, SrcReg2; in optimizeCmpPostRA() local
5405 Register SrcReg2 = MI->getOperand(2).getReg(); in isSignOrZeroExtended() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1713 Register &SrcReg2, int64_t &Mask, in analyzeCompare()
1722 Register SrcReg2, int64_t Mask, in optimizeCompareInstr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1415 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1763 Register SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
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| H A D | ARMBaseInstrInfo.cpp | 2789 Register &SrcReg2, int64_t &CmpMask, in analyzeCompare()
2860 Register SrcReg, Register SrcReg2, in isRedundantFlagInstr()
3015 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, in optimizeCompareInstr()
3302 Register SrcReg, SrcReg2; in shouldSink() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 1431 Register SrcReg, SrcReg2; in convertToThreeAddress() local
4766 Register &SrcReg2, int64_t &CmpMask, in analyzeCompare()
4842 Register SrcReg, Register SrcReg2, in isRedundantFlagInstr()
5204 Register SrcReg2, int64_t CmpMask, in optimizeCompareInstr()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 670 Register SrcReg, SrcReg2; in optimizeCmpInstr() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1881 Register &SrcReg2, int64_t &Mask, in analyzeCompare()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 9708 Register &SrcReg2, int64_t &CmpMask, in analyzeCompare()
9767 Register SrcReg2, int64_t CmpMask, in optimizeCompareInstr()
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