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Searched defs:SrcR (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonTfrCleanup.cpp204 unsigned SrcR = MI->getOperand(1).getReg(); in rewriteIfImm() local
244 unsigned DefR, SrcR; in eraseIfRedundant() local
H A DRDFCopy.cpp47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg()); in interpretAsCopy() local
H A DHexagonRDFOpt.cpp118 auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonGenInsert.cpp470 unsigned SrcR, InsR; member
486 unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR; in operator <<() local
674 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR, in isValidInsertForm()
864 for (unsigned SrcR : AVs) { in findRecordInsertForms() local
H A DHexagonFrameLowering.cpp1724 Register SrcR = MI->getOperand(1).getReg(); in expandCopy() local
1748 Register SrcR = MI->getOperand(2).getReg(); in expandStoreInt() local
1811 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVecPred() local
1898 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVec2() local
1987 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVec() local
H A DHexagonConstPropagation.cpp1942 RegisterSubReg SrcR(MI.getOperand(1)); in evaluate() local
H A DHexagonBitSimplify.cpp2246 unsigned SrcR = B0.RefI.Reg; in genBitSplit() local
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp725 const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index; processInstructionForSlowLEA() local