| /freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/ |
| H A D | Execution.cpp | 109 GenericValue Src2, Type *Ty) { in executeFAddInst()
120 GenericValue Src2, Type *Ty) { in executeFSubInst()
131 GenericValue Src2, Type *Ty) { in executeFMulInst()
142 GenericValue Src2, Type *Ty) { in executeFDivInst()
153 GenericValue Src2, Type *Ty) { in executeFRemInst()
192 static GenericValue executeICMP_EQ(GenericValue Src1, GenericValue Src2, in executeICMP_EQ()
206 static GenericValue executeICMP_NE(GenericValue Src1, GenericValue Src2, in executeICMP_NE()
220 static GenericValue executeICMP_ULT(GenericValue Src1, GenericValue Src2, in executeICMP_ULT()
234 static GenericValue executeICMP_SLT(GenericValue Src1, GenericValue Src2, in executeICMP_SLT()
248 static GenericValue executeICMP_UGT(GenericValue Src1, GenericValue Src2, in executeICMP_UGT()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUMacroFusion.cpp | 46 const MachineOperand *Src2 = TII.getNamedOperand(SecondMI, in shouldScheduleAdjacent() local
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| H A D | AMDGPUCombinerHelper.cpp | 421 Register Src2) { in matchExpandPromotedF16FMed3()
434 Register Src2) { in applyExpandPromotedF16FMed3()
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| H A D | SIShrinkInstructions.cpp | 420 MachineOperand &Src2 = *TII->getNamedOperand(MI, AMDGPU::OpName::src2); in shrinkMadFma() local
977 const MachineOperand *Src2 = in runOnMachineFunction() local
1005 const MachineOperand *Src2 = TII->getNamedOperand(MI, in runOnMachineFunction() local
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| H A D | GCNDPPCombine.cpp | 344 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in createDPPInst() local
691 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in combineDPPMov() local
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| H A D | SIOptimizeExecMasking.cpp | 146 const MachineOperand &Src2 = MI.getOperand(2); in isLogicalOpOnExec() local
162 const MachineOperand &Src2 = MI.getOperand(2); in isLogicalOpOnExec() local
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| H A D | SIPeepholeSDWA.cpp | 665 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in matchSDWAOperand() local
1084 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in convertToSDWA() local
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| H A D | AMDGPURegBankCombiner.cpp | 318 MachineInstr *Src2 = getDefIgnoringCopies(MI.getOperand(3).getReg(), MRI); in matchFPMed3ToClamp() local
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| H A D | AMDGPUInstCombineIntrinsic.cpp | 46 const APFloat &Src2) { in fmed3AMDGCN()
765 Value *Src2 = II.getArgOperand(2); in instCombineIntrinsic() local
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| H A D | SIInstrInfo.cpp | 3524 MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2); in foldImmediate() local
3935 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2); in convertToThreeAddress() local
4417 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2); in canShrink() local
4503 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2); in buildShrunkInst() local
5006 const MachineOperand &Src2 = MI.getOperand(Src2Idx); in verifyInstruction() local
5980 MachineOperand &Src2 = MI.getOperand(VOP3Idx[2]); in legalizeOperandsVOP3() local
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| H A D | SIISelLowering.cpp | 5134 MachineOperand &Src2 = MI.getOperand(4); in EmitInstrWithCustomInserter() local
6124 SDValue Src2, MVT ValT) -> SDValue { in lowerLaneOp()
6161 SDValue Src1, Src2; in lowerLaneOp() local
13277 SDValue Src2 = N->getOperand(2); in performFMed3Combine() local
14187 SDValue Src2 = in performAddCombine() local
15066 SDValue Src2 = Node->getOperand(5); in PostISelFolding() local
15261 if (auto *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2)) { in AdjustInstrPostInstrSelection() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPeephole.cpp | 152 MachineOperand &Src2 = MI.getOperand(2); in runOnMachineFunction() local
169 MachineOperand &Src2 = MI.getOperand(2); in runOnMachineFunction() local
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| H A D | HexagonGenMux.cpp | 299 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); in genMuxInBlock() local
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| H A D | HexagonConstPropagation.cpp | 2576 const MachineOperand &Src2 = MI.getOperand(2); in evaluateHexCompare() local
2598 const MachineOperand &Src1, const MachineOperand &Src2, in evaluateHexCompare2() argument
2633 const MachineOperand &Src2 = MI.getOperand(2); evaluateHexLogical() local
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZSelectionDAGInfo.cpp | 174 SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, in EmitTargetCodeForMemcmp()
226 SDValue Src2, MachinePointerInfo Op1PtrInfo, in EmitTargetCodeForStrcmp()
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| H A D | SystemZISelLowering.cpp | 4597 SDValue Src2 = Node->getVal(); in lowerATOMIC_LOAD_OP() local
4652 SDValue Src2 = Node->getVal(); in lowerATOMIC_LOAD_SUB() local
8564 MachineOperand Src2 = earlyUseOperand(MI.getOperand(3)); in emitAtomicLoadBinary() local
8659 Register Src2 = MI.getOperand(3).getReg(); in emitAtomicLoadMinMax() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEAsmPrinter.cpp | 154 MCOperand &Src2, MCOperand &RD, in emitBinary()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcAsmPrinter.cpp | 136 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | GISelKnownBits.cpp | 751 Register Src2 = MI.getOperand(2).getReg(); in computeNumSignBits() local
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| H A D | MachineIRBuilder.cpp | 770 const SrcOp &Src2, in buildShuffleVector()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 70 Register Src2 = MI.getOperand(2).getReg(); in matchExtractVecEltPairwiseAdd() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TwoAddressInstructionPass.cpp | 515 unsigned Src2 = UseOp->getOperandNo(); in findOnlyInterestingUse() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParser.cpp | 3842 unsigned Src2 = Inst.getOperand(Inst.getNumOperands() - in validateInstruction() local
3881 unsigned Src2 = Inst.getOperand(3).getReg(); in validateInstruction() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 1602 SDValue Src2 = Node->getOperand(2); in Select() local
1661 SDValue Src2 = Node->getOperand(3); in Select() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 1262 Register Src2; in convertToThreeAddressWithLEA() local
1570 const MachineOperand &Src2 = MI.getOperand(2); in convertToThreeAddress() local
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