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Searched defs:Src1 (Results 1 – 25 of 55) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp108 static void executeFAddInst(GenericValue &Dest, GenericValue Src1, in executeFAddInst()
119 static void executeFSubInst(GenericValue &Dest, GenericValue Src1, in executeFSubInst()
130 static void executeFMulInst(GenericValue &Dest, GenericValue Src1, in executeFMulInst()
141 static void executeFDivInst(GenericValue &Dest, GenericValue Src1, in executeFDivInst()
152 static void executeFRemInst(GenericValue &Dest, GenericValue Src1, in executeFRemInst()
192 static GenericValue executeICMP_EQ(GenericValue Src1, GenericValue Src2, in executeICMP_EQ()
206 static GenericValue executeICMP_NE(GenericValue Src1, GenericValue Src2, in executeICMP_NE()
220 static GenericValue executeICMP_ULT(GenericValue Src1, GenericValue Src2, in executeICMP_ULT()
234 static GenericValue executeICMP_SLT(GenericValue Src1, GenericValue Src2, in executeICMP_SLT()
248 static GenericValue executeICMP_UGT(GenericValue Src1, GenericValue Src2, in executeICMP_UGT()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIOptimizeExecMasking.cpp143 const MachineOperand &Src1 = MI.getOperand(1); in isLogicalOpOnExec() local
159 const MachineOperand &Src1 = MI.getOperand(1); in isLogicalOpOnExec() local
537 MachineOperand &Src1 = SaveExecInst->getOperand(2); in optimizeExecSequence() local
584 MachineOperand *Src1 = TII->getNamedOperand(VCmp, AMDGPU::OpName::src1); in optimizeVCMPSaveExecSequence() local
686 MachineOperand *Src1 = TII->getNamedOperand(*VCmp, AMDGPU::OpName::src1); in tryRecordVCmpxAndSaveexecSequence() local
H A DR600ExpandSpecialInstrs.cpp149 Register Src1 = in runOnMachineFunction() local
200 unsigned Src1 = 0; in runOnMachineFunction() local
H A DSIPeepholeSDWA.cpp590 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in matchSDWAOperand() local
627 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in matchSDWAOperand() local
660 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in matchSDWAOperand() local
707 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in matchSDWAOperand() local
1010 if (MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1)) { in isConvertibleToSDWA() local
1068 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in convertToSDWA() local
H A DAMDGPUCombinerHelper.cpp420 Register Src1, in matchExpandPromotedF16FMed3()
433 Register Src1, in applyExpandPromotedF16FMed3()
H A DSIShrinkInstructions.cpp247 MachineOperand &Src1 = MI.getOperand(1); in shrinkScalarCompare() local
419 MachineOperand &Src1 = *TII->getNamedOperand(MI, AMDGPU::OpName::src1); in shrinkMadFma() local
513 MachineOperand *Src1 = &MI.getOperand(2); in shrinkScalarLogicOp() local
848 MachineOperand *Src1 = &MI.getOperand(2); in runOnMachineFunction() local
H A DGCNDPPCombine.cpp314 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst() local
490 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst() local
685 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in combineDPPMov() local
H A DAMDGPUInstCombineIntrinsic.cpp45 static APFloat fmed3AMDGCN(const APFloat &Src0, const APFloat &Src1, in fmed3AMDGCN()
602 Value *Src1 = II.getArgOperand(1); in instCombineIntrinsic() local
632 Value *Src1 = II.getArgOperand(1); in instCombineIntrinsic() local
661 Value *Src1 = II.getArgOperand(1); in instCombineIntrinsic() local
764 Value *Src1 = II.getArgOperand(1); in instCombineIntrinsic() local
853 Value *Src1 = II.getArgOperand(1); in instCombineIntrinsic() local
H A DSIFoldOperands.cpp1231 MachineOperand *Src1 = getImmOrMaterializedImm(MI->getOperand(Src1Idx)); in tryConstantFoldOp() local
1317 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in tryFoldCndMask() local
1358 Register Src1 = MI.getOperand(2).getReg(); in tryFoldZeroHighBits() local
1532 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isClamp() local
1680 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isOMod() local
1717 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isOMod() local
H A DSIInstrInfo.cpp2721 MachineOperand &Src1, in swapSourceModifiers()
2788 MachineOperand &Src1 = MI.getOperand(Src1Idx); in commuteInstructionImpl() local
3523 MachineOperand *Src1 = getNamedOperand(UseMI, AMDGPU::OpName::src1); in foldImmediate() local
3932 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1); in convertToThreeAddress() local
4426 const MachineOperand *Src1 in canShrink() local
4451 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1); in canShrink() local
5005 const MachineOperand &Src1 = MI.getOperand(Src1Idx); in verifyInstruction() local
5027 const MachineOperand &Src1 = MI.getOperand(Src1Idx); in verifyInstruction() local
5857 MachineOperand &Src1 = MI.getOperand(Src1Idx); in legalizeOperandsVOP2() local
5979 MachineOperand &Src1 = MI.getOperand(VOP3Idx[1]); in legalizeOperandsVOP3() local
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H A DAMDGPURegBankCombiner.cpp317 MachineInstr *Src1 = getDefIgnoringCopies(MI.getOperand(2).getReg(), MRI); in matchFPMed3ToClamp() local
H A DAMDGPUPostLegalizerCombiner.cpp420 Register Src1 = MI.getOperand(2).getReg(); in matchCombine_s_mul_u64() local
H A DSIISelLowering.cpp4976 MachineOperand &Src1 = MI.getOperand(3); in EmitInstrWithCustomInserter() local
4999 MachineOperand &Src1 = MI.getOperand(2); in EmitInstrWithCustomInserter() local
5051 MachineOperand &Src1 = MI.getOperand(2); in EmitInstrWithCustomInserter() local
5133 MachineOperand &Src1 = MI.getOperand(3); in EmitInstrWithCustomInserter() local
5290 const MachineOperand &Src1 = MI.getOperand(2); in EmitInstrWithCustomInserter() local
6056 SDValue Src1 = N->getOperand(2); in lowerFCMPIntrinsic() local
6124 SDValue Src2, MVT ValT) -> SDValue { in lowerLaneOp()
6161 SDValue Src1, Src2; in lowerLaneOp() local
6313 SDValue Src1 = N->getOperand(2); in ReplaceNodeResults() local
6325 SDValue Src1 = N->getOperand(2); in ReplaceNodeResults() local
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H A DSILoadStoreOptimizer.cpp1264 const auto *Src1 = TII->getNamedOperand(*Paired.I, OpName); in copyFromSrcRegs() local
2052 const auto *Src1 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1); in processBaseWithConstOffset() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp151 MachineOperand &Src1 = MI.getOperand(1); in runOnMachineFunction() local
168 MachineOperand &Src1 = MI.getOperand(1); in runOnMachineFunction() local
H A DHexagonGenMux.cpp205 unsigned HexagonGenMux::getMuxOpcode(const MachineOperand &Src1, in getMuxOpcode()
299 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); in genMuxInBlock() local
H A DHexagonConstPropagation.cpp2575 const MachineOperand &Src1 = MI.getOperand(1); in evaluateHexCompare() local
2598 const MachineOperand &Src1, const MachineOperand &Src2, in evaluateHexCompare2() argument
2632 const MachineOperand &Src1 = MI.getOperand(1); evaluateHexLogical() local
3026 const MachineOperand &Src1 = MI.getOperand(1); rewriteHexConstUses() local
[all...]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp112 void GISelKnownBits::computeKnownBitsMin(Register Src0, Register Src1, in computeKnownBitsMin()
619 unsigned GISelKnownBits::computeNumSignBitsMin(Register Src0, Register Src1, in computeNumSignBitsMin()
747 Register Src1 = MI.getOperand(1).getReg(); in computeNumSignBits() local
H A DCSEMIRBuilder.cpp262 const SrcOp &Src1 = SrcOps[1]; in buildInstr() local
H A DMachineIRBuilder.cpp769 const SrcOp &Src1, in buildShuffleVector()
936 const SrcOp &Src1, in buildInsertSubvector()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h1791 const SrcOp &Src1) { in buildAnd()
1813 const SrcOp &Src1) { in buildXor()
1979 const SrcOp &Src1) { in buildFCopysign()
2013 const SrcOp &Src1) { in buildSMin()
2019 const SrcOp &Src1) { in buildSMax()
2025 const SrcOp &Src1) { in buildUMin()
2031 const SrcOp &Src1) { in buildUMax()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp173 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, in EmitTargetCodeForMemcmp()
225 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, in EmitTargetCodeForStrcmp()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp299 unsigned Src1 = 0, SubReg1; in transformInstruction() local
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp54 Register Src1) { in PairedCopy()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp69 Register Src1 = MI.getOperand(1).getReg(); in matchExtractVecEltPairwiseAdd() local

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