1 //==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API of helper functions used throughout the
10 /// GlobalISel pipeline.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H
15 #define LLVM_CODEGEN_GLOBALISEL_UTILS_H
16
17 #include "GISelWorkList.h"
18 #include "llvm/ADT/APFloat.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/CodeGen/Register.h"
21 #include "llvm/CodeGenTypes/LowLevelType.h"
22 #include "llvm/IR/DebugLoc.h"
23 #include "llvm/Support/Alignment.h"
24 #include "llvm/Support/Casting.h"
25 #include "llvm/Support/Compiler.h"
26
27 #include <cstdint>
28
29 namespace llvm {
30
31 class AnalysisUsage;
32 class LostDebugLocObserver;
33 class MachineBasicBlock;
34 class BlockFrequencyInfo;
35 class GISelValueTracking;
36 class MachineFunction;
37 class MachineInstr;
38 class MachineIRBuilder;
39 class MachineOperand;
40 class MachineOptimizationRemarkEmitter;
41 class MachineOptimizationRemarkMissed;
42 struct MachinePointerInfo;
43 class MachineRegisterInfo;
44 class MCInstrDesc;
45 class ProfileSummaryInfo;
46 class RegisterBankInfo;
47 class TargetInstrInfo;
48 class TargetLowering;
49 class TargetPassConfig;
50 class TargetRegisterInfo;
51 class TargetRegisterClass;
52 class ConstantFP;
53 class APFloat;
54
55 // Convenience macros for dealing with vector reduction opcodes.
56 #define GISEL_VECREDUCE_CASES_ALL \
57 case TargetOpcode::G_VECREDUCE_SEQ_FADD: \
58 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: \
59 case TargetOpcode::G_VECREDUCE_FADD: \
60 case TargetOpcode::G_VECREDUCE_FMUL: \
61 case TargetOpcode::G_VECREDUCE_FMAX: \
62 case TargetOpcode::G_VECREDUCE_FMIN: \
63 case TargetOpcode::G_VECREDUCE_FMAXIMUM: \
64 case TargetOpcode::G_VECREDUCE_FMINIMUM: \
65 case TargetOpcode::G_VECREDUCE_ADD: \
66 case TargetOpcode::G_VECREDUCE_MUL: \
67 case TargetOpcode::G_VECREDUCE_AND: \
68 case TargetOpcode::G_VECREDUCE_OR: \
69 case TargetOpcode::G_VECREDUCE_XOR: \
70 case TargetOpcode::G_VECREDUCE_SMAX: \
71 case TargetOpcode::G_VECREDUCE_SMIN: \
72 case TargetOpcode::G_VECREDUCE_UMAX: \
73 case TargetOpcode::G_VECREDUCE_UMIN:
74
75 #define GISEL_VECREDUCE_CASES_NONSEQ \
76 case TargetOpcode::G_VECREDUCE_FADD: \
77 case TargetOpcode::G_VECREDUCE_FMUL: \
78 case TargetOpcode::G_VECREDUCE_FMAX: \
79 case TargetOpcode::G_VECREDUCE_FMIN: \
80 case TargetOpcode::G_VECREDUCE_FMAXIMUM: \
81 case TargetOpcode::G_VECREDUCE_FMINIMUM: \
82 case TargetOpcode::G_VECREDUCE_ADD: \
83 case TargetOpcode::G_VECREDUCE_MUL: \
84 case TargetOpcode::G_VECREDUCE_AND: \
85 case TargetOpcode::G_VECREDUCE_OR: \
86 case TargetOpcode::G_VECREDUCE_XOR: \
87 case TargetOpcode::G_VECREDUCE_SMAX: \
88 case TargetOpcode::G_VECREDUCE_SMIN: \
89 case TargetOpcode::G_VECREDUCE_UMAX: \
90 case TargetOpcode::G_VECREDUCE_UMIN:
91
92 /// Try to constrain Reg to the specified register class. If this fails,
93 /// create a new virtual register in the correct class.
94 ///
95 /// \return The virtual register constrained to the right register class.
96 LLVM_ABI Register constrainRegToClass(MachineRegisterInfo &MRI,
97 const TargetInstrInfo &TII,
98 const RegisterBankInfo &RBI, Register Reg,
99 const TargetRegisterClass &RegClass);
100
101 /// Constrain the Register operand OpIdx, so that it is now constrained to the
102 /// TargetRegisterClass passed as an argument (RegClass).
103 /// If this fails, create a new virtual register in the correct class and insert
104 /// a COPY before \p InsertPt if it is a use or after if it is a definition.
105 /// In both cases, the function also updates the register of RegMo. The debug
106 /// location of \p InsertPt is used for the new copy.
107 ///
108 /// \return The virtual register constrained to the right register class.
109 LLVM_ABI Register constrainOperandRegClass(
110 const MachineFunction &MF, const TargetRegisterInfo &TRI,
111 MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
112 const RegisterBankInfo &RBI, MachineInstr &InsertPt,
113 const TargetRegisterClass &RegClass, MachineOperand &RegMO);
114
115 /// Try to constrain Reg so that it is usable by argument OpIdx of the provided
116 /// MCInstrDesc \p II. If this fails, create a new virtual register in the
117 /// correct class and insert a COPY before \p InsertPt if it is a use or after
118 /// if it is a definition. In both cases, the function also updates the register
119 /// of RegMo.
120 /// This is equivalent to constrainOperandRegClass(..., RegClass, ...)
121 /// with RegClass obtained from the MCInstrDesc. The debug location of \p
122 /// InsertPt is used for the new copy.
123 ///
124 /// \return The virtual register constrained to the right register class.
125 LLVM_ABI Register constrainOperandRegClass(
126 const MachineFunction &MF, const TargetRegisterInfo &TRI,
127 MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
128 const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
129 MachineOperand &RegMO, unsigned OpIdx);
130
131 /// Mutate the newly-selected instruction \p I to constrain its (possibly
132 /// generic) virtual register operands to the instruction's register class.
133 /// This could involve inserting COPYs before (for uses) or after (for defs).
134 /// This requires the number of operands to match the instruction description.
135 /// \returns whether operand regclass constraining succeeded.
136 ///
137 // FIXME: Not all instructions have the same number of operands. We should
138 // probably expose a constrain helper per operand and let the target selector
139 // constrain individual registers, like fast-isel.
140 LLVM_ABI bool constrainSelectedInstRegOperands(MachineInstr &I,
141 const TargetInstrInfo &TII,
142 const TargetRegisterInfo &TRI,
143 const RegisterBankInfo &RBI);
144
145 /// Check if DstReg can be replaced with SrcReg depending on the register
146 /// constraints.
147 LLVM_ABI bool canReplaceReg(Register DstReg, Register SrcReg,
148 MachineRegisterInfo &MRI);
149
150 /// Check whether an instruction \p MI is dead: it only defines dead virtual
151 /// registers, and doesn't have other side effects.
152 LLVM_ABI bool isTriviallyDead(const MachineInstr &MI,
153 const MachineRegisterInfo &MRI);
154
155 /// Report an ISel error as a missed optimization remark to the LLVMContext's
156 /// diagnostic stream. Set the FailedISel MachineFunction property.
157 LLVM_ABI void reportGISelFailure(MachineFunction &MF,
158 const TargetPassConfig &TPC,
159 MachineOptimizationRemarkEmitter &MORE,
160 MachineOptimizationRemarkMissed &R);
161
162 LLVM_ABI void reportGISelFailure(MachineFunction &MF,
163 const TargetPassConfig &TPC,
164 MachineOptimizationRemarkEmitter &MORE,
165 const char *PassName, StringRef Msg,
166 const MachineInstr &MI);
167
168 /// Report an ISel warning as a missed optimization remark to the LLVMContext's
169 /// diagnostic stream.
170 LLVM_ABI void reportGISelWarning(MachineFunction &MF,
171 const TargetPassConfig &TPC,
172 MachineOptimizationRemarkEmitter &MORE,
173 MachineOptimizationRemarkMissed &R);
174
175 /// Returns the inverse opcode of \p MinMaxOpc, which is a generic min/max
176 /// opcode like G_SMIN.
177 LLVM_ABI unsigned getInverseGMinMaxOpcode(unsigned MinMaxOpc);
178
179 /// If \p VReg is defined by a G_CONSTANT, return the corresponding value.
180 LLVM_ABI std::optional<APInt>
181 getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI);
182
183 /// If \p VReg is defined by a G_CONSTANT fits in int64_t returns it.
184 LLVM_ABI std::optional<int64_t>
185 getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI);
186
187 /// \p VReg is defined by a G_CONSTANT, return the corresponding value.
188 LLVM_ABI const APInt &getIConstantFromReg(Register VReg,
189 const MachineRegisterInfo &MRI);
190
191 /// Simple struct used to hold a constant integer value and a virtual
192 /// register.
193 struct ValueAndVReg {
194 APInt Value;
195 Register VReg;
196 };
197
198 /// If \p VReg is defined by a statically evaluable chain of instructions rooted
199 /// on a G_CONSTANT returns its APInt value and def register.
200 LLVM_ABI std::optional<ValueAndVReg>
201 getIConstantVRegValWithLookThrough(Register VReg,
202 const MachineRegisterInfo &MRI,
203 bool LookThroughInstrs = true);
204
205 /// If \p VReg is defined by a statically evaluable chain of instructions rooted
206 /// on a G_CONSTANT or G_FCONSTANT returns its value as APInt and def register.
207 LLVM_ABI std::optional<ValueAndVReg> getAnyConstantVRegValWithLookThrough(
208 Register VReg, const MachineRegisterInfo &MRI,
209 bool LookThroughInstrs = true, bool LookThroughAnyExt = false);
210
211 struct FPValueAndVReg {
212 APFloat Value;
213 Register VReg;
214 };
215
216 /// If \p VReg is defined by a statically evaluable chain of instructions rooted
217 /// on a G_FCONSTANT returns its APFloat value and def register.
218 LLVM_ABI std::optional<FPValueAndVReg>
219 getFConstantVRegValWithLookThrough(Register VReg,
220 const MachineRegisterInfo &MRI,
221 bool LookThroughInstrs = true);
222
223 LLVM_ABI const ConstantFP *getConstantFPVRegVal(Register VReg,
224 const MachineRegisterInfo &MRI);
225
226 /// See if Reg is defined by an single def instruction that is
227 /// Opcode. Also try to do trivial folding if it's a COPY with
228 /// same types. Returns null otherwise.
229 LLVM_ABI MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
230 const MachineRegisterInfo &MRI);
231
232 /// Simple struct used to hold a Register value and the instruction which
233 /// defines it.
234 struct DefinitionAndSourceRegister {
235 MachineInstr *MI;
236 Register Reg;
237 };
238
239 /// Find the def instruction for \p Reg, and underlying value Register folding
240 /// away any copies.
241 ///
242 /// Also walks through hints such as G_ASSERT_ZEXT.
243 LLVM_ABI std::optional<DefinitionAndSourceRegister>
244 getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI);
245
246 /// Find the def instruction for \p Reg, folding away any trivial copies. May
247 /// return nullptr if \p Reg is not a generic virtual register.
248 ///
249 /// Also walks through hints such as G_ASSERT_ZEXT.
250 LLVM_ABI MachineInstr *getDefIgnoringCopies(Register Reg,
251 const MachineRegisterInfo &MRI);
252
253 /// Find the source register for \p Reg, folding away any trivial copies. It
254 /// will be an output register of the instruction that getDefIgnoringCopies
255 /// returns. May return an invalid register if \p Reg is not a generic virtual
256 /// register.
257 ///
258 /// Also walks through hints such as G_ASSERT_ZEXT.
259 LLVM_ABI Register getSrcRegIgnoringCopies(Register Reg,
260 const MachineRegisterInfo &MRI);
261
262 /// Helper function to split a wide generic register into bitwise blocks with
263 /// the given Type (which implies the number of blocks needed). The generic
264 /// registers created are appended to Ops, starting at bit 0 of Reg.
265 LLVM_ABI void extractParts(Register Reg, LLT Ty, int NumParts,
266 SmallVectorImpl<Register> &VRegs,
267 MachineIRBuilder &MIRBuilder,
268 MachineRegisterInfo &MRI);
269
270 /// Version which handles irregular splits.
271 LLVM_ABI bool extractParts(Register Reg, LLT RegTy, LLT MainTy, LLT &LeftoverTy,
272 SmallVectorImpl<Register> &VRegs,
273 SmallVectorImpl<Register> &LeftoverVRegs,
274 MachineIRBuilder &MIRBuilder,
275 MachineRegisterInfo &MRI);
276
277 /// Version which handles irregular sub-vector splits.
278 LLVM_ABI void extractVectorParts(Register Reg, unsigned NumElts,
279 SmallVectorImpl<Register> &VRegs,
280 MachineIRBuilder &MIRBuilder,
281 MachineRegisterInfo &MRI);
282
283 // Templated variant of getOpcodeDef returning a MachineInstr derived T.
284 /// See if Reg is defined by an single def instruction of type T
285 /// Also try to do trivial folding if it's a COPY with
286 /// same types. Returns null otherwise.
287 template <class T>
getOpcodeDef(Register Reg,const MachineRegisterInfo & MRI)288 T *getOpcodeDef(Register Reg, const MachineRegisterInfo &MRI) {
289 MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI);
290 return dyn_cast_or_null<T>(DefMI);
291 }
292
293 /// Returns an APFloat from Val converted to the appropriate size.
294 LLVM_ABI APFloat getAPFloatFromSize(double Val, unsigned Size);
295
296 /// Modify analysis usage so it preserves passes required for the SelectionDAG
297 /// fallback.
298 LLVM_ABI void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU);
299
300 LLVM_ABI std::optional<APInt> ConstantFoldBinOp(unsigned Opcode,
301 const Register Op1,
302 const Register Op2,
303 const MachineRegisterInfo &MRI);
304 LLVM_ABI std::optional<APFloat>
305 ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2,
306 const MachineRegisterInfo &MRI);
307
308 /// Tries to constant fold a vector binop with sources \p Op1 and \p Op2.
309 /// Returns an empty vector on failure.
310 LLVM_ABI SmallVector<APInt>
311 ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2,
312 const MachineRegisterInfo &MRI);
313
314 LLVM_ABI std::optional<APInt>
315 ConstantFoldCastOp(unsigned Opcode, LLT DstTy, const Register Op0,
316 const MachineRegisterInfo &MRI);
317
318 LLVM_ABI std::optional<APInt> ConstantFoldExtOp(unsigned Opcode,
319 const Register Op1,
320 uint64_t Imm,
321 const MachineRegisterInfo &MRI);
322
323 LLVM_ABI std::optional<APFloat>
324 ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src,
325 const MachineRegisterInfo &MRI);
326
327 /// Tries to constant fold a counting-zero operation (G_CTLZ or G_CTTZ) on \p
328 /// Src. If \p Src is a vector then it tries to do an element-wise constant
329 /// fold.
330 LLVM_ABI std::optional<SmallVector<unsigned>>
331 ConstantFoldCountZeros(Register Src, const MachineRegisterInfo &MRI,
332 std::function<unsigned(APInt)> CB);
333
334 LLVM_ABI std::optional<SmallVector<APInt>>
335 ConstantFoldICmp(unsigned Pred, const Register Op1, const Register Op2,
336 unsigned DstScalarSizeInBits, unsigned ExtOp,
337 const MachineRegisterInfo &MRI);
338
339 /// Test if the given value is known to have exactly one bit set. This differs
340 /// from computeKnownBits in that it doesn't necessarily determine which bit is
341 /// set.
342 LLVM_ABI bool
343 isKnownToBeAPowerOfTwo(Register Val, const MachineRegisterInfo &MRI,
344 GISelValueTracking *ValueTracking = nullptr);
345
346 /// Returns true if \p Val can be assumed to never be a NaN. If \p SNaN is true,
347 /// this returns if \p Val can be assumed to never be a signaling NaN.
348 LLVM_ABI bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
349 bool SNaN = false);
350
351 /// Returns true if \p Val can be assumed to never be a signaling NaN.
isKnownNeverSNaN(Register Val,const MachineRegisterInfo & MRI)352 inline bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI) {
353 return isKnownNeverNaN(Val, MRI, true);
354 }
355
356 LLVM_ABI Align inferAlignFromPtrInfo(MachineFunction &MF,
357 const MachinePointerInfo &MPO);
358
359 /// Return a virtual register corresponding to the incoming argument register \p
360 /// PhysReg. This register is expected to have class \p RC, and optional type \p
361 /// RegTy. This assumes all references to the register will use the same type.
362 ///
363 /// If there is an existing live-in argument register, it will be returned.
364 /// This will also ensure there is a valid copy
365 LLVM_ABI Register getFunctionLiveInPhysReg(
366 MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg,
367 const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy = LLT());
368
369 /// Return the least common multiple type of \p OrigTy and \p TargetTy, by
370 /// changing the number of vector elements or scalar bitwidth. The intent is a
371 /// G_MERGE_VALUES, G_BUILD_VECTOR, or G_CONCAT_VECTORS can be constructed from
372 /// \p OrigTy elements, and unmerged into \p TargetTy. It is an error to call
373 /// this function where one argument is a fixed vector and the other is a
374 /// scalable vector, since it is illegal to build a G_{MERGE|UNMERGE}_VALUES
375 /// between fixed and scalable vectors.
376 LLVM_ABI LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy);
377
378 LLVM_ABI LLVM_READNONE
379 /// Return smallest type that covers both \p OrigTy and \p TargetTy and is
380 /// multiple of TargetTy.
381 LLT
382 getCoverTy(LLT OrigTy, LLT TargetTy);
383
384 /// Return a type where the total size is the greatest common divisor of \p
385 /// OrigTy and \p TargetTy. This will try to either change the number of vector
386 /// elements, or bitwidth of scalars. The intent is the result type can be used
387 /// as the result of a G_UNMERGE_VALUES from \p OrigTy, and then some
388 /// combination of G_MERGE_VALUES, G_BUILD_VECTOR and G_CONCAT_VECTORS (possibly
389 /// with intermediate casts) can re-form \p TargetTy.
390 ///
391 /// If these are vectors with different element types, this will try to produce
392 /// a vector with a compatible total size, but the element type of \p OrigTy. If
393 /// this can't be satisfied, this will produce a scalar smaller than the
394 /// original vector elements. It is an error to call this function where
395 /// one argument is a fixed vector and the other is a scalable vector, since it
396 /// is illegal to build a G_{MERGE|UNMERGE}_VALUES between fixed and scalable
397 /// vectors.
398 ///
399 /// In the worst case, this returns LLT::scalar(1)
400 LLVM_ABI LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy);
401
402 /// Represents a value which can be a Register or a constant.
403 ///
404 /// This is useful in situations where an instruction may have an interesting
405 /// register operand or interesting constant operand. For a concrete example,
406 /// \see getVectorSplat.
407 class RegOrConstant {
408 int64_t Cst;
409 Register Reg;
410 bool IsReg;
411
412 public:
RegOrConstant(Register Reg)413 explicit RegOrConstant(Register Reg) : Reg(Reg), IsReg(true) {}
RegOrConstant(int64_t Cst)414 explicit RegOrConstant(int64_t Cst) : Cst(Cst), IsReg(false) {}
isReg()415 bool isReg() const { return IsReg; }
isCst()416 bool isCst() const { return !IsReg; }
getReg()417 Register getReg() const {
418 assert(isReg() && "Expected a register!");
419 return Reg;
420 }
getCst()421 int64_t getCst() const {
422 assert(isCst() && "Expected a constant!");
423 return Cst;
424 }
425 };
426
427 /// \returns The splat index of a G_SHUFFLE_VECTOR \p MI when \p MI is a splat.
428 /// If \p MI is not a splat, returns std::nullopt.
429 LLVM_ABI std::optional<int> getSplatIndex(MachineInstr &MI);
430
431 /// \returns the scalar integral splat value of \p Reg if possible.
432 LLVM_ABI std::optional<APInt>
433 getIConstantSplatVal(const Register Reg, const MachineRegisterInfo &MRI);
434
435 /// \returns the scalar integral splat value defined by \p MI if possible.
436 LLVM_ABI std::optional<APInt>
437 getIConstantSplatVal(const MachineInstr &MI, const MachineRegisterInfo &MRI);
438
439 /// \returns the scalar sign extended integral splat value of \p Reg if
440 /// possible.
441 LLVM_ABI std::optional<int64_t>
442 getIConstantSplatSExtVal(const Register Reg, const MachineRegisterInfo &MRI);
443
444 /// \returns the scalar sign extended integral splat value defined by \p MI if
445 /// possible.
446 LLVM_ABI std::optional<int64_t>
447 getIConstantSplatSExtVal(const MachineInstr &MI,
448 const MachineRegisterInfo &MRI);
449
450 /// Returns a floating point scalar constant of a build vector splat if it
451 /// exists. When \p AllowUndef == true some elements can be undef but not all.
452 LLVM_ABI std::optional<FPValueAndVReg>
453 getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI,
454 bool AllowUndef = true);
455
456 /// Return true if the specified register is defined by G_BUILD_VECTOR or
457 /// G_BUILD_VECTOR_TRUNC where all of the elements are \p SplatValue or undef.
458 LLVM_ABI bool isBuildVectorConstantSplat(const Register Reg,
459 const MachineRegisterInfo &MRI,
460 int64_t SplatValue, bool AllowUndef);
461
462 /// Return true if the specified instruction is a G_BUILD_VECTOR or
463 /// G_BUILD_VECTOR_TRUNC where all of the elements are \p SplatValue or undef.
464 LLVM_ABI bool isBuildVectorConstantSplat(const MachineInstr &MI,
465 const MachineRegisterInfo &MRI,
466 int64_t SplatValue, bool AllowUndef);
467
468 /// Return true if the specified instruction is a G_BUILD_VECTOR or
469 /// G_BUILD_VECTOR_TRUNC where all of the elements are 0 or undef.
470 LLVM_ABI bool isBuildVectorAllZeros(const MachineInstr &MI,
471 const MachineRegisterInfo &MRI,
472 bool AllowUndef = false);
473
474 /// Return true if the specified instruction is a G_BUILD_VECTOR or
475 /// G_BUILD_VECTOR_TRUNC where all of the elements are ~0 or undef.
476 LLVM_ABI bool isBuildVectorAllOnes(const MachineInstr &MI,
477 const MachineRegisterInfo &MRI,
478 bool AllowUndef = false);
479
480 /// Return true if the specified instruction is known to be a constant, or a
481 /// vector of constants.
482 ///
483 /// If \p AllowFP is true, this will consider G_FCONSTANT in addition to
484 /// G_CONSTANT. If \p AllowOpaqueConstants is true, constant-like instructions
485 /// such as G_GLOBAL_VALUE will also be considered.
486 LLVM_ABI bool isConstantOrConstantVector(const MachineInstr &MI,
487 const MachineRegisterInfo &MRI,
488 bool AllowFP = true,
489 bool AllowOpaqueConstants = true);
490
491 /// Return true if the value is a constant 0 integer or a splatted vector of a
492 /// constant 0 integer (with no undefs if \p AllowUndefs is false). This will
493 /// handle G_BUILD_VECTOR and G_BUILD_VECTOR_TRUNC as truncation is not an issue
494 /// for null values.
495 LLVM_ABI bool isNullOrNullSplat(const MachineInstr &MI,
496 const MachineRegisterInfo &MRI,
497 bool AllowUndefs = false);
498
499 /// Return true if the value is a constant -1 integer or a splatted vector of a
500 /// constant -1 integer (with no undefs if \p AllowUndefs is false).
501 LLVM_ABI bool isAllOnesOrAllOnesSplat(const MachineInstr &MI,
502 const MachineRegisterInfo &MRI,
503 bool AllowUndefs = false);
504
505 /// \returns a value when \p MI is a vector splat. The splat can be either a
506 /// Register or a constant.
507 ///
508 /// Examples:
509 ///
510 /// \code
511 /// %reg = COPY $physreg
512 /// %reg_splat = G_BUILD_VECTOR %reg, %reg, ..., %reg
513 /// \endcode
514 ///
515 /// If called on the G_BUILD_VECTOR above, this will return a RegOrConstant
516 /// containing %reg.
517 ///
518 /// \code
519 /// %cst = G_CONSTANT iN 4
520 /// %constant_splat = G_BUILD_VECTOR %cst, %cst, ..., %cst
521 /// \endcode
522 ///
523 /// In the above case, this will return a RegOrConstant containing 4.
524 LLVM_ABI std::optional<RegOrConstant>
525 getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI);
526
527 /// Determines if \p MI defines a constant integer or a build vector of
528 /// constant integers. Treats undef values as constants.
529 LLVM_ABI bool isConstantOrConstantVector(MachineInstr &MI,
530 const MachineRegisterInfo &MRI);
531
532 /// Determines if \p MI defines a constant integer or a splat vector of
533 /// constant integers.
534 /// \returns the scalar constant or std::nullopt.
535 LLVM_ABI std::optional<APInt>
536 isConstantOrConstantSplatVector(MachineInstr &MI,
537 const MachineRegisterInfo &MRI);
538
539 /// Determines if \p MI defines a float constant integer or a splat vector of
540 /// float constant integers.
541 /// \returns the float constant or std::nullopt.
542 LLVM_ABI std::optional<APFloat>
543 isConstantOrConstantSplatVectorFP(MachineInstr &MI,
544 const MachineRegisterInfo &MRI);
545
546 /// Attempt to match a unary predicate against a scalar/splat constant or every
547 /// element of a constant G_BUILD_VECTOR. If \p ConstVal is null, the source
548 /// value was undef.
549 LLVM_ABI bool
550 matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg,
551 std::function<bool(const Constant *ConstVal)> Match,
552 bool AllowUndefs = false);
553
554 /// Returns true if given the TargetLowering's boolean contents information,
555 /// the value \p Val contains a true value.
556 LLVM_ABI bool isConstTrueVal(const TargetLowering &TLI, int64_t Val,
557 bool IsVector, bool IsFP);
558 /// \returns true if given the TargetLowering's boolean contents information,
559 /// the value \p Val contains a false value.
560 LLVM_ABI bool isConstFalseVal(const TargetLowering &TLI, int64_t Val,
561 bool IsVector, bool IsFP);
562
563 /// Returns an integer representing true, as defined by the
564 /// TargetBooleanContents.
565 LLVM_ABI int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector,
566 bool IsFP);
567
568 using SmallInstListTy = GISelWorkList<4>;
569 LLVM_ABI void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI,
570 LostDebugLocObserver *LocObserver,
571 SmallInstListTy &DeadInstChain);
572 LLVM_ABI void eraseInstrs(ArrayRef<MachineInstr *> DeadInstrs,
573 MachineRegisterInfo &MRI,
574 LostDebugLocObserver *LocObserver = nullptr);
575 LLVM_ABI void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI,
576 LostDebugLocObserver *LocObserver = nullptr);
577
578 /// Assuming the instruction \p MI is going to be deleted, attempt to salvage
579 /// debug users of \p MI by writing the effect of \p MI in a DIExpression.
580 LLVM_ABI void salvageDebugInfo(const MachineRegisterInfo &MRI,
581 MachineInstr &MI);
582
583 /// Returns whether opcode \p Opc is a pre-isel generic floating-point opcode,
584 /// having only floating-point operands.
585 LLVM_ABI bool isPreISelGenericFloatingPointOpcode(unsigned Opc);
586
587 /// Returns true if \p Reg can create undef or poison from non-undef &
588 /// non-poison operands. \p ConsiderFlagsAndMetadata controls whether poison
589 /// producing flags and metadata on the instruction are considered. This can be
590 /// used to see if the instruction could still introduce undef or poison even
591 /// without poison generating flags and metadata which might be on the
592 /// instruction.
593 LLVM_ABI bool canCreateUndefOrPoison(Register Reg,
594 const MachineRegisterInfo &MRI,
595 bool ConsiderFlagsAndMetadata = true);
596
597 /// Returns true if \p Reg can create poison from non-poison operands.
598 LLVM_ABI bool canCreatePoison(Register Reg, const MachineRegisterInfo &MRI,
599 bool ConsiderFlagsAndMetadata = true);
600
601 /// Returns true if \p Reg cannot be poison and undef.
602 LLVM_ABI bool isGuaranteedNotToBeUndefOrPoison(Register Reg,
603 const MachineRegisterInfo &MRI,
604 unsigned Depth = 0);
605
606 /// Returns true if \p Reg cannot be poison, but may be undef.
607 LLVM_ABI bool isGuaranteedNotToBePoison(Register Reg,
608 const MachineRegisterInfo &MRI,
609 unsigned Depth = 0);
610
611 /// Returns true if \p Reg cannot be undef, but may be poison.
612 LLVM_ABI bool isGuaranteedNotToBeUndef(Register Reg,
613 const MachineRegisterInfo &MRI,
614 unsigned Depth = 0);
615
616 /// Get the type back from LLT. It won't be 100 percent accurate but returns an
617 /// estimate of the type.
618 LLVM_ABI Type *getTypeForLLT(LLT Ty, LLVMContext &C);
619
620 /// Returns true if the instruction \p MI is one of the assert
621 /// instructions.
622 LLVM_ABI bool isAssertMI(const MachineInstr &MI);
623
624 /// An integer-like constant.
625 ///
626 /// It abstracts over scalar, fixed-length vectors, and scalable vectors.
627 /// In the common case, it provides a common API and feels like an APInt,
628 /// while still providing low-level access.
629 /// It can be used for constant-folding.
630 ///
631 /// bool isZero()
632 /// abstracts over the kind.
633 ///
634 /// switch(const.getKind())
635 /// {
636 /// }
637 /// provides low-level access.
638 class GIConstant {
639 public:
640 enum class GIConstantKind { Scalar, FixedVector, ScalableVector };
641
642 private:
643 GIConstantKind Kind;
644 SmallVector<APInt> Values;
645 APInt Value;
646
647 public:
GIConstant(ArrayRef<APInt> Values)648 GIConstant(ArrayRef<APInt> Values)
649 : Kind(GIConstantKind::FixedVector), Values(Values) {};
GIConstant(const APInt & Value,GIConstantKind Kind)650 GIConstant(const APInt &Value, GIConstantKind Kind)
651 : Kind(Kind), Value(Value) {};
652
653 /// Returns the kind of of this constant, e.g, Scalar.
getKind()654 GIConstantKind getKind() const { return Kind; }
655
656 /// Returns the value, if this constant is a scalar.
657 LLVM_ABI APInt getScalarValue() const;
658
659 LLVM_ABI static std::optional<GIConstant>
660 getConstant(Register Const, const MachineRegisterInfo &MRI);
661 };
662
663 /// An floating-point-like constant.
664 ///
665 /// It abstracts over scalar, fixed-length vectors, and scalable vectors.
666 /// In the common case, it provides a common API and feels like an APFloat,
667 /// while still providing low-level access.
668 /// It can be used for constant-folding.
669 ///
670 /// bool isZero()
671 /// abstracts over the kind.
672 ///
673 /// switch(const.getKind())
674 /// {
675 /// }
676 /// provides low-level access.
677 class GFConstant {
678 using VecTy = SmallVector<APFloat>;
679 using const_iterator = VecTy::const_iterator;
680
681 public:
682 enum class GFConstantKind { Scalar, FixedVector, ScalableVector };
683
684 private:
685 GFConstantKind Kind;
686 SmallVector<APFloat> Values;
687
688 public:
GFConstant(ArrayRef<APFloat> Values)689 GFConstant(ArrayRef<APFloat> Values)
690 : Kind(GFConstantKind::FixedVector), Values(Values) {};
GFConstant(const APFloat & Value,GFConstantKind Kind)691 GFConstant(const APFloat &Value, GFConstantKind Kind) : Kind(Kind) {
692 Values.push_back(Value);
693 }
694
695 /// Returns the kind of of this constant, e.g, Scalar.
getKind()696 GFConstantKind getKind() const { return Kind; }
697
begin()698 const_iterator begin() const {
699 assert(Kind != GFConstantKind::ScalableVector &&
700 "Expected fixed vector or scalar constant");
701 return Values.begin();
702 }
703
end()704 const_iterator end() const {
705 assert(Kind != GFConstantKind::ScalableVector &&
706 "Expected fixed vector or scalar constant");
707 return Values.end();
708 }
709
size()710 size_t size() const {
711 assert(Kind == GFConstantKind::FixedVector && "Expected fixed vector");
712 return Values.size();
713 }
714
715 /// Returns the value, if this constant is a scalar.
716 LLVM_ABI APFloat getScalarValue() const;
717
718 LLVM_ABI static std::optional<GFConstant>
719 getConstant(Register Const, const MachineRegisterInfo &MRI);
720 };
721
722 } // End namespace llvm.
723 #endif
724