| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSimplifyDemanded.cpp | 636 if (Instruction *Shr = dyn_cast<Instruction>(I->getOperand(0))) in SimplifyDemandedUseBits() local
1319 Instruction *Shr, const APInt &ShrOp1, Instruction *Shl, in simplifyShrShlDemandedBits()
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| H A D | InstCombineShifts.cpp | 1116 BinaryOperator *Shr; in visitShl() local
1157 Value *Shr = Op0BO->getOperand(0); in visitShl() local
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| H A D | InstCombineMulDivRem.cpp | 1697 Value *Shr = Builder.CreateLShr(Op0, CNegLog2, I.getName(), I.isExact()); in visitSDiv() local
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| H A D | InstCombineCompares.cpp | 2456 BinaryOperator *Shr, in foldICmpShrConstant()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ExpandLargeFpConvert.cpp | 369 Value *Shr = in expandIToFP() local
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | SimplifyIndVar.cpp | 838 BinaryOperator *Shr = cast<BinaryOperator>(U); in strengthenRightShift() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 2451 auto *Shr = dyn_cast_or_null<Instruction>(Add->getUniqueUndroppableUser()); in isExtPartOfAvgExpr() local
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| H A D | AArch64ISelLowering.cpp | 19438 auto IsRSHRN = [](SDValue Shr) { in performConcatVectorsCombine()
19478 SDValue Shr = in performConcatVectorsCombine() local
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| /freebsd/contrib/llvm-project/clang/lib/AST/Interp/ |
| H A D | Interp.h | 2329 inline bool Shr(InterpState &S, CodePtr OpPC) { in Shr() function
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 2010 auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt); in widenScalarUnmergeValues() local
7836 auto Shr = MIRBuilder.buildLShr(SrcIntTy, SrcReg, ShiftAmt); in lowerExtract() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 2751 SDValue Shr = DAG.getNode(ISD::SRL, dl, SrcVT, Op0, ShiftConst); in ExpandLegalINT_TO_FP() local
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| H A D | DAGCombiner.cpp | 27712 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt); in SimplifySelectCC() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 2432 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); in LowerFTRUNC() local
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| H A D | AMDGPULegalizerInfo.cpp | 2541 auto Shr = B.buildAShr(S64, FractMask, Exp); in legalizeIntrinsicTrunc() local
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