xref: /freebsd/sys/dev/cxgb/common/cxgb_regs.h (revision 78d146160dc5339c9cdf7799551bcc442a6eb95b)
1 /**************************************************************************
2 SPDX-License-Identifier: BSD-2-Clause
3 
4 Copyright (c) 2007, Chelsio Inc.
5 All rights reserved.
6 
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9 
10  1. Redistributions of source code must retain the above copyright notice,
11     this list of conditions and the following disclaimer.
12 
13  2. Neither the name of the Chelsio Corporation nor the names of its
14     contributors may be used to endorse or promote products derived from
15     this software without specific prior written permission.
16 
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 POSSIBILITY OF SUCH DAMAGE.
28 
29 ***************************************************************************/
30 /* This file is automatically generated --- do not edit */
31 
32 /* registers for module SGE3 */
33 #define SGE3_BASE_ADDR 0x0
34 
35 #define A_SG_CONTROL 0x0
36 
37 #define S_CONGMODE    29
38 #define V_CONGMODE(x) ((x) << S_CONGMODE)
39 #define F_CONGMODE    V_CONGMODE(1U)
40 
41 #define S_TNLFLMODE    28
42 #define V_TNLFLMODE(x) ((x) << S_TNLFLMODE)
43 #define F_TNLFLMODE    V_TNLFLMODE(1U)
44 
45 #define S_FATLPERREN    27
46 #define V_FATLPERREN(x) ((x) << S_FATLPERREN)
47 #define F_FATLPERREN    V_FATLPERREN(1U)
48 
49 #define S_URGTNL    26
50 #define V_URGTNL(x) ((x) << S_URGTNL)
51 #define F_URGTNL    V_URGTNL(1U)
52 
53 #define S_NEWNOTIFY    25
54 #define V_NEWNOTIFY(x) ((x) << S_NEWNOTIFY)
55 #define F_NEWNOTIFY    V_NEWNOTIFY(1U)
56 
57 #define S_AVOIDCQOVFL    24
58 #define V_AVOIDCQOVFL(x) ((x) << S_AVOIDCQOVFL)
59 #define F_AVOIDCQOVFL    V_AVOIDCQOVFL(1U)
60 
61 #define S_OPTONEINTMULTQ    23
62 #define V_OPTONEINTMULTQ(x) ((x) << S_OPTONEINTMULTQ)
63 #define F_OPTONEINTMULTQ    V_OPTONEINTMULTQ(1U)
64 
65 #define S_CQCRDTCTRL    22
66 #define V_CQCRDTCTRL(x) ((x) << S_CQCRDTCTRL)
67 #define F_CQCRDTCTRL    V_CQCRDTCTRL(1U)
68 
69 #define S_EGRENUPBP    21
70 #define V_EGRENUPBP(x) ((x) << S_EGRENUPBP)
71 #define F_EGRENUPBP    V_EGRENUPBP(1U)
72 
73 #define S_DROPPKT    20
74 #define V_DROPPKT(x) ((x) << S_DROPPKT)
75 #define F_DROPPKT    V_DROPPKT(1U)
76 
77 #define S_EGRGENCTRL    19
78 #define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL)
79 #define F_EGRGENCTRL    V_EGRGENCTRL(1U)
80 
81 #define S_USERSPACESIZE    14
82 #define M_USERSPACESIZE    0x1f
83 #define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE)
84 #define G_USERSPACESIZE(x) (((x) >> S_USERSPACESIZE) & M_USERSPACESIZE)
85 
86 #define S_HOSTPAGESIZE    11
87 #define M_HOSTPAGESIZE    0x7
88 #define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE)
89 #define G_HOSTPAGESIZE(x) (((x) >> S_HOSTPAGESIZE) & M_HOSTPAGESIZE)
90 
91 #define S_PCIRELAX    10
92 #define V_PCIRELAX(x) ((x) << S_PCIRELAX)
93 #define F_PCIRELAX    V_PCIRELAX(1U)
94 
95 #define S_FLMODE    9
96 #define V_FLMODE(x) ((x) << S_FLMODE)
97 #define F_FLMODE    V_FLMODE(1U)
98 
99 #define S_PKTSHIFT    6
100 #define M_PKTSHIFT    0x7
101 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
102 #define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT)
103 
104 #define S_ONEINTMULTQ    5
105 #define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ)
106 #define F_ONEINTMULTQ    V_ONEINTMULTQ(1U)
107 
108 #define S_FLPICKAVAIL    4
109 #define V_FLPICKAVAIL(x) ((x) << S_FLPICKAVAIL)
110 #define F_FLPICKAVAIL    V_FLPICKAVAIL(1U)
111 
112 #define S_BIGENDIANEGRESS    3
113 #define V_BIGENDIANEGRESS(x) ((x) << S_BIGENDIANEGRESS)
114 #define F_BIGENDIANEGRESS    V_BIGENDIANEGRESS(1U)
115 
116 #define S_BIGENDIANINGRESS    2
117 #define V_BIGENDIANINGRESS(x) ((x) << S_BIGENDIANINGRESS)
118 #define F_BIGENDIANINGRESS    V_BIGENDIANINGRESS(1U)
119 
120 #define S_ISCSICOALESCING    1
121 #define V_ISCSICOALESCING(x) ((x) << S_ISCSICOALESCING)
122 #define F_ISCSICOALESCING    V_ISCSICOALESCING(1U)
123 
124 #define S_GLOBALENABLE    0
125 #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
126 #define F_GLOBALENABLE    V_GLOBALENABLE(1U)
127 
128 #define A_SG_KDOORBELL 0x4
129 
130 #define S_SELEGRCNTX    31
131 #define V_SELEGRCNTX(x) ((x) << S_SELEGRCNTX)
132 #define F_SELEGRCNTX    V_SELEGRCNTX(1U)
133 
134 #define S_EGRCNTX    0
135 #define M_EGRCNTX    0xffff
136 #define V_EGRCNTX(x) ((x) << S_EGRCNTX)
137 #define G_EGRCNTX(x) (((x) >> S_EGRCNTX) & M_EGRCNTX)
138 
139 #define A_SG_GTS 0x8
140 
141 #define S_RSPQ    29
142 #define M_RSPQ    0x7
143 #define V_RSPQ(x) ((x) << S_RSPQ)
144 #define G_RSPQ(x) (((x) >> S_RSPQ) & M_RSPQ)
145 
146 #define S_NEWTIMER    16
147 #define M_NEWTIMER    0x1fff
148 #define V_NEWTIMER(x) ((x) << S_NEWTIMER)
149 #define G_NEWTIMER(x) (((x) >> S_NEWTIMER) & M_NEWTIMER)
150 
151 #define S_NEWINDEX    0
152 #define M_NEWINDEX    0xffff
153 #define V_NEWINDEX(x) ((x) << S_NEWINDEX)
154 #define G_NEWINDEX(x) (((x) >> S_NEWINDEX) & M_NEWINDEX)
155 
156 #define A_SG_CONTEXT_CMD 0xc
157 
158 #define S_CONTEXT_CMD_OPCODE    28
159 #define M_CONTEXT_CMD_OPCODE    0xf
160 #define V_CONTEXT_CMD_OPCODE(x) ((x) << S_CONTEXT_CMD_OPCODE)
161 #define G_CONTEXT_CMD_OPCODE(x) (((x) >> S_CONTEXT_CMD_OPCODE) & M_CONTEXT_CMD_OPCODE)
162 
163 #define S_CONTEXT_CMD_BUSY    27
164 #define V_CONTEXT_CMD_BUSY(x) ((x) << S_CONTEXT_CMD_BUSY)
165 #define F_CONTEXT_CMD_BUSY    V_CONTEXT_CMD_BUSY(1U)
166 
167 #define S_CQ_CREDIT    20
168 #define M_CQ_CREDIT    0x7f
169 #define V_CQ_CREDIT(x) ((x) << S_CQ_CREDIT)
170 #define G_CQ_CREDIT(x) (((x) >> S_CQ_CREDIT) & M_CQ_CREDIT)
171 
172 #define S_CQ    19
173 #define V_CQ(x) ((x) << S_CQ)
174 #define F_CQ    V_CQ(1U)
175 
176 #define S_RESPONSEQ    18
177 #define V_RESPONSEQ(x) ((x) << S_RESPONSEQ)
178 #define F_RESPONSEQ    V_RESPONSEQ(1U)
179 
180 #define S_EGRESS    17
181 #define V_EGRESS(x) ((x) << S_EGRESS)
182 #define F_EGRESS    V_EGRESS(1U)
183 
184 #define S_FREELIST    16
185 #define V_FREELIST(x) ((x) << S_FREELIST)
186 #define F_FREELIST    V_FREELIST(1U)
187 
188 #define S_CONTEXT    0
189 #define M_CONTEXT    0xffff
190 #define V_CONTEXT(x) ((x) << S_CONTEXT)
191 #define G_CONTEXT(x) (((x) >> S_CONTEXT) & M_CONTEXT)
192 
193 #define A_SG_CONTEXT_DATA0 0x10
194 #define A_SG_CONTEXT_DATA1 0x14
195 #define A_SG_CONTEXT_DATA2 0x18
196 #define A_SG_CONTEXT_DATA3 0x1c
197 #define A_SG_CONTEXT_MASK0 0x20
198 #define A_SG_CONTEXT_MASK1 0x24
199 #define A_SG_CONTEXT_MASK2 0x28
200 #define A_SG_CONTEXT_MASK3 0x2c
201 #define A_SG_RSPQ_CREDIT_RETURN 0x30
202 
203 #define S_CREDITS    0
204 #define M_CREDITS    0xffff
205 #define V_CREDITS(x) ((x) << S_CREDITS)
206 #define G_CREDITS(x) (((x) >> S_CREDITS) & M_CREDITS)
207 
208 #define A_SG_DATA_INTR 0x34
209 
210 #define S_ERRINTR    31
211 #define V_ERRINTR(x) ((x) << S_ERRINTR)
212 #define F_ERRINTR    V_ERRINTR(1U)
213 
214 #define S_DATAINTR    0
215 #define M_DATAINTR    0xff
216 #define V_DATAINTR(x) ((x) << S_DATAINTR)
217 #define G_DATAINTR(x) (((x) >> S_DATAINTR) & M_DATAINTR)
218 
219 #define A_SG_HI_DRB_HI_THRSH 0x38
220 
221 #define S_HIDRBHITHRSH    0
222 #define M_HIDRBHITHRSH    0x3ff
223 #define V_HIDRBHITHRSH(x) ((x) << S_HIDRBHITHRSH)
224 #define G_HIDRBHITHRSH(x) (((x) >> S_HIDRBHITHRSH) & M_HIDRBHITHRSH)
225 
226 #define A_SG_HI_DRB_LO_THRSH 0x3c
227 
228 #define S_HIDRBLOTHRSH    0
229 #define M_HIDRBLOTHRSH    0x3ff
230 #define V_HIDRBLOTHRSH(x) ((x) << S_HIDRBLOTHRSH)
231 #define G_HIDRBLOTHRSH(x) (((x) >> S_HIDRBLOTHRSH) & M_HIDRBLOTHRSH)
232 
233 #define A_SG_LO_DRB_HI_THRSH 0x40
234 
235 #define S_LODRBHITHRSH    0
236 #define M_LODRBHITHRSH    0x3ff
237 #define V_LODRBHITHRSH(x) ((x) << S_LODRBHITHRSH)
238 #define G_LODRBHITHRSH(x) (((x) >> S_LODRBHITHRSH) & M_LODRBHITHRSH)
239 
240 #define A_SG_LO_DRB_LO_THRSH 0x44
241 
242 #define S_LODRBLOTHRSH    0
243 #define M_LODRBLOTHRSH    0x3ff
244 #define V_LODRBLOTHRSH(x) ((x) << S_LODRBLOTHRSH)
245 #define G_LODRBLOTHRSH(x) (((x) >> S_LODRBLOTHRSH) & M_LODRBLOTHRSH)
246 
247 #define A_SG_ONE_INT_MULT_Q_COALESCING_TIMER 0x48
248 #define A_SG_RSPQ_FL_STATUS 0x4c
249 
250 #define S_RSPQ0STARVED    0
251 #define V_RSPQ0STARVED(x) ((x) << S_RSPQ0STARVED)
252 #define F_RSPQ0STARVED    V_RSPQ0STARVED(1U)
253 
254 #define S_RSPQ1STARVED    1
255 #define V_RSPQ1STARVED(x) ((x) << S_RSPQ1STARVED)
256 #define F_RSPQ1STARVED    V_RSPQ1STARVED(1U)
257 
258 #define S_RSPQ2STARVED    2
259 #define V_RSPQ2STARVED(x) ((x) << S_RSPQ2STARVED)
260 #define F_RSPQ2STARVED    V_RSPQ2STARVED(1U)
261 
262 #define S_RSPQ3STARVED    3
263 #define V_RSPQ3STARVED(x) ((x) << S_RSPQ3STARVED)
264 #define F_RSPQ3STARVED    V_RSPQ3STARVED(1U)
265 
266 #define S_RSPQ4STARVED    4
267 #define V_RSPQ4STARVED(x) ((x) << S_RSPQ4STARVED)
268 #define F_RSPQ4STARVED    V_RSPQ4STARVED(1U)
269 
270 #define S_RSPQ5STARVED    5
271 #define V_RSPQ5STARVED(x) ((x) << S_RSPQ5STARVED)
272 #define F_RSPQ5STARVED    V_RSPQ5STARVED(1U)
273 
274 #define S_RSPQ6STARVED    6
275 #define V_RSPQ6STARVED(x) ((x) << S_RSPQ6STARVED)
276 #define F_RSPQ6STARVED    V_RSPQ6STARVED(1U)
277 
278 #define S_RSPQ7STARVED    7
279 #define V_RSPQ7STARVED(x) ((x) << S_RSPQ7STARVED)
280 #define F_RSPQ7STARVED    V_RSPQ7STARVED(1U)
281 
282 #define S_RSPQXSTARVED    0
283 #define M_RSPQXSTARVED    0xff
284 #define V_RSPQXSTARVED(x) ((x) << S_RSPQXSTARVED)
285 #define G_RSPQXSTARVED(x) (((x) >> S_RSPQXSTARVED) & M_RSPQXSTARVED)
286 
287 #define S_RSPQ0DISABLED    8
288 #define V_RSPQ0DISABLED(x) ((x) << S_RSPQ0DISABLED)
289 #define F_RSPQ0DISABLED    V_RSPQ0DISABLED(1U)
290 
291 #define S_RSPQ1DISABLED    9
292 #define V_RSPQ1DISABLED(x) ((x) << S_RSPQ1DISABLED)
293 #define F_RSPQ1DISABLED    V_RSPQ1DISABLED(1U)
294 
295 #define S_RSPQ2DISABLED    10
296 #define V_RSPQ2DISABLED(x) ((x) << S_RSPQ2DISABLED)
297 #define F_RSPQ2DISABLED    V_RSPQ2DISABLED(1U)
298 
299 #define S_RSPQ3DISABLED    11
300 #define V_RSPQ3DISABLED(x) ((x) << S_RSPQ3DISABLED)
301 #define F_RSPQ3DISABLED    V_RSPQ3DISABLED(1U)
302 
303 #define S_RSPQ4DISABLED    12
304 #define V_RSPQ4DISABLED(x) ((x) << S_RSPQ4DISABLED)
305 #define F_RSPQ4DISABLED    V_RSPQ4DISABLED(1U)
306 
307 #define S_RSPQ5DISABLED    13
308 #define V_RSPQ5DISABLED(x) ((x) << S_RSPQ5DISABLED)
309 #define F_RSPQ5DISABLED    V_RSPQ5DISABLED(1U)
310 
311 #define S_RSPQ6DISABLED    14
312 #define V_RSPQ6DISABLED(x) ((x) << S_RSPQ6DISABLED)
313 #define F_RSPQ6DISABLED    V_RSPQ6DISABLED(1U)
314 
315 #define S_RSPQ7DISABLED    15
316 #define V_RSPQ7DISABLED(x) ((x) << S_RSPQ7DISABLED)
317 #define F_RSPQ7DISABLED    V_RSPQ7DISABLED(1U)
318 
319 #define S_FL0EMPTY    16
320 #define V_FL0EMPTY(x) ((x) << S_FL0EMPTY)
321 #define F_FL0EMPTY    V_FL0EMPTY(1U)
322 
323 #define S_FL1EMPTY    17
324 #define V_FL1EMPTY(x) ((x) << S_FL1EMPTY)
325 #define F_FL1EMPTY    V_FL1EMPTY(1U)
326 
327 #define S_FL2EMPTY    18
328 #define V_FL2EMPTY(x) ((x) << S_FL2EMPTY)
329 #define F_FL2EMPTY    V_FL2EMPTY(1U)
330 
331 #define S_FL3EMPTY    19
332 #define V_FL3EMPTY(x) ((x) << S_FL3EMPTY)
333 #define F_FL3EMPTY    V_FL3EMPTY(1U)
334 
335 #define S_FL4EMPTY    20
336 #define V_FL4EMPTY(x) ((x) << S_FL4EMPTY)
337 #define F_FL4EMPTY    V_FL4EMPTY(1U)
338 
339 #define S_FL5EMPTY    21
340 #define V_FL5EMPTY(x) ((x) << S_FL5EMPTY)
341 #define F_FL5EMPTY    V_FL5EMPTY(1U)
342 
343 #define S_FL6EMPTY    22
344 #define V_FL6EMPTY(x) ((x) << S_FL6EMPTY)
345 #define F_FL6EMPTY    V_FL6EMPTY(1U)
346 
347 #define S_FL7EMPTY    23
348 #define V_FL7EMPTY(x) ((x) << S_FL7EMPTY)
349 #define F_FL7EMPTY    V_FL7EMPTY(1U)
350 
351 #define S_FL8EMPTY    24
352 #define V_FL8EMPTY(x) ((x) << S_FL8EMPTY)
353 #define F_FL8EMPTY    V_FL8EMPTY(1U)
354 
355 #define S_FL9EMPTY    25
356 #define V_FL9EMPTY(x) ((x) << S_FL9EMPTY)
357 #define F_FL9EMPTY    V_FL9EMPTY(1U)
358 
359 #define S_FL10EMPTY    26
360 #define V_FL10EMPTY(x) ((x) << S_FL10EMPTY)
361 #define F_FL10EMPTY    V_FL10EMPTY(1U)
362 
363 #define S_FL11EMPTY    27
364 #define V_FL11EMPTY(x) ((x) << S_FL11EMPTY)
365 #define F_FL11EMPTY    V_FL11EMPTY(1U)
366 
367 #define S_FL12EMPTY    28
368 #define V_FL12EMPTY(x) ((x) << S_FL12EMPTY)
369 #define F_FL12EMPTY    V_FL12EMPTY(1U)
370 
371 #define S_FL13EMPTY    29
372 #define V_FL13EMPTY(x) ((x) << S_FL13EMPTY)
373 #define F_FL13EMPTY    V_FL13EMPTY(1U)
374 
375 #define S_FL14EMPTY    30
376 #define V_FL14EMPTY(x) ((x) << S_FL14EMPTY)
377 #define F_FL14EMPTY    V_FL14EMPTY(1U)
378 
379 #define S_FL15EMPTY    31
380 #define V_FL15EMPTY(x) ((x) << S_FL15EMPTY)
381 #define F_FL15EMPTY    V_FL15EMPTY(1U)
382 
383 #define S_FLXEMPTY    16
384 #define M_FLXEMPTY    0xffff
385 #define V_FLXEMPTY(x) ((x) << S_FLXEMPTY)
386 #define G_FLXEMPTY(x) (((x) >> S_FLXEMPTY) & M_FLXEMPTY)
387 
388 #define A_SG_EGR_PRI_CNT 0x50
389 
390 #define S_EGRERROPCODE    24
391 #define M_EGRERROPCODE    0xff
392 #define V_EGRERROPCODE(x) ((x) << S_EGRERROPCODE)
393 #define G_EGRERROPCODE(x) (((x) >> S_EGRERROPCODE) & M_EGRERROPCODE)
394 
395 #define S_EGRHIOPCODE    16
396 #define M_EGRHIOPCODE    0xff
397 #define V_EGRHIOPCODE(x) ((x) << S_EGRHIOPCODE)
398 #define G_EGRHIOPCODE(x) (((x) >> S_EGRHIOPCODE) & M_EGRHIOPCODE)
399 
400 #define S_EGRLOOPCODE    8
401 #define M_EGRLOOPCODE    0xff
402 #define V_EGRLOOPCODE(x) ((x) << S_EGRLOOPCODE)
403 #define G_EGRLOOPCODE(x) (((x) >> S_EGRLOOPCODE) & M_EGRLOOPCODE)
404 
405 #define S_EGRPRICNT    0
406 #define M_EGRPRICNT    0x1f
407 #define V_EGRPRICNT(x) ((x) << S_EGRPRICNT)
408 #define G_EGRPRICNT(x) (((x) >> S_EGRPRICNT) & M_EGRPRICNT)
409 
410 #define A_SG_EGR_RCQ_DRB_THRSH 0x54
411 
412 #define S_HIRCQDRBTHRSH    16
413 #define M_HIRCQDRBTHRSH    0x7ff
414 #define V_HIRCQDRBTHRSH(x) ((x) << S_HIRCQDRBTHRSH)
415 #define G_HIRCQDRBTHRSH(x) (((x) >> S_HIRCQDRBTHRSH) & M_HIRCQDRBTHRSH)
416 
417 #define S_LORCQDRBTHRSH    0
418 #define M_LORCQDRBTHRSH    0x7ff
419 #define V_LORCQDRBTHRSH(x) ((x) << S_LORCQDRBTHRSH)
420 #define G_LORCQDRBTHRSH(x) (((x) >> S_LORCQDRBTHRSH) & M_LORCQDRBTHRSH)
421 
422 #define A_SG_EGR_CNTX_BADDR 0x58
423 
424 #define S_EGRCNTXBADDR    5
425 #define M_EGRCNTXBADDR    0x7ffffff
426 #define V_EGRCNTXBADDR(x) ((x) << S_EGRCNTXBADDR)
427 #define G_EGRCNTXBADDR(x) (((x) >> S_EGRCNTXBADDR) & M_EGRCNTXBADDR)
428 
429 #define A_SG_INT_CAUSE 0x5c
430 
431 #define S_HIRCQPARITYERROR    31
432 #define V_HIRCQPARITYERROR(x) ((x) << S_HIRCQPARITYERROR)
433 #define F_HIRCQPARITYERROR    V_HIRCQPARITYERROR(1U)
434 
435 #define S_LORCQPARITYERROR    30
436 #define V_LORCQPARITYERROR(x) ((x) << S_LORCQPARITYERROR)
437 #define F_LORCQPARITYERROR    V_LORCQPARITYERROR(1U)
438 
439 #define S_HIDRBPARITYERROR    29
440 #define V_HIDRBPARITYERROR(x) ((x) << S_HIDRBPARITYERROR)
441 #define F_HIDRBPARITYERROR    V_HIDRBPARITYERROR(1U)
442 
443 #define S_LODRBPARITYERROR    28
444 #define V_LODRBPARITYERROR(x) ((x) << S_LODRBPARITYERROR)
445 #define F_LODRBPARITYERROR    V_LODRBPARITYERROR(1U)
446 
447 #define S_FLPARITYERROR    22
448 #define M_FLPARITYERROR    0x3f
449 #define V_FLPARITYERROR(x) ((x) << S_FLPARITYERROR)
450 #define G_FLPARITYERROR(x) (((x) >> S_FLPARITYERROR) & M_FLPARITYERROR)
451 
452 #define S_ITPARITYERROR    20
453 #define M_ITPARITYERROR    0x3
454 #define V_ITPARITYERROR(x) ((x) << S_ITPARITYERROR)
455 #define G_ITPARITYERROR(x) (((x) >> S_ITPARITYERROR) & M_ITPARITYERROR)
456 
457 #define S_IRPARITYERROR    19
458 #define V_IRPARITYERROR(x) ((x) << S_IRPARITYERROR)
459 #define F_IRPARITYERROR    V_IRPARITYERROR(1U)
460 
461 #define S_RCPARITYERROR    18
462 #define V_RCPARITYERROR(x) ((x) << S_RCPARITYERROR)
463 #define F_RCPARITYERROR    V_RCPARITYERROR(1U)
464 
465 #define S_OCPARITYERROR    17
466 #define V_OCPARITYERROR(x) ((x) << S_OCPARITYERROR)
467 #define F_OCPARITYERROR    V_OCPARITYERROR(1U)
468 
469 #define S_CPPARITYERROR    16
470 #define V_CPPARITYERROR(x) ((x) << S_CPPARITYERROR)
471 #define F_CPPARITYERROR    V_CPPARITYERROR(1U)
472 
473 #define S_R_REQ_FRAMINGERROR    15
474 #define V_R_REQ_FRAMINGERROR(x) ((x) << S_R_REQ_FRAMINGERROR)
475 #define F_R_REQ_FRAMINGERROR    V_R_REQ_FRAMINGERROR(1U)
476 
477 #define S_UC_REQ_FRAMINGERROR    14
478 #define V_UC_REQ_FRAMINGERROR(x) ((x) << S_UC_REQ_FRAMINGERROR)
479 #define F_UC_REQ_FRAMINGERROR    V_UC_REQ_FRAMINGERROR(1U)
480 
481 #define S_HICTLDRBDROPERR    13
482 #define V_HICTLDRBDROPERR(x) ((x) << S_HICTLDRBDROPERR)
483 #define F_HICTLDRBDROPERR    V_HICTLDRBDROPERR(1U)
484 
485 #define S_LOCTLDRBDROPERR    12
486 #define V_LOCTLDRBDROPERR(x) ((x) << S_LOCTLDRBDROPERR)
487 #define F_LOCTLDRBDROPERR    V_LOCTLDRBDROPERR(1U)
488 
489 #define S_HIPIODRBDROPERR    11
490 #define V_HIPIODRBDROPERR(x) ((x) << S_HIPIODRBDROPERR)
491 #define F_HIPIODRBDROPERR    V_HIPIODRBDROPERR(1U)
492 
493 #define S_LOPIODRBDROPERR    10
494 #define V_LOPIODRBDROPERR(x) ((x) << S_LOPIODRBDROPERR)
495 #define F_LOPIODRBDROPERR    V_LOPIODRBDROPERR(1U)
496 
497 #define S_HICRDTUNDFLOWERR    9
498 #define V_HICRDTUNDFLOWERR(x) ((x) << S_HICRDTUNDFLOWERR)
499 #define F_HICRDTUNDFLOWERR    V_HICRDTUNDFLOWERR(1U)
500 
501 #define S_LOCRDTUNDFLOWERR    8
502 #define V_LOCRDTUNDFLOWERR(x) ((x) << S_LOCRDTUNDFLOWERR)
503 #define F_LOCRDTUNDFLOWERR    V_LOCRDTUNDFLOWERR(1U)
504 
505 #define S_HIPRIORITYDBFULL    7
506 #define V_HIPRIORITYDBFULL(x) ((x) << S_HIPRIORITYDBFULL)
507 #define F_HIPRIORITYDBFULL    V_HIPRIORITYDBFULL(1U)
508 
509 #define S_HIPRIORITYDBEMPTY    6
510 #define V_HIPRIORITYDBEMPTY(x) ((x) << S_HIPRIORITYDBEMPTY)
511 #define F_HIPRIORITYDBEMPTY    V_HIPRIORITYDBEMPTY(1U)
512 
513 #define S_LOPRIORITYDBFULL    5
514 #define V_LOPRIORITYDBFULL(x) ((x) << S_LOPRIORITYDBFULL)
515 #define F_LOPRIORITYDBFULL    V_LOPRIORITYDBFULL(1U)
516 
517 #define S_LOPRIORITYDBEMPTY    4
518 #define V_LOPRIORITYDBEMPTY(x) ((x) << S_LOPRIORITYDBEMPTY)
519 #define F_LOPRIORITYDBEMPTY    V_LOPRIORITYDBEMPTY(1U)
520 
521 #define S_RSPQDISABLED    3
522 #define V_RSPQDISABLED(x) ((x) << S_RSPQDISABLED)
523 #define F_RSPQDISABLED    V_RSPQDISABLED(1U)
524 
525 #define S_RSPQCREDITOVERFOW    2
526 #define V_RSPQCREDITOVERFOW(x) ((x) << S_RSPQCREDITOVERFOW)
527 #define F_RSPQCREDITOVERFOW    V_RSPQCREDITOVERFOW(1U)
528 
529 #define S_FLEMPTY    1
530 #define V_FLEMPTY(x) ((x) << S_FLEMPTY)
531 #define F_FLEMPTY    V_FLEMPTY(1U)
532 
533 #define S_RSPQSTARVE    0
534 #define V_RSPQSTARVE(x) ((x) << S_RSPQSTARVE)
535 #define F_RSPQSTARVE    V_RSPQSTARVE(1U)
536 
537 #define A_SG_INT_ENABLE 0x60
538 #define A_SG_CMDQ_CREDIT_TH 0x64
539 
540 #define S_TIMEOUT    8
541 #define M_TIMEOUT    0xffffff
542 #define V_TIMEOUT(x) ((x) << S_TIMEOUT)
543 #define G_TIMEOUT(x) (((x) >> S_TIMEOUT) & M_TIMEOUT)
544 
545 #define S_THRESHOLD    0
546 #define M_THRESHOLD    0xff
547 #define V_THRESHOLD(x) ((x) << S_THRESHOLD)
548 #define G_THRESHOLD(x) (((x) >> S_THRESHOLD) & M_THRESHOLD)
549 
550 #define A_SG_TIMER_TICK 0x68
551 #define A_SG_CQ_CONTEXT_BADDR 0x6c
552 
553 #define S_BASEADDR    5
554 #define M_BASEADDR    0x7ffffff
555 #define V_BASEADDR(x) ((x) << S_BASEADDR)
556 #define G_BASEADDR(x) (((x) >> S_BASEADDR) & M_BASEADDR)
557 
558 #define A_SG_OCO_BASE 0x70
559 
560 #define S_BASE1    16
561 #define M_BASE1    0xffff
562 #define V_BASE1(x) ((x) << S_BASE1)
563 #define G_BASE1(x) (((x) >> S_BASE1) & M_BASE1)
564 
565 #define S_BASE0    0
566 #define M_BASE0    0xffff
567 #define V_BASE0(x) ((x) << S_BASE0)
568 #define G_BASE0(x) (((x) >> S_BASE0) & M_BASE0)
569 
570 #define A_SG_DRB_PRI_THRESH 0x74
571 
572 #define S_DRBPRITHRSH    0
573 #define M_DRBPRITHRSH    0xffff
574 #define V_DRBPRITHRSH(x) ((x) << S_DRBPRITHRSH)
575 #define G_DRBPRITHRSH(x) (((x) >> S_DRBPRITHRSH) & M_DRBPRITHRSH)
576 
577 #define A_SG_DEBUG_INDEX 0x78
578 #define A_SG_DEBUG_DATA 0x7c
579 
580 /* registers for module PCIX1 */
581 #define PCIX1_BASE_ADDR 0x80
582 
583 #define A_PCIX_INT_ENABLE 0x80
584 
585 #define S_MSIXPARERR    22
586 #define M_MSIXPARERR    0x7
587 #define V_MSIXPARERR(x) ((x) << S_MSIXPARERR)
588 #define G_MSIXPARERR(x) (((x) >> S_MSIXPARERR) & M_MSIXPARERR)
589 
590 #define S_CFPARERR    18
591 #define M_CFPARERR    0xf
592 #define V_CFPARERR(x) ((x) << S_CFPARERR)
593 #define G_CFPARERR(x) (((x) >> S_CFPARERR) & M_CFPARERR)
594 
595 #define S_RFPARERR    14
596 #define M_RFPARERR    0xf
597 #define V_RFPARERR(x) ((x) << S_RFPARERR)
598 #define G_RFPARERR(x) (((x) >> S_RFPARERR) & M_RFPARERR)
599 
600 #define S_WFPARERR    12
601 #define M_WFPARERR    0x3
602 #define V_WFPARERR(x) ((x) << S_WFPARERR)
603 #define G_WFPARERR(x) (((x) >> S_WFPARERR) & M_WFPARERR)
604 
605 #define S_PIOPARERR    11
606 #define V_PIOPARERR(x) ((x) << S_PIOPARERR)
607 #define F_PIOPARERR    V_PIOPARERR(1U)
608 
609 #define S_DETUNCECCERR    10
610 #define V_DETUNCECCERR(x) ((x) << S_DETUNCECCERR)
611 #define F_DETUNCECCERR    V_DETUNCECCERR(1U)
612 
613 #define S_DETCORECCERR    9
614 #define V_DETCORECCERR(x) ((x) << S_DETCORECCERR)
615 #define F_DETCORECCERR    V_DETCORECCERR(1U)
616 
617 #define S_RCVSPLCMPERR    8
618 #define V_RCVSPLCMPERR(x) ((x) << S_RCVSPLCMPERR)
619 #define F_RCVSPLCMPERR    V_RCVSPLCMPERR(1U)
620 
621 #define S_UNXSPLCMP    7
622 #define V_UNXSPLCMP(x) ((x) << S_UNXSPLCMP)
623 #define F_UNXSPLCMP    V_UNXSPLCMP(1U)
624 
625 #define S_SPLCMPDIS    6
626 #define V_SPLCMPDIS(x) ((x) << S_SPLCMPDIS)
627 #define F_SPLCMPDIS    V_SPLCMPDIS(1U)
628 
629 #define S_DETPARERR    5
630 #define V_DETPARERR(x) ((x) << S_DETPARERR)
631 #define F_DETPARERR    V_DETPARERR(1U)
632 
633 #define S_SIGSYSERR    4
634 #define V_SIGSYSERR(x) ((x) << S_SIGSYSERR)
635 #define F_SIGSYSERR    V_SIGSYSERR(1U)
636 
637 #define S_RCVMSTABT    3
638 #define V_RCVMSTABT(x) ((x) << S_RCVMSTABT)
639 #define F_RCVMSTABT    V_RCVMSTABT(1U)
640 
641 #define S_RCVTARABT    2
642 #define V_RCVTARABT(x) ((x) << S_RCVTARABT)
643 #define F_RCVTARABT    V_RCVTARABT(1U)
644 
645 #define S_SIGTARABT    1
646 #define V_SIGTARABT(x) ((x) << S_SIGTARABT)
647 #define F_SIGTARABT    V_SIGTARABT(1U)
648 
649 #define S_MSTDETPARERR    0
650 #define V_MSTDETPARERR(x) ((x) << S_MSTDETPARERR)
651 #define F_MSTDETPARERR    V_MSTDETPARERR(1U)
652 
653 #define A_PCIX_INT_CAUSE 0x84
654 #define A_PCIX_CFG 0x88
655 
656 #define S_DMASTOPEN    19
657 #define V_DMASTOPEN(x) ((x) << S_DMASTOPEN)
658 #define F_DMASTOPEN    V_DMASTOPEN(1U)
659 
660 #define S_CLIDECEN    18
661 #define V_CLIDECEN(x) ((x) << S_CLIDECEN)
662 #define F_CLIDECEN    V_CLIDECEN(1U)
663 
664 #define S_LATTMRDIS    17
665 #define V_LATTMRDIS(x) ((x) << S_LATTMRDIS)
666 #define F_LATTMRDIS    V_LATTMRDIS(1U)
667 
668 #define S_LOWPWREN    16
669 #define V_LOWPWREN(x) ((x) << S_LOWPWREN)
670 #define F_LOWPWREN    V_LOWPWREN(1U)
671 
672 #define S_ASYNCINTVEC    11
673 #define M_ASYNCINTVEC    0x1f
674 #define V_ASYNCINTVEC(x) ((x) << S_ASYNCINTVEC)
675 #define G_ASYNCINTVEC(x) (((x) >> S_ASYNCINTVEC) & M_ASYNCINTVEC)
676 
677 #define S_MAXSPLTRNC    8
678 #define M_MAXSPLTRNC    0x7
679 #define V_MAXSPLTRNC(x) ((x) << S_MAXSPLTRNC)
680 #define G_MAXSPLTRNC(x) (((x) >> S_MAXSPLTRNC) & M_MAXSPLTRNC)
681 
682 #define S_MAXSPLTRNR    5
683 #define M_MAXSPLTRNR    0x7
684 #define V_MAXSPLTRNR(x) ((x) << S_MAXSPLTRNR)
685 #define G_MAXSPLTRNR(x) (((x) >> S_MAXSPLTRNR) & M_MAXSPLTRNR)
686 
687 #define S_MAXWRBYTECNT    3
688 #define M_MAXWRBYTECNT    0x3
689 #define V_MAXWRBYTECNT(x) ((x) << S_MAXWRBYTECNT)
690 #define G_MAXWRBYTECNT(x) (((x) >> S_MAXWRBYTECNT) & M_MAXWRBYTECNT)
691 
692 #define S_WRREQATOMICEN    2
693 #define V_WRREQATOMICEN(x) ((x) << S_WRREQATOMICEN)
694 #define F_WRREQATOMICEN    V_WRREQATOMICEN(1U)
695 
696 #define S_RSTWRMMODE    1
697 #define V_RSTWRMMODE(x) ((x) << S_RSTWRMMODE)
698 #define F_RSTWRMMODE    V_RSTWRMMODE(1U)
699 
700 #define S_PIOACK64EN    0
701 #define V_PIOACK64EN(x) ((x) << S_PIOACK64EN)
702 #define F_PIOACK64EN    V_PIOACK64EN(1U)
703 
704 #define A_PCIX_MODE 0x8c
705 
706 #define S_PCLKRANGE    6
707 #define M_PCLKRANGE    0x3
708 #define V_PCLKRANGE(x) ((x) << S_PCLKRANGE)
709 #define G_PCLKRANGE(x) (((x) >> S_PCLKRANGE) & M_PCLKRANGE)
710 
711 #define S_PCIXINITPAT    2
712 #define M_PCIXINITPAT    0xf
713 #define V_PCIXINITPAT(x) ((x) << S_PCIXINITPAT)
714 #define G_PCIXINITPAT(x) (((x) >> S_PCIXINITPAT) & M_PCIXINITPAT)
715 
716 #define S_66MHZ    1
717 #define V_66MHZ(x) ((x) << S_66MHZ)
718 #define F_66MHZ    V_66MHZ(1U)
719 
720 #define S_64BIT    0
721 #define V_64BIT(x) ((x) << S_64BIT)
722 #define F_64BIT    V_64BIT(1U)
723 
724 #define A_PCIX_CAL 0x90
725 
726 #define S_BUSY    31
727 #define V_BUSY(x) ((x) << S_BUSY)
728 #define F_BUSY    V_BUSY(1U)
729 
730 #define S_PERCALDIV    22
731 #define M_PERCALDIV    0xff
732 #define V_PERCALDIV(x) ((x) << S_PERCALDIV)
733 #define G_PERCALDIV(x) (((x) >> S_PERCALDIV) & M_PERCALDIV)
734 
735 #define S_PERCALEN    21
736 #define V_PERCALEN(x) ((x) << S_PERCALEN)
737 #define F_PERCALEN    V_PERCALEN(1U)
738 
739 #define S_SGLCALEN    20
740 #define V_SGLCALEN(x) ((x) << S_SGLCALEN)
741 #define F_SGLCALEN    V_SGLCALEN(1U)
742 
743 #define S_ZINUPDMODE    19
744 #define V_ZINUPDMODE(x) ((x) << S_ZINUPDMODE)
745 #define F_ZINUPDMODE    V_ZINUPDMODE(1U)
746 
747 #define S_ZINSEL    18
748 #define V_ZINSEL(x) ((x) << S_ZINSEL)
749 #define F_ZINSEL    V_ZINSEL(1U)
750 
751 #define S_ZPDMAN    15
752 #define M_ZPDMAN    0x7
753 #define V_ZPDMAN(x) ((x) << S_ZPDMAN)
754 #define G_ZPDMAN(x) (((x) >> S_ZPDMAN) & M_ZPDMAN)
755 
756 #define S_ZPUMAN    12
757 #define M_ZPUMAN    0x7
758 #define V_ZPUMAN(x) ((x) << S_ZPUMAN)
759 #define G_ZPUMAN(x) (((x) >> S_ZPUMAN) & M_ZPUMAN)
760 
761 #define S_ZPDOUT    9
762 #define M_ZPDOUT    0x7
763 #define V_ZPDOUT(x) ((x) << S_ZPDOUT)
764 #define G_ZPDOUT(x) (((x) >> S_ZPDOUT) & M_ZPDOUT)
765 
766 #define S_ZPUOUT    6
767 #define M_ZPUOUT    0x7
768 #define V_ZPUOUT(x) ((x) << S_ZPUOUT)
769 #define G_ZPUOUT(x) (((x) >> S_ZPUOUT) & M_ZPUOUT)
770 
771 #define S_ZPDIN    3
772 #define M_ZPDIN    0x7
773 #define V_ZPDIN(x) ((x) << S_ZPDIN)
774 #define G_ZPDIN(x) (((x) >> S_ZPDIN) & M_ZPDIN)
775 
776 #define S_ZPUIN    0
777 #define M_ZPUIN    0x7
778 #define V_ZPUIN(x) ((x) << S_ZPUIN)
779 #define G_ZPUIN(x) (((x) >> S_ZPUIN) & M_ZPUIN)
780 
781 #define A_PCIX_WOL 0x94
782 
783 #define S_WAKEUP1    3
784 #define V_WAKEUP1(x) ((x) << S_WAKEUP1)
785 #define F_WAKEUP1    V_WAKEUP1(1U)
786 
787 #define S_WAKEUP0    2
788 #define V_WAKEUP0(x) ((x) << S_WAKEUP0)
789 #define F_WAKEUP0    V_WAKEUP0(1U)
790 
791 #define S_SLEEPMODE1    1
792 #define V_SLEEPMODE1(x) ((x) << S_SLEEPMODE1)
793 #define F_SLEEPMODE1    V_SLEEPMODE1(1U)
794 
795 #define S_SLEEPMODE0    0
796 #define V_SLEEPMODE0(x) ((x) << S_SLEEPMODE0)
797 #define F_SLEEPMODE0    V_SLEEPMODE0(1U)
798 
799 #define A_PCIX_STAT0 0x98
800 
801 #define S_PIOREQFIFOLEVEL    26
802 #define M_PIOREQFIFOLEVEL    0x3f
803 #define V_PIOREQFIFOLEVEL(x) ((x) << S_PIOREQFIFOLEVEL)
804 #define G_PIOREQFIFOLEVEL(x) (((x) >> S_PIOREQFIFOLEVEL) & M_PIOREQFIFOLEVEL)
805 
806 #define S_RFINIST    24
807 #define M_RFINIST    0x3
808 #define V_RFINIST(x) ((x) << S_RFINIST)
809 #define G_RFINIST(x) (((x) >> S_RFINIST) & M_RFINIST)
810 
811 #define S_RFRESPRDST    22
812 #define M_RFRESPRDST    0x3
813 #define V_RFRESPRDST(x) ((x) << S_RFRESPRDST)
814 #define G_RFRESPRDST(x) (((x) >> S_RFRESPRDST) & M_RFRESPRDST)
815 
816 #define S_TARCST    19
817 #define M_TARCST    0x7
818 #define V_TARCST(x) ((x) << S_TARCST)
819 #define G_TARCST(x) (((x) >> S_TARCST) & M_TARCST)
820 
821 #define S_TARXST    16
822 #define M_TARXST    0x7
823 #define V_TARXST(x) ((x) << S_TARXST)
824 #define G_TARXST(x) (((x) >> S_TARXST) & M_TARXST)
825 
826 #define S_WFREQWRST    13
827 #define M_WFREQWRST    0x7
828 #define V_WFREQWRST(x) ((x) << S_WFREQWRST)
829 #define G_WFREQWRST(x) (((x) >> S_WFREQWRST) & M_WFREQWRST)
830 
831 #define S_WFRESPFIFOEMPTY    12
832 #define V_WFRESPFIFOEMPTY(x) ((x) << S_WFRESPFIFOEMPTY)
833 #define F_WFRESPFIFOEMPTY    V_WFRESPFIFOEMPTY(1U)
834 
835 #define S_WFREQFIFOEMPTY    11
836 #define V_WFREQFIFOEMPTY(x) ((x) << S_WFREQFIFOEMPTY)
837 #define F_WFREQFIFOEMPTY    V_WFREQFIFOEMPTY(1U)
838 
839 #define S_RFRESPFIFOEMPTY    10
840 #define V_RFRESPFIFOEMPTY(x) ((x) << S_RFRESPFIFOEMPTY)
841 #define F_RFRESPFIFOEMPTY    V_RFRESPFIFOEMPTY(1U)
842 
843 #define S_RFREQFIFOEMPTY    9
844 #define V_RFREQFIFOEMPTY(x) ((x) << S_RFREQFIFOEMPTY)
845 #define F_RFREQFIFOEMPTY    V_RFREQFIFOEMPTY(1U)
846 
847 #define S_PIORESPFIFOLEVEL    7
848 #define M_PIORESPFIFOLEVEL    0x3
849 #define V_PIORESPFIFOLEVEL(x) ((x) << S_PIORESPFIFOLEVEL)
850 #define G_PIORESPFIFOLEVEL(x) (((x) >> S_PIORESPFIFOLEVEL) & M_PIORESPFIFOLEVEL)
851 
852 #define S_CFRESPFIFOEMPTY    6
853 #define V_CFRESPFIFOEMPTY(x) ((x) << S_CFRESPFIFOEMPTY)
854 #define F_CFRESPFIFOEMPTY    V_CFRESPFIFOEMPTY(1U)
855 
856 #define S_CFREQFIFOEMPTY    5
857 #define V_CFREQFIFOEMPTY(x) ((x) << S_CFREQFIFOEMPTY)
858 #define F_CFREQFIFOEMPTY    V_CFREQFIFOEMPTY(1U)
859 
860 #define S_VPDRESPFIFOEMPTY    4
861 #define V_VPDRESPFIFOEMPTY(x) ((x) << S_VPDRESPFIFOEMPTY)
862 #define F_VPDRESPFIFOEMPTY    V_VPDRESPFIFOEMPTY(1U)
863 
864 #define S_VPDREQFIFOEMPTY    3
865 #define V_VPDREQFIFOEMPTY(x) ((x) << S_VPDREQFIFOEMPTY)
866 #define F_VPDREQFIFOEMPTY    V_VPDREQFIFOEMPTY(1U)
867 
868 #define S_PIO_RSPPND    2
869 #define V_PIO_RSPPND(x) ((x) << S_PIO_RSPPND)
870 #define F_PIO_RSPPND    V_PIO_RSPPND(1U)
871 
872 #define S_DLYTRNPND    1
873 #define V_DLYTRNPND(x) ((x) << S_DLYTRNPND)
874 #define F_DLYTRNPND    V_DLYTRNPND(1U)
875 
876 #define S_SPLTRNPND    0
877 #define V_SPLTRNPND(x) ((x) << S_SPLTRNPND)
878 #define F_SPLTRNPND    V_SPLTRNPND(1U)
879 
880 #define A_PCIX_STAT1 0x9c
881 
882 #define S_WFINIST    26
883 #define M_WFINIST    0xf
884 #define V_WFINIST(x) ((x) << S_WFINIST)
885 #define G_WFINIST(x) (((x) >> S_WFINIST) & M_WFINIST)
886 
887 #define S_ARBST    23
888 #define M_ARBST    0x7
889 #define V_ARBST(x) ((x) << S_ARBST)
890 #define G_ARBST(x) (((x) >> S_ARBST) & M_ARBST)
891 
892 #define S_PMIST    21
893 #define M_PMIST    0x3
894 #define V_PMIST(x) ((x) << S_PMIST)
895 #define G_PMIST(x) (((x) >> S_PMIST) & M_PMIST)
896 
897 #define S_CALST    19
898 #define M_CALST    0x3
899 #define V_CALST(x) ((x) << S_CALST)
900 #define G_CALST(x) (((x) >> S_CALST) & M_CALST)
901 
902 #define S_CFREQRDST    17
903 #define M_CFREQRDST    0x3
904 #define V_CFREQRDST(x) ((x) << S_CFREQRDST)
905 #define G_CFREQRDST(x) (((x) >> S_CFREQRDST) & M_CFREQRDST)
906 
907 #define S_CFINIST    15
908 #define M_CFINIST    0x3
909 #define V_CFINIST(x) ((x) << S_CFINIST)
910 #define G_CFINIST(x) (((x) >> S_CFINIST) & M_CFINIST)
911 
912 #define S_CFRESPRDST    13
913 #define M_CFRESPRDST    0x3
914 #define V_CFRESPRDST(x) ((x) << S_CFRESPRDST)
915 #define G_CFRESPRDST(x) (((x) >> S_CFRESPRDST) & M_CFRESPRDST)
916 
917 #define S_INICST    10
918 #define M_INICST    0x7
919 #define V_INICST(x) ((x) << S_INICST)
920 #define G_INICST(x) (((x) >> S_INICST) & M_INICST)
921 
922 #define S_INIXST    7
923 #define M_INIXST    0x7
924 #define V_INIXST(x) ((x) << S_INIXST)
925 #define G_INIXST(x) (((x) >> S_INIXST) & M_INIXST)
926 
927 #define S_INTST    4
928 #define M_INTST    0x7
929 #define V_INTST(x) ((x) << S_INTST)
930 #define G_INTST(x) (((x) >> S_INTST) & M_INTST)
931 
932 #define S_PIOST    2
933 #define M_PIOST    0x3
934 #define V_PIOST(x) ((x) << S_PIOST)
935 #define G_PIOST(x) (((x) >> S_PIOST) & M_PIOST)
936 
937 #define S_RFREQRDST    0
938 #define M_RFREQRDST    0x3
939 #define V_RFREQRDST(x) ((x) << S_RFREQRDST)
940 #define G_RFREQRDST(x) (((x) >> S_RFREQRDST) & M_RFREQRDST)
941 
942 /* registers for module PCIE0 */
943 #define PCIE0_BASE_ADDR 0x80
944 
945 #define A_PCIE_INT_ENABLE 0x80
946 
947 #define S_BISTERR    19
948 #define M_BISTERR    0xff
949 #define V_BISTERR(x) ((x) << S_BISTERR)
950 #define G_BISTERR(x) (((x) >> S_BISTERR) & M_BISTERR)
951 
952 #define S_TXPARERR    18
953 #define V_TXPARERR(x) ((x) << S_TXPARERR)
954 #define F_TXPARERR    V_TXPARERR(1U)
955 
956 #define S_RXPARERR    17
957 #define V_RXPARERR(x) ((x) << S_RXPARERR)
958 #define F_RXPARERR    V_RXPARERR(1U)
959 
960 #define S_RETRYLUTPARERR    16
961 #define V_RETRYLUTPARERR(x) ((x) << S_RETRYLUTPARERR)
962 #define F_RETRYLUTPARERR    V_RETRYLUTPARERR(1U)
963 
964 #define S_RETRYBUFPARERR    15
965 #define V_RETRYBUFPARERR(x) ((x) << S_RETRYBUFPARERR)
966 #define F_RETRYBUFPARERR    V_RETRYBUFPARERR(1U)
967 
968 #define S_PCIE_MSIXPARERR    12
969 #define M_PCIE_MSIXPARERR    0x7
970 #define V_PCIE_MSIXPARERR(x) ((x) << S_PCIE_MSIXPARERR)
971 #define G_PCIE_MSIXPARERR(x) (((x) >> S_PCIE_MSIXPARERR) & M_PCIE_MSIXPARERR)
972 
973 #define S_PCIE_CFPARERR    11
974 #define V_PCIE_CFPARERR(x) ((x) << S_PCIE_CFPARERR)
975 #define F_PCIE_CFPARERR    V_PCIE_CFPARERR(1U)
976 
977 #define S_PCIE_RFPARERR    10
978 #define V_PCIE_RFPARERR(x) ((x) << S_PCIE_RFPARERR)
979 #define F_PCIE_RFPARERR    V_PCIE_RFPARERR(1U)
980 
981 #define S_PCIE_WFPARERR    9
982 #define V_PCIE_WFPARERR(x) ((x) << S_PCIE_WFPARERR)
983 #define F_PCIE_WFPARERR    V_PCIE_WFPARERR(1U)
984 
985 #define S_PCIE_PIOPARERR    8
986 #define V_PCIE_PIOPARERR(x) ((x) << S_PCIE_PIOPARERR)
987 #define F_PCIE_PIOPARERR    V_PCIE_PIOPARERR(1U)
988 
989 #define S_UNXSPLCPLERRC    7
990 #define V_UNXSPLCPLERRC(x) ((x) << S_UNXSPLCPLERRC)
991 #define F_UNXSPLCPLERRC    V_UNXSPLCPLERRC(1U)
992 
993 #define S_UNXSPLCPLERRR    6
994 #define V_UNXSPLCPLERRR(x) ((x) << S_UNXSPLCPLERRR)
995 #define F_UNXSPLCPLERRR    V_UNXSPLCPLERRR(1U)
996 
997 #define S_VPDADDRCHNG    5
998 #define V_VPDADDRCHNG(x) ((x) << S_VPDADDRCHNG)
999 #define F_VPDADDRCHNG    V_VPDADDRCHNG(1U)
1000 
1001 #define S_BUSMSTREN    4
1002 #define V_BUSMSTREN(x) ((x) << S_BUSMSTREN)
1003 #define F_BUSMSTREN    V_BUSMSTREN(1U)
1004 
1005 #define S_PMSTCHNG    3
1006 #define V_PMSTCHNG(x) ((x) << S_PMSTCHNG)
1007 #define F_PMSTCHNG    V_PMSTCHNG(1U)
1008 
1009 #define S_PEXMSG    2
1010 #define V_PEXMSG(x) ((x) << S_PEXMSG)
1011 #define F_PEXMSG    V_PEXMSG(1U)
1012 
1013 #define S_ZEROLENRD    1
1014 #define V_ZEROLENRD(x) ((x) << S_ZEROLENRD)
1015 #define F_ZEROLENRD    V_ZEROLENRD(1U)
1016 
1017 #define S_PEXERR    0
1018 #define V_PEXERR(x) ((x) << S_PEXERR)
1019 #define F_PEXERR    V_PEXERR(1U)
1020 
1021 #define A_PCIE_INT_CAUSE 0x84
1022 #define A_PCIE_CFG 0x88
1023 
1024 #define S_PCIE_DMASTOPEN    24
1025 #define V_PCIE_DMASTOPEN(x) ((x) << S_PCIE_DMASTOPEN)
1026 #define F_PCIE_DMASTOPEN    V_PCIE_DMASTOPEN(1U)
1027 
1028 #define S_PRIORITYINTA    23
1029 #define V_PRIORITYINTA(x) ((x) << S_PRIORITYINTA)
1030 #define F_PRIORITYINTA    V_PRIORITYINTA(1U)
1031 
1032 #define S_INIFULLPKT    22
1033 #define V_INIFULLPKT(x) ((x) << S_INIFULLPKT)
1034 #define F_INIFULLPKT    V_INIFULLPKT(1U)
1035 
1036 #define S_ENABLELINKDWNDRST    21
1037 #define V_ENABLELINKDWNDRST(x) ((x) << S_ENABLELINKDWNDRST)
1038 #define F_ENABLELINKDWNDRST    V_ENABLELINKDWNDRST(1U)
1039 
1040 #define S_ENABLELINKDOWNRST    20
1041 #define V_ENABLELINKDOWNRST(x) ((x) << S_ENABLELINKDOWNRST)
1042 #define F_ENABLELINKDOWNRST    V_ENABLELINKDOWNRST(1U)
1043 
1044 #define S_ENABLEHOTRST    19
1045 #define V_ENABLEHOTRST(x) ((x) << S_ENABLEHOTRST)
1046 #define F_ENABLEHOTRST    V_ENABLEHOTRST(1U)
1047 
1048 #define S_INIWAITFORGNT    18
1049 #define V_INIWAITFORGNT(x) ((x) << S_INIWAITFORGNT)
1050 #define F_INIWAITFORGNT    V_INIWAITFORGNT(1U)
1051 
1052 #define S_INIBEDIS    17
1053 #define V_INIBEDIS(x) ((x) << S_INIBEDIS)
1054 #define F_INIBEDIS    V_INIBEDIS(1U)
1055 
1056 #define S_PCIE_CLIDECEN    16
1057 #define V_PCIE_CLIDECEN(x) ((x) << S_PCIE_CLIDECEN)
1058 #define F_PCIE_CLIDECEN    V_PCIE_CLIDECEN(1U)
1059 
1060 #define S_PCIE_MAXSPLTRNC    7
1061 #define M_PCIE_MAXSPLTRNC    0xf
1062 #define V_PCIE_MAXSPLTRNC(x) ((x) << S_PCIE_MAXSPLTRNC)
1063 #define G_PCIE_MAXSPLTRNC(x) (((x) >> S_PCIE_MAXSPLTRNC) & M_PCIE_MAXSPLTRNC)
1064 
1065 #define S_PCIE_MAXSPLTRNR    1
1066 #define M_PCIE_MAXSPLTRNR    0x3f
1067 #define V_PCIE_MAXSPLTRNR(x) ((x) << S_PCIE_MAXSPLTRNR)
1068 #define G_PCIE_MAXSPLTRNR(x) (((x) >> S_PCIE_MAXSPLTRNR) & M_PCIE_MAXSPLTRNR)
1069 
1070 #define S_CRSTWRMMODE    0
1071 #define V_CRSTWRMMODE(x) ((x) << S_CRSTWRMMODE)
1072 #define F_CRSTWRMMODE    V_CRSTWRMMODE(1U)
1073 
1074 #define A_PCIE_MODE 0x8c
1075 
1076 #define S_TAR_STATE    29
1077 #define M_TAR_STATE    0x7
1078 #define V_TAR_STATE(x) ((x) << S_TAR_STATE)
1079 #define G_TAR_STATE(x) (((x) >> S_TAR_STATE) & M_TAR_STATE)
1080 
1081 #define S_RF_STATEINI    26
1082 #define M_RF_STATEINI    0x7
1083 #define V_RF_STATEINI(x) ((x) << S_RF_STATEINI)
1084 #define G_RF_STATEINI(x) (((x) >> S_RF_STATEINI) & M_RF_STATEINI)
1085 
1086 #define S_CF_STATEINI    23
1087 #define M_CF_STATEINI    0x7
1088 #define V_CF_STATEINI(x) ((x) << S_CF_STATEINI)
1089 #define G_CF_STATEINI(x) (((x) >> S_CF_STATEINI) & M_CF_STATEINI)
1090 
1091 #define S_PIO_STATEPL    20
1092 #define M_PIO_STATEPL    0x7
1093 #define V_PIO_STATEPL(x) ((x) << S_PIO_STATEPL)
1094 #define G_PIO_STATEPL(x) (((x) >> S_PIO_STATEPL) & M_PIO_STATEPL)
1095 
1096 #define S_PIO_STATEISC    18
1097 #define M_PIO_STATEISC    0x3
1098 #define V_PIO_STATEISC(x) ((x) << S_PIO_STATEISC)
1099 #define G_PIO_STATEISC(x) (((x) >> S_PIO_STATEISC) & M_PIO_STATEISC)
1100 
1101 #define S_NUMFSTTRNSEQRX    10
1102 #define M_NUMFSTTRNSEQRX    0xff
1103 #define V_NUMFSTTRNSEQRX(x) ((x) << S_NUMFSTTRNSEQRX)
1104 #define G_NUMFSTTRNSEQRX(x) (((x) >> S_NUMFSTTRNSEQRX) & M_NUMFSTTRNSEQRX)
1105 
1106 #define S_LNKCNTLSTATE    2
1107 #define M_LNKCNTLSTATE    0xff
1108 #define V_LNKCNTLSTATE(x) ((x) << S_LNKCNTLSTATE)
1109 #define G_LNKCNTLSTATE(x) (((x) >> S_LNKCNTLSTATE) & M_LNKCNTLSTATE)
1110 
1111 #define S_VC0UP    1
1112 #define V_VC0UP(x) ((x) << S_VC0UP)
1113 #define F_VC0UP    V_VC0UP(1U)
1114 
1115 #define S_LNKINITIAL    0
1116 #define V_LNKINITIAL(x) ((x) << S_LNKINITIAL)
1117 #define F_LNKINITIAL    V_LNKINITIAL(1U)
1118 
1119 #define A_PCIE_STAT 0x90
1120 
1121 #define S_INI_STATE    28
1122 #define M_INI_STATE    0xf
1123 #define V_INI_STATE(x) ((x) << S_INI_STATE)
1124 #define G_INI_STATE(x) (((x) >> S_INI_STATE) & M_INI_STATE)
1125 
1126 #define S_WF_STATEINI    24
1127 #define M_WF_STATEINI    0xf
1128 #define V_WF_STATEINI(x) ((x) << S_WF_STATEINI)
1129 #define G_WF_STATEINI(x) (((x) >> S_WF_STATEINI) & M_WF_STATEINI)
1130 
1131 #define S_PLM_REQFIFOCNT    22
1132 #define M_PLM_REQFIFOCNT    0x3
1133 #define V_PLM_REQFIFOCNT(x) ((x) << S_PLM_REQFIFOCNT)
1134 #define G_PLM_REQFIFOCNT(x) (((x) >> S_PLM_REQFIFOCNT) & M_PLM_REQFIFOCNT)
1135 
1136 #define S_ER_REQFIFOEMPTY    21
1137 #define V_ER_REQFIFOEMPTY(x) ((x) << S_ER_REQFIFOEMPTY)
1138 #define F_ER_REQFIFOEMPTY    V_ER_REQFIFOEMPTY(1U)
1139 
1140 #define S_WF_RSPFIFOEMPTY    20
1141 #define V_WF_RSPFIFOEMPTY(x) ((x) << S_WF_RSPFIFOEMPTY)
1142 #define F_WF_RSPFIFOEMPTY    V_WF_RSPFIFOEMPTY(1U)
1143 
1144 #define S_WF_REQFIFOEMPTY    19
1145 #define V_WF_REQFIFOEMPTY(x) ((x) << S_WF_REQFIFOEMPTY)
1146 #define F_WF_REQFIFOEMPTY    V_WF_REQFIFOEMPTY(1U)
1147 
1148 #define S_RF_RSPFIFOEMPTY    18
1149 #define V_RF_RSPFIFOEMPTY(x) ((x) << S_RF_RSPFIFOEMPTY)
1150 #define F_RF_RSPFIFOEMPTY    V_RF_RSPFIFOEMPTY(1U)
1151 
1152 #define S_RF_REQFIFOEMPTY    17
1153 #define V_RF_REQFIFOEMPTY(x) ((x) << S_RF_REQFIFOEMPTY)
1154 #define F_RF_REQFIFOEMPTY    V_RF_REQFIFOEMPTY(1U)
1155 
1156 #define S_RF_ACTEMPTY    16
1157 #define V_RF_ACTEMPTY(x) ((x) << S_RF_ACTEMPTY)
1158 #define F_RF_ACTEMPTY    V_RF_ACTEMPTY(1U)
1159 
1160 #define S_PIO_RSPFIFOCNT    11
1161 #define M_PIO_RSPFIFOCNT    0x1f
1162 #define V_PIO_RSPFIFOCNT(x) ((x) << S_PIO_RSPFIFOCNT)
1163 #define G_PIO_RSPFIFOCNT(x) (((x) >> S_PIO_RSPFIFOCNT) & M_PIO_RSPFIFOCNT)
1164 
1165 #define S_PIO_REQFIFOCNT    5
1166 #define M_PIO_REQFIFOCNT    0x3f
1167 #define V_PIO_REQFIFOCNT(x) ((x) << S_PIO_REQFIFOCNT)
1168 #define G_PIO_REQFIFOCNT(x) (((x) >> S_PIO_REQFIFOCNT) & M_PIO_REQFIFOCNT)
1169 
1170 #define S_CF_RSPFIFOEMPTY    4
1171 #define V_CF_RSPFIFOEMPTY(x) ((x) << S_CF_RSPFIFOEMPTY)
1172 #define F_CF_RSPFIFOEMPTY    V_CF_RSPFIFOEMPTY(1U)
1173 
1174 #define S_CF_REQFIFOEMPTY    3
1175 #define V_CF_REQFIFOEMPTY(x) ((x) << S_CF_REQFIFOEMPTY)
1176 #define F_CF_REQFIFOEMPTY    V_CF_REQFIFOEMPTY(1U)
1177 
1178 #define S_CF_ACTEMPTY    2
1179 #define V_CF_ACTEMPTY(x) ((x) << S_CF_ACTEMPTY)
1180 #define F_CF_ACTEMPTY    V_CF_ACTEMPTY(1U)
1181 
1182 #define S_VPD_RSPFIFOEMPTY    1
1183 #define V_VPD_RSPFIFOEMPTY(x) ((x) << S_VPD_RSPFIFOEMPTY)
1184 #define F_VPD_RSPFIFOEMPTY    V_VPD_RSPFIFOEMPTY(1U)
1185 
1186 #define S_VPD_REQFIFOEMPTY    0
1187 #define V_VPD_REQFIFOEMPTY(x) ((x) << S_VPD_REQFIFOEMPTY)
1188 #define F_VPD_REQFIFOEMPTY    V_VPD_REQFIFOEMPTY(1U)
1189 
1190 #define A_PCIE_CAL 0x90
1191 
1192 #define S_CALBUSY    31
1193 #define V_CALBUSY(x) ((x) << S_CALBUSY)
1194 #define F_CALBUSY    V_CALBUSY(1U)
1195 
1196 #define S_CALFAULT    30
1197 #define V_CALFAULT(x) ((x) << S_CALFAULT)
1198 #define F_CALFAULT    V_CALFAULT(1U)
1199 
1200 #define S_PCIE_ZINSEL    11
1201 #define V_PCIE_ZINSEL(x) ((x) << S_PCIE_ZINSEL)
1202 #define F_PCIE_ZINSEL    V_PCIE_ZINSEL(1U)
1203 
1204 #define S_ZMAN    8
1205 #define M_ZMAN    0x7
1206 #define V_ZMAN(x) ((x) << S_ZMAN)
1207 #define G_ZMAN(x) (((x) >> S_ZMAN) & M_ZMAN)
1208 
1209 #define S_ZOUT    3
1210 #define M_ZOUT    0x1f
1211 #define V_ZOUT(x) ((x) << S_ZOUT)
1212 #define G_ZOUT(x) (((x) >> S_ZOUT) & M_ZOUT)
1213 
1214 #define S_ZIN    0
1215 #define M_ZIN    0x7
1216 #define V_ZIN(x) ((x) << S_ZIN)
1217 #define G_ZIN(x) (((x) >> S_ZIN) & M_ZIN)
1218 
1219 #define A_PCIE_WOL 0x94
1220 
1221 #define S_CF_RSPSTATE    12
1222 #define M_CF_RSPSTATE    0x3
1223 #define V_CF_RSPSTATE(x) ((x) << S_CF_RSPSTATE)
1224 #define G_CF_RSPSTATE(x) (((x) >> S_CF_RSPSTATE) & M_CF_RSPSTATE)
1225 
1226 #define S_RF_RSPSTATE    10
1227 #define M_RF_RSPSTATE    0x3
1228 #define V_RF_RSPSTATE(x) ((x) << S_RF_RSPSTATE)
1229 #define G_RF_RSPSTATE(x) (((x) >> S_RF_RSPSTATE) & M_RF_RSPSTATE)
1230 
1231 #define S_PME_STATE    7
1232 #define M_PME_STATE    0x7
1233 #define V_PME_STATE(x) ((x) << S_PME_STATE)
1234 #define G_PME_STATE(x) (((x) >> S_PME_STATE) & M_PME_STATE)
1235 
1236 #define S_INT_STATE    4
1237 #define M_INT_STATE    0x7
1238 #define V_INT_STATE(x) ((x) << S_INT_STATE)
1239 #define G_INT_STATE(x) (((x) >> S_INT_STATE) & M_INT_STATE)
1240 
1241 #define A_PCIE_PEX_CTRL0 0x98
1242 
1243 #define S_CPLTIMEOUTRETRY    31
1244 #define V_CPLTIMEOUTRETRY(x) ((x) << S_CPLTIMEOUTRETRY)
1245 #define F_CPLTIMEOUTRETRY    V_CPLTIMEOUTRETRY(1U)
1246 
1247 #define S_STRICTTSMN    30
1248 #define V_STRICTTSMN(x) ((x) << S_STRICTTSMN)
1249 #define F_STRICTTSMN    V_STRICTTSMN(1U)
1250 
1251 #define S_NUMFSTTRNSEQ    22
1252 #define M_NUMFSTTRNSEQ    0xff
1253 #define V_NUMFSTTRNSEQ(x) ((x) << S_NUMFSTTRNSEQ)
1254 #define G_NUMFSTTRNSEQ(x) (((x) >> S_NUMFSTTRNSEQ) & M_NUMFSTTRNSEQ)
1255 
1256 #define S_REPLAYLMT    2
1257 #define M_REPLAYLMT    0xfffff
1258 #define V_REPLAYLMT(x) ((x) << S_REPLAYLMT)
1259 #define G_REPLAYLMT(x) (((x) >> S_REPLAYLMT) & M_REPLAYLMT)
1260 
1261 #define S_TXPNDCHKEN    1
1262 #define V_TXPNDCHKEN(x) ((x) << S_TXPNDCHKEN)
1263 #define F_TXPNDCHKEN    V_TXPNDCHKEN(1U)
1264 
1265 #define S_CPLPNDCHKEN    0
1266 #define V_CPLPNDCHKEN(x) ((x) << S_CPLPNDCHKEN)
1267 #define F_CPLPNDCHKEN    V_CPLPNDCHKEN(1U)
1268 
1269 #define A_PCIE_PEX_CTRL1 0x9c
1270 
1271 #define S_RXPHYERREN    31
1272 #define V_RXPHYERREN(x) ((x) << S_RXPHYERREN)
1273 #define F_RXPHYERREN    V_RXPHYERREN(1U)
1274 
1275 #define S_DLLPTIMEOUTLMT    13
1276 #define M_DLLPTIMEOUTLMT    0x3ffff
1277 #define V_DLLPTIMEOUTLMT(x) ((x) << S_DLLPTIMEOUTLMT)
1278 #define G_DLLPTIMEOUTLMT(x) (((x) >> S_DLLPTIMEOUTLMT) & M_DLLPTIMEOUTLMT)
1279 
1280 #define S_ACKLAT    0
1281 #define M_ACKLAT    0x1fff
1282 #define V_ACKLAT(x) ((x) << S_ACKLAT)
1283 #define G_ACKLAT(x) (((x) >> S_ACKLAT) & M_ACKLAT)
1284 
1285 #define S_T3A_DLLPTIMEOUTLMT    11
1286 #define M_T3A_DLLPTIMEOUTLMT    0xfffff
1287 #define V_T3A_DLLPTIMEOUTLMT(x) ((x) << S_T3A_DLLPTIMEOUTLMT)
1288 #define G_T3A_DLLPTIMEOUTLMT(x) (((x) >> S_T3A_DLLPTIMEOUTLMT) & M_T3A_DLLPTIMEOUTLMT)
1289 
1290 #define S_T3A_ACKLAT    0
1291 #define M_T3A_ACKLAT    0x7ff
1292 #define V_T3A_ACKLAT(x) ((x) << S_T3A_ACKLAT)
1293 #define G_T3A_ACKLAT(x) (((x) >> S_T3A_ACKLAT) & M_T3A_ACKLAT)
1294 
1295 #define A_PCIE_PEX_CTRL2 0xa0
1296 
1297 #define S_LNKCNTLDETDIR    30
1298 #define V_LNKCNTLDETDIR(x) ((x) << S_LNKCNTLDETDIR)
1299 #define F_LNKCNTLDETDIR    V_LNKCNTLDETDIR(1U)
1300 
1301 #define S_ENTERL1REN    29
1302 #define V_ENTERL1REN(x) ((x) << S_ENTERL1REN)
1303 #define F_ENTERL1REN    V_ENTERL1REN(1U)
1304 
1305 #define S_PMEXITL1REQ    28
1306 #define V_PMEXITL1REQ(x) ((x) << S_PMEXITL1REQ)
1307 #define F_PMEXITL1REQ    V_PMEXITL1REQ(1U)
1308 
1309 #define S_PMTXIDLE    27
1310 #define V_PMTXIDLE(x) ((x) << S_PMTXIDLE)
1311 #define F_PMTXIDLE    V_PMTXIDLE(1U)
1312 
1313 #define S_PCIMODELOOP    26
1314 #define V_PCIMODELOOP(x) ((x) << S_PCIMODELOOP)
1315 #define F_PCIMODELOOP    V_PCIMODELOOP(1U)
1316 
1317 #define S_L1ASPMTXRXL0STIME    14
1318 #define M_L1ASPMTXRXL0STIME    0xfff
1319 #define V_L1ASPMTXRXL0STIME(x) ((x) << S_L1ASPMTXRXL0STIME)
1320 #define G_L1ASPMTXRXL0STIME(x) (((x) >> S_L1ASPMTXRXL0STIME) & M_L1ASPMTXRXL0STIME)
1321 
1322 #define S_L0SIDLETIME    3
1323 #define M_L0SIDLETIME    0x7ff
1324 #define V_L0SIDLETIME(x) ((x) << S_L0SIDLETIME)
1325 #define G_L0SIDLETIME(x) (((x) >> S_L0SIDLETIME) & M_L0SIDLETIME)
1326 
1327 #define S_ENTERL1ASPMEN    2
1328 #define V_ENTERL1ASPMEN(x) ((x) << S_ENTERL1ASPMEN)
1329 #define F_ENTERL1ASPMEN    V_ENTERL1ASPMEN(1U)
1330 
1331 #define S_ENTERL1EN    1
1332 #define V_ENTERL1EN(x) ((x) << S_ENTERL1EN)
1333 #define F_ENTERL1EN    V_ENTERL1EN(1U)
1334 
1335 #define S_ENTERL0SEN    0
1336 #define V_ENTERL0SEN(x) ((x) << S_ENTERL0SEN)
1337 #define F_ENTERL0SEN    V_ENTERL0SEN(1U)
1338 
1339 #define S_ENTERL23    3
1340 #define V_ENTERL23(x) ((x) << S_ENTERL23)
1341 #define F_ENTERL23    V_ENTERL23(1U)
1342 
1343 #define A_PCIE_PEX_ERR 0xa4
1344 
1345 #define S_CPLTIMEOUTID    18
1346 #define M_CPLTIMEOUTID    0x7f
1347 #define V_CPLTIMEOUTID(x) ((x) << S_CPLTIMEOUTID)
1348 #define G_CPLTIMEOUTID(x) (((x) >> S_CPLTIMEOUTID) & M_CPLTIMEOUTID)
1349 
1350 #define S_FLOWCTLOFLOWERR    17
1351 #define V_FLOWCTLOFLOWERR(x) ((x) << S_FLOWCTLOFLOWERR)
1352 #define F_FLOWCTLOFLOWERR    V_FLOWCTLOFLOWERR(1U)
1353 
1354 #define S_REPLAYTIMEOUT    16
1355 #define V_REPLAYTIMEOUT(x) ((x) << S_REPLAYTIMEOUT)
1356 #define F_REPLAYTIMEOUT    V_REPLAYTIMEOUT(1U)
1357 
1358 #define S_REPLAYROLLOVER    15
1359 #define V_REPLAYROLLOVER(x) ((x) << S_REPLAYROLLOVER)
1360 #define F_REPLAYROLLOVER    V_REPLAYROLLOVER(1U)
1361 
1362 #define S_BADDLLP    14
1363 #define V_BADDLLP(x) ((x) << S_BADDLLP)
1364 #define F_BADDLLP    V_BADDLLP(1U)
1365 
1366 #define S_DLLPERR    13
1367 #define V_DLLPERR(x) ((x) << S_DLLPERR)
1368 #define F_DLLPERR    V_DLLPERR(1U)
1369 
1370 #define S_FLOWCTLPROTERR    12
1371 #define V_FLOWCTLPROTERR(x) ((x) << S_FLOWCTLPROTERR)
1372 #define F_FLOWCTLPROTERR    V_FLOWCTLPROTERR(1U)
1373 
1374 #define S_CPLTIMEOUT    11
1375 #define V_CPLTIMEOUT(x) ((x) << S_CPLTIMEOUT)
1376 #define F_CPLTIMEOUT    V_CPLTIMEOUT(1U)
1377 
1378 #define S_PHYRCVERR    10
1379 #define V_PHYRCVERR(x) ((x) << S_PHYRCVERR)
1380 #define F_PHYRCVERR    V_PHYRCVERR(1U)
1381 
1382 #define S_DISTLP    9
1383 #define V_DISTLP(x) ((x) << S_DISTLP)
1384 #define F_DISTLP    V_DISTLP(1U)
1385 
1386 #define S_BADECRC    8
1387 #define V_BADECRC(x) ((x) << S_BADECRC)
1388 #define F_BADECRC    V_BADECRC(1U)
1389 
1390 #define S_BADTLP    7
1391 #define V_BADTLP(x) ((x) << S_BADTLP)
1392 #define F_BADTLP    V_BADTLP(1U)
1393 
1394 #define S_MALTLP    6
1395 #define V_MALTLP(x) ((x) << S_MALTLP)
1396 #define F_MALTLP    V_MALTLP(1U)
1397 
1398 #define S_UNXCPL    5
1399 #define V_UNXCPL(x) ((x) << S_UNXCPL)
1400 #define F_UNXCPL    V_UNXCPL(1U)
1401 
1402 #define S_UNSREQ    4
1403 #define V_UNSREQ(x) ((x) << S_UNSREQ)
1404 #define F_UNSREQ    V_UNSREQ(1U)
1405 
1406 #define S_PSNREQ    3
1407 #define V_PSNREQ(x) ((x) << S_PSNREQ)
1408 #define F_PSNREQ    V_PSNREQ(1U)
1409 
1410 #define S_UNSCPL    2
1411 #define V_UNSCPL(x) ((x) << S_UNSCPL)
1412 #define F_UNSCPL    V_UNSCPL(1U)
1413 
1414 #define S_CPLABT    1
1415 #define V_CPLABT(x) ((x) << S_CPLABT)
1416 #define F_CPLABT    V_CPLABT(1U)
1417 
1418 #define S_PSNCPL    0
1419 #define V_PSNCPL(x) ((x) << S_PSNCPL)
1420 #define F_PSNCPL    V_PSNCPL(1U)
1421 
1422 #define A_PCIE_SERDES_CTRL 0xa8
1423 
1424 #define S_PMASEL    3
1425 #define V_PMASEL(x) ((x) << S_PMASEL)
1426 #define F_PMASEL    V_PMASEL(1U)
1427 
1428 #define S_LANE    0
1429 #define M_LANE    0x7
1430 #define V_LANE(x) ((x) << S_LANE)
1431 #define G_LANE(x) (((x) >> S_LANE) & M_LANE)
1432 
1433 #define A_PCIE_PIPE_CTRL 0xa8
1434 
1435 #define S_RECDETUSEC    19
1436 #define M_RECDETUSEC    0x7
1437 #define V_RECDETUSEC(x) ((x) << S_RECDETUSEC)
1438 #define G_RECDETUSEC(x) (((x) >> S_RECDETUSEC) & M_RECDETUSEC)
1439 
1440 #define S_PLLLCKCYC    6
1441 #define M_PLLLCKCYC    0x1fff
1442 #define V_PLLLCKCYC(x) ((x) << S_PLLLCKCYC)
1443 #define G_PLLLCKCYC(x) (((x) >> S_PLLLCKCYC) & M_PLLLCKCYC)
1444 
1445 #define S_ELECIDLEDETCYC    3
1446 #define M_ELECIDLEDETCYC    0x7
1447 #define V_ELECIDLEDETCYC(x) ((x) << S_ELECIDLEDETCYC)
1448 #define G_ELECIDLEDETCYC(x) (((x) >> S_ELECIDLEDETCYC) & M_ELECIDLEDETCYC)
1449 
1450 #define S_USECDRLOS    2
1451 #define V_USECDRLOS(x) ((x) << S_USECDRLOS)
1452 #define F_USECDRLOS    V_USECDRLOS(1U)
1453 
1454 #define S_PCLKREQINP1    1
1455 #define V_PCLKREQINP1(x) ((x) << S_PCLKREQINP1)
1456 #define F_PCLKREQINP1    V_PCLKREQINP1(1U)
1457 
1458 #define S_PCLKOFFINP1    0
1459 #define V_PCLKOFFINP1(x) ((x) << S_PCLKOFFINP1)
1460 #define F_PCLKOFFINP1    V_PCLKOFFINP1(1U)
1461 
1462 #define A_PCIE_SERDES_QUAD_CTRL0 0xac
1463 
1464 #define S_TESTSIG    10
1465 #define M_TESTSIG    0x7ffff
1466 #define V_TESTSIG(x) ((x) << S_TESTSIG)
1467 #define G_TESTSIG(x) (((x) >> S_TESTSIG) & M_TESTSIG)
1468 
1469 #define S_OFFSET    2
1470 #define M_OFFSET    0xff
1471 #define V_OFFSET(x) ((x) << S_OFFSET)
1472 #define G_OFFSET(x) (((x) >> S_OFFSET) & M_OFFSET)
1473 
1474 #define S_OFFSETEN    1
1475 #define V_OFFSETEN(x) ((x) << S_OFFSETEN)
1476 #define F_OFFSETEN    V_OFFSETEN(1U)
1477 
1478 #define S_IDDQB    0
1479 #define V_IDDQB(x) ((x) << S_IDDQB)
1480 #define F_IDDQB    V_IDDQB(1U)
1481 
1482 #define S_MANMODE    31
1483 #define V_MANMODE(x) ((x) << S_MANMODE)
1484 #define F_MANMODE    V_MANMODE(1U)
1485 
1486 #define S_MANLPBKEN    29
1487 #define M_MANLPBKEN    0x3
1488 #define V_MANLPBKEN(x) ((x) << S_MANLPBKEN)
1489 #define G_MANLPBKEN(x) (((x) >> S_MANLPBKEN) & M_MANLPBKEN)
1490 
1491 #define S_MANTXRECDETEN    28
1492 #define V_MANTXRECDETEN(x) ((x) << S_MANTXRECDETEN)
1493 #define F_MANTXRECDETEN    V_MANTXRECDETEN(1U)
1494 
1495 #define S_MANTXBEACON    27
1496 #define V_MANTXBEACON(x) ((x) << S_MANTXBEACON)
1497 #define F_MANTXBEACON    V_MANTXBEACON(1U)
1498 
1499 #define S_MANTXEI    26
1500 #define V_MANTXEI(x) ((x) << S_MANTXEI)
1501 #define F_MANTXEI    V_MANTXEI(1U)
1502 
1503 #define S_MANRXPOLARITY    25
1504 #define V_MANRXPOLARITY(x) ((x) << S_MANRXPOLARITY)
1505 #define F_MANRXPOLARITY    V_MANRXPOLARITY(1U)
1506 
1507 #define S_MANTXRST    24
1508 #define V_MANTXRST(x) ((x) << S_MANTXRST)
1509 #define F_MANTXRST    V_MANTXRST(1U)
1510 
1511 #define S_MANRXRST    23
1512 #define V_MANRXRST(x) ((x) << S_MANRXRST)
1513 #define F_MANRXRST    V_MANRXRST(1U)
1514 
1515 #define S_MANTXEN    22
1516 #define V_MANTXEN(x) ((x) << S_MANTXEN)
1517 #define F_MANTXEN    V_MANTXEN(1U)
1518 
1519 #define S_MANRXEN    21
1520 #define V_MANRXEN(x) ((x) << S_MANRXEN)
1521 #define F_MANRXEN    V_MANRXEN(1U)
1522 
1523 #define S_MANEN    20
1524 #define V_MANEN(x) ((x) << S_MANEN)
1525 #define F_MANEN    V_MANEN(1U)
1526 
1527 #define S_PCIE_CMURANGE    17
1528 #define M_PCIE_CMURANGE    0x7
1529 #define V_PCIE_CMURANGE(x) ((x) << S_PCIE_CMURANGE)
1530 #define G_PCIE_CMURANGE(x) (((x) >> S_PCIE_CMURANGE) & M_PCIE_CMURANGE)
1531 
1532 #define S_PCIE_BGENB    16
1533 #define V_PCIE_BGENB(x) ((x) << S_PCIE_BGENB)
1534 #define F_PCIE_BGENB    V_PCIE_BGENB(1U)
1535 
1536 #define S_PCIE_ENSKPDROP    15
1537 #define V_PCIE_ENSKPDROP(x) ((x) << S_PCIE_ENSKPDROP)
1538 #define F_PCIE_ENSKPDROP    V_PCIE_ENSKPDROP(1U)
1539 
1540 #define S_PCIE_ENCOMMA    14
1541 #define V_PCIE_ENCOMMA(x) ((x) << S_PCIE_ENCOMMA)
1542 #define F_PCIE_ENCOMMA    V_PCIE_ENCOMMA(1U)
1543 
1544 #define S_PCIE_EN8B10B    13
1545 #define V_PCIE_EN8B10B(x) ((x) << S_PCIE_EN8B10B)
1546 #define F_PCIE_EN8B10B    V_PCIE_EN8B10B(1U)
1547 
1548 #define S_PCIE_ENELBUF    12
1549 #define V_PCIE_ENELBUF(x) ((x) << S_PCIE_ENELBUF)
1550 #define F_PCIE_ENELBUF    V_PCIE_ENELBUF(1U)
1551 
1552 #define S_PCIE_GAIN    7
1553 #define M_PCIE_GAIN    0x1f
1554 #define V_PCIE_GAIN(x) ((x) << S_PCIE_GAIN)
1555 #define G_PCIE_GAIN(x) (((x) >> S_PCIE_GAIN) & M_PCIE_GAIN)
1556 
1557 #define S_PCIE_BANDGAP    3
1558 #define M_PCIE_BANDGAP    0xf
1559 #define V_PCIE_BANDGAP(x) ((x) << S_PCIE_BANDGAP)
1560 #define G_PCIE_BANDGAP(x) (((x) >> S_PCIE_BANDGAP) & M_PCIE_BANDGAP)
1561 
1562 #define S_RXCOMADJ    2
1563 #define V_RXCOMADJ(x) ((x) << S_RXCOMADJ)
1564 #define F_RXCOMADJ    V_RXCOMADJ(1U)
1565 
1566 #define S_PREEMPH    0
1567 #define M_PREEMPH    0x3
1568 #define V_PREEMPH(x) ((x) << S_PREEMPH)
1569 #define G_PREEMPH(x) (((x) >> S_PREEMPH) & M_PREEMPH)
1570 
1571 #define A_PCIE_SERDES_QUAD_CTRL1 0xb0
1572 
1573 #define S_FASTINIT    28
1574 #define V_FASTINIT(x) ((x) << S_FASTINIT)
1575 #define F_FASTINIT    V_FASTINIT(1U)
1576 
1577 #define S_CTCDISABLE    27
1578 #define V_CTCDISABLE(x) ((x) << S_CTCDISABLE)
1579 #define F_CTCDISABLE    V_CTCDISABLE(1U)
1580 
1581 #define S_MANRESETPLL    26
1582 #define V_MANRESETPLL(x) ((x) << S_MANRESETPLL)
1583 #define F_MANRESETPLL    V_MANRESETPLL(1U)
1584 
1585 #define S_MANL2PWRDN    25
1586 #define V_MANL2PWRDN(x) ((x) << S_MANL2PWRDN)
1587 #define F_MANL2PWRDN    V_MANL2PWRDN(1U)
1588 
1589 #define S_MANQUADEN    24
1590 #define V_MANQUADEN(x) ((x) << S_MANQUADEN)
1591 #define F_MANQUADEN    V_MANQUADEN(1U)
1592 
1593 #define S_RXEQCTL    22
1594 #define M_RXEQCTL    0x3
1595 #define V_RXEQCTL(x) ((x) << S_RXEQCTL)
1596 #define G_RXEQCTL(x) (((x) >> S_RXEQCTL) & M_RXEQCTL)
1597 
1598 #define S_HIVMODE    21
1599 #define V_HIVMODE(x) ((x) << S_HIVMODE)
1600 #define F_HIVMODE    V_HIVMODE(1U)
1601 
1602 #define S_REFSEL    19
1603 #define M_REFSEL    0x3
1604 #define V_REFSEL(x) ((x) << S_REFSEL)
1605 #define G_REFSEL(x) (((x) >> S_REFSEL) & M_REFSEL)
1606 
1607 #define S_RXTERMADJ    17
1608 #define M_RXTERMADJ    0x3
1609 #define V_RXTERMADJ(x) ((x) << S_RXTERMADJ)
1610 #define G_RXTERMADJ(x) (((x) >> S_RXTERMADJ) & M_RXTERMADJ)
1611 
1612 #define S_TXTERMADJ    15
1613 #define M_TXTERMADJ    0x3
1614 #define V_TXTERMADJ(x) ((x) << S_TXTERMADJ)
1615 #define G_TXTERMADJ(x) (((x) >> S_TXTERMADJ) & M_TXTERMADJ)
1616 
1617 #define S_DEQ    11
1618 #define M_DEQ    0xf
1619 #define V_DEQ(x) ((x) << S_DEQ)
1620 #define G_DEQ(x) (((x) >> S_DEQ) & M_DEQ)
1621 
1622 #define S_DTX    7
1623 #define M_DTX    0xf
1624 #define V_DTX(x) ((x) << S_DTX)
1625 #define G_DTX(x) (((x) >> S_DTX) & M_DTX)
1626 
1627 #define S_LODRV    6
1628 #define V_LODRV(x) ((x) << S_LODRV)
1629 #define F_LODRV    V_LODRV(1U)
1630 
1631 #define S_HIDRV    5
1632 #define V_HIDRV(x) ((x) << S_HIDRV)
1633 #define F_HIDRV    V_HIDRV(1U)
1634 
1635 #define S_INTPARRESET    4
1636 #define V_INTPARRESET(x) ((x) << S_INTPARRESET)
1637 #define F_INTPARRESET    V_INTPARRESET(1U)
1638 
1639 #define S_INTPARLPBK    3
1640 #define V_INTPARLPBK(x) ((x) << S_INTPARLPBK)
1641 #define F_INTPARLPBK    V_INTPARLPBK(1U)
1642 
1643 #define S_INTSERLPBKWDRV    2
1644 #define V_INTSERLPBKWDRV(x) ((x) << S_INTSERLPBKWDRV)
1645 #define F_INTSERLPBKWDRV    V_INTSERLPBKWDRV(1U)
1646 
1647 #define S_PW    1
1648 #define V_PW(x) ((x) << S_PW)
1649 #define F_PW    V_PW(1U)
1650 
1651 #define S_PCLKDETECT    0
1652 #define V_PCLKDETECT(x) ((x) << S_PCLKDETECT)
1653 #define F_PCLKDETECT    V_PCLKDETECT(1U)
1654 
1655 #define A_PCIE_SERDES_STATUS0 0xb0
1656 
1657 #define S_RXERRLANE7    21
1658 #define M_RXERRLANE7    0x7
1659 #define V_RXERRLANE7(x) ((x) << S_RXERRLANE7)
1660 #define G_RXERRLANE7(x) (((x) >> S_RXERRLANE7) & M_RXERRLANE7)
1661 
1662 #define S_RXERRLANE6    18
1663 #define M_RXERRLANE6    0x7
1664 #define V_RXERRLANE6(x) ((x) << S_RXERRLANE6)
1665 #define G_RXERRLANE6(x) (((x) >> S_RXERRLANE6) & M_RXERRLANE6)
1666 
1667 #define S_RXERRLANE5    15
1668 #define M_RXERRLANE5    0x7
1669 #define V_RXERRLANE5(x) ((x) << S_RXERRLANE5)
1670 #define G_RXERRLANE5(x) (((x) >> S_RXERRLANE5) & M_RXERRLANE5)
1671 
1672 #define S_RXERRLANE4    12
1673 #define M_RXERRLANE4    0x7
1674 #define V_RXERRLANE4(x) ((x) << S_RXERRLANE4)
1675 #define G_RXERRLANE4(x) (((x) >> S_RXERRLANE4) & M_RXERRLANE4)
1676 
1677 #define S_PCIE_RXERRLANE3    9
1678 #define M_PCIE_RXERRLANE3    0x7
1679 #define V_PCIE_RXERRLANE3(x) ((x) << S_PCIE_RXERRLANE3)
1680 #define G_PCIE_RXERRLANE3(x) (((x) >> S_PCIE_RXERRLANE3) & M_PCIE_RXERRLANE3)
1681 
1682 #define S_PCIE_RXERRLANE2    6
1683 #define M_PCIE_RXERRLANE2    0x7
1684 #define V_PCIE_RXERRLANE2(x) ((x) << S_PCIE_RXERRLANE2)
1685 #define G_PCIE_RXERRLANE2(x) (((x) >> S_PCIE_RXERRLANE2) & M_PCIE_RXERRLANE2)
1686 
1687 #define S_PCIE_RXERRLANE1    3
1688 #define M_PCIE_RXERRLANE1    0x7
1689 #define V_PCIE_RXERRLANE1(x) ((x) << S_PCIE_RXERRLANE1)
1690 #define G_PCIE_RXERRLANE1(x) (((x) >> S_PCIE_RXERRLANE1) & M_PCIE_RXERRLANE1)
1691 
1692 #define S_PCIE_RXERRLANE0    0
1693 #define M_PCIE_RXERRLANE0    0x7
1694 #define V_PCIE_RXERRLANE0(x) ((x) << S_PCIE_RXERRLANE0)
1695 #define G_PCIE_RXERRLANE0(x) (((x) >> S_PCIE_RXERRLANE0) & M_PCIE_RXERRLANE0)
1696 
1697 #define A_PCIE_SERDES_LANE_CTRL 0xb4
1698 
1699 #define S_EXTBISTCHKERRCLR    22
1700 #define V_EXTBISTCHKERRCLR(x) ((x) << S_EXTBISTCHKERRCLR)
1701 #define F_EXTBISTCHKERRCLR    V_EXTBISTCHKERRCLR(1U)
1702 
1703 #define S_EXTBISTCHKEN    21
1704 #define V_EXTBISTCHKEN(x) ((x) << S_EXTBISTCHKEN)
1705 #define F_EXTBISTCHKEN    V_EXTBISTCHKEN(1U)
1706 
1707 #define S_EXTBISTGENEN    20
1708 #define V_EXTBISTGENEN(x) ((x) << S_EXTBISTGENEN)
1709 #define F_EXTBISTGENEN    V_EXTBISTGENEN(1U)
1710 
1711 #define S_EXTBISTPAT    17
1712 #define M_EXTBISTPAT    0x7
1713 #define V_EXTBISTPAT(x) ((x) << S_EXTBISTPAT)
1714 #define G_EXTBISTPAT(x) (((x) >> S_EXTBISTPAT) & M_EXTBISTPAT)
1715 
1716 #define S_EXTPARRESET    16
1717 #define V_EXTPARRESET(x) ((x) << S_EXTPARRESET)
1718 #define F_EXTPARRESET    V_EXTPARRESET(1U)
1719 
1720 #define S_EXTPARLPBK    15
1721 #define V_EXTPARLPBK(x) ((x) << S_EXTPARLPBK)
1722 #define F_EXTPARLPBK    V_EXTPARLPBK(1U)
1723 
1724 #define S_MANRXTERMEN    14
1725 #define V_MANRXTERMEN(x) ((x) << S_MANRXTERMEN)
1726 #define F_MANRXTERMEN    V_MANRXTERMEN(1U)
1727 
1728 #define S_MANBEACONTXEN    13
1729 #define V_MANBEACONTXEN(x) ((x) << S_MANBEACONTXEN)
1730 #define F_MANBEACONTXEN    V_MANBEACONTXEN(1U)
1731 
1732 #define S_MANRXDETECTEN    12
1733 #define V_MANRXDETECTEN(x) ((x) << S_MANRXDETECTEN)
1734 #define F_MANRXDETECTEN    V_MANRXDETECTEN(1U)
1735 
1736 #define S_MANTXIDLEEN    11
1737 #define V_MANTXIDLEEN(x) ((x) << S_MANTXIDLEEN)
1738 #define F_MANTXIDLEEN    V_MANTXIDLEEN(1U)
1739 
1740 #define S_MANRXIDLEEN    10
1741 #define V_MANRXIDLEEN(x) ((x) << S_MANRXIDLEEN)
1742 #define F_MANRXIDLEEN    V_MANRXIDLEEN(1U)
1743 
1744 #define S_MANL1PWRDN    9
1745 #define V_MANL1PWRDN(x) ((x) << S_MANL1PWRDN)
1746 #define F_MANL1PWRDN    V_MANL1PWRDN(1U)
1747 
1748 #define S_MANRESET    8
1749 #define V_MANRESET(x) ((x) << S_MANRESET)
1750 #define F_MANRESET    V_MANRESET(1U)
1751 
1752 #define S_MANFMOFFSET    3
1753 #define M_MANFMOFFSET    0x1f
1754 #define V_MANFMOFFSET(x) ((x) << S_MANFMOFFSET)
1755 #define G_MANFMOFFSET(x) (((x) >> S_MANFMOFFSET) & M_MANFMOFFSET)
1756 
1757 #define S_MANFMOFFSETEN    2
1758 #define V_MANFMOFFSETEN(x) ((x) << S_MANFMOFFSETEN)
1759 #define F_MANFMOFFSETEN    V_MANFMOFFSETEN(1U)
1760 
1761 #define S_MANLANEEN    1
1762 #define V_MANLANEEN(x) ((x) << S_MANLANEEN)
1763 #define F_MANLANEEN    V_MANLANEEN(1U)
1764 
1765 #define S_INTSERLPBK    0
1766 #define V_INTSERLPBK(x) ((x) << S_INTSERLPBK)
1767 #define F_INTSERLPBK    V_INTSERLPBK(1U)
1768 
1769 #define A_PCIE_SERDES_STATUS1 0xb4
1770 
1771 #define S_CMULOCK    31
1772 #define V_CMULOCK(x) ((x) << S_CMULOCK)
1773 #define F_CMULOCK    V_CMULOCK(1U)
1774 
1775 #define S_RXKLOCKLANE7    23
1776 #define V_RXKLOCKLANE7(x) ((x) << S_RXKLOCKLANE7)
1777 #define F_RXKLOCKLANE7    V_RXKLOCKLANE7(1U)
1778 
1779 #define S_RXKLOCKLANE6    22
1780 #define V_RXKLOCKLANE6(x) ((x) << S_RXKLOCKLANE6)
1781 #define F_RXKLOCKLANE6    V_RXKLOCKLANE6(1U)
1782 
1783 #define S_RXKLOCKLANE5    21
1784 #define V_RXKLOCKLANE5(x) ((x) << S_RXKLOCKLANE5)
1785 #define F_RXKLOCKLANE5    V_RXKLOCKLANE5(1U)
1786 
1787 #define S_RXKLOCKLANE4    20
1788 #define V_RXKLOCKLANE4(x) ((x) << S_RXKLOCKLANE4)
1789 #define F_RXKLOCKLANE4    V_RXKLOCKLANE4(1U)
1790 
1791 #define S_PCIE_RXKLOCKLANE3    19
1792 #define V_PCIE_RXKLOCKLANE3(x) ((x) << S_PCIE_RXKLOCKLANE3)
1793 #define F_PCIE_RXKLOCKLANE3    V_PCIE_RXKLOCKLANE3(1U)
1794 
1795 #define S_PCIE_RXKLOCKLANE2    18
1796 #define V_PCIE_RXKLOCKLANE2(x) ((x) << S_PCIE_RXKLOCKLANE2)
1797 #define F_PCIE_RXKLOCKLANE2    V_PCIE_RXKLOCKLANE2(1U)
1798 
1799 #define S_PCIE_RXKLOCKLANE1    17
1800 #define V_PCIE_RXKLOCKLANE1(x) ((x) << S_PCIE_RXKLOCKLANE1)
1801 #define F_PCIE_RXKLOCKLANE1    V_PCIE_RXKLOCKLANE1(1U)
1802 
1803 #define S_PCIE_RXKLOCKLANE0    16
1804 #define V_PCIE_RXKLOCKLANE0(x) ((x) << S_PCIE_RXKLOCKLANE0)
1805 #define F_PCIE_RXKLOCKLANE0    V_PCIE_RXKLOCKLANE0(1U)
1806 
1807 #define S_RXUFLOWLANE7    15
1808 #define V_RXUFLOWLANE7(x) ((x) << S_RXUFLOWLANE7)
1809 #define F_RXUFLOWLANE7    V_RXUFLOWLANE7(1U)
1810 
1811 #define S_RXUFLOWLANE6    14
1812 #define V_RXUFLOWLANE6(x) ((x) << S_RXUFLOWLANE6)
1813 #define F_RXUFLOWLANE6    V_RXUFLOWLANE6(1U)
1814 
1815 #define S_RXUFLOWLANE5    13
1816 #define V_RXUFLOWLANE5(x) ((x) << S_RXUFLOWLANE5)
1817 #define F_RXUFLOWLANE5    V_RXUFLOWLANE5(1U)
1818 
1819 #define S_RXUFLOWLANE4    12
1820 #define V_RXUFLOWLANE4(x) ((x) << S_RXUFLOWLANE4)
1821 #define F_RXUFLOWLANE4    V_RXUFLOWLANE4(1U)
1822 
1823 #define S_PCIE_RXUFLOWLANE3    11
1824 #define V_PCIE_RXUFLOWLANE3(x) ((x) << S_PCIE_RXUFLOWLANE3)
1825 #define F_PCIE_RXUFLOWLANE3    V_PCIE_RXUFLOWLANE3(1U)
1826 
1827 #define S_PCIE_RXUFLOWLANE2    10
1828 #define V_PCIE_RXUFLOWLANE2(x) ((x) << S_PCIE_RXUFLOWLANE2)
1829 #define F_PCIE_RXUFLOWLANE2    V_PCIE_RXUFLOWLANE2(1U)
1830 
1831 #define S_PCIE_RXUFLOWLANE1    9
1832 #define V_PCIE_RXUFLOWLANE1(x) ((x) << S_PCIE_RXUFLOWLANE1)
1833 #define F_PCIE_RXUFLOWLANE1    V_PCIE_RXUFLOWLANE1(1U)
1834 
1835 #define S_PCIE_RXUFLOWLANE0    8
1836 #define V_PCIE_RXUFLOWLANE0(x) ((x) << S_PCIE_RXUFLOWLANE0)
1837 #define F_PCIE_RXUFLOWLANE0    V_PCIE_RXUFLOWLANE0(1U)
1838 
1839 #define S_RXOFLOWLANE7    7
1840 #define V_RXOFLOWLANE7(x) ((x) << S_RXOFLOWLANE7)
1841 #define F_RXOFLOWLANE7    V_RXOFLOWLANE7(1U)
1842 
1843 #define S_RXOFLOWLANE6    6
1844 #define V_RXOFLOWLANE6(x) ((x) << S_RXOFLOWLANE6)
1845 #define F_RXOFLOWLANE6    V_RXOFLOWLANE6(1U)
1846 
1847 #define S_RXOFLOWLANE5    5
1848 #define V_RXOFLOWLANE5(x) ((x) << S_RXOFLOWLANE5)
1849 #define F_RXOFLOWLANE5    V_RXOFLOWLANE5(1U)
1850 
1851 #define S_RXOFLOWLANE4    4
1852 #define V_RXOFLOWLANE4(x) ((x) << S_RXOFLOWLANE4)
1853 #define F_RXOFLOWLANE4    V_RXOFLOWLANE4(1U)
1854 
1855 #define S_PCIE_RXOFLOWLANE3    3
1856 #define V_PCIE_RXOFLOWLANE3(x) ((x) << S_PCIE_RXOFLOWLANE3)
1857 #define F_PCIE_RXOFLOWLANE3    V_PCIE_RXOFLOWLANE3(1U)
1858 
1859 #define S_PCIE_RXOFLOWLANE2    2
1860 #define V_PCIE_RXOFLOWLANE2(x) ((x) << S_PCIE_RXOFLOWLANE2)
1861 #define F_PCIE_RXOFLOWLANE2    V_PCIE_RXOFLOWLANE2(1U)
1862 
1863 #define S_PCIE_RXOFLOWLANE1    1
1864 #define V_PCIE_RXOFLOWLANE1(x) ((x) << S_PCIE_RXOFLOWLANE1)
1865 #define F_PCIE_RXOFLOWLANE1    V_PCIE_RXOFLOWLANE1(1U)
1866 
1867 #define S_PCIE_RXOFLOWLANE0    0
1868 #define V_PCIE_RXOFLOWLANE0(x) ((x) << S_PCIE_RXOFLOWLANE0)
1869 #define F_PCIE_RXOFLOWLANE0    V_PCIE_RXOFLOWLANE0(1U)
1870 
1871 #define A_PCIE_SERDES_LANE_STAT 0xb8
1872 
1873 #define S_EXTBISTCHKERRCNT    8
1874 #define M_EXTBISTCHKERRCNT    0xffffff
1875 #define V_EXTBISTCHKERRCNT(x) ((x) << S_EXTBISTCHKERRCNT)
1876 #define G_EXTBISTCHKERRCNT(x) (((x) >> S_EXTBISTCHKERRCNT) & M_EXTBISTCHKERRCNT)
1877 
1878 #define S_EXTBISTCHKFMD    7
1879 #define V_EXTBISTCHKFMD(x) ((x) << S_EXTBISTCHKFMD)
1880 #define F_EXTBISTCHKFMD    V_EXTBISTCHKFMD(1U)
1881 
1882 #define S_BEACONDETECTCHG    6
1883 #define V_BEACONDETECTCHG(x) ((x) << S_BEACONDETECTCHG)
1884 #define F_BEACONDETECTCHG    V_BEACONDETECTCHG(1U)
1885 
1886 #define S_RXDETECTCHG    5
1887 #define V_RXDETECTCHG(x) ((x) << S_RXDETECTCHG)
1888 #define F_RXDETECTCHG    V_RXDETECTCHG(1U)
1889 
1890 #define S_TXIDLEDETECTCHG    4
1891 #define V_TXIDLEDETECTCHG(x) ((x) << S_TXIDLEDETECTCHG)
1892 #define F_TXIDLEDETECTCHG    V_TXIDLEDETECTCHG(1U)
1893 
1894 #define S_BEACONDETECT    2
1895 #define V_BEACONDETECT(x) ((x) << S_BEACONDETECT)
1896 #define F_BEACONDETECT    V_BEACONDETECT(1U)
1897 
1898 #define S_RXDETECT    1
1899 #define V_RXDETECT(x) ((x) << S_RXDETECT)
1900 #define F_RXDETECT    V_RXDETECT(1U)
1901 
1902 #define S_TXIDLEDETECT    0
1903 #define V_TXIDLEDETECT(x) ((x) << S_TXIDLEDETECT)
1904 #define F_TXIDLEDETECT    V_TXIDLEDETECT(1U)
1905 
1906 #define A_PCIE_SERDES_STATUS2 0xb8
1907 
1908 #define S_TXRECDETLANE7    31
1909 #define V_TXRECDETLANE7(x) ((x) << S_TXRECDETLANE7)
1910 #define F_TXRECDETLANE7    V_TXRECDETLANE7(1U)
1911 
1912 #define S_TXRECDETLANE6    30
1913 #define V_TXRECDETLANE6(x) ((x) << S_TXRECDETLANE6)
1914 #define F_TXRECDETLANE6    V_TXRECDETLANE6(1U)
1915 
1916 #define S_TXRECDETLANE5    29
1917 #define V_TXRECDETLANE5(x) ((x) << S_TXRECDETLANE5)
1918 #define F_TXRECDETLANE5    V_TXRECDETLANE5(1U)
1919 
1920 #define S_TXRECDETLANE4    28
1921 #define V_TXRECDETLANE4(x) ((x) << S_TXRECDETLANE4)
1922 #define F_TXRECDETLANE4    V_TXRECDETLANE4(1U)
1923 
1924 #define S_TXRECDETLANE3    27
1925 #define V_TXRECDETLANE3(x) ((x) << S_TXRECDETLANE3)
1926 #define F_TXRECDETLANE3    V_TXRECDETLANE3(1U)
1927 
1928 #define S_TXRECDETLANE2    26
1929 #define V_TXRECDETLANE2(x) ((x) << S_TXRECDETLANE2)
1930 #define F_TXRECDETLANE2    V_TXRECDETLANE2(1U)
1931 
1932 #define S_TXRECDETLANE1    25
1933 #define V_TXRECDETLANE1(x) ((x) << S_TXRECDETLANE1)
1934 #define F_TXRECDETLANE1    V_TXRECDETLANE1(1U)
1935 
1936 #define S_TXRECDETLANE0    24
1937 #define V_TXRECDETLANE0(x) ((x) << S_TXRECDETLANE0)
1938 #define F_TXRECDETLANE0    V_TXRECDETLANE0(1U)
1939 
1940 #define S_RXEIDLANE7    23
1941 #define V_RXEIDLANE7(x) ((x) << S_RXEIDLANE7)
1942 #define F_RXEIDLANE7    V_RXEIDLANE7(1U)
1943 
1944 #define S_RXEIDLANE6    22
1945 #define V_RXEIDLANE6(x) ((x) << S_RXEIDLANE6)
1946 #define F_RXEIDLANE6    V_RXEIDLANE6(1U)
1947 
1948 #define S_RXEIDLANE5    21
1949 #define V_RXEIDLANE5(x) ((x) << S_RXEIDLANE5)
1950 #define F_RXEIDLANE5    V_RXEIDLANE5(1U)
1951 
1952 #define S_RXEIDLANE4    20
1953 #define V_RXEIDLANE4(x) ((x) << S_RXEIDLANE4)
1954 #define F_RXEIDLANE4    V_RXEIDLANE4(1U)
1955 
1956 #define S_RXEIDLANE3    19
1957 #define V_RXEIDLANE3(x) ((x) << S_RXEIDLANE3)
1958 #define F_RXEIDLANE3    V_RXEIDLANE3(1U)
1959 
1960 #define S_RXEIDLANE2    18
1961 #define V_RXEIDLANE2(x) ((x) << S_RXEIDLANE2)
1962 #define F_RXEIDLANE2    V_RXEIDLANE2(1U)
1963 
1964 #define S_RXEIDLANE1    17
1965 #define V_RXEIDLANE1(x) ((x) << S_RXEIDLANE1)
1966 #define F_RXEIDLANE1    V_RXEIDLANE1(1U)
1967 
1968 #define S_RXEIDLANE0    16
1969 #define V_RXEIDLANE0(x) ((x) << S_RXEIDLANE0)
1970 #define F_RXEIDLANE0    V_RXEIDLANE0(1U)
1971 
1972 #define S_RXREMSKIPLANE7    15
1973 #define V_RXREMSKIPLANE7(x) ((x) << S_RXREMSKIPLANE7)
1974 #define F_RXREMSKIPLANE7    V_RXREMSKIPLANE7(1U)
1975 
1976 #define S_RXREMSKIPLANE6    14
1977 #define V_RXREMSKIPLANE6(x) ((x) << S_RXREMSKIPLANE6)
1978 #define F_RXREMSKIPLANE6    V_RXREMSKIPLANE6(1U)
1979 
1980 #define S_RXREMSKIPLANE5    13
1981 #define V_RXREMSKIPLANE5(x) ((x) << S_RXREMSKIPLANE5)
1982 #define F_RXREMSKIPLANE5    V_RXREMSKIPLANE5(1U)
1983 
1984 #define S_RXREMSKIPLANE4    12
1985 #define V_RXREMSKIPLANE4(x) ((x) << S_RXREMSKIPLANE4)
1986 #define F_RXREMSKIPLANE4    V_RXREMSKIPLANE4(1U)
1987 
1988 #define S_PCIE_RXREMSKIPLANE3    11
1989 #define V_PCIE_RXREMSKIPLANE3(x) ((x) << S_PCIE_RXREMSKIPLANE3)
1990 #define F_PCIE_RXREMSKIPLANE3    V_PCIE_RXREMSKIPLANE3(1U)
1991 
1992 #define S_PCIE_RXREMSKIPLANE2    10
1993 #define V_PCIE_RXREMSKIPLANE2(x) ((x) << S_PCIE_RXREMSKIPLANE2)
1994 #define F_PCIE_RXREMSKIPLANE2    V_PCIE_RXREMSKIPLANE2(1U)
1995 
1996 #define S_PCIE_RXREMSKIPLANE1    9
1997 #define V_PCIE_RXREMSKIPLANE1(x) ((x) << S_PCIE_RXREMSKIPLANE1)
1998 #define F_PCIE_RXREMSKIPLANE1    V_PCIE_RXREMSKIPLANE1(1U)
1999 
2000 #define S_PCIE_RXREMSKIPLANE0    8
2001 #define V_PCIE_RXREMSKIPLANE0(x) ((x) << S_PCIE_RXREMSKIPLANE0)
2002 #define F_PCIE_RXREMSKIPLANE0    V_PCIE_RXREMSKIPLANE0(1U)
2003 
2004 #define S_RXADDSKIPLANE7    7
2005 #define V_RXADDSKIPLANE7(x) ((x) << S_RXADDSKIPLANE7)
2006 #define F_RXADDSKIPLANE7    V_RXADDSKIPLANE7(1U)
2007 
2008 #define S_RXADDSKIPLANE6    6
2009 #define V_RXADDSKIPLANE6(x) ((x) << S_RXADDSKIPLANE6)
2010 #define F_RXADDSKIPLANE6    V_RXADDSKIPLANE6(1U)
2011 
2012 #define S_RXADDSKIPLANE5    5
2013 #define V_RXADDSKIPLANE5(x) ((x) << S_RXADDSKIPLANE5)
2014 #define F_RXADDSKIPLANE5    V_RXADDSKIPLANE5(1U)
2015 
2016 #define S_RXADDSKIPLANE4    4
2017 #define V_RXADDSKIPLANE4(x) ((x) << S_RXADDSKIPLANE4)
2018 #define F_RXADDSKIPLANE4    V_RXADDSKIPLANE4(1U)
2019 
2020 #define S_PCIE_RXADDSKIPLANE3    3
2021 #define V_PCIE_RXADDSKIPLANE3(x) ((x) << S_PCIE_RXADDSKIPLANE3)
2022 #define F_PCIE_RXADDSKIPLANE3    V_PCIE_RXADDSKIPLANE3(1U)
2023 
2024 #define S_PCIE_RXADDSKIPLANE2    2
2025 #define V_PCIE_RXADDSKIPLANE2(x) ((x) << S_PCIE_RXADDSKIPLANE2)
2026 #define F_PCIE_RXADDSKIPLANE2    V_PCIE_RXADDSKIPLANE2(1U)
2027 
2028 #define S_PCIE_RXADDSKIPLANE1    1
2029 #define V_PCIE_RXADDSKIPLANE1(x) ((x) << S_PCIE_RXADDSKIPLANE1)
2030 #define F_PCIE_RXADDSKIPLANE1    V_PCIE_RXADDSKIPLANE1(1U)
2031 
2032 #define S_PCIE_RXADDSKIPLANE0    0
2033 #define V_PCIE_RXADDSKIPLANE0(x) ((x) << S_PCIE_RXADDSKIPLANE0)
2034 #define F_PCIE_RXADDSKIPLANE0    V_PCIE_RXADDSKIPLANE0(1U)
2035 
2036 #define A_PCIE_PEX_WMARK 0xbc
2037 
2038 #define S_P_WMARK    18
2039 #define M_P_WMARK    0x7ff
2040 #define V_P_WMARK(x) ((x) << S_P_WMARK)
2041 #define G_P_WMARK(x) (((x) >> S_P_WMARK) & M_P_WMARK)
2042 
2043 #define S_NP_WMARK    11
2044 #define M_NP_WMARK    0x7f
2045 #define V_NP_WMARK(x) ((x) << S_NP_WMARK)
2046 #define G_NP_WMARK(x) (((x) >> S_NP_WMARK) & M_NP_WMARK)
2047 
2048 #define S_CPL_WMARK    0
2049 #define M_CPL_WMARK    0x7ff
2050 #define V_CPL_WMARK(x) ((x) << S_CPL_WMARK)
2051 #define G_CPL_WMARK(x) (((x) >> S_CPL_WMARK) & M_CPL_WMARK)
2052 
2053 #define A_PCIE_SERDES_BIST 0xbc
2054 
2055 #define S_PCIE_BISTDONE    24
2056 #define M_PCIE_BISTDONE    0xff
2057 #define V_PCIE_BISTDONE(x) ((x) << S_PCIE_BISTDONE)
2058 #define G_PCIE_BISTDONE(x) (((x) >> S_PCIE_BISTDONE) & M_PCIE_BISTDONE)
2059 
2060 #define S_PCIE_BISTCYCLETHRESH    3
2061 #define M_PCIE_BISTCYCLETHRESH    0xffff
2062 #define V_PCIE_BISTCYCLETHRESH(x) ((x) << S_PCIE_BISTCYCLETHRESH)
2063 #define G_PCIE_BISTCYCLETHRESH(x) (((x) >> S_PCIE_BISTCYCLETHRESH) & M_PCIE_BISTCYCLETHRESH)
2064 
2065 #define S_BISTMODE    0
2066 #define M_BISTMODE    0x7
2067 #define V_BISTMODE(x) ((x) << S_BISTMODE)
2068 #define G_BISTMODE(x) (((x) >> S_BISTMODE) & M_BISTMODE)
2069 
2070 /* registers for module T3DBG */
2071 #define T3DBG_BASE_ADDR 0xc0
2072 
2073 #define A_T3DBG_DBG0_CFG 0xc0
2074 
2075 #define S_REGSELECT    9
2076 #define M_REGSELECT    0xff
2077 #define V_REGSELECT(x) ((x) << S_REGSELECT)
2078 #define G_REGSELECT(x) (((x) >> S_REGSELECT) & M_REGSELECT)
2079 
2080 #define S_MODULESELECT    4
2081 #define M_MODULESELECT    0x1f
2082 #define V_MODULESELECT(x) ((x) << S_MODULESELECT)
2083 #define G_MODULESELECT(x) (((x) >> S_MODULESELECT) & M_MODULESELECT)
2084 
2085 #define S_CLKSELECT    0
2086 #define M_CLKSELECT    0xf
2087 #define V_CLKSELECT(x) ((x) << S_CLKSELECT)
2088 #define G_CLKSELECT(x) (((x) >> S_CLKSELECT) & M_CLKSELECT)
2089 
2090 #define A_T3DBG_DBG0_EN 0xc4
2091 
2092 #define S_SDRBYTE0    8
2093 #define V_SDRBYTE0(x) ((x) << S_SDRBYTE0)
2094 #define F_SDRBYTE0    V_SDRBYTE0(1U)
2095 
2096 #define S_DDREN    4
2097 #define V_DDREN(x) ((x) << S_DDREN)
2098 #define F_DDREN    V_DDREN(1U)
2099 
2100 #define S_PORTEN    0
2101 #define V_PORTEN(x) ((x) << S_PORTEN)
2102 #define F_PORTEN    V_PORTEN(1U)
2103 
2104 #define A_T3DBG_DBG1_CFG 0xc8
2105 #define A_T3DBG_DBG1_EN 0xcc
2106 #define A_T3DBG_GPIO_EN 0xd0
2107 
2108 #define S_GPIO11_OEN    27
2109 #define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN)
2110 #define F_GPIO11_OEN    V_GPIO11_OEN(1U)
2111 
2112 #define S_GPIO10_OEN    26
2113 #define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN)
2114 #define F_GPIO10_OEN    V_GPIO10_OEN(1U)
2115 
2116 #define S_GPIO9_OEN    25
2117 #define V_GPIO9_OEN(x) ((x) << S_GPIO9_OEN)
2118 #define F_GPIO9_OEN    V_GPIO9_OEN(1U)
2119 
2120 #define S_GPIO8_OEN    24
2121 #define V_GPIO8_OEN(x) ((x) << S_GPIO8_OEN)
2122 #define F_GPIO8_OEN    V_GPIO8_OEN(1U)
2123 
2124 #define S_GPIO7_OEN    23
2125 #define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN)
2126 #define F_GPIO7_OEN    V_GPIO7_OEN(1U)
2127 
2128 #define S_GPIO6_OEN    22
2129 #define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN)
2130 #define F_GPIO6_OEN    V_GPIO6_OEN(1U)
2131 
2132 #define S_GPIO5_OEN    21
2133 #define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN)
2134 #define F_GPIO5_OEN    V_GPIO5_OEN(1U)
2135 
2136 #define S_GPIO4_OEN    20
2137 #define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN)
2138 #define F_GPIO4_OEN    V_GPIO4_OEN(1U)
2139 
2140 #define S_GPIO3_OEN    19
2141 #define V_GPIO3_OEN(x) ((x) << S_GPIO3_OEN)
2142 #define F_GPIO3_OEN    V_GPIO3_OEN(1U)
2143 
2144 #define S_GPIO2_OEN    18
2145 #define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN)
2146 #define F_GPIO2_OEN    V_GPIO2_OEN(1U)
2147 
2148 #define S_GPIO1_OEN    17
2149 #define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN)
2150 #define F_GPIO1_OEN    V_GPIO1_OEN(1U)
2151 
2152 #define S_GPIO0_OEN    16
2153 #define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN)
2154 #define F_GPIO0_OEN    V_GPIO0_OEN(1U)
2155 
2156 #define S_GPIO11_OUT_VAL    11
2157 #define V_GPIO11_OUT_VAL(x) ((x) << S_GPIO11_OUT_VAL)
2158 #define F_GPIO11_OUT_VAL    V_GPIO11_OUT_VAL(1U)
2159 
2160 #define S_GPIO10_OUT_VAL    10
2161 #define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL)
2162 #define F_GPIO10_OUT_VAL    V_GPIO10_OUT_VAL(1U)
2163 
2164 #define S_GPIO9_OUT_VAL    9
2165 #define V_GPIO9_OUT_VAL(x) ((x) << S_GPIO9_OUT_VAL)
2166 #define F_GPIO9_OUT_VAL    V_GPIO9_OUT_VAL(1U)
2167 
2168 #define S_GPIO8_OUT_VAL    8
2169 #define V_GPIO8_OUT_VAL(x) ((x) << S_GPIO8_OUT_VAL)
2170 #define F_GPIO8_OUT_VAL    V_GPIO8_OUT_VAL(1U)
2171 
2172 #define S_GPIO7_OUT_VAL    7
2173 #define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL)
2174 #define F_GPIO7_OUT_VAL    V_GPIO7_OUT_VAL(1U)
2175 
2176 #define S_GPIO6_OUT_VAL    6
2177 #define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL)
2178 #define F_GPIO6_OUT_VAL    V_GPIO6_OUT_VAL(1U)
2179 
2180 #define S_GPIO5_OUT_VAL    5
2181 #define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL)
2182 #define F_GPIO5_OUT_VAL    V_GPIO5_OUT_VAL(1U)
2183 
2184 #define S_GPIO4_OUT_VAL    4
2185 #define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL)
2186 #define F_GPIO4_OUT_VAL    V_GPIO4_OUT_VAL(1U)
2187 
2188 #define S_GPIO3_OUT_VAL    3
2189 #define V_GPIO3_OUT_VAL(x) ((x) << S_GPIO3_OUT_VAL)
2190 #define F_GPIO3_OUT_VAL    V_GPIO3_OUT_VAL(1U)
2191 
2192 #define S_GPIO2_OUT_VAL    2
2193 #define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL)
2194 #define F_GPIO2_OUT_VAL    V_GPIO2_OUT_VAL(1U)
2195 
2196 #define S_GPIO1_OUT_VAL    1
2197 #define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL)
2198 #define F_GPIO1_OUT_VAL    V_GPIO1_OUT_VAL(1U)
2199 
2200 #define S_GPIO0_OUT_VAL    0
2201 #define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL)
2202 #define F_GPIO0_OUT_VAL    V_GPIO0_OUT_VAL(1U)
2203 
2204 #define A_T3DBG_GPIO_IN 0xd4
2205 
2206 #define S_GPIO11_CHG_DET    27
2207 #define V_GPIO11_CHG_DET(x) ((x) << S_GPIO11_CHG_DET)
2208 #define F_GPIO11_CHG_DET    V_GPIO11_CHG_DET(1U)
2209 
2210 #define S_GPIO10_CHG_DET    26
2211 #define V_GPIO10_CHG_DET(x) ((x) << S_GPIO10_CHG_DET)
2212 #define F_GPIO10_CHG_DET    V_GPIO10_CHG_DET(1U)
2213 
2214 #define S_GPIO9_CHG_DET    25
2215 #define V_GPIO9_CHG_DET(x) ((x) << S_GPIO9_CHG_DET)
2216 #define F_GPIO9_CHG_DET    V_GPIO9_CHG_DET(1U)
2217 
2218 #define S_GPIO8_CHG_DET    24
2219 #define V_GPIO8_CHG_DET(x) ((x) << S_GPIO8_CHG_DET)
2220 #define F_GPIO8_CHG_DET    V_GPIO8_CHG_DET(1U)
2221 
2222 #define S_GPIO7_CHG_DET    23
2223 #define V_GPIO7_CHG_DET(x) ((x) << S_GPIO7_CHG_DET)
2224 #define F_GPIO7_CHG_DET    V_GPIO7_CHG_DET(1U)
2225 
2226 #define S_GPIO6_CHG_DET    22
2227 #define V_GPIO6_CHG_DET(x) ((x) << S_GPIO6_CHG_DET)
2228 #define F_GPIO6_CHG_DET    V_GPIO6_CHG_DET(1U)
2229 
2230 #define S_GPIO5_CHG_DET    21
2231 #define V_GPIO5_CHG_DET(x) ((x) << S_GPIO5_CHG_DET)
2232 #define F_GPIO5_CHG_DET    V_GPIO5_CHG_DET(1U)
2233 
2234 #define S_GPIO4_CHG_DET    20
2235 #define V_GPIO4_CHG_DET(x) ((x) << S_GPIO4_CHG_DET)
2236 #define F_GPIO4_CHG_DET    V_GPIO4_CHG_DET(1U)
2237 
2238 #define S_GPIO3_CHG_DET    19
2239 #define V_GPIO3_CHG_DET(x) ((x) << S_GPIO3_CHG_DET)
2240 #define F_GPIO3_CHG_DET    V_GPIO3_CHG_DET(1U)
2241 
2242 #define S_GPIO2_CHG_DET    18
2243 #define V_GPIO2_CHG_DET(x) ((x) << S_GPIO2_CHG_DET)
2244 #define F_GPIO2_CHG_DET    V_GPIO2_CHG_DET(1U)
2245 
2246 #define S_GPIO1_CHG_DET    17
2247 #define V_GPIO1_CHG_DET(x) ((x) << S_GPIO1_CHG_DET)
2248 #define F_GPIO1_CHG_DET    V_GPIO1_CHG_DET(1U)
2249 
2250 #define S_GPIO0_CHG_DET    16
2251 #define V_GPIO0_CHG_DET(x) ((x) << S_GPIO0_CHG_DET)
2252 #define F_GPIO0_CHG_DET    V_GPIO0_CHG_DET(1U)
2253 
2254 #define S_GPIO11_IN    11
2255 #define V_GPIO11_IN(x) ((x) << S_GPIO11_IN)
2256 #define F_GPIO11_IN    V_GPIO11_IN(1U)
2257 
2258 #define S_GPIO10_IN    10
2259 #define V_GPIO10_IN(x) ((x) << S_GPIO10_IN)
2260 #define F_GPIO10_IN    V_GPIO10_IN(1U)
2261 
2262 #define S_GPIO9_IN    9
2263 #define V_GPIO9_IN(x) ((x) << S_GPIO9_IN)
2264 #define F_GPIO9_IN    V_GPIO9_IN(1U)
2265 
2266 #define S_GPIO8_IN    8
2267 #define V_GPIO8_IN(x) ((x) << S_GPIO8_IN)
2268 #define F_GPIO8_IN    V_GPIO8_IN(1U)
2269 
2270 #define S_GPIO7_IN    7
2271 #define V_GPIO7_IN(x) ((x) << S_GPIO7_IN)
2272 #define F_GPIO7_IN    V_GPIO7_IN(1U)
2273 
2274 #define S_GPIO6_IN    6
2275 #define V_GPIO6_IN(x) ((x) << S_GPIO6_IN)
2276 #define F_GPIO6_IN    V_GPIO6_IN(1U)
2277 
2278 #define S_GPIO5_IN    5
2279 #define V_GPIO5_IN(x) ((x) << S_GPIO5_IN)
2280 #define F_GPIO5_IN    V_GPIO5_IN(1U)
2281 
2282 #define S_GPIO4_IN    4
2283 #define V_GPIO4_IN(x) ((x) << S_GPIO4_IN)
2284 #define F_GPIO4_IN    V_GPIO4_IN(1U)
2285 
2286 #define S_GPIO3_IN    3
2287 #define V_GPIO3_IN(x) ((x) << S_GPIO3_IN)
2288 #define F_GPIO3_IN    V_GPIO3_IN(1U)
2289 
2290 #define S_GPIO2_IN    2
2291 #define V_GPIO2_IN(x) ((x) << S_GPIO2_IN)
2292 #define F_GPIO2_IN    V_GPIO2_IN(1U)
2293 
2294 #define S_GPIO1_IN    1
2295 #define V_GPIO1_IN(x) ((x) << S_GPIO1_IN)
2296 #define F_GPIO1_IN    V_GPIO1_IN(1U)
2297 
2298 #define S_GPIO0_IN    0
2299 #define V_GPIO0_IN(x) ((x) << S_GPIO0_IN)
2300 #define F_GPIO0_IN    V_GPIO0_IN(1U)
2301 
2302 #define A_T3DBG_INT_ENABLE 0xd8
2303 
2304 #define S_C_LOCK    21
2305 #define V_C_LOCK(x) ((x) << S_C_LOCK)
2306 #define F_C_LOCK    V_C_LOCK(1U)
2307 
2308 #define S_M_LOCK    20
2309 #define V_M_LOCK(x) ((x) << S_M_LOCK)
2310 #define F_M_LOCK    V_M_LOCK(1U)
2311 
2312 #define S_U_LOCK    19
2313 #define V_U_LOCK(x) ((x) << S_U_LOCK)
2314 #define F_U_LOCK    V_U_LOCK(1U)
2315 
2316 #define S_R_LOCK    18
2317 #define V_R_LOCK(x) ((x) << S_R_LOCK)
2318 #define F_R_LOCK    V_R_LOCK(1U)
2319 
2320 #define S_PX_LOCK    17
2321 #define V_PX_LOCK(x) ((x) << S_PX_LOCK)
2322 #define F_PX_LOCK    V_PX_LOCK(1U)
2323 
2324 #define S_GPIO11    11
2325 #define V_GPIO11(x) ((x) << S_GPIO11)
2326 #define F_GPIO11    V_GPIO11(1U)
2327 
2328 #define S_GPIO10    10
2329 #define V_GPIO10(x) ((x) << S_GPIO10)
2330 #define F_GPIO10    V_GPIO10(1U)
2331 
2332 #define S_GPIO9    9
2333 #define V_GPIO9(x) ((x) << S_GPIO9)
2334 #define F_GPIO9    V_GPIO9(1U)
2335 
2336 #define S_GPIO8    8
2337 #define V_GPIO8(x) ((x) << S_GPIO8)
2338 #define F_GPIO8    V_GPIO8(1U)
2339 
2340 #define S_GPIO7    7
2341 #define V_GPIO7(x) ((x) << S_GPIO7)
2342 #define F_GPIO7    V_GPIO7(1U)
2343 
2344 #define S_GPIO6    6
2345 #define V_GPIO6(x) ((x) << S_GPIO6)
2346 #define F_GPIO6    V_GPIO6(1U)
2347 
2348 #define S_GPIO5    5
2349 #define V_GPIO5(x) ((x) << S_GPIO5)
2350 #define F_GPIO5    V_GPIO5(1U)
2351 
2352 #define S_GPIO4    4
2353 #define V_GPIO4(x) ((x) << S_GPIO4)
2354 #define F_GPIO4    V_GPIO4(1U)
2355 
2356 #define S_GPIO3    3
2357 #define V_GPIO3(x) ((x) << S_GPIO3)
2358 #define F_GPIO3    V_GPIO3(1U)
2359 
2360 #define S_GPIO2    2
2361 #define V_GPIO2(x) ((x) << S_GPIO2)
2362 #define F_GPIO2    V_GPIO2(1U)
2363 
2364 #define S_GPIO1    1
2365 #define V_GPIO1(x) ((x) << S_GPIO1)
2366 #define F_GPIO1    V_GPIO1(1U)
2367 
2368 #define S_GPIO0    0
2369 #define V_GPIO0(x) ((x) << S_GPIO0)
2370 #define F_GPIO0    V_GPIO0(1U)
2371 
2372 #define S_PE_LOCK    16
2373 #define V_PE_LOCK(x) ((x) << S_PE_LOCK)
2374 #define F_PE_LOCK    V_PE_LOCK(1U)
2375 
2376 #define A_T3DBG_INT_CAUSE 0xdc
2377 #define A_T3DBG_DBG0_RST_VALUE 0xe0
2378 
2379 #define S_DEBUGDATA    0
2380 #define M_DEBUGDATA    0xff
2381 #define V_DEBUGDATA(x) ((x) << S_DEBUGDATA)
2382 #define G_DEBUGDATA(x) (((x) >> S_DEBUGDATA) & M_DEBUGDATA)
2383 
2384 #define A_T3DBG_PLL_OCLK_PAD_EN 0xe4
2385 
2386 #define S_PCIE_OCLK_EN    20
2387 #define V_PCIE_OCLK_EN(x) ((x) << S_PCIE_OCLK_EN)
2388 #define F_PCIE_OCLK_EN    V_PCIE_OCLK_EN(1U)
2389 
2390 #define S_PCLKTREE_DBG_EN    17
2391 #define V_PCLKTREE_DBG_EN(x) ((x) << S_PCLKTREE_DBG_EN)
2392 #define F_PCLKTREE_DBG_EN    V_PCLKTREE_DBG_EN(1U)
2393 
2394 #define S_PCIX_OCLK_EN    16
2395 #define V_PCIX_OCLK_EN(x) ((x) << S_PCIX_OCLK_EN)
2396 #define F_PCIX_OCLK_EN    V_PCIX_OCLK_EN(1U)
2397 
2398 #define S_U_OCLK_EN    12
2399 #define V_U_OCLK_EN(x) ((x) << S_U_OCLK_EN)
2400 #define F_U_OCLK_EN    V_U_OCLK_EN(1U)
2401 
2402 #define S_R_OCLK_EN    8
2403 #define V_R_OCLK_EN(x) ((x) << S_R_OCLK_EN)
2404 #define F_R_OCLK_EN    V_R_OCLK_EN(1U)
2405 
2406 #define S_M_OCLK_EN    4
2407 #define V_M_OCLK_EN(x) ((x) << S_M_OCLK_EN)
2408 #define F_M_OCLK_EN    V_M_OCLK_EN(1U)
2409 
2410 #define S_C_OCLK_EN    0
2411 #define V_C_OCLK_EN(x) ((x) << S_C_OCLK_EN)
2412 #define F_C_OCLK_EN    V_C_OCLK_EN(1U)
2413 
2414 #define A_T3DBG_PLL_LOCK 0xe8
2415 
2416 #define S_PCIX_LOCK    16
2417 #define V_PCIX_LOCK(x) ((x) << S_PCIX_LOCK)
2418 #define F_PCIX_LOCK    V_PCIX_LOCK(1U)
2419 
2420 #define S_PLL_U_LOCK    12
2421 #define V_PLL_U_LOCK(x) ((x) << S_PLL_U_LOCK)
2422 #define F_PLL_U_LOCK    V_PLL_U_LOCK(1U)
2423 
2424 #define S_PLL_R_LOCK    8
2425 #define V_PLL_R_LOCK(x) ((x) << S_PLL_R_LOCK)
2426 #define F_PLL_R_LOCK    V_PLL_R_LOCK(1U)
2427 
2428 #define S_PLL_M_LOCK    4
2429 #define V_PLL_M_LOCK(x) ((x) << S_PLL_M_LOCK)
2430 #define F_PLL_M_LOCK    V_PLL_M_LOCK(1U)
2431 
2432 #define S_PLL_C_LOCK    0
2433 #define V_PLL_C_LOCK(x) ((x) << S_PLL_C_LOCK)
2434 #define F_PLL_C_LOCK    V_PLL_C_LOCK(1U)
2435 
2436 #define S_PCIE_LOCK    20
2437 #define V_PCIE_LOCK(x) ((x) << S_PCIE_LOCK)
2438 #define F_PCIE_LOCK    V_PCIE_LOCK(1U)
2439 
2440 #define A_T3DBG_SERDES_RBC_CFG 0xec
2441 
2442 #define S_X_RBC_LANE_SEL    16
2443 #define M_X_RBC_LANE_SEL    0x3
2444 #define V_X_RBC_LANE_SEL(x) ((x) << S_X_RBC_LANE_SEL)
2445 #define G_X_RBC_LANE_SEL(x) (((x) >> S_X_RBC_LANE_SEL) & M_X_RBC_LANE_SEL)
2446 
2447 #define S_X_RBC_DBG_EN    12
2448 #define V_X_RBC_DBG_EN(x) ((x) << S_X_RBC_DBG_EN)
2449 #define F_X_RBC_DBG_EN    V_X_RBC_DBG_EN(1U)
2450 
2451 #define S_X_SERDES_SEL    8
2452 #define V_X_SERDES_SEL(x) ((x) << S_X_SERDES_SEL)
2453 #define F_X_SERDES_SEL    V_X_SERDES_SEL(1U)
2454 
2455 #define S_PE_RBC_LANE_SEL    4
2456 #define M_PE_RBC_LANE_SEL    0x7
2457 #define V_PE_RBC_LANE_SEL(x) ((x) << S_PE_RBC_LANE_SEL)
2458 #define G_PE_RBC_LANE_SEL(x) (((x) >> S_PE_RBC_LANE_SEL) & M_PE_RBC_LANE_SEL)
2459 
2460 #define S_PE_RBC_DBG_EN    0
2461 #define V_PE_RBC_DBG_EN(x) ((x) << S_PE_RBC_DBG_EN)
2462 #define F_PE_RBC_DBG_EN    V_PE_RBC_DBG_EN(1U)
2463 
2464 #define A_T3DBG_GPIO_ACT_LOW 0xf0
2465 
2466 #define S_C_LOCK_ACT_LOW    21
2467 #define V_C_LOCK_ACT_LOW(x) ((x) << S_C_LOCK_ACT_LOW)
2468 #define F_C_LOCK_ACT_LOW    V_C_LOCK_ACT_LOW(1U)
2469 
2470 #define S_M_LOCK_ACT_LOW    20
2471 #define V_M_LOCK_ACT_LOW(x) ((x) << S_M_LOCK_ACT_LOW)
2472 #define F_M_LOCK_ACT_LOW    V_M_LOCK_ACT_LOW(1U)
2473 
2474 #define S_U_LOCK_ACT_LOW    19
2475 #define V_U_LOCK_ACT_LOW(x) ((x) << S_U_LOCK_ACT_LOW)
2476 #define F_U_LOCK_ACT_LOW    V_U_LOCK_ACT_LOW(1U)
2477 
2478 #define S_R_LOCK_ACT_LOW    18
2479 #define V_R_LOCK_ACT_LOW(x) ((x) << S_R_LOCK_ACT_LOW)
2480 #define F_R_LOCK_ACT_LOW    V_R_LOCK_ACT_LOW(1U)
2481 
2482 #define S_PX_LOCK_ACT_LOW    17
2483 #define V_PX_LOCK_ACT_LOW(x) ((x) << S_PX_LOCK_ACT_LOW)
2484 #define F_PX_LOCK_ACT_LOW    V_PX_LOCK_ACT_LOW(1U)
2485 
2486 #define S_GPIO11_ACT_LOW    11
2487 #define V_GPIO11_ACT_LOW(x) ((x) << S_GPIO11_ACT_LOW)
2488 #define F_GPIO11_ACT_LOW    V_GPIO11_ACT_LOW(1U)
2489 
2490 #define S_GPIO10_ACT_LOW    10
2491 #define V_GPIO10_ACT_LOW(x) ((x) << S_GPIO10_ACT_LOW)
2492 #define F_GPIO10_ACT_LOW    V_GPIO10_ACT_LOW(1U)
2493 
2494 #define S_GPIO9_ACT_LOW    9
2495 #define V_GPIO9_ACT_LOW(x) ((x) << S_GPIO9_ACT_LOW)
2496 #define F_GPIO9_ACT_LOW    V_GPIO9_ACT_LOW(1U)
2497 
2498 #define S_GPIO8_ACT_LOW    8
2499 #define V_GPIO8_ACT_LOW(x) ((x) << S_GPIO8_ACT_LOW)
2500 #define F_GPIO8_ACT_LOW    V_GPIO8_ACT_LOW(1U)
2501 
2502 #define S_GPIO7_ACT_LOW    7
2503 #define V_GPIO7_ACT_LOW(x) ((x) << S_GPIO7_ACT_LOW)
2504 #define F_GPIO7_ACT_LOW    V_GPIO7_ACT_LOW(1U)
2505 
2506 #define S_GPIO6_ACT_LOW    6
2507 #define V_GPIO6_ACT_LOW(x) ((x) << S_GPIO6_ACT_LOW)
2508 #define F_GPIO6_ACT_LOW    V_GPIO6_ACT_LOW(1U)
2509 
2510 #define S_GPIO5_ACT_LOW    5
2511 #define V_GPIO5_ACT_LOW(x) ((x) << S_GPIO5_ACT_LOW)
2512 #define F_GPIO5_ACT_LOW    V_GPIO5_ACT_LOW(1U)
2513 
2514 #define S_GPIO4_ACT_LOW    4
2515 #define V_GPIO4_ACT_LOW(x) ((x) << S_GPIO4_ACT_LOW)
2516 #define F_GPIO4_ACT_LOW    V_GPIO4_ACT_LOW(1U)
2517 
2518 #define S_GPIO3_ACT_LOW    3
2519 #define V_GPIO3_ACT_LOW(x) ((x) << S_GPIO3_ACT_LOW)
2520 #define F_GPIO3_ACT_LOW    V_GPIO3_ACT_LOW(1U)
2521 
2522 #define S_GPIO2_ACT_LOW    2
2523 #define V_GPIO2_ACT_LOW(x) ((x) << S_GPIO2_ACT_LOW)
2524 #define F_GPIO2_ACT_LOW    V_GPIO2_ACT_LOW(1U)
2525 
2526 #define S_GPIO1_ACT_LOW    1
2527 #define V_GPIO1_ACT_LOW(x) ((x) << S_GPIO1_ACT_LOW)
2528 #define F_GPIO1_ACT_LOW    V_GPIO1_ACT_LOW(1U)
2529 
2530 #define S_GPIO0_ACT_LOW    0
2531 #define V_GPIO0_ACT_LOW(x) ((x) << S_GPIO0_ACT_LOW)
2532 #define F_GPIO0_ACT_LOW    V_GPIO0_ACT_LOW(1U)
2533 
2534 #define S_PE_LOCK_ACT_LOW    16
2535 #define V_PE_LOCK_ACT_LOW(x) ((x) << S_PE_LOCK_ACT_LOW)
2536 #define F_PE_LOCK_ACT_LOW    V_PE_LOCK_ACT_LOW(1U)
2537 
2538 #define A_T3DBG_PMON_CFG 0xf4
2539 
2540 #define S_PMON_DONE    29
2541 #define V_PMON_DONE(x) ((x) << S_PMON_DONE)
2542 #define F_PMON_DONE    V_PMON_DONE(1U)
2543 
2544 #define S_PMON_FAIL    28
2545 #define V_PMON_FAIL(x) ((x) << S_PMON_FAIL)
2546 #define F_PMON_FAIL    V_PMON_FAIL(1U)
2547 
2548 #define S_PMON_FDEL_AUTO    22
2549 #define M_PMON_FDEL_AUTO    0x3f
2550 #define V_PMON_FDEL_AUTO(x) ((x) << S_PMON_FDEL_AUTO)
2551 #define G_PMON_FDEL_AUTO(x) (((x) >> S_PMON_FDEL_AUTO) & M_PMON_FDEL_AUTO)
2552 
2553 #define S_PMON_CDEL_AUTO    16
2554 #define M_PMON_CDEL_AUTO    0x3f
2555 #define V_PMON_CDEL_AUTO(x) ((x) << S_PMON_CDEL_AUTO)
2556 #define G_PMON_CDEL_AUTO(x) (((x) >> S_PMON_CDEL_AUTO) & M_PMON_CDEL_AUTO)
2557 
2558 #define S_PMON_FDEL_MANUAL    10
2559 #define M_PMON_FDEL_MANUAL    0x3f
2560 #define V_PMON_FDEL_MANUAL(x) ((x) << S_PMON_FDEL_MANUAL)
2561 #define G_PMON_FDEL_MANUAL(x) (((x) >> S_PMON_FDEL_MANUAL) & M_PMON_FDEL_MANUAL)
2562 
2563 #define S_PMON_CDEL_MANUAL    4
2564 #define M_PMON_CDEL_MANUAL    0x3f
2565 #define V_PMON_CDEL_MANUAL(x) ((x) << S_PMON_CDEL_MANUAL)
2566 #define G_PMON_CDEL_MANUAL(x) (((x) >> S_PMON_CDEL_MANUAL) & M_PMON_CDEL_MANUAL)
2567 
2568 #define S_PMON_MANUAL    1
2569 #define V_PMON_MANUAL(x) ((x) << S_PMON_MANUAL)
2570 #define F_PMON_MANUAL    V_PMON_MANUAL(1U)
2571 
2572 #define S_PMON_AUTO    0
2573 #define V_PMON_AUTO(x) ((x) << S_PMON_AUTO)
2574 #define F_PMON_AUTO    V_PMON_AUTO(1U)
2575 
2576 #define A_T3DBG_SERDES_REFCLK_CFG 0xf8
2577 
2578 #define S_PE_REFCLK_DBG_EN    12
2579 #define V_PE_REFCLK_DBG_EN(x) ((x) << S_PE_REFCLK_DBG_EN)
2580 #define F_PE_REFCLK_DBG_EN    V_PE_REFCLK_DBG_EN(1U)
2581 
2582 #define S_X_REFCLK_DBG_EN    8
2583 #define V_X_REFCLK_DBG_EN(x) ((x) << S_X_REFCLK_DBG_EN)
2584 #define F_X_REFCLK_DBG_EN    V_X_REFCLK_DBG_EN(1U)
2585 
2586 #define S_PE_REFCLK_TERMADJ    5
2587 #define M_PE_REFCLK_TERMADJ    0x3
2588 #define V_PE_REFCLK_TERMADJ(x) ((x) << S_PE_REFCLK_TERMADJ)
2589 #define G_PE_REFCLK_TERMADJ(x) (((x) >> S_PE_REFCLK_TERMADJ) & M_PE_REFCLK_TERMADJ)
2590 
2591 #define S_PE_REFCLK_PD    4
2592 #define V_PE_REFCLK_PD(x) ((x) << S_PE_REFCLK_PD)
2593 #define F_PE_REFCLK_PD    V_PE_REFCLK_PD(1U)
2594 
2595 #define S_X_REFCLK_TERMADJ    1
2596 #define M_X_REFCLK_TERMADJ    0x3
2597 #define V_X_REFCLK_TERMADJ(x) ((x) << S_X_REFCLK_TERMADJ)
2598 #define G_X_REFCLK_TERMADJ(x) (((x) >> S_X_REFCLK_TERMADJ) & M_X_REFCLK_TERMADJ)
2599 
2600 #define S_X_REFCLK_PD    0
2601 #define V_X_REFCLK_PD(x) ((x) << S_X_REFCLK_PD)
2602 #define F_X_REFCLK_PD    V_X_REFCLK_PD(1U)
2603 
2604 #define A_T3DBG_PCIE_PMA_BSPIN_CFG 0xfc
2605 
2606 #define S_BSMODEQUAD1    31
2607 #define V_BSMODEQUAD1(x) ((x) << S_BSMODEQUAD1)
2608 #define F_BSMODEQUAD1    V_BSMODEQUAD1(1U)
2609 
2610 #define S_BSINSELLANE7    29
2611 #define M_BSINSELLANE7    0x3
2612 #define V_BSINSELLANE7(x) ((x) << S_BSINSELLANE7)
2613 #define G_BSINSELLANE7(x) (((x) >> S_BSINSELLANE7) & M_BSINSELLANE7)
2614 
2615 #define S_BSENLANE7    28
2616 #define V_BSENLANE7(x) ((x) << S_BSENLANE7)
2617 #define F_BSENLANE7    V_BSENLANE7(1U)
2618 
2619 #define S_BSINSELLANE6    25
2620 #define M_BSINSELLANE6    0x3
2621 #define V_BSINSELLANE6(x) ((x) << S_BSINSELLANE6)
2622 #define G_BSINSELLANE6(x) (((x) >> S_BSINSELLANE6) & M_BSINSELLANE6)
2623 
2624 #define S_BSENLANE6    24
2625 #define V_BSENLANE6(x) ((x) << S_BSENLANE6)
2626 #define F_BSENLANE6    V_BSENLANE6(1U)
2627 
2628 #define S_BSINSELLANE5    21
2629 #define M_BSINSELLANE5    0x3
2630 #define V_BSINSELLANE5(x) ((x) << S_BSINSELLANE5)
2631 #define G_BSINSELLANE5(x) (((x) >> S_BSINSELLANE5) & M_BSINSELLANE5)
2632 
2633 #define S_BSENLANE5    20
2634 #define V_BSENLANE5(x) ((x) << S_BSENLANE5)
2635 #define F_BSENLANE5    V_BSENLANE5(1U)
2636 
2637 #define S_BSINSELLANE4    17
2638 #define M_BSINSELLANE4    0x3
2639 #define V_BSINSELLANE4(x) ((x) << S_BSINSELLANE4)
2640 #define G_BSINSELLANE4(x) (((x) >> S_BSINSELLANE4) & M_BSINSELLANE4)
2641 
2642 #define S_BSENLANE4    16
2643 #define V_BSENLANE4(x) ((x) << S_BSENLANE4)
2644 #define F_BSENLANE4    V_BSENLANE4(1U)
2645 
2646 #define S_BSMODEQUAD0    15
2647 #define V_BSMODEQUAD0(x) ((x) << S_BSMODEQUAD0)
2648 #define F_BSMODEQUAD0    V_BSMODEQUAD0(1U)
2649 
2650 #define S_BSINSELLANE3    13
2651 #define M_BSINSELLANE3    0x3
2652 #define V_BSINSELLANE3(x) ((x) << S_BSINSELLANE3)
2653 #define G_BSINSELLANE3(x) (((x) >> S_BSINSELLANE3) & M_BSINSELLANE3)
2654 
2655 #define S_BSENLANE3    12
2656 #define V_BSENLANE3(x) ((x) << S_BSENLANE3)
2657 #define F_BSENLANE3    V_BSENLANE3(1U)
2658 
2659 #define S_BSINSELLANE2    9
2660 #define M_BSINSELLANE2    0x3
2661 #define V_BSINSELLANE2(x) ((x) << S_BSINSELLANE2)
2662 #define G_BSINSELLANE2(x) (((x) >> S_BSINSELLANE2) & M_BSINSELLANE2)
2663 
2664 #define S_BSENLANE2    8
2665 #define V_BSENLANE2(x) ((x) << S_BSENLANE2)
2666 #define F_BSENLANE2    V_BSENLANE2(1U)
2667 
2668 #define S_BSINSELLANE1    5
2669 #define M_BSINSELLANE1    0x3
2670 #define V_BSINSELLANE1(x) ((x) << S_BSINSELLANE1)
2671 #define G_BSINSELLANE1(x) (((x) >> S_BSINSELLANE1) & M_BSINSELLANE1)
2672 
2673 #define S_BSENLANE1    4
2674 #define V_BSENLANE1(x) ((x) << S_BSENLANE1)
2675 #define F_BSENLANE1    V_BSENLANE1(1U)
2676 
2677 #define S_BSINSELLANE0    1
2678 #define M_BSINSELLANE0    0x3
2679 #define V_BSINSELLANE0(x) ((x) << S_BSINSELLANE0)
2680 #define G_BSINSELLANE0(x) (((x) >> S_BSINSELLANE0) & M_BSINSELLANE0)
2681 
2682 #define S_BSENLANE0    0
2683 #define V_BSENLANE0(x) ((x) << S_BSENLANE0)
2684 #define F_BSENLANE0    V_BSENLANE0(1U)
2685 
2686 /* registers for module MC7_PMRX */
2687 #define MC7_PMRX_BASE_ADDR 0x100
2688 
2689 #define A_MC7_CFG 0x100
2690 
2691 #define S_IMPSETUPDATE    14
2692 #define V_IMPSETUPDATE(x) ((x) << S_IMPSETUPDATE)
2693 #define F_IMPSETUPDATE    V_IMPSETUPDATE(1U)
2694 
2695 #define S_IFEN    13
2696 #define V_IFEN(x) ((x) << S_IFEN)
2697 #define F_IFEN    V_IFEN(1U)
2698 
2699 #define S_TERM300    12
2700 #define V_TERM300(x) ((x) << S_TERM300)
2701 #define F_TERM300    V_TERM300(1U)
2702 
2703 #define S_TERM150    11
2704 #define V_TERM150(x) ((x) << S_TERM150)
2705 #define F_TERM150    V_TERM150(1U)
2706 
2707 #define S_SLOW    10
2708 #define V_SLOW(x) ((x) << S_SLOW)
2709 #define F_SLOW    V_SLOW(1U)
2710 
2711 #define S_WIDTH    8
2712 #define M_WIDTH    0x3
2713 #define V_WIDTH(x) ((x) << S_WIDTH)
2714 #define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH)
2715 
2716 #define S_ODTEN    7
2717 #define V_ODTEN(x) ((x) << S_ODTEN)
2718 #define F_ODTEN    V_ODTEN(1U)
2719 
2720 #define S_BKS    6
2721 #define V_BKS(x) ((x) << S_BKS)
2722 #define F_BKS    V_BKS(1U)
2723 
2724 #define S_ORG    5
2725 #define V_ORG(x) ((x) << S_ORG)
2726 #define F_ORG    V_ORG(1U)
2727 
2728 #define S_DEN    2
2729 #define M_DEN    0x7
2730 #define V_DEN(x) ((x) << S_DEN)
2731 #define G_DEN(x) (((x) >> S_DEN) & M_DEN)
2732 
2733 #define S_RDY    1
2734 #define V_RDY(x) ((x) << S_RDY)
2735 #define F_RDY    V_RDY(1U)
2736 
2737 #define S_CLKEN    0
2738 #define V_CLKEN(x) ((x) << S_CLKEN)
2739 #define F_CLKEN    V_CLKEN(1U)
2740 
2741 #define A_MC7_MODE 0x104
2742 
2743 #define S_MODE    0
2744 #define M_MODE    0xffff
2745 #define V_MODE(x) ((x) << S_MODE)
2746 #define G_MODE(x) (((x) >> S_MODE) & M_MODE)
2747 
2748 #define A_MC7_EXT_MODE1 0x108
2749 
2750 #define S_OCDADJUSTMODE    20
2751 #define V_OCDADJUSTMODE(x) ((x) << S_OCDADJUSTMODE)
2752 #define F_OCDADJUSTMODE    V_OCDADJUSTMODE(1U)
2753 
2754 #define S_OCDCODE    16
2755 #define M_OCDCODE    0xf
2756 #define V_OCDCODE(x) ((x) << S_OCDCODE)
2757 #define G_OCDCODE(x) (((x) >> S_OCDCODE) & M_OCDCODE)
2758 
2759 #define S_EXTMODE1    0
2760 #define M_EXTMODE1    0xffff
2761 #define V_EXTMODE1(x) ((x) << S_EXTMODE1)
2762 #define G_EXTMODE1(x) (((x) >> S_EXTMODE1) & M_EXTMODE1)
2763 
2764 #define A_MC7_EXT_MODE2 0x10c
2765 
2766 #define S_EXTMODE2    0
2767 #define M_EXTMODE2    0xffff
2768 #define V_EXTMODE2(x) ((x) << S_EXTMODE2)
2769 #define G_EXTMODE2(x) (((x) >> S_EXTMODE2) & M_EXTMODE2)
2770 
2771 #define A_MC7_EXT_MODE3 0x110
2772 
2773 #define S_EXTMODE3    0
2774 #define M_EXTMODE3    0xffff
2775 #define V_EXTMODE3(x) ((x) << S_EXTMODE3)
2776 #define G_EXTMODE3(x) (((x) >> S_EXTMODE3) & M_EXTMODE3)
2777 
2778 #define A_MC7_PRE 0x114
2779 #define A_MC7_REF 0x118
2780 
2781 #define S_PREREFDIV    1
2782 #define M_PREREFDIV    0x3fff
2783 #define V_PREREFDIV(x) ((x) << S_PREREFDIV)
2784 #define G_PREREFDIV(x) (((x) >> S_PREREFDIV) & M_PREREFDIV)
2785 
2786 #define S_PERREFEN    0
2787 #define V_PERREFEN(x) ((x) << S_PERREFEN)
2788 #define F_PERREFEN    V_PERREFEN(1U)
2789 
2790 #define A_MC7_DLL 0x11c
2791 
2792 #define S_DLLLOCK    31
2793 #define V_DLLLOCK(x) ((x) << S_DLLLOCK)
2794 #define F_DLLLOCK    V_DLLLOCK(1U)
2795 
2796 #define S_DLLDELTA    24
2797 #define M_DLLDELTA    0x7f
2798 #define V_DLLDELTA(x) ((x) << S_DLLDELTA)
2799 #define G_DLLDELTA(x) (((x) >> S_DLLDELTA) & M_DLLDELTA)
2800 
2801 #define S_MANDELTA    3
2802 #define M_MANDELTA    0x7f
2803 #define V_MANDELTA(x) ((x) << S_MANDELTA)
2804 #define G_MANDELTA(x) (((x) >> S_MANDELTA) & M_MANDELTA)
2805 
2806 #define S_DLLDELTASEL    2
2807 #define V_DLLDELTASEL(x) ((x) << S_DLLDELTASEL)
2808 #define F_DLLDELTASEL    V_DLLDELTASEL(1U)
2809 
2810 #define S_DLLENB    1
2811 #define V_DLLENB(x) ((x) << S_DLLENB)
2812 #define F_DLLENB    V_DLLENB(1U)
2813 
2814 #define S_DLLRST    0
2815 #define V_DLLRST(x) ((x) << S_DLLRST)
2816 #define F_DLLRST    V_DLLRST(1U)
2817 
2818 #define A_MC7_PARM 0x120
2819 
2820 #define S_ACTTOPREDLY    26
2821 #define M_ACTTOPREDLY    0xf
2822 #define V_ACTTOPREDLY(x) ((x) << S_ACTTOPREDLY)
2823 #define G_ACTTOPREDLY(x) (((x) >> S_ACTTOPREDLY) & M_ACTTOPREDLY)
2824 
2825 #define S_ACTTORDWRDLY    23
2826 #define M_ACTTORDWRDLY    0x7
2827 #define V_ACTTORDWRDLY(x) ((x) << S_ACTTORDWRDLY)
2828 #define G_ACTTORDWRDLY(x) (((x) >> S_ACTTORDWRDLY) & M_ACTTORDWRDLY)
2829 
2830 #define S_PRECYC    20
2831 #define M_PRECYC    0x7
2832 #define V_PRECYC(x) ((x) << S_PRECYC)
2833 #define G_PRECYC(x) (((x) >> S_PRECYC) & M_PRECYC)
2834 
2835 #define S_REFCYC    13
2836 #define M_REFCYC    0x7f
2837 #define V_REFCYC(x) ((x) << S_REFCYC)
2838 #define G_REFCYC(x) (((x) >> S_REFCYC) & M_REFCYC)
2839 
2840 #define S_BKCYC    8
2841 #define M_BKCYC    0x1f
2842 #define V_BKCYC(x) ((x) << S_BKCYC)
2843 #define G_BKCYC(x) (((x) >> S_BKCYC) & M_BKCYC)
2844 
2845 #define S_WRTORDDLY    4
2846 #define M_WRTORDDLY    0xf
2847 #define V_WRTORDDLY(x) ((x) << S_WRTORDDLY)
2848 #define G_WRTORDDLY(x) (((x) >> S_WRTORDDLY) & M_WRTORDDLY)
2849 
2850 #define S_RDTOWRDLY    0
2851 #define M_RDTOWRDLY    0xf
2852 #define V_RDTOWRDLY(x) ((x) << S_RDTOWRDLY)
2853 #define G_RDTOWRDLY(x) (((x) >> S_RDTOWRDLY) & M_RDTOWRDLY)
2854 
2855 #define A_MC7_HWM_WRR 0x124
2856 
2857 #define S_MEM_HWM    26
2858 #define M_MEM_HWM    0x3f
2859 #define V_MEM_HWM(x) ((x) << S_MEM_HWM)
2860 #define G_MEM_HWM(x) (((x) >> S_MEM_HWM) & M_MEM_HWM)
2861 
2862 #define S_ULP_HWM    22
2863 #define M_ULP_HWM    0xf
2864 #define V_ULP_HWM(x) ((x) << S_ULP_HWM)
2865 #define G_ULP_HWM(x) (((x) >> S_ULP_HWM) & M_ULP_HWM)
2866 
2867 #define S_TOT_RLD_WT    14
2868 #define M_TOT_RLD_WT    0xff
2869 #define V_TOT_RLD_WT(x) ((x) << S_TOT_RLD_WT)
2870 #define G_TOT_RLD_WT(x) (((x) >> S_TOT_RLD_WT) & M_TOT_RLD_WT)
2871 
2872 #define S_MEM_RLD_WT    7
2873 #define M_MEM_RLD_WT    0x7f
2874 #define V_MEM_RLD_WT(x) ((x) << S_MEM_RLD_WT)
2875 #define G_MEM_RLD_WT(x) (((x) >> S_MEM_RLD_WT) & M_MEM_RLD_WT)
2876 
2877 #define S_ULP_RLD_WT    0
2878 #define M_ULP_RLD_WT    0x7f
2879 #define V_ULP_RLD_WT(x) ((x) << S_ULP_RLD_WT)
2880 #define G_ULP_RLD_WT(x) (((x) >> S_ULP_RLD_WT) & M_ULP_RLD_WT)
2881 
2882 #define A_MC7_CAL 0x128
2883 
2884 #define S_BUSY    31
2885 #define V_BUSY(x) ((x) << S_BUSY)
2886 #define F_BUSY    V_BUSY(1U)
2887 
2888 #define S_CAL_FAULT    30
2889 #define V_CAL_FAULT(x) ((x) << S_CAL_FAULT)
2890 #define F_CAL_FAULT    V_CAL_FAULT(1U)
2891 
2892 #define S_PER_CAL_DIV    22
2893 #define M_PER_CAL_DIV    0xff
2894 #define V_PER_CAL_DIV(x) ((x) << S_PER_CAL_DIV)
2895 #define G_PER_CAL_DIV(x) (((x) >> S_PER_CAL_DIV) & M_PER_CAL_DIV)
2896 
2897 #define S_PER_CAL_EN    21
2898 #define V_PER_CAL_EN(x) ((x) << S_PER_CAL_EN)
2899 #define F_PER_CAL_EN    V_PER_CAL_EN(1U)
2900 
2901 #define S_SGL_CAL_EN    20
2902 #define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN)
2903 #define F_SGL_CAL_EN    V_SGL_CAL_EN(1U)
2904 
2905 #define S_IMP_UPD_MODE    19
2906 #define V_IMP_UPD_MODE(x) ((x) << S_IMP_UPD_MODE)
2907 #define F_IMP_UPD_MODE    V_IMP_UPD_MODE(1U)
2908 
2909 #define S_IMP_SEL    18
2910 #define V_IMP_SEL(x) ((x) << S_IMP_SEL)
2911 #define F_IMP_SEL    V_IMP_SEL(1U)
2912 
2913 #define S_IMP_MAN_PD    15
2914 #define M_IMP_MAN_PD    0x7
2915 #define V_IMP_MAN_PD(x) ((x) << S_IMP_MAN_PD)
2916 #define G_IMP_MAN_PD(x) (((x) >> S_IMP_MAN_PD) & M_IMP_MAN_PD)
2917 
2918 #define S_IMP_MAN_PU    12
2919 #define M_IMP_MAN_PU    0x7
2920 #define V_IMP_MAN_PU(x) ((x) << S_IMP_MAN_PU)
2921 #define G_IMP_MAN_PU(x) (((x) >> S_IMP_MAN_PU) & M_IMP_MAN_PU)
2922 
2923 #define S_IMP_CAL_PD    9
2924 #define M_IMP_CAL_PD    0x7
2925 #define V_IMP_CAL_PD(x) ((x) << S_IMP_CAL_PD)
2926 #define G_IMP_CAL_PD(x) (((x) >> S_IMP_CAL_PD) & M_IMP_CAL_PD)
2927 
2928 #define S_IMP_CAL_PU    6
2929 #define M_IMP_CAL_PU    0x7
2930 #define V_IMP_CAL_PU(x) ((x) << S_IMP_CAL_PU)
2931 #define G_IMP_CAL_PU(x) (((x) >> S_IMP_CAL_PU) & M_IMP_CAL_PU)
2932 
2933 #define S_IMP_SET_PD    3
2934 #define M_IMP_SET_PD    0x7
2935 #define V_IMP_SET_PD(x) ((x) << S_IMP_SET_PD)
2936 #define G_IMP_SET_PD(x) (((x) >> S_IMP_SET_PD) & M_IMP_SET_PD)
2937 
2938 #define S_IMP_SET_PU    0
2939 #define M_IMP_SET_PU    0x7
2940 #define V_IMP_SET_PU(x) ((x) << S_IMP_SET_PU)
2941 #define G_IMP_SET_PU(x) (((x) >> S_IMP_SET_PU) & M_IMP_SET_PU)
2942 
2943 #define A_MC7_ERR_ADDR 0x12c
2944 
2945 #define S_ERRADDRESS    3
2946 #define M_ERRADDRESS    0x1fffffff
2947 #define V_ERRADDRESS(x) ((x) << S_ERRADDRESS)
2948 #define G_ERRADDRESS(x) (((x) >> S_ERRADDRESS) & M_ERRADDRESS)
2949 
2950 #define S_ERRAGENT    1
2951 #define M_ERRAGENT    0x3
2952 #define V_ERRAGENT(x) ((x) << S_ERRAGENT)
2953 #define G_ERRAGENT(x) (((x) >> S_ERRAGENT) & M_ERRAGENT)
2954 
2955 #define S_ERROP    0
2956 #define V_ERROP(x) ((x) << S_ERROP)
2957 #define F_ERROP    V_ERROP(1U)
2958 
2959 #define A_MC7_ECC 0x130
2960 
2961 #define S_UECNT    10
2962 #define M_UECNT    0xff
2963 #define V_UECNT(x) ((x) << S_UECNT)
2964 #define G_UECNT(x) (((x) >> S_UECNT) & M_UECNT)
2965 
2966 #define S_CECNT    2
2967 #define M_CECNT    0xff
2968 #define V_CECNT(x) ((x) << S_CECNT)
2969 #define G_CECNT(x) (((x) >> S_CECNT) & M_CECNT)
2970 
2971 #define S_ECCCHKEN    1
2972 #define V_ECCCHKEN(x) ((x) << S_ECCCHKEN)
2973 #define F_ECCCHKEN    V_ECCCHKEN(1U)
2974 
2975 #define S_ECCGENEN    0
2976 #define V_ECCGENEN(x) ((x) << S_ECCGENEN)
2977 #define F_ECCGENEN    V_ECCGENEN(1U)
2978 
2979 #define A_MC7_CE_ADDR 0x134
2980 #define A_MC7_CE_DATA0 0x138
2981 #define A_MC7_CE_DATA1 0x13c
2982 #define A_MC7_CE_DATA2 0x140
2983 
2984 #define S_DATA    0
2985 #define M_DATA    0xff
2986 #define V_DATA(x) ((x) << S_DATA)
2987 #define G_DATA(x) (((x) >> S_DATA) & M_DATA)
2988 
2989 #define A_MC7_UE_ADDR 0x144
2990 #define A_MC7_UE_DATA0 0x148
2991 #define A_MC7_UE_DATA1 0x14c
2992 #define A_MC7_UE_DATA2 0x150
2993 #define A_MC7_BD_ADDR 0x154
2994 
2995 #define S_ADDR    3
2996 #define M_ADDR    0x1fffffff
2997 #define V_ADDR(x) ((x) << S_ADDR)
2998 #define G_ADDR(x) (((x) >> S_ADDR) & M_ADDR)
2999 
3000 #define A_MC7_BD_DATA0 0x158
3001 #define A_MC7_BD_DATA1 0x15c
3002 #define A_MC7_BD_DATA2 0x160
3003 #define A_MC7_BD_OP 0x164
3004 
3005 #define S_OP    0
3006 #define V_OP(x) ((x) << S_OP)
3007 #define F_OP    V_OP(1U)
3008 
3009 #define A_MC7_BIST_ADDR_BEG 0x168
3010 
3011 #define S_ADDRBEG    5
3012 #define M_ADDRBEG    0x7ffffff
3013 #define V_ADDRBEG(x) ((x) << S_ADDRBEG)
3014 #define G_ADDRBEG(x) (((x) >> S_ADDRBEG) & M_ADDRBEG)
3015 
3016 #define A_MC7_BIST_ADDR_END 0x16c
3017 
3018 #define S_ADDREND    5
3019 #define M_ADDREND    0x7ffffff
3020 #define V_ADDREND(x) ((x) << S_ADDREND)
3021 #define G_ADDREND(x) (((x) >> S_ADDREND) & M_ADDREND)
3022 
3023 #define A_MC7_BIST_DATA 0x170
3024 #define A_MC7_BIST_OP 0x174
3025 
3026 #define S_GAP    4
3027 #define M_GAP    0x1f
3028 #define V_GAP(x) ((x) << S_GAP)
3029 #define G_GAP(x) (((x) >> S_GAP) & M_GAP)
3030 
3031 #define S_CONT    3
3032 #define V_CONT(x) ((x) << S_CONT)
3033 #define F_CONT    V_CONT(1U)
3034 
3035 #define S_DATAPAT    1
3036 #define M_DATAPAT    0x3
3037 #define V_DATAPAT(x) ((x) << S_DATAPAT)
3038 #define G_DATAPAT(x) (((x) >> S_DATAPAT) & M_DATAPAT)
3039 
3040 #define A_MC7_INT_ENABLE 0x178
3041 
3042 #define S_AE    17
3043 #define V_AE(x) ((x) << S_AE)
3044 #define F_AE    V_AE(1U)
3045 
3046 #define S_PE    2
3047 #define M_PE    0x7fff
3048 #define V_PE(x) ((x) << S_PE)
3049 #define G_PE(x) (((x) >> S_PE) & M_PE)
3050 
3051 #define S_UE    1
3052 #define V_UE(x) ((x) << S_UE)
3053 #define F_UE    V_UE(1U)
3054 
3055 #define S_CE    0
3056 #define V_CE(x) ((x) << S_CE)
3057 #define F_CE    V_CE(1U)
3058 
3059 #define A_MC7_INT_CAUSE 0x17c
3060 
3061 /* registers for module MC7_PMTX */
3062 #define MC7_PMTX_BASE_ADDR 0x180
3063 
3064 /* registers for module MC7_CM */
3065 #define MC7_CM_BASE_ADDR 0x200
3066 
3067 /* registers for module CIM */
3068 #define CIM_BASE_ADDR 0x280
3069 
3070 #define A_CIM_BOOT_CFG 0x280
3071 
3072 #define S_BOOTADDR    2
3073 #define M_BOOTADDR    0x3fffffff
3074 #define V_BOOTADDR(x) ((x) << S_BOOTADDR)
3075 #define G_BOOTADDR(x) (((x) >> S_BOOTADDR) & M_BOOTADDR)
3076 
3077 #define S_BOOTSDRAM    1
3078 #define V_BOOTSDRAM(x) ((x) << S_BOOTSDRAM)
3079 #define F_BOOTSDRAM    V_BOOTSDRAM(1U)
3080 
3081 #define S_UPCRST    0
3082 #define V_UPCRST(x) ((x) << S_UPCRST)
3083 #define F_UPCRST    V_UPCRST(1U)
3084 
3085 #define A_CIM_FLASH_BASE_ADDR 0x284
3086 
3087 #define S_FLASHBASEADDR    2
3088 #define M_FLASHBASEADDR    0x3fffff
3089 #define V_FLASHBASEADDR(x) ((x) << S_FLASHBASEADDR)
3090 #define G_FLASHBASEADDR(x) (((x) >> S_FLASHBASEADDR) & M_FLASHBASEADDR)
3091 
3092 #define A_CIM_FLASH_ADDR_SIZE 0x288
3093 
3094 #define S_FLASHADDRSIZE    2
3095 #define M_FLASHADDRSIZE    0x3fffff
3096 #define V_FLASHADDRSIZE(x) ((x) << S_FLASHADDRSIZE)
3097 #define G_FLASHADDRSIZE(x) (((x) >> S_FLASHADDRSIZE) & M_FLASHADDRSIZE)
3098 
3099 #define A_CIM_SDRAM_BASE_ADDR 0x28c
3100 
3101 #define S_SDRAMBASEADDR    2
3102 #define M_SDRAMBASEADDR    0x3fffffff
3103 #define V_SDRAMBASEADDR(x) ((x) << S_SDRAMBASEADDR)
3104 #define G_SDRAMBASEADDR(x) (((x) >> S_SDRAMBASEADDR) & M_SDRAMBASEADDR)
3105 
3106 #define A_CIM_SDRAM_ADDR_SIZE 0x290
3107 
3108 #define S_SDRAMADDRSIZE    2
3109 #define M_SDRAMADDRSIZE    0x3fffffff
3110 #define V_SDRAMADDRSIZE(x) ((x) << S_SDRAMADDRSIZE)
3111 #define G_SDRAMADDRSIZE(x) (((x) >> S_SDRAMADDRSIZE) & M_SDRAMADDRSIZE)
3112 
3113 #define A_CIM_UP_SPARE_INT 0x294
3114 
3115 #define S_UPSPAREINT    0
3116 #define M_UPSPAREINT    0x7
3117 #define V_UPSPAREINT(x) ((x) << S_UPSPAREINT)
3118 #define G_UPSPAREINT(x) (((x) >> S_UPSPAREINT) & M_UPSPAREINT)
3119 
3120 #define A_CIM_HOST_INT_ENABLE 0x298
3121 
3122 #define S_DTAGPARERR    28
3123 #define V_DTAGPARERR(x) ((x) << S_DTAGPARERR)
3124 #define F_DTAGPARERR    V_DTAGPARERR(1U)
3125 
3126 #define S_ITAGPARERR    27
3127 #define V_ITAGPARERR(x) ((x) << S_ITAGPARERR)
3128 #define F_ITAGPARERR    V_ITAGPARERR(1U)
3129 
3130 #define S_IBQTPPARERR    26
3131 #define V_IBQTPPARERR(x) ((x) << S_IBQTPPARERR)
3132 #define F_IBQTPPARERR    V_IBQTPPARERR(1U)
3133 
3134 #define S_IBQULPPARERR    25
3135 #define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR)
3136 #define F_IBQULPPARERR    V_IBQULPPARERR(1U)
3137 
3138 #define S_IBQSGEHIPARERR    24
3139 #define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR)
3140 #define F_IBQSGEHIPARERR    V_IBQSGEHIPARERR(1U)
3141 
3142 #define S_IBQSGELOPARERR    23
3143 #define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR)
3144 #define F_IBQSGELOPARERR    V_IBQSGELOPARERR(1U)
3145 
3146 #define S_OBQULPLOPARERR    22
3147 #define V_OBQULPLOPARERR(x) ((x) << S_OBQULPLOPARERR)
3148 #define F_OBQULPLOPARERR    V_OBQULPLOPARERR(1U)
3149 
3150 #define S_OBQULPHIPARERR    21
3151 #define V_OBQULPHIPARERR(x) ((x) << S_OBQULPHIPARERR)
3152 #define F_OBQULPHIPARERR    V_OBQULPHIPARERR(1U)
3153 
3154 #define S_OBQSGEPARERR    20
3155 #define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR)
3156 #define F_OBQSGEPARERR    V_OBQSGEPARERR(1U)
3157 
3158 #define S_DCACHEPARERR    19
3159 #define V_DCACHEPARERR(x) ((x) << S_DCACHEPARERR)
3160 #define F_DCACHEPARERR    V_DCACHEPARERR(1U)
3161 
3162 #define S_ICACHEPARERR    18
3163 #define V_ICACHEPARERR(x) ((x) << S_ICACHEPARERR)
3164 #define F_ICACHEPARERR    V_ICACHEPARERR(1U)
3165 
3166 #define S_DRAMPARERR    17
3167 #define V_DRAMPARERR(x) ((x) << S_DRAMPARERR)
3168 #define F_DRAMPARERR    V_DRAMPARERR(1U)
3169 
3170 #define S_TIMER1INTEN    15
3171 #define V_TIMER1INTEN(x) ((x) << S_TIMER1INTEN)
3172 #define F_TIMER1INTEN    V_TIMER1INTEN(1U)
3173 
3174 #define S_TIMER0INTEN    14
3175 #define V_TIMER0INTEN(x) ((x) << S_TIMER0INTEN)
3176 #define F_TIMER0INTEN    V_TIMER0INTEN(1U)
3177 
3178 #define S_PREFDROPINTEN    13
3179 #define V_PREFDROPINTEN(x) ((x) << S_PREFDROPINTEN)
3180 #define F_PREFDROPINTEN    V_PREFDROPINTEN(1U)
3181 
3182 #define S_BLKWRPLINTEN    12
3183 #define V_BLKWRPLINTEN(x) ((x) << S_BLKWRPLINTEN)
3184 #define F_BLKWRPLINTEN    V_BLKWRPLINTEN(1U)
3185 
3186 #define S_BLKRDPLINTEN    11
3187 #define V_BLKRDPLINTEN(x) ((x) << S_BLKRDPLINTEN)
3188 #define F_BLKRDPLINTEN    V_BLKRDPLINTEN(1U)
3189 
3190 #define S_BLKWRCTLINTEN    10
3191 #define V_BLKWRCTLINTEN(x) ((x) << S_BLKWRCTLINTEN)
3192 #define F_BLKWRCTLINTEN    V_BLKWRCTLINTEN(1U)
3193 
3194 #define S_BLKRDCTLINTEN    9
3195 #define V_BLKRDCTLINTEN(x) ((x) << S_BLKRDCTLINTEN)
3196 #define F_BLKRDCTLINTEN    V_BLKRDCTLINTEN(1U)
3197 
3198 #define S_BLKWRFLASHINTEN    8
3199 #define V_BLKWRFLASHINTEN(x) ((x) << S_BLKWRFLASHINTEN)
3200 #define F_BLKWRFLASHINTEN    V_BLKWRFLASHINTEN(1U)
3201 
3202 #define S_BLKRDFLASHINTEN    7
3203 #define V_BLKRDFLASHINTEN(x) ((x) << S_BLKRDFLASHINTEN)
3204 #define F_BLKRDFLASHINTEN    V_BLKRDFLASHINTEN(1U)
3205 
3206 #define S_SGLWRFLASHINTEN    6
3207 #define V_SGLWRFLASHINTEN(x) ((x) << S_SGLWRFLASHINTEN)
3208 #define F_SGLWRFLASHINTEN    V_SGLWRFLASHINTEN(1U)
3209 
3210 #define S_WRBLKFLASHINTEN    5
3211 #define V_WRBLKFLASHINTEN(x) ((x) << S_WRBLKFLASHINTEN)
3212 #define F_WRBLKFLASHINTEN    V_WRBLKFLASHINTEN(1U)
3213 
3214 #define S_BLKWRBOOTINTEN    4
3215 #define V_BLKWRBOOTINTEN(x) ((x) << S_BLKWRBOOTINTEN)
3216 #define F_BLKWRBOOTINTEN    V_BLKWRBOOTINTEN(1U)
3217 
3218 #define S_BLKRDBOOTINTEN    3
3219 #define V_BLKRDBOOTINTEN(x) ((x) << S_BLKRDBOOTINTEN)
3220 #define F_BLKRDBOOTINTEN    V_BLKRDBOOTINTEN(1U)
3221 
3222 #define S_FLASHRANGEINTEN    2
3223 #define V_FLASHRANGEINTEN(x) ((x) << S_FLASHRANGEINTEN)
3224 #define F_FLASHRANGEINTEN    V_FLASHRANGEINTEN(1U)
3225 
3226 #define S_SDRAMRANGEINTEN    1
3227 #define V_SDRAMRANGEINTEN(x) ((x) << S_SDRAMRANGEINTEN)
3228 #define F_SDRAMRANGEINTEN    V_SDRAMRANGEINTEN(1U)
3229 
3230 #define S_RSVDSPACEINTEN    0
3231 #define V_RSVDSPACEINTEN(x) ((x) << S_RSVDSPACEINTEN)
3232 #define F_RSVDSPACEINTEN    V_RSVDSPACEINTEN(1U)
3233 
3234 #define A_CIM_HOST_INT_CAUSE 0x29c
3235 
3236 #define S_TIMER1INT    15
3237 #define V_TIMER1INT(x) ((x) << S_TIMER1INT)
3238 #define F_TIMER1INT    V_TIMER1INT(1U)
3239 
3240 #define S_TIMER0INT    14
3241 #define V_TIMER0INT(x) ((x) << S_TIMER0INT)
3242 #define F_TIMER0INT    V_TIMER0INT(1U)
3243 
3244 #define S_PREFDROPINT    13
3245 #define V_PREFDROPINT(x) ((x) << S_PREFDROPINT)
3246 #define F_PREFDROPINT    V_PREFDROPINT(1U)
3247 
3248 #define S_BLKWRPLINT    12
3249 #define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT)
3250 #define F_BLKWRPLINT    V_BLKWRPLINT(1U)
3251 
3252 #define S_BLKRDPLINT    11
3253 #define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT)
3254 #define F_BLKRDPLINT    V_BLKRDPLINT(1U)
3255 
3256 #define S_BLKWRCTLINT    10
3257 #define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT)
3258 #define F_BLKWRCTLINT    V_BLKWRCTLINT(1U)
3259 
3260 #define S_BLKRDCTLINT    9
3261 #define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT)
3262 #define F_BLKRDCTLINT    V_BLKRDCTLINT(1U)
3263 
3264 #define S_BLKWRFLASHINT    8
3265 #define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT)
3266 #define F_BLKWRFLASHINT    V_BLKWRFLASHINT(1U)
3267 
3268 #define S_BLKRDFLASHINT    7
3269 #define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT)
3270 #define F_BLKRDFLASHINT    V_BLKRDFLASHINT(1U)
3271 
3272 #define S_SGLWRFLASHINT    6
3273 #define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT)
3274 #define F_SGLWRFLASHINT    V_SGLWRFLASHINT(1U)
3275 
3276 #define S_WRBLKFLASHINT    5
3277 #define V_WRBLKFLASHINT(x) ((x) << S_WRBLKFLASHINT)
3278 #define F_WRBLKFLASHINT    V_WRBLKFLASHINT(1U)
3279 
3280 #define S_BLKWRBOOTINT    4
3281 #define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT)
3282 #define F_BLKWRBOOTINT    V_BLKWRBOOTINT(1U)
3283 
3284 #define S_BLKRDBOOTINT    3
3285 #define V_BLKRDBOOTINT(x) ((x) << S_BLKRDBOOTINT)
3286 #define F_BLKRDBOOTINT    V_BLKRDBOOTINT(1U)
3287 
3288 #define S_FLASHRANGEINT    2
3289 #define V_FLASHRANGEINT(x) ((x) << S_FLASHRANGEINT)
3290 #define F_FLASHRANGEINT    V_FLASHRANGEINT(1U)
3291 
3292 #define S_SDRAMRANGEINT    1
3293 #define V_SDRAMRANGEINT(x) ((x) << S_SDRAMRANGEINT)
3294 #define F_SDRAMRANGEINT    V_SDRAMRANGEINT(1U)
3295 
3296 #define S_RSVDSPACEINT    0
3297 #define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT)
3298 #define F_RSVDSPACEINT    V_RSVDSPACEINT(1U)
3299 
3300 #define A_CIM_UP_INT_ENABLE 0x2a0
3301 
3302 #define S_MSTPLINTEN    16
3303 #define V_MSTPLINTEN(x) ((x) << S_MSTPLINTEN)
3304 #define F_MSTPLINTEN    V_MSTPLINTEN(1U)
3305 
3306 #define A_CIM_UP_INT_CAUSE 0x2a4
3307 
3308 #define S_MSTPLINT    16
3309 #define V_MSTPLINT(x) ((x) << S_MSTPLINT)
3310 #define F_MSTPLINT    V_MSTPLINT(1U)
3311 
3312 #define A_CIM_IBQ_FULLA_THRSH 0x2a8
3313 
3314 #define S_IBQ0FULLTHRSH    0
3315 #define M_IBQ0FULLTHRSH    0x1ff
3316 #define V_IBQ0FULLTHRSH(x) ((x) << S_IBQ0FULLTHRSH)
3317 #define G_IBQ0FULLTHRSH(x) (((x) >> S_IBQ0FULLTHRSH) & M_IBQ0FULLTHRSH)
3318 
3319 #define S_IBQ1FULLTHRSH    16
3320 #define M_IBQ1FULLTHRSH    0x1ff
3321 #define V_IBQ1FULLTHRSH(x) ((x) << S_IBQ1FULLTHRSH)
3322 #define G_IBQ1FULLTHRSH(x) (((x) >> S_IBQ1FULLTHRSH) & M_IBQ1FULLTHRSH)
3323 
3324 #define A_CIM_IBQ_FULLB_THRSH 0x2ac
3325 
3326 #define S_IBQ2FULLTHRSH    0
3327 #define M_IBQ2FULLTHRSH    0x1ff
3328 #define V_IBQ2FULLTHRSH(x) ((x) << S_IBQ2FULLTHRSH)
3329 #define G_IBQ2FULLTHRSH(x) (((x) >> S_IBQ2FULLTHRSH) & M_IBQ2FULLTHRSH)
3330 
3331 #define S_IBQ3FULLTHRSH    16
3332 #define M_IBQ3FULLTHRSH    0x1ff
3333 #define V_IBQ3FULLTHRSH(x) ((x) << S_IBQ3FULLTHRSH)
3334 #define G_IBQ3FULLTHRSH(x) (((x) >> S_IBQ3FULLTHRSH) & M_IBQ3FULLTHRSH)
3335 
3336 #define A_CIM_HOST_ACC_CTRL 0x2b0
3337 
3338 #define S_HOSTBUSY    17
3339 #define V_HOSTBUSY(x) ((x) << S_HOSTBUSY)
3340 #define F_HOSTBUSY    V_HOSTBUSY(1U)
3341 
3342 #define S_HOSTWRITE    16
3343 #define V_HOSTWRITE(x) ((x) << S_HOSTWRITE)
3344 #define F_HOSTWRITE    V_HOSTWRITE(1U)
3345 
3346 #define S_HOSTADDR    0
3347 #define M_HOSTADDR    0xffff
3348 #define V_HOSTADDR(x) ((x) << S_HOSTADDR)
3349 #define G_HOSTADDR(x) (((x) >> S_HOSTADDR) & M_HOSTADDR)
3350 
3351 #define A_CIM_HOST_ACC_DATA 0x2b4
3352 #define A_CIM_IBQ_DBG_CFG 0x2c0
3353 
3354 #define S_IBQDBGADDR    16
3355 #define M_IBQDBGADDR    0x1ff
3356 #define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR)
3357 #define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR)
3358 
3359 #define S_IBQDBGQID    3
3360 #define M_IBQDBGQID    0x3
3361 #define V_IBQDBGQID(x) ((x) << S_IBQDBGQID)
3362 #define G_IBQDBGQID(x) (((x) >> S_IBQDBGQID) & M_IBQDBGQID)
3363 
3364 #define S_IBQDBGWR    2
3365 #define V_IBQDBGWR(x) ((x) << S_IBQDBGWR)
3366 #define F_IBQDBGWR    V_IBQDBGWR(1U)
3367 
3368 #define S_IBQDBGBUSY    1
3369 #define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY)
3370 #define F_IBQDBGBUSY    V_IBQDBGBUSY(1U)
3371 
3372 #define S_IBQDBGEN    0
3373 #define V_IBQDBGEN(x) ((x) << S_IBQDBGEN)
3374 #define F_IBQDBGEN    V_IBQDBGEN(1U)
3375 
3376 #define A_CIM_OBQ_DBG_CFG 0x2c4
3377 
3378 #define S_OBQDBGADDR    16
3379 #define M_OBQDBGADDR    0x1ff
3380 #define V_OBQDBGADDR(x) ((x) << S_OBQDBGADDR)
3381 #define G_OBQDBGADDR(x) (((x) >> S_OBQDBGADDR) & M_OBQDBGADDR)
3382 
3383 #define S_OBQDBGQID    3
3384 #define M_OBQDBGQID    0x3
3385 #define V_OBQDBGQID(x) ((x) << S_OBQDBGQID)
3386 #define G_OBQDBGQID(x) (((x) >> S_OBQDBGQID) & M_OBQDBGQID)
3387 
3388 #define S_OBQDBGWR    2
3389 #define V_OBQDBGWR(x) ((x) << S_OBQDBGWR)
3390 #define F_OBQDBGWR    V_OBQDBGWR(1U)
3391 
3392 #define S_OBQDBGBUSY    1
3393 #define V_OBQDBGBUSY(x) ((x) << S_OBQDBGBUSY)
3394 #define F_OBQDBGBUSY    V_OBQDBGBUSY(1U)
3395 
3396 #define S_OBQDBGEN    0
3397 #define V_OBQDBGEN(x) ((x) << S_OBQDBGEN)
3398 #define F_OBQDBGEN    V_OBQDBGEN(1U)
3399 
3400 #define A_CIM_IBQ_DBG_DATA 0x2c8
3401 #define A_CIM_OBQ_DBG_DATA 0x2cc
3402 #define A_CIM_CDEBUGDATA 0x2d0
3403 
3404 #define S_CDEBUGDATAH    16
3405 #define M_CDEBUGDATAH    0xffff
3406 #define V_CDEBUGDATAH(x) ((x) << S_CDEBUGDATAH)
3407 #define G_CDEBUGDATAH(x) (((x) >> S_CDEBUGDATAH) & M_CDEBUGDATAH)
3408 
3409 #define S_CDEBUGDATAL    0
3410 #define M_CDEBUGDATAL    0xffff
3411 #define V_CDEBUGDATAL(x) ((x) << S_CDEBUGDATAL)
3412 #define G_CDEBUGDATAL(x) (((x) >> S_CDEBUGDATAL) & M_CDEBUGDATAL)
3413 
3414 #define A_CIM_DEBUGCFG 0x2e0
3415 
3416 #define S_POLADBGRDPTR    23
3417 #define M_POLADBGRDPTR    0x1ff
3418 #define V_POLADBGRDPTR(x) ((x) << S_POLADBGRDPTR)
3419 #define G_POLADBGRDPTR(x) (((x) >> S_POLADBGRDPTR) & M_POLADBGRDPTR)
3420 
3421 #define S_PILADBGRDPTR    14
3422 #define M_PILADBGRDPTR    0x1ff
3423 #define V_PILADBGRDPTR(x) ((x) << S_PILADBGRDPTR)
3424 #define G_PILADBGRDPTR(x) (((x) >> S_PILADBGRDPTR) & M_PILADBGRDPTR)
3425 
3426 #define S_CIM_LADBGEN    12
3427 #define V_CIM_LADBGEN(x) ((x) << S_CIM_LADBGEN)
3428 #define F_CIM_LADBGEN    V_CIM_LADBGEN(1U)
3429 
3430 #define S_DEBUGSELHI    5
3431 #define M_DEBUGSELHI    0x1f
3432 #define V_DEBUGSELHI(x) ((x) << S_DEBUGSELHI)
3433 #define G_DEBUGSELHI(x) (((x) >> S_DEBUGSELHI) & M_DEBUGSELHI)
3434 
3435 #define S_DEBUGSELLO    0
3436 #define M_DEBUGSELLO    0x1f
3437 #define V_DEBUGSELLO(x) ((x) << S_DEBUGSELLO)
3438 #define G_DEBUGSELLO(x) (((x) >> S_DEBUGSELLO) & M_DEBUGSELLO)
3439 
3440 #define A_CIM_DEBUGSTS 0x2e4
3441 
3442 #define S_POLADBGWRPTR    16
3443 #define M_POLADBGWRPTR    0x1ff
3444 #define V_POLADBGWRPTR(x) ((x) << S_POLADBGWRPTR)
3445 #define G_POLADBGWRPTR(x) (((x) >> S_POLADBGWRPTR) & M_POLADBGWRPTR)
3446 
3447 #define S_PILADBGWRPTR    0
3448 #define M_PILADBGWRPTR    0x1ff
3449 #define V_PILADBGWRPTR(x) ((x) << S_PILADBGWRPTR)
3450 #define G_PILADBGWRPTR(x) (((x) >> S_PILADBGWRPTR) & M_PILADBGWRPTR)
3451 
3452 #define A_CIM_PO_LA_DEBUGDATA 0x2e8
3453 #define A_CIM_PI_LA_DEBUGDATA 0x2ec
3454 
3455 /* registers for module TP1 */
3456 #define TP1_BASE_ADDR 0x300
3457 
3458 #define A_TP_IN_CONFIG 0x300
3459 
3460 #define S_RXFBARBPRIO    25
3461 #define V_RXFBARBPRIO(x) ((x) << S_RXFBARBPRIO)
3462 #define F_RXFBARBPRIO    V_RXFBARBPRIO(1U)
3463 
3464 #define S_TXFBARBPRIO    24
3465 #define V_TXFBARBPRIO(x) ((x) << S_TXFBARBPRIO)
3466 #define F_TXFBARBPRIO    V_TXFBARBPRIO(1U)
3467 
3468 #define S_DBMAXOPCNT    16
3469 #define M_DBMAXOPCNT    0xff
3470 #define V_DBMAXOPCNT(x) ((x) << S_DBMAXOPCNT)
3471 #define G_DBMAXOPCNT(x) (((x) >> S_DBMAXOPCNT) & M_DBMAXOPCNT)
3472 
3473 #define S_IPV6ENABLE    15
3474 #define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE)
3475 #define F_IPV6ENABLE    V_IPV6ENABLE(1U)
3476 
3477 #define S_NICMODE    14
3478 #define V_NICMODE(x) ((x) << S_NICMODE)
3479 #define F_NICMODE    V_NICMODE(1U)
3480 
3481 #define S_ECHECKSUMCHECKTCP    13
3482 #define V_ECHECKSUMCHECKTCP(x) ((x) << S_ECHECKSUMCHECKTCP)
3483 #define F_ECHECKSUMCHECKTCP    V_ECHECKSUMCHECKTCP(1U)
3484 
3485 #define S_ECHECKSUMCHECKIP    12
3486 #define V_ECHECKSUMCHECKIP(x) ((x) << S_ECHECKSUMCHECKIP)
3487 #define F_ECHECKSUMCHECKIP    V_ECHECKSUMCHECKIP(1U)
3488 
3489 #define S_ECPL    10
3490 #define V_ECPL(x) ((x) << S_ECPL)
3491 #define F_ECPL    V_ECPL(1U)
3492 
3493 #define S_EETHERNET    8
3494 #define V_EETHERNET(x) ((x) << S_EETHERNET)
3495 #define F_EETHERNET    V_EETHERNET(1U)
3496 
3497 #define S_ETUNNEL    7
3498 #define V_ETUNNEL(x) ((x) << S_ETUNNEL)
3499 #define F_ETUNNEL    V_ETUNNEL(1U)
3500 
3501 #define S_CCHECKSUMCHECKTCP    6
3502 #define V_CCHECKSUMCHECKTCP(x) ((x) << S_CCHECKSUMCHECKTCP)
3503 #define F_CCHECKSUMCHECKTCP    V_CCHECKSUMCHECKTCP(1U)
3504 
3505 #define S_CCHECKSUMCHECKIP    5
3506 #define V_CCHECKSUMCHECKIP(x) ((x) << S_CCHECKSUMCHECKIP)
3507 #define F_CCHECKSUMCHECKIP    V_CCHECKSUMCHECKIP(1U)
3508 
3509 #define S_CCPL    3
3510 #define V_CCPL(x) ((x) << S_CCPL)
3511 #define F_CCPL    V_CCPL(1U)
3512 
3513 #define S_CETHERNET    1
3514 #define V_CETHERNET(x) ((x) << S_CETHERNET)
3515 #define F_CETHERNET    V_CETHERNET(1U)
3516 
3517 #define S_CTUNNEL    0
3518 #define V_CTUNNEL(x) ((x) << S_CTUNNEL)
3519 #define F_CTUNNEL    V_CTUNNEL(1U)
3520 
3521 #define A_TP_OUT_CONFIG 0x304
3522 
3523 #define S_IPIDSPLITMODE    16
3524 #define V_IPIDSPLITMODE(x) ((x) << S_IPIDSPLITMODE)
3525 #define F_IPIDSPLITMODE    V_IPIDSPLITMODE(1U)
3526 
3527 #define S_VLANEXTRACTIONENABLE2NDPORT    13
3528 #define V_VLANEXTRACTIONENABLE2NDPORT(x) ((x) << S_VLANEXTRACTIONENABLE2NDPORT)
3529 #define F_VLANEXTRACTIONENABLE2NDPORT    V_VLANEXTRACTIONENABLE2NDPORT(1U)
3530 
3531 #define S_VLANEXTRACTIONENABLE    12
3532 #define V_VLANEXTRACTIONENABLE(x) ((x) << S_VLANEXTRACTIONENABLE)
3533 #define F_VLANEXTRACTIONENABLE    V_VLANEXTRACTIONENABLE(1U)
3534 
3535 #define S_ECHECKSUMGENERATETCP    11
3536 #define V_ECHECKSUMGENERATETCP(x) ((x) << S_ECHECKSUMGENERATETCP)
3537 #define F_ECHECKSUMGENERATETCP    V_ECHECKSUMGENERATETCP(1U)
3538 
3539 #define S_ECHECKSUMGENERATEIP    10
3540 #define V_ECHECKSUMGENERATEIP(x) ((x) << S_ECHECKSUMGENERATEIP)
3541 #define F_ECHECKSUMGENERATEIP    V_ECHECKSUMGENERATEIP(1U)
3542 
3543 #define S_OUT_ECPL    8
3544 #define V_OUT_ECPL(x) ((x) << S_OUT_ECPL)
3545 #define F_OUT_ECPL    V_OUT_ECPL(1U)
3546 
3547 #define S_OUT_EETHERNET    6
3548 #define V_OUT_EETHERNET(x) ((x) << S_OUT_EETHERNET)
3549 #define F_OUT_EETHERNET    V_OUT_EETHERNET(1U)
3550 
3551 #define S_CCHECKSUMGENERATETCP    5
3552 #define V_CCHECKSUMGENERATETCP(x) ((x) << S_CCHECKSUMGENERATETCP)
3553 #define F_CCHECKSUMGENERATETCP    V_CCHECKSUMGENERATETCP(1U)
3554 
3555 #define S_CCHECKSUMGENERATEIP    4
3556 #define V_CCHECKSUMGENERATEIP(x) ((x) << S_CCHECKSUMGENERATEIP)
3557 #define F_CCHECKSUMGENERATEIP    V_CCHECKSUMGENERATEIP(1U)
3558 
3559 #define S_OUT_CCPL    2
3560 #define V_OUT_CCPL(x) ((x) << S_OUT_CCPL)
3561 #define F_OUT_CCPL    V_OUT_CCPL(1U)
3562 
3563 #define S_OUT_CETHERNET    0
3564 #define V_OUT_CETHERNET(x) ((x) << S_OUT_CETHERNET)
3565 #define F_OUT_CETHERNET    V_OUT_CETHERNET(1U)
3566 
3567 #define A_TP_GLOBAL_CONFIG 0x308
3568 
3569 #define S_SYNCOOKIEPARAMS    26
3570 #define M_SYNCOOKIEPARAMS    0x3f
3571 #define V_SYNCOOKIEPARAMS(x) ((x) << S_SYNCOOKIEPARAMS)
3572 #define G_SYNCOOKIEPARAMS(x) (((x) >> S_SYNCOOKIEPARAMS) & M_SYNCOOKIEPARAMS)
3573 
3574 #define S_RXFLOWCONTROLDISABLE    25
3575 #define V_RXFLOWCONTROLDISABLE(x) ((x) << S_RXFLOWCONTROLDISABLE)
3576 #define F_RXFLOWCONTROLDISABLE    V_RXFLOWCONTROLDISABLE(1U)
3577 
3578 #define S_TXPACINGENABLE    24
3579 #define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE)
3580 #define F_TXPACINGENABLE    V_TXPACINGENABLE(1U)
3581 
3582 #define S_ATTACKFILTERENABLE    23
3583 #define V_ATTACKFILTERENABLE(x) ((x) << S_ATTACKFILTERENABLE)
3584 #define F_ATTACKFILTERENABLE    V_ATTACKFILTERENABLE(1U)
3585 
3586 #define S_SYNCOOKIENOOPTIONS    22
3587 #define V_SYNCOOKIENOOPTIONS(x) ((x) << S_SYNCOOKIENOOPTIONS)
3588 #define F_SYNCOOKIENOOPTIONS    V_SYNCOOKIENOOPTIONS(1U)
3589 
3590 #define S_PROTECTEDMODE    21
3591 #define V_PROTECTEDMODE(x) ((x) << S_PROTECTEDMODE)
3592 #define F_PROTECTEDMODE    V_PROTECTEDMODE(1U)
3593 
3594 #define S_PINGDROP    20
3595 #define V_PINGDROP(x) ((x) << S_PINGDROP)
3596 #define F_PINGDROP    V_PINGDROP(1U)
3597 
3598 #define S_FRAGMENTDROP    19
3599 #define V_FRAGMENTDROP(x) ((x) << S_FRAGMENTDROP)
3600 #define F_FRAGMENTDROP    V_FRAGMENTDROP(1U)
3601 
3602 #define S_FIVETUPLELOOKUP    17
3603 #define M_FIVETUPLELOOKUP    0x3
3604 #define V_FIVETUPLELOOKUP(x) ((x) << S_FIVETUPLELOOKUP)
3605 #define G_FIVETUPLELOOKUP(x) (((x) >> S_FIVETUPLELOOKUP) & M_FIVETUPLELOOKUP)
3606 
3607 #define S_PATHMTU    15
3608 #define V_PATHMTU(x) ((x) << S_PATHMTU)
3609 #define F_PATHMTU    V_PATHMTU(1U)
3610 
3611 #define S_IPIDENTSPLIT    14
3612 #define V_IPIDENTSPLIT(x) ((x) << S_IPIDENTSPLIT)
3613 #define F_IPIDENTSPLIT    V_IPIDENTSPLIT(1U)
3614 
3615 #define S_IPCHECKSUMOFFLOAD    13
3616 #define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD)
3617 #define F_IPCHECKSUMOFFLOAD    V_IPCHECKSUMOFFLOAD(1U)
3618 
3619 #define S_UDPCHECKSUMOFFLOAD    12
3620 #define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD)
3621 #define F_UDPCHECKSUMOFFLOAD    V_UDPCHECKSUMOFFLOAD(1U)
3622 
3623 #define S_TCPCHECKSUMOFFLOAD    11
3624 #define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD)
3625 #define F_TCPCHECKSUMOFFLOAD    V_TCPCHECKSUMOFFLOAD(1U)
3626 
3627 #define S_QOSMAPPING    10
3628 #define V_QOSMAPPING(x) ((x) << S_QOSMAPPING)
3629 #define F_QOSMAPPING    V_QOSMAPPING(1U)
3630 
3631 #define S_TCAMSERVERUSE    8
3632 #define M_TCAMSERVERUSE    0x3
3633 #define V_TCAMSERVERUSE(x) ((x) << S_TCAMSERVERUSE)
3634 #define G_TCAMSERVERUSE(x) (((x) >> S_TCAMSERVERUSE) & M_TCAMSERVERUSE)
3635 
3636 #define S_IPTTL    0
3637 #define M_IPTTL    0xff
3638 #define V_IPTTL(x) ((x) << S_IPTTL)
3639 #define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL)
3640 
3641 #define A_TP_GLOBAL_RX_CREDIT 0x30c
3642 #define A_TP_CMM_SIZE 0x310
3643 
3644 #define S_CMMEMMGRSIZE    0
3645 #define M_CMMEMMGRSIZE    0xfffffff
3646 #define V_CMMEMMGRSIZE(x) ((x) << S_CMMEMMGRSIZE)
3647 #define G_CMMEMMGRSIZE(x) (((x) >> S_CMMEMMGRSIZE) & M_CMMEMMGRSIZE)
3648 
3649 #define A_TP_CMM_MM_BASE 0x314
3650 
3651 #define S_CMMEMMGRBASE    0
3652 #define M_CMMEMMGRBASE    0xfffffff
3653 #define V_CMMEMMGRBASE(x) ((x) << S_CMMEMMGRBASE)
3654 #define G_CMMEMMGRBASE(x) (((x) >> S_CMMEMMGRBASE) & M_CMMEMMGRBASE)
3655 
3656 #define A_TP_CMM_TIMER_BASE 0x318
3657 
3658 #define S_CMTIMERMAXNUM    28
3659 #define M_CMTIMERMAXNUM    0x3
3660 #define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM)
3661 #define G_CMTIMERMAXNUM(x) (((x) >> S_CMTIMERMAXNUM) & M_CMTIMERMAXNUM)
3662 
3663 #define S_CMTIMERBASE    0
3664 #define M_CMTIMERBASE    0xfffffff
3665 #define V_CMTIMERBASE(x) ((x) << S_CMTIMERBASE)
3666 #define G_CMTIMERBASE(x) (((x) >> S_CMTIMERBASE) & M_CMTIMERBASE)
3667 
3668 #define A_TP_PMM_SIZE 0x31c
3669 
3670 #define S_PMSIZE    0
3671 #define M_PMSIZE    0xfffffff
3672 #define V_PMSIZE(x) ((x) << S_PMSIZE)
3673 #define G_PMSIZE(x) (((x) >> S_PMSIZE) & M_PMSIZE)
3674 
3675 #define A_TP_PMM_TX_BASE 0x320
3676 #define A_TP_PMM_DEFRAG_BASE 0x324
3677 #define A_TP_PMM_RX_BASE 0x328
3678 #define A_TP_PMM_RX_PAGE_SIZE 0x32c
3679 #define A_TP_PMM_RX_MAX_PAGE 0x330
3680 
3681 #define S_PMRXMAXPAGE    0
3682 #define M_PMRXMAXPAGE    0x1fffff
3683 #define V_PMRXMAXPAGE(x) ((x) << S_PMRXMAXPAGE)
3684 #define G_PMRXMAXPAGE(x) (((x) >> S_PMRXMAXPAGE) & M_PMRXMAXPAGE)
3685 
3686 #define A_TP_PMM_TX_PAGE_SIZE 0x334
3687 #define A_TP_PMM_TX_MAX_PAGE 0x338
3688 
3689 #define S_PMTXMAXPAGE    0
3690 #define M_PMTXMAXPAGE    0x1fffff
3691 #define V_PMTXMAXPAGE(x) ((x) << S_PMTXMAXPAGE)
3692 #define G_PMTXMAXPAGE(x) (((x) >> S_PMTXMAXPAGE) & M_PMTXMAXPAGE)
3693 
3694 #define A_TP_TCP_OPTIONS 0x340
3695 
3696 #define S_MTUDEFAULT    16
3697 #define M_MTUDEFAULT    0xffff
3698 #define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT)
3699 #define G_MTUDEFAULT(x) (((x) >> S_MTUDEFAULT) & M_MTUDEFAULT)
3700 
3701 #define S_MTUENABLE    10
3702 #define V_MTUENABLE(x) ((x) << S_MTUENABLE)
3703 #define F_MTUENABLE    V_MTUENABLE(1U)
3704 
3705 #define S_SACKTX    9
3706 #define V_SACKTX(x) ((x) << S_SACKTX)
3707 #define F_SACKTX    V_SACKTX(1U)
3708 
3709 #define S_SACKRX    8
3710 #define V_SACKRX(x) ((x) << S_SACKRX)
3711 #define F_SACKRX    V_SACKRX(1U)
3712 
3713 #define S_SACKMODE    4
3714 #define M_SACKMODE    0x3
3715 #define V_SACKMODE(x) ((x) << S_SACKMODE)
3716 #define G_SACKMODE(x) (((x) >> S_SACKMODE) & M_SACKMODE)
3717 
3718 #define S_WINDOWSCALEMODE    2
3719 #define M_WINDOWSCALEMODE    0x3
3720 #define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE)
3721 #define G_WINDOWSCALEMODE(x) (((x) >> S_WINDOWSCALEMODE) & M_WINDOWSCALEMODE)
3722 
3723 #define S_TIMESTAMPSMODE    0
3724 #define M_TIMESTAMPSMODE    0x3
3725 #define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE)
3726 #define G_TIMESTAMPSMODE(x) (((x) >> S_TIMESTAMPSMODE) & M_TIMESTAMPSMODE)
3727 
3728 #define A_TP_DACK_CONFIG 0x344
3729 
3730 #define S_AUTOSTATE3    30
3731 #define M_AUTOSTATE3    0x3
3732 #define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3)
3733 #define G_AUTOSTATE3(x) (((x) >> S_AUTOSTATE3) & M_AUTOSTATE3)
3734 
3735 #define S_AUTOSTATE2    28
3736 #define M_AUTOSTATE2    0x3
3737 #define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2)
3738 #define G_AUTOSTATE2(x) (((x) >> S_AUTOSTATE2) & M_AUTOSTATE2)
3739 
3740 #define S_AUTOSTATE1    26
3741 #define M_AUTOSTATE1    0x3
3742 #define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1)
3743 #define G_AUTOSTATE1(x) (((x) >> S_AUTOSTATE1) & M_AUTOSTATE1)
3744 
3745 #define S_BYTETHRESHOLD    5
3746 #define M_BYTETHRESHOLD    0xfffff
3747 #define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD)
3748 #define G_BYTETHRESHOLD(x) (((x) >> S_BYTETHRESHOLD) & M_BYTETHRESHOLD)
3749 
3750 #define S_MSSTHRESHOLD    3
3751 #define M_MSSTHRESHOLD    0x3
3752 #define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD)
3753 #define G_MSSTHRESHOLD(x) (((x) >> S_MSSTHRESHOLD) & M_MSSTHRESHOLD)
3754 
3755 #define S_AUTOCAREFUL    2
3756 #define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL)
3757 #define F_AUTOCAREFUL    V_AUTOCAREFUL(1U)
3758 
3759 #define S_AUTOENABLE    1
3760 #define V_AUTOENABLE(x) ((x) << S_AUTOENABLE)
3761 #define F_AUTOENABLE    V_AUTOENABLE(1U)
3762 
3763 #define S_DACK_MODE    0
3764 #define V_DACK_MODE(x) ((x) << S_DACK_MODE)
3765 #define F_DACK_MODE    V_DACK_MODE(1U)
3766 
3767 #define A_TP_PC_CONFIG 0x348
3768 
3769 #define S_CMCACHEDISABLE    31
3770 #define V_CMCACHEDISABLE(x) ((x) << S_CMCACHEDISABLE)
3771 #define F_CMCACHEDISABLE    V_CMCACHEDISABLE(1U)
3772 
3773 #define S_ENABLEOCSPIFULL    30
3774 #define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL)
3775 #define F_ENABLEOCSPIFULL    V_ENABLEOCSPIFULL(1U)
3776 
3777 #define S_ENABLEFLMERRORDDP    29
3778 #define V_ENABLEFLMERRORDDP(x) ((x) << S_ENABLEFLMERRORDDP)
3779 #define F_ENABLEFLMERRORDDP    V_ENABLEFLMERRORDDP(1U)
3780 
3781 #define S_LOCKTID    28
3782 #define V_LOCKTID(x) ((x) << S_LOCKTID)
3783 #define F_LOCKTID    V_LOCKTID(1U)
3784 
3785 #define S_FIXRCVWND    27
3786 #define V_FIXRCVWND(x) ((x) << S_FIXRCVWND)
3787 #define F_FIXRCVWND    V_FIXRCVWND(1U)
3788 
3789 #define S_TXTOSQUEUEMAPMODE    26
3790 #define V_TXTOSQUEUEMAPMODE(x) ((x) << S_TXTOSQUEUEMAPMODE)
3791 #define F_TXTOSQUEUEMAPMODE    V_TXTOSQUEUEMAPMODE(1U)
3792 
3793 #define S_RDDPCONGEN    25
3794 #define V_RDDPCONGEN(x) ((x) << S_RDDPCONGEN)
3795 #define F_RDDPCONGEN    V_RDDPCONGEN(1U)
3796 
3797 #define S_ENABLEONFLYPDU    24
3798 #define V_ENABLEONFLYPDU(x) ((x) << S_ENABLEONFLYPDU)
3799 #define F_ENABLEONFLYPDU    V_ENABLEONFLYPDU(1U)
3800 
3801 #define S_ENABLEEPCMDAFULL    23
3802 #define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL)
3803 #define F_ENABLEEPCMDAFULL    V_ENABLEEPCMDAFULL(1U)
3804 
3805 #define S_MODULATEUNIONMODE    22
3806 #define V_MODULATEUNIONMODE(x) ((x) << S_MODULATEUNIONMODE)
3807 #define F_MODULATEUNIONMODE    V_MODULATEUNIONMODE(1U)
3808 
3809 #define S_TXDATAACKRATEENABLE    21
3810 #define V_TXDATAACKRATEENABLE(x) ((x) << S_TXDATAACKRATEENABLE)
3811 #define F_TXDATAACKRATEENABLE    V_TXDATAACKRATEENABLE(1U)
3812 
3813 #define S_TXDEFERENABLE    20
3814 #define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE)
3815 #define F_TXDEFERENABLE    V_TXDEFERENABLE(1U)
3816 
3817 #define S_RXCONGESTIONMODE    19
3818 #define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE)
3819 #define F_RXCONGESTIONMODE    V_RXCONGESTIONMODE(1U)
3820 
3821 #define S_HEARBEATONCEDACK    18
3822 #define V_HEARBEATONCEDACK(x) ((x) << S_HEARBEATONCEDACK)
3823 #define F_HEARBEATONCEDACK    V_HEARBEATONCEDACK(1U)
3824 
3825 #define S_HEARBEATONCEHEAP    17
3826 #define V_HEARBEATONCEHEAP(x) ((x) << S_HEARBEATONCEHEAP)
3827 #define F_HEARBEATONCEHEAP    V_HEARBEATONCEHEAP(1U)
3828 
3829 #define S_HEARBEATDACK    16
3830 #define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK)
3831 #define F_HEARBEATDACK    V_HEARBEATDACK(1U)
3832 
3833 #define S_TXCONGESTIONMODE    15
3834 #define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE)
3835 #define F_TXCONGESTIONMODE    V_TXCONGESTIONMODE(1U)
3836 
3837 #define S_ACCEPTLATESTRCVADV    14
3838 #define V_ACCEPTLATESTRCVADV(x) ((x) << S_ACCEPTLATESTRCVADV)
3839 #define F_ACCEPTLATESTRCVADV    V_ACCEPTLATESTRCVADV(1U)
3840 
3841 #define S_DISABLESYNDATA    13
3842 #define V_DISABLESYNDATA(x) ((x) << S_DISABLESYNDATA)
3843 #define F_DISABLESYNDATA    V_DISABLESYNDATA(1U)
3844 
3845 #define S_DISABLEWINDOWPSH    12
3846 #define V_DISABLEWINDOWPSH(x) ((x) << S_DISABLEWINDOWPSH)
3847 #define F_DISABLEWINDOWPSH    V_DISABLEWINDOWPSH(1U)
3848 
3849 #define S_DISABLEFINOLDDATA    11
3850 #define V_DISABLEFINOLDDATA(x) ((x) << S_DISABLEFINOLDDATA)
3851 #define F_DISABLEFINOLDDATA    V_DISABLEFINOLDDATA(1U)
3852 
3853 #define S_ENABLEFLMERROR    10
3854 #define V_ENABLEFLMERROR(x) ((x) << S_ENABLEFLMERROR)
3855 #define F_ENABLEFLMERROR    V_ENABLEFLMERROR(1U)
3856 
3857 #define S_DISABLENEXTMTU    9
3858 #define V_DISABLENEXTMTU(x) ((x) << S_DISABLENEXTMTU)
3859 #define F_DISABLENEXTMTU    V_DISABLENEXTMTU(1U)
3860 
3861 #define S_FILTERPEERFIN    8
3862 #define V_FILTERPEERFIN(x) ((x) << S_FILTERPEERFIN)
3863 #define F_FILTERPEERFIN    V_FILTERPEERFIN(1U)
3864 
3865 #define S_ENABLEFEEDBACKSEND    7
3866 #define V_ENABLEFEEDBACKSEND(x) ((x) << S_ENABLEFEEDBACKSEND)
3867 #define F_ENABLEFEEDBACKSEND    V_ENABLEFEEDBACKSEND(1U)
3868 
3869 #define S_ENABLERDMAERROR    6
3870 #define V_ENABLERDMAERROR(x) ((x) << S_ENABLERDMAERROR)
3871 #define F_ENABLERDMAERROR    V_ENABLERDMAERROR(1U)
3872 
3873 #define S_ENABLEDDPFLOWCONTROL    5
3874 #define V_ENABLEDDPFLOWCONTROL(x) ((x) << S_ENABLEDDPFLOWCONTROL)
3875 #define F_ENABLEDDPFLOWCONTROL    V_ENABLEDDPFLOWCONTROL(1U)
3876 
3877 #define S_DISABLEHELDFIN    4
3878 #define V_DISABLEHELDFIN(x) ((x) << S_DISABLEHELDFIN)
3879 #define F_DISABLEHELDFIN    V_DISABLEHELDFIN(1U)
3880 
3881 #define S_TABLELATENCYDELTA    0
3882 #define M_TABLELATENCYDELTA    0xf
3883 #define V_TABLELATENCYDELTA(x) ((x) << S_TABLELATENCYDELTA)
3884 #define G_TABLELATENCYDELTA(x) (((x) >> S_TABLELATENCYDELTA) & M_TABLELATENCYDELTA)
3885 
3886 #define A_TP_PC_CONFIG2 0x34c
3887 
3888 #define S_DISBLEDAPARBIT0    15
3889 #define V_DISBLEDAPARBIT0(x) ((x) << S_DISBLEDAPARBIT0)
3890 #define F_DISBLEDAPARBIT0    V_DISBLEDAPARBIT0(1U)
3891 
3892 #define S_ENABLEARPMISS    13
3893 #define V_ENABLEARPMISS(x) ((x) << S_ENABLEARPMISS)
3894 #define F_ENABLEARPMISS    V_ENABLEARPMISS(1U)
3895 
3896 #define S_ENABLENONOFDTNLSYN    12
3897 #define V_ENABLENONOFDTNLSYN(x) ((x) << S_ENABLENONOFDTNLSYN)
3898 #define F_ENABLENONOFDTNLSYN    V_ENABLENONOFDTNLSYN(1U)
3899 
3900 #define S_ENABLEIPV6RSS    11
3901 #define V_ENABLEIPV6RSS(x) ((x) << S_ENABLEIPV6RSS)
3902 #define F_ENABLEIPV6RSS    V_ENABLEIPV6RSS(1U)
3903 
3904 #define S_ENABLEDROPRQEMPTYPKT    10
3905 #define V_ENABLEDROPRQEMPTYPKT(x) ((x) << S_ENABLEDROPRQEMPTYPKT)
3906 #define F_ENABLEDROPRQEMPTYPKT    V_ENABLEDROPRQEMPTYPKT(1U)
3907 
3908 #define S_ENABLETXPORTFROMDA2    9
3909 #define V_ENABLETXPORTFROMDA2(x) ((x) << S_ENABLETXPORTFROMDA2)
3910 #define F_ENABLETXPORTFROMDA2    V_ENABLETXPORTFROMDA2(1U)
3911 
3912 #define S_ENABLERXPKTTMSTPRSS    8
3913 #define V_ENABLERXPKTTMSTPRSS(x) ((x) << S_ENABLERXPKTTMSTPRSS)
3914 #define F_ENABLERXPKTTMSTPRSS    V_ENABLERXPKTTMSTPRSS(1U)
3915 
3916 #define S_ENABLESNDUNAINRXDATA    7
3917 #define V_ENABLESNDUNAINRXDATA(x) ((x) << S_ENABLESNDUNAINRXDATA)
3918 #define F_ENABLESNDUNAINRXDATA    V_ENABLESNDUNAINRXDATA(1U)
3919 
3920 #define S_ENABLERXPORTFROMADDR    6
3921 #define V_ENABLERXPORTFROMADDR(x) ((x) << S_ENABLERXPORTFROMADDR)
3922 #define F_ENABLERXPORTFROMADDR    V_ENABLERXPORTFROMADDR(1U)
3923 
3924 #define S_ENABLETXPORTFROMDA    5
3925 #define V_ENABLETXPORTFROMDA(x) ((x) << S_ENABLETXPORTFROMDA)
3926 #define F_ENABLETXPORTFROMDA    V_ENABLETXPORTFROMDA(1U)
3927 
3928 #define S_ENABLECHDRAFULL    4
3929 #define V_ENABLECHDRAFULL(x) ((x) << S_ENABLECHDRAFULL)
3930 #define F_ENABLECHDRAFULL    V_ENABLECHDRAFULL(1U)
3931 
3932 #define S_ENABLENONOFDSCBBIT    3
3933 #define V_ENABLENONOFDSCBBIT(x) ((x) << S_ENABLENONOFDSCBBIT)
3934 #define F_ENABLENONOFDSCBBIT    V_ENABLENONOFDSCBBIT(1U)
3935 
3936 #define S_ENABLENONOFDTIDRSS    2
3937 #define V_ENABLENONOFDTIDRSS(x) ((x) << S_ENABLENONOFDTIDRSS)
3938 #define F_ENABLENONOFDTIDRSS    V_ENABLENONOFDTIDRSS(1U)
3939 
3940 #define S_ENABLENONOFDTCBRSS    1
3941 #define V_ENABLENONOFDTCBRSS(x) ((x) << S_ENABLENONOFDTCBRSS)
3942 #define F_ENABLENONOFDTCBRSS    V_ENABLENONOFDTCBRSS(1U)
3943 
3944 #define S_ENABLEOLDRXFORWARD    0
3945 #define V_ENABLEOLDRXFORWARD(x) ((x) << S_ENABLEOLDRXFORWARD)
3946 #define F_ENABLEOLDRXFORWARD    V_ENABLEOLDRXFORWARD(1U)
3947 
3948 #define S_CHDRAFULL    4
3949 #define V_CHDRAFULL(x) ((x) << S_CHDRAFULL)
3950 #define F_CHDRAFULL    V_CHDRAFULL(1U)
3951 
3952 #define A_TP_TCP_BACKOFF_REG0 0x350
3953 
3954 #define S_TIMERBACKOFFINDEX3    24
3955 #define M_TIMERBACKOFFINDEX3    0xff
3956 #define V_TIMERBACKOFFINDEX3(x) ((x) << S_TIMERBACKOFFINDEX3)
3957 #define G_TIMERBACKOFFINDEX3(x) (((x) >> S_TIMERBACKOFFINDEX3) & M_TIMERBACKOFFINDEX3)
3958 
3959 #define S_TIMERBACKOFFINDEX2    16
3960 #define M_TIMERBACKOFFINDEX2    0xff
3961 #define V_TIMERBACKOFFINDEX2(x) ((x) << S_TIMERBACKOFFINDEX2)
3962 #define G_TIMERBACKOFFINDEX2(x) (((x) >> S_TIMERBACKOFFINDEX2) & M_TIMERBACKOFFINDEX2)
3963 
3964 #define S_TIMERBACKOFFINDEX1    8
3965 #define M_TIMERBACKOFFINDEX1    0xff
3966 #define V_TIMERBACKOFFINDEX1(x) ((x) << S_TIMERBACKOFFINDEX1)
3967 #define G_TIMERBACKOFFINDEX1(x) (((x) >> S_TIMERBACKOFFINDEX1) & M_TIMERBACKOFFINDEX1)
3968 
3969 #define S_TIMERBACKOFFINDEX0    0
3970 #define M_TIMERBACKOFFINDEX0    0xff
3971 #define V_TIMERBACKOFFINDEX0(x) ((x) << S_TIMERBACKOFFINDEX0)
3972 #define G_TIMERBACKOFFINDEX0(x) (((x) >> S_TIMERBACKOFFINDEX0) & M_TIMERBACKOFFINDEX0)
3973 
3974 #define A_TP_TCP_BACKOFF_REG1 0x354
3975 
3976 #define S_TIMERBACKOFFINDEX7    24
3977 #define M_TIMERBACKOFFINDEX7    0xff
3978 #define V_TIMERBACKOFFINDEX7(x) ((x) << S_TIMERBACKOFFINDEX7)
3979 #define G_TIMERBACKOFFINDEX7(x) (((x) >> S_TIMERBACKOFFINDEX7) & M_TIMERBACKOFFINDEX7)
3980 
3981 #define S_TIMERBACKOFFINDEX6    16
3982 #define M_TIMERBACKOFFINDEX6    0xff
3983 #define V_TIMERBACKOFFINDEX6(x) ((x) << S_TIMERBACKOFFINDEX6)
3984 #define G_TIMERBACKOFFINDEX6(x) (((x) >> S_TIMERBACKOFFINDEX6) & M_TIMERBACKOFFINDEX6)
3985 
3986 #define S_TIMERBACKOFFINDEX5    8
3987 #define M_TIMERBACKOFFINDEX5    0xff
3988 #define V_TIMERBACKOFFINDEX5(x) ((x) << S_TIMERBACKOFFINDEX5)
3989 #define G_TIMERBACKOFFINDEX5(x) (((x) >> S_TIMERBACKOFFINDEX5) & M_TIMERBACKOFFINDEX5)
3990 
3991 #define S_TIMERBACKOFFINDEX4    0
3992 #define M_TIMERBACKOFFINDEX4    0xff
3993 #define V_TIMERBACKOFFINDEX4(x) ((x) << S_TIMERBACKOFFINDEX4)
3994 #define G_TIMERBACKOFFINDEX4(x) (((x) >> S_TIMERBACKOFFINDEX4) & M_TIMERBACKOFFINDEX4)
3995 
3996 #define A_TP_TCP_BACKOFF_REG2 0x358
3997 
3998 #define S_TIMERBACKOFFINDEX11    24
3999 #define M_TIMERBACKOFFINDEX11    0xff
4000 #define V_TIMERBACKOFFINDEX11(x) ((x) << S_TIMERBACKOFFINDEX11)
4001 #define G_TIMERBACKOFFINDEX11(x) (((x) >> S_TIMERBACKOFFINDEX11) & M_TIMERBACKOFFINDEX11)
4002 
4003 #define S_TIMERBACKOFFINDEX10    16
4004 #define M_TIMERBACKOFFINDEX10    0xff
4005 #define V_TIMERBACKOFFINDEX10(x) ((x) << S_TIMERBACKOFFINDEX10)
4006 #define G_TIMERBACKOFFINDEX10(x) (((x) >> S_TIMERBACKOFFINDEX10) & M_TIMERBACKOFFINDEX10)
4007 
4008 #define S_TIMERBACKOFFINDEX9    8
4009 #define M_TIMERBACKOFFINDEX9    0xff
4010 #define V_TIMERBACKOFFINDEX9(x) ((x) << S_TIMERBACKOFFINDEX9)
4011 #define G_TIMERBACKOFFINDEX9(x) (((x) >> S_TIMERBACKOFFINDEX9) & M_TIMERBACKOFFINDEX9)
4012 
4013 #define S_TIMERBACKOFFINDEX8    0
4014 #define M_TIMERBACKOFFINDEX8    0xff
4015 #define V_TIMERBACKOFFINDEX8(x) ((x) << S_TIMERBACKOFFINDEX8)
4016 #define G_TIMERBACKOFFINDEX8(x) (((x) >> S_TIMERBACKOFFINDEX8) & M_TIMERBACKOFFINDEX8)
4017 
4018 #define A_TP_TCP_BACKOFF_REG3 0x35c
4019 
4020 #define S_TIMERBACKOFFINDEX15    24
4021 #define M_TIMERBACKOFFINDEX15    0xff
4022 #define V_TIMERBACKOFFINDEX15(x) ((x) << S_TIMERBACKOFFINDEX15)
4023 #define G_TIMERBACKOFFINDEX15(x) (((x) >> S_TIMERBACKOFFINDEX15) & M_TIMERBACKOFFINDEX15)
4024 
4025 #define S_TIMERBACKOFFINDEX14    16
4026 #define M_TIMERBACKOFFINDEX14    0xff
4027 #define V_TIMERBACKOFFINDEX14(x) ((x) << S_TIMERBACKOFFINDEX14)
4028 #define G_TIMERBACKOFFINDEX14(x) (((x) >> S_TIMERBACKOFFINDEX14) & M_TIMERBACKOFFINDEX14)
4029 
4030 #define S_TIMERBACKOFFINDEX13    8
4031 #define M_TIMERBACKOFFINDEX13    0xff
4032 #define V_TIMERBACKOFFINDEX13(x) ((x) << S_TIMERBACKOFFINDEX13)
4033 #define G_TIMERBACKOFFINDEX13(x) (((x) >> S_TIMERBACKOFFINDEX13) & M_TIMERBACKOFFINDEX13)
4034 
4035 #define S_TIMERBACKOFFINDEX12    0
4036 #define M_TIMERBACKOFFINDEX12    0xff
4037 #define V_TIMERBACKOFFINDEX12(x) ((x) << S_TIMERBACKOFFINDEX12)
4038 #define G_TIMERBACKOFFINDEX12(x) (((x) >> S_TIMERBACKOFFINDEX12) & M_TIMERBACKOFFINDEX12)
4039 
4040 #define A_TP_PARA_REG0 0x360
4041 
4042 #define S_INITCWND    24
4043 #define M_INITCWND    0x7
4044 #define V_INITCWND(x) ((x) << S_INITCWND)
4045 #define G_INITCWND(x) (((x) >> S_INITCWND) & M_INITCWND)
4046 
4047 #define S_DUPACKTHRESH    20
4048 #define M_DUPACKTHRESH    0xf
4049 #define V_DUPACKTHRESH(x) ((x) << S_DUPACKTHRESH)
4050 #define G_DUPACKTHRESH(x) (((x) >> S_DUPACKTHRESH) & M_DUPACKTHRESH)
4051 
4052 #define A_TP_PARA_REG1 0x364
4053 
4054 #define S_INITRWND    16
4055 #define M_INITRWND    0xffff
4056 #define V_INITRWND(x) ((x) << S_INITRWND)
4057 #define G_INITRWND(x) (((x) >> S_INITRWND) & M_INITRWND)
4058 
4059 #define S_INITIALSSTHRESH    0
4060 #define M_INITIALSSTHRESH    0xffff
4061 #define V_INITIALSSTHRESH(x) ((x) << S_INITIALSSTHRESH)
4062 #define G_INITIALSSTHRESH(x) (((x) >> S_INITIALSSTHRESH) & M_INITIALSSTHRESH)
4063 
4064 #define A_TP_PARA_REG2 0x368
4065 
4066 #define S_MAXRXDATA    16
4067 #define M_MAXRXDATA    0xffff
4068 #define V_MAXRXDATA(x) ((x) << S_MAXRXDATA)
4069 #define G_MAXRXDATA(x) (((x) >> S_MAXRXDATA) & M_MAXRXDATA)
4070 
4071 #define S_RXCOALESCESIZE    0
4072 #define M_RXCOALESCESIZE    0xffff
4073 #define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE)
4074 #define G_RXCOALESCESIZE(x) (((x) >> S_RXCOALESCESIZE) & M_RXCOALESCESIZE)
4075 
4076 #define A_TP_PARA_REG3 0x36c
4077 
4078 #define S_TUNNELCNGDROP1    21
4079 #define V_TUNNELCNGDROP1(x) ((x) << S_TUNNELCNGDROP1)
4080 #define F_TUNNELCNGDROP1    V_TUNNELCNGDROP1(1U)
4081 
4082 #define S_TUNNELCNGDROP0    20
4083 #define V_TUNNELCNGDROP0(x) ((x) << S_TUNNELCNGDROP0)
4084 #define F_TUNNELCNGDROP0    V_TUNNELCNGDROP0(1U)
4085 
4086 #define S_TXDATAACKIDX    16
4087 #define M_TXDATAACKIDX    0xf
4088 #define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX)
4089 #define G_TXDATAACKIDX(x) (((x) >> S_TXDATAACKIDX) & M_TXDATAACKIDX)
4090 
4091 #define S_RXFRAGENABLE    12
4092 #define M_RXFRAGENABLE    0x7
4093 #define V_RXFRAGENABLE(x) ((x) << S_RXFRAGENABLE)
4094 #define G_RXFRAGENABLE(x) (((x) >> S_RXFRAGENABLE) & M_RXFRAGENABLE)
4095 
4096 #define S_TXPACEFIXEDSTRICT    11
4097 #define V_TXPACEFIXEDSTRICT(x) ((x) << S_TXPACEFIXEDSTRICT)
4098 #define F_TXPACEFIXEDSTRICT    V_TXPACEFIXEDSTRICT(1U)
4099 
4100 #define S_TXPACEAUTOSTRICT    10
4101 #define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT)
4102 #define F_TXPACEAUTOSTRICT    V_TXPACEAUTOSTRICT(1U)
4103 
4104 #define S_TXPACEFIXED    9
4105 #define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED)
4106 #define F_TXPACEFIXED    V_TXPACEFIXED(1U)
4107 
4108 #define S_TXPACEAUTO    8
4109 #define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO)
4110 #define F_TXPACEAUTO    V_TXPACEAUTO(1U)
4111 
4112 #define S_RXURGTUNNEL    6
4113 #define V_RXURGTUNNEL(x) ((x) << S_RXURGTUNNEL)
4114 #define F_RXURGTUNNEL    V_RXURGTUNNEL(1U)
4115 
4116 #define S_RXURGMODE    5
4117 #define V_RXURGMODE(x) ((x) << S_RXURGMODE)
4118 #define F_RXURGMODE    V_RXURGMODE(1U)
4119 
4120 #define S_TXURGMODE    4
4121 #define V_TXURGMODE(x) ((x) << S_TXURGMODE)
4122 #define F_TXURGMODE    V_TXURGMODE(1U)
4123 
4124 #define S_CNGCTRLMODE    2
4125 #define M_CNGCTRLMODE    0x3
4126 #define V_CNGCTRLMODE(x) ((x) << S_CNGCTRLMODE)
4127 #define G_CNGCTRLMODE(x) (((x) >> S_CNGCTRLMODE) & M_CNGCTRLMODE)
4128 
4129 #define S_RXCOALESCEENABLE    1
4130 #define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE)
4131 #define F_RXCOALESCEENABLE    V_RXCOALESCEENABLE(1U)
4132 
4133 #define S_RXCOALESCEPSHEN    0
4134 #define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN)
4135 #define F_RXCOALESCEPSHEN    V_RXCOALESCEPSHEN(1U)
4136 
4137 #define A_TP_PARA_REG4 0x370
4138 
4139 #define S_HIGHSPEEDCFG    24
4140 #define M_HIGHSPEEDCFG    0xff
4141 #define V_HIGHSPEEDCFG(x) ((x) << S_HIGHSPEEDCFG)
4142 #define G_HIGHSPEEDCFG(x) (((x) >> S_HIGHSPEEDCFG) & M_HIGHSPEEDCFG)
4143 
4144 #define S_NEWRENOCFG    16
4145 #define M_NEWRENOCFG    0xff
4146 #define V_NEWRENOCFG(x) ((x) << S_NEWRENOCFG)
4147 #define G_NEWRENOCFG(x) (((x) >> S_NEWRENOCFG) & M_NEWRENOCFG)
4148 
4149 #define S_TAHOECFG    8
4150 #define M_TAHOECFG    0xff
4151 #define V_TAHOECFG(x) ((x) << S_TAHOECFG)
4152 #define G_TAHOECFG(x) (((x) >> S_TAHOECFG) & M_TAHOECFG)
4153 
4154 #define S_RENOCFG    0
4155 #define M_RENOCFG    0xff
4156 #define V_RENOCFG(x) ((x) << S_RENOCFG)
4157 #define G_RENOCFG(x) (((x) >> S_RENOCFG) & M_RENOCFG)
4158 
4159 #define A_TP_PARA_REG5 0x374
4160 
4161 #define S_INDICATESIZE    16
4162 #define M_INDICATESIZE    0xffff
4163 #define V_INDICATESIZE(x) ((x) << S_INDICATESIZE)
4164 #define G_INDICATESIZE(x) (((x) >> S_INDICATESIZE) & M_INDICATESIZE)
4165 
4166 #define S_SCHDENABLE    8
4167 #define V_SCHDENABLE(x) ((x) << S_SCHDENABLE)
4168 #define F_SCHDENABLE    V_SCHDENABLE(1U)
4169 
4170 #define S_RXDDPOFFINIT    3
4171 #define V_RXDDPOFFINIT(x) ((x) << S_RXDDPOFFINIT)
4172 #define F_RXDDPOFFINIT    V_RXDDPOFFINIT(1U)
4173 
4174 #define S_ONFLYDDPENABLE    2
4175 #define V_ONFLYDDPENABLE(x) ((x) << S_ONFLYDDPENABLE)
4176 #define F_ONFLYDDPENABLE    V_ONFLYDDPENABLE(1U)
4177 
4178 #define S_DACKTIMERSPIN    1
4179 #define V_DACKTIMERSPIN(x) ((x) << S_DACKTIMERSPIN)
4180 #define F_DACKTIMERSPIN    V_DACKTIMERSPIN(1U)
4181 
4182 #define S_PUSHTIMERENABLE    0
4183 #define V_PUSHTIMERENABLE(x) ((x) << S_PUSHTIMERENABLE)
4184 #define F_PUSHTIMERENABLE    V_PUSHTIMERENABLE(1U)
4185 
4186 #define A_TP_PARA_REG6 0x378
4187 
4188 #define S_TXPDUSIZEADJ    16
4189 #define M_TXPDUSIZEADJ    0xff
4190 #define V_TXPDUSIZEADJ(x) ((x) << S_TXPDUSIZEADJ)
4191 #define G_TXPDUSIZEADJ(x) (((x) >> S_TXPDUSIZEADJ) & M_TXPDUSIZEADJ)
4192 
4193 #define S_ENABLEDEFERACK    12
4194 #define V_ENABLEDEFERACK(x) ((x) << S_ENABLEDEFERACK)
4195 #define F_ENABLEDEFERACK    V_ENABLEDEFERACK(1U)
4196 
4197 #define S_ENABLEESND    11
4198 #define V_ENABLEESND(x) ((x) << S_ENABLEESND)
4199 #define F_ENABLEESND    V_ENABLEESND(1U)
4200 
4201 #define S_ENABLECSND    10
4202 #define V_ENABLECSND(x) ((x) << S_ENABLECSND)
4203 #define F_ENABLECSND    V_ENABLECSND(1U)
4204 
4205 #define S_ENABLEPDUE    9
4206 #define V_ENABLEPDUE(x) ((x) << S_ENABLEPDUE)
4207 #define F_ENABLEPDUE    V_ENABLEPDUE(1U)
4208 
4209 #define S_ENABLEPDUC    8
4210 #define V_ENABLEPDUC(x) ((x) << S_ENABLEPDUC)
4211 #define F_ENABLEPDUC    V_ENABLEPDUC(1U)
4212 
4213 #define S_ENABLEBUFI    7
4214 #define V_ENABLEBUFI(x) ((x) << S_ENABLEBUFI)
4215 #define F_ENABLEBUFI    V_ENABLEBUFI(1U)
4216 
4217 #define S_ENABLEBUFE    6
4218 #define V_ENABLEBUFE(x) ((x) << S_ENABLEBUFE)
4219 #define F_ENABLEBUFE    V_ENABLEBUFE(1U)
4220 
4221 #define S_ENABLEDEFER    5
4222 #define V_ENABLEDEFER(x) ((x) << S_ENABLEDEFER)
4223 #define F_ENABLEDEFER    V_ENABLEDEFER(1U)
4224 
4225 #define S_ENABLECLEARRXMTOOS    4
4226 #define V_ENABLECLEARRXMTOOS(x) ((x) << S_ENABLECLEARRXMTOOS)
4227 #define F_ENABLECLEARRXMTOOS    V_ENABLECLEARRXMTOOS(1U)
4228 
4229 #define S_DISABLEPDUCNG    3
4230 #define V_DISABLEPDUCNG(x) ((x) << S_DISABLEPDUCNG)
4231 #define F_DISABLEPDUCNG    V_DISABLEPDUCNG(1U)
4232 
4233 #define S_DISABLEPDUTIMEOUT    2
4234 #define V_DISABLEPDUTIMEOUT(x) ((x) << S_DISABLEPDUTIMEOUT)
4235 #define F_DISABLEPDUTIMEOUT    V_DISABLEPDUTIMEOUT(1U)
4236 
4237 #define S_DISABLEPDURXMT    1
4238 #define V_DISABLEPDURXMT(x) ((x) << S_DISABLEPDURXMT)
4239 #define F_DISABLEPDURXMT    V_DISABLEPDURXMT(1U)
4240 
4241 #define S_DISABLEPDUXMT    0
4242 #define V_DISABLEPDUXMT(x) ((x) << S_DISABLEPDUXMT)
4243 #define F_DISABLEPDUXMT    V_DISABLEPDUXMT(1U)
4244 
4245 #define S_ENABLEEPDU    14
4246 #define V_ENABLEEPDU(x) ((x) << S_ENABLEEPDU)
4247 #define F_ENABLEEPDU    V_ENABLEEPDU(1U)
4248 
4249 #define S_T3A_ENABLEESND    13
4250 #define V_T3A_ENABLEESND(x) ((x) << S_T3A_ENABLEESND)
4251 #define F_T3A_ENABLEESND    V_T3A_ENABLEESND(1U)
4252 
4253 #define S_T3A_ENABLECSND    12
4254 #define V_T3A_ENABLECSND(x) ((x) << S_T3A_ENABLECSND)
4255 #define F_T3A_ENABLECSND    V_T3A_ENABLECSND(1U)
4256 
4257 #define S_T3A_ENABLEDEFERACK    9
4258 #define V_T3A_ENABLEDEFERACK(x) ((x) << S_T3A_ENABLEDEFERACK)
4259 #define F_T3A_ENABLEDEFERACK    V_T3A_ENABLEDEFERACK(1U)
4260 
4261 #define S_ENABLEPDUI    7
4262 #define V_ENABLEPDUI(x) ((x) << S_ENABLEPDUI)
4263 #define F_ENABLEPDUI    V_ENABLEPDUI(1U)
4264 
4265 #define S_T3A_ENABLEPDUE    6
4266 #define V_T3A_ENABLEPDUE(x) ((x) << S_T3A_ENABLEPDUE)
4267 #define F_T3A_ENABLEPDUE    V_T3A_ENABLEPDUE(1U)
4268 
4269 #define A_TP_PARA_REG7 0x37c
4270 
4271 #define S_PMMAXXFERLEN1    16
4272 #define M_PMMAXXFERLEN1    0xffff
4273 #define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1)
4274 #define G_PMMAXXFERLEN1(x) (((x) >> S_PMMAXXFERLEN1) & M_PMMAXXFERLEN1)
4275 
4276 #define S_PMMAXXFERLEN0    0
4277 #define M_PMMAXXFERLEN0    0xffff
4278 #define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0)
4279 #define G_PMMAXXFERLEN0(x) (((x) >> S_PMMAXXFERLEN0) & M_PMMAXXFERLEN0)
4280 
4281 #define A_TP_TIMER_RESOLUTION 0x390
4282 
4283 #define S_TIMERRESOLUTION    16
4284 #define M_TIMERRESOLUTION    0xff
4285 #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
4286 #define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION)
4287 
4288 #define S_TIMESTAMPRESOLUTION    8
4289 #define M_TIMESTAMPRESOLUTION    0xff
4290 #define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION)
4291 #define G_TIMESTAMPRESOLUTION(x) (((x) >> S_TIMESTAMPRESOLUTION) & M_TIMESTAMPRESOLUTION)
4292 
4293 #define S_DELAYEDACKRESOLUTION    0
4294 #define M_DELAYEDACKRESOLUTION    0xff
4295 #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
4296 #define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION)
4297 
4298 #define A_TP_MSL 0x394
4299 
4300 #define S_MSL    0
4301 #define M_MSL    0x3fffffff
4302 #define V_MSL(x) ((x) << S_MSL)
4303 #define G_MSL(x) (((x) >> S_MSL) & M_MSL)
4304 
4305 #define A_TP_RXT_MIN 0x398
4306 
4307 #define S_RXTMIN    0
4308 #define M_RXTMIN    0x3fffffff
4309 #define V_RXTMIN(x) ((x) << S_RXTMIN)
4310 #define G_RXTMIN(x) (((x) >> S_RXTMIN) & M_RXTMIN)
4311 
4312 #define A_TP_RXT_MAX 0x39c
4313 
4314 #define S_RXTMAX    0
4315 #define M_RXTMAX    0x3fffffff
4316 #define V_RXTMAX(x) ((x) << S_RXTMAX)
4317 #define G_RXTMAX(x) (((x) >> S_RXTMAX) & M_RXTMAX)
4318 
4319 #define A_TP_PERS_MIN 0x3a0
4320 
4321 #define S_PERSMIN    0
4322 #define M_PERSMIN    0x3fffffff
4323 #define V_PERSMIN(x) ((x) << S_PERSMIN)
4324 #define G_PERSMIN(x) (((x) >> S_PERSMIN) & M_PERSMIN)
4325 
4326 #define A_TP_PERS_MAX 0x3a4
4327 
4328 #define S_PERSMAX    0
4329 #define M_PERSMAX    0x3fffffff
4330 #define V_PERSMAX(x) ((x) << S_PERSMAX)
4331 #define G_PERSMAX(x) (((x) >> S_PERSMAX) & M_PERSMAX)
4332 
4333 #define A_TP_KEEP_IDLE 0x3a8
4334 
4335 #define S_KEEPALIVEIDLE    0
4336 #define M_KEEPALIVEIDLE    0x3fffffff
4337 #define V_KEEPALIVEIDLE(x) ((x) << S_KEEPALIVEIDLE)
4338 #define G_KEEPALIVEIDLE(x) (((x) >> S_KEEPALIVEIDLE) & M_KEEPALIVEIDLE)
4339 
4340 #define A_TP_KEEP_INTVL 0x3ac
4341 
4342 #define S_KEEPALIVEINTVL    0
4343 #define M_KEEPALIVEINTVL    0x3fffffff
4344 #define V_KEEPALIVEINTVL(x) ((x) << S_KEEPALIVEINTVL)
4345 #define G_KEEPALIVEINTVL(x) (((x) >> S_KEEPALIVEINTVL) & M_KEEPALIVEINTVL)
4346 
4347 #define A_TP_INIT_SRTT 0x3b0
4348 
4349 #define S_INITSRTT    0
4350 #define M_INITSRTT    0xffff
4351 #define V_INITSRTT(x) ((x) << S_INITSRTT)
4352 #define G_INITSRTT(x) (((x) >> S_INITSRTT) & M_INITSRTT)
4353 
4354 #define A_TP_DACK_TIMER 0x3b4
4355 
4356 #define S_DACKTIME    0
4357 #define M_DACKTIME    0xfff
4358 #define V_DACKTIME(x) ((x) << S_DACKTIME)
4359 #define G_DACKTIME(x) (((x) >> S_DACKTIME) & M_DACKTIME)
4360 
4361 #define A_TP_FINWAIT2_TIMER 0x3b8
4362 
4363 #define S_FINWAIT2TIME    0
4364 #define M_FINWAIT2TIME    0x3fffffff
4365 #define V_FINWAIT2TIME(x) ((x) << S_FINWAIT2TIME)
4366 #define G_FINWAIT2TIME(x) (((x) >> S_FINWAIT2TIME) & M_FINWAIT2TIME)
4367 
4368 #define A_TP_FAST_FINWAIT2_TIMER 0x3bc
4369 
4370 #define S_FASTFINWAIT2TIME    0
4371 #define M_FASTFINWAIT2TIME    0x3fffffff
4372 #define V_FASTFINWAIT2TIME(x) ((x) << S_FASTFINWAIT2TIME)
4373 #define G_FASTFINWAIT2TIME(x) (((x) >> S_FASTFINWAIT2TIME) & M_FASTFINWAIT2TIME)
4374 
4375 #define A_TP_SHIFT_CNT 0x3c0
4376 
4377 #define S_SYNSHIFTMAX    24
4378 #define M_SYNSHIFTMAX    0xff
4379 #define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX)
4380 #define G_SYNSHIFTMAX(x) (((x) >> S_SYNSHIFTMAX) & M_SYNSHIFTMAX)
4381 
4382 #define S_RXTSHIFTMAXR1    20
4383 #define M_RXTSHIFTMAXR1    0xf
4384 #define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1)
4385 #define G_RXTSHIFTMAXR1(x) (((x) >> S_RXTSHIFTMAXR1) & M_RXTSHIFTMAXR1)
4386 
4387 #define S_RXTSHIFTMAXR2    16
4388 #define M_RXTSHIFTMAXR2    0xf
4389 #define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2)
4390 #define G_RXTSHIFTMAXR2(x) (((x) >> S_RXTSHIFTMAXR2) & M_RXTSHIFTMAXR2)
4391 
4392 #define S_PERSHIFTBACKOFFMAX    12
4393 #define M_PERSHIFTBACKOFFMAX    0xf
4394 #define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX)
4395 #define G_PERSHIFTBACKOFFMAX(x) (((x) >> S_PERSHIFTBACKOFFMAX) & M_PERSHIFTBACKOFFMAX)
4396 
4397 #define S_PERSHIFTMAX    8
4398 #define M_PERSHIFTMAX    0xf
4399 #define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX)
4400 #define G_PERSHIFTMAX(x) (((x) >> S_PERSHIFTMAX) & M_PERSHIFTMAX)
4401 
4402 #define S_KEEPALIVEMAX    0
4403 #define M_KEEPALIVEMAX    0xff
4404 #define V_KEEPALIVEMAX(x) ((x) << S_KEEPALIVEMAX)
4405 #define G_KEEPALIVEMAX(x) (((x) >> S_KEEPALIVEMAX) & M_KEEPALIVEMAX)
4406 
4407 #define A_TP_TIME_HI 0x3c8
4408 #define A_TP_TIME_LO 0x3cc
4409 #define A_TP_MTU_PORT_TABLE 0x3d0
4410 
4411 #define S_PORT1MTUVALUE    16
4412 #define M_PORT1MTUVALUE    0xffff
4413 #define V_PORT1MTUVALUE(x) ((x) << S_PORT1MTUVALUE)
4414 #define G_PORT1MTUVALUE(x) (((x) >> S_PORT1MTUVALUE) & M_PORT1MTUVALUE)
4415 
4416 #define S_PORT0MTUVALUE    0
4417 #define M_PORT0MTUVALUE    0xffff
4418 #define V_PORT0MTUVALUE(x) ((x) << S_PORT0MTUVALUE)
4419 #define G_PORT0MTUVALUE(x) (((x) >> S_PORT0MTUVALUE) & M_PORT0MTUVALUE)
4420 
4421 #define A_TP_ULP_TABLE 0x3d4
4422 
4423 #define S_ULPTYPE7FIELD    28
4424 #define M_ULPTYPE7FIELD    0xf
4425 #define V_ULPTYPE7FIELD(x) ((x) << S_ULPTYPE7FIELD)
4426 #define G_ULPTYPE7FIELD(x) (((x) >> S_ULPTYPE7FIELD) & M_ULPTYPE7FIELD)
4427 
4428 #define S_ULPTYPE6FIELD    24
4429 #define M_ULPTYPE6FIELD    0xf
4430 #define V_ULPTYPE6FIELD(x) ((x) << S_ULPTYPE6FIELD)
4431 #define G_ULPTYPE6FIELD(x) (((x) >> S_ULPTYPE6FIELD) & M_ULPTYPE6FIELD)
4432 
4433 #define S_ULPTYPE5FIELD    20
4434 #define M_ULPTYPE5FIELD    0xf
4435 #define V_ULPTYPE5FIELD(x) ((x) << S_ULPTYPE5FIELD)
4436 #define G_ULPTYPE5FIELD(x) (((x) >> S_ULPTYPE5FIELD) & M_ULPTYPE5FIELD)
4437 
4438 #define S_ULPTYPE4FIELD    16
4439 #define M_ULPTYPE4FIELD    0xf
4440 #define V_ULPTYPE4FIELD(x) ((x) << S_ULPTYPE4FIELD)
4441 #define G_ULPTYPE4FIELD(x) (((x) >> S_ULPTYPE4FIELD) & M_ULPTYPE4FIELD)
4442 
4443 #define S_ULPTYPE3FIELD    12
4444 #define M_ULPTYPE3FIELD    0xf
4445 #define V_ULPTYPE3FIELD(x) ((x) << S_ULPTYPE3FIELD)
4446 #define G_ULPTYPE3FIELD(x) (((x) >> S_ULPTYPE3FIELD) & M_ULPTYPE3FIELD)
4447 
4448 #define S_ULPTYPE2FIELD    8
4449 #define M_ULPTYPE2FIELD    0xf
4450 #define V_ULPTYPE2FIELD(x) ((x) << S_ULPTYPE2FIELD)
4451 #define G_ULPTYPE2FIELD(x) (((x) >> S_ULPTYPE2FIELD) & M_ULPTYPE2FIELD)
4452 
4453 #define S_ULPTYPE1FIELD    4
4454 #define M_ULPTYPE1FIELD    0xf
4455 #define V_ULPTYPE1FIELD(x) ((x) << S_ULPTYPE1FIELD)
4456 #define G_ULPTYPE1FIELD(x) (((x) >> S_ULPTYPE1FIELD) & M_ULPTYPE1FIELD)
4457 
4458 #define S_ULPTYPE0FIELD    0
4459 #define M_ULPTYPE0FIELD    0xf
4460 #define V_ULPTYPE0FIELD(x) ((x) << S_ULPTYPE0FIELD)
4461 #define G_ULPTYPE0FIELD(x) (((x) >> S_ULPTYPE0FIELD) & M_ULPTYPE0FIELD)
4462 
4463 #define A_TP_PACE_TABLE 0x3d8
4464 #define A_TP_CCTRL_TABLE 0x3dc
4465 #define A_TP_TOS_TABLE 0x3e0
4466 #define A_TP_MTU_TABLE 0x3e4
4467 #define A_TP_RSS_MAP_TABLE 0x3e8
4468 #define A_TP_RSS_LKP_TABLE 0x3ec
4469 #define A_TP_RSS_CONFIG 0x3f0
4470 
4471 #define S_TNL4TUPEN    29
4472 #define V_TNL4TUPEN(x) ((x) << S_TNL4TUPEN)
4473 #define F_TNL4TUPEN    V_TNL4TUPEN(1U)
4474 
4475 #define S_TNL2TUPEN    28
4476 #define V_TNL2TUPEN(x) ((x) << S_TNL2TUPEN)
4477 #define F_TNL2TUPEN    V_TNL2TUPEN(1U)
4478 
4479 #define S_TNLPRTEN    26
4480 #define V_TNLPRTEN(x) ((x) << S_TNLPRTEN)
4481 #define F_TNLPRTEN    V_TNLPRTEN(1U)
4482 
4483 #define S_TNLMAPEN    25
4484 #define V_TNLMAPEN(x) ((x) << S_TNLMAPEN)
4485 #define F_TNLMAPEN    V_TNLMAPEN(1U)
4486 
4487 #define S_TNLLKPEN    24
4488 #define V_TNLLKPEN(x) ((x) << S_TNLLKPEN)
4489 #define F_TNLLKPEN    V_TNLLKPEN(1U)
4490 
4491 #define S_OFD4TUPEN    21
4492 #define V_OFD4TUPEN(x) ((x) << S_OFD4TUPEN)
4493 #define F_OFD4TUPEN    V_OFD4TUPEN(1U)
4494 
4495 #define S_OFD2TUPEN    20
4496 #define V_OFD2TUPEN(x) ((x) << S_OFD2TUPEN)
4497 #define F_OFD2TUPEN    V_OFD2TUPEN(1U)
4498 
4499 #define S_OFDMAPEN    17
4500 #define V_OFDMAPEN(x) ((x) << S_OFDMAPEN)
4501 #define F_OFDMAPEN    V_OFDMAPEN(1U)
4502 
4503 #define S_OFDLKPEN    16
4504 #define V_OFDLKPEN(x) ((x) << S_OFDLKPEN)
4505 #define F_OFDLKPEN    V_OFDLKPEN(1U)
4506 
4507 #define S_SYN4TUPEN    13
4508 #define V_SYN4TUPEN(x) ((x) << S_SYN4TUPEN)
4509 #define F_SYN4TUPEN    V_SYN4TUPEN(1U)
4510 
4511 #define S_SYN2TUPEN    12
4512 #define V_SYN2TUPEN(x) ((x) << S_SYN2TUPEN)
4513 #define F_SYN2TUPEN    V_SYN2TUPEN(1U)
4514 
4515 #define S_SYNMAPEN    9
4516 #define V_SYNMAPEN(x) ((x) << S_SYNMAPEN)
4517 #define F_SYNMAPEN    V_SYNMAPEN(1U)
4518 
4519 #define S_SYNLKPEN    8
4520 #define V_SYNLKPEN(x) ((x) << S_SYNLKPEN)
4521 #define F_SYNLKPEN    V_SYNLKPEN(1U)
4522 
4523 #define S_RRCPLMAPEN    7
4524 #define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN)
4525 #define F_RRCPLMAPEN    V_RRCPLMAPEN(1U)
4526 
4527 #define S_RRCPLCPUSIZE    4
4528 #define M_RRCPLCPUSIZE    0x7
4529 #define V_RRCPLCPUSIZE(x) ((x) << S_RRCPLCPUSIZE)
4530 #define G_RRCPLCPUSIZE(x) (((x) >> S_RRCPLCPUSIZE) & M_RRCPLCPUSIZE)
4531 
4532 #define S_RQFEEDBACKENABLE    3
4533 #define V_RQFEEDBACKENABLE(x) ((x) << S_RQFEEDBACKENABLE)
4534 #define F_RQFEEDBACKENABLE    V_RQFEEDBACKENABLE(1U)
4535 
4536 #define S_HASHTOEPLITZ    2
4537 #define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ)
4538 #define F_HASHTOEPLITZ    V_HASHTOEPLITZ(1U)
4539 
4540 #define S_HASHSAVE    1
4541 #define V_HASHSAVE(x) ((x) << S_HASHSAVE)
4542 #define F_HASHSAVE    V_HASHSAVE(1U)
4543 
4544 #define S_DISABLE    0
4545 #define V_DISABLE(x) ((x) << S_DISABLE)
4546 #define F_DISABLE    V_DISABLE(1U)
4547 
4548 #define A_TP_RSS_CONFIG_TNL 0x3f4
4549 
4550 #define S_MASKSIZE    28
4551 #define M_MASKSIZE    0x7
4552 #define V_MASKSIZE(x) ((x) << S_MASKSIZE)
4553 #define G_MASKSIZE(x) (((x) >> S_MASKSIZE) & M_MASKSIZE)
4554 
4555 #define S_DEFAULTCPUBASE    22
4556 #define M_DEFAULTCPUBASE    0x3f
4557 #define V_DEFAULTCPUBASE(x) ((x) << S_DEFAULTCPUBASE)
4558 #define G_DEFAULTCPUBASE(x) (((x) >> S_DEFAULTCPUBASE) & M_DEFAULTCPUBASE)
4559 
4560 #define S_DEFAULTCPU    16
4561 #define M_DEFAULTCPU    0x3f
4562 #define V_DEFAULTCPU(x) ((x) << S_DEFAULTCPU)
4563 #define G_DEFAULTCPU(x) (((x) >> S_DEFAULTCPU) & M_DEFAULTCPU)
4564 
4565 #define S_DEFAULTQUEUE    0
4566 #define M_DEFAULTQUEUE    0xffff
4567 #define V_DEFAULTQUEUE(x) ((x) << S_DEFAULTQUEUE)
4568 #define G_DEFAULTQUEUE(x) (((x) >> S_DEFAULTQUEUE) & M_DEFAULTQUEUE)
4569 
4570 #define A_TP_RSS_CONFIG_OFD 0x3f8
4571 #define A_TP_RSS_CONFIG_SYN 0x3fc
4572 #define A_TP_RSS_SECRET_KEY0 0x400
4573 #define A_TP_RSS_SECRET_KEY1 0x404
4574 #define A_TP_RSS_SECRET_KEY2 0x408
4575 #define A_TP_RSS_SECRET_KEY3 0x40c
4576 #define A_TP_TM_PIO_ADDR 0x418
4577 #define A_TP_TM_PIO_DATA 0x41c
4578 #define A_TP_TX_MOD_QUE_TABLE 0x420
4579 #define A_TP_TX_RESOURCE_LIMIT 0x424
4580 
4581 #define S_TX_RESOURCE_LIMIT_CH1_PC    24
4582 #define M_TX_RESOURCE_LIMIT_CH1_PC    0xff
4583 #define V_TX_RESOURCE_LIMIT_CH1_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH1_PC)
4584 #define G_TX_RESOURCE_LIMIT_CH1_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH1_PC) & M_TX_RESOURCE_LIMIT_CH1_PC)
4585 
4586 #define S_TX_RESOURCE_LIMIT_CH1_NON_PC    16
4587 #define M_TX_RESOURCE_LIMIT_CH1_NON_PC    0xff
4588 #define V_TX_RESOURCE_LIMIT_CH1_NON_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH1_NON_PC)
4589 #define G_TX_RESOURCE_LIMIT_CH1_NON_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH1_NON_PC) & M_TX_RESOURCE_LIMIT_CH1_NON_PC)
4590 
4591 #define S_TX_RESOURCE_LIMIT_CH0_PC    8
4592 #define M_TX_RESOURCE_LIMIT_CH0_PC    0xff
4593 #define V_TX_RESOURCE_LIMIT_CH0_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH0_PC)
4594 #define G_TX_RESOURCE_LIMIT_CH0_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH0_PC) & M_TX_RESOURCE_LIMIT_CH0_PC)
4595 
4596 #define S_TX_RESOURCE_LIMIT_CH0_NON_PC    0
4597 #define M_TX_RESOURCE_LIMIT_CH0_NON_PC    0xff
4598 #define V_TX_RESOURCE_LIMIT_CH0_NON_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH0_NON_PC)
4599 #define G_TX_RESOURCE_LIMIT_CH0_NON_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH0_NON_PC) & M_TX_RESOURCE_LIMIT_CH0_NON_PC)
4600 
4601 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x428
4602 
4603 #define S_RX_MOD_WEIGHT    24
4604 #define M_RX_MOD_WEIGHT    0xff
4605 #define V_RX_MOD_WEIGHT(x) ((x) << S_RX_MOD_WEIGHT)
4606 #define G_RX_MOD_WEIGHT(x) (((x) >> S_RX_MOD_WEIGHT) & M_RX_MOD_WEIGHT)
4607 
4608 #define S_TX_MOD_WEIGHT    16
4609 #define M_TX_MOD_WEIGHT    0xff
4610 #define V_TX_MOD_WEIGHT(x) ((x) << S_TX_MOD_WEIGHT)
4611 #define G_TX_MOD_WEIGHT(x) (((x) >> S_TX_MOD_WEIGHT) & M_TX_MOD_WEIGHT)
4612 
4613 #define S_TX_MOD_TIMER_MODE    8
4614 #define M_TX_MOD_TIMER_MODE    0xff
4615 #define V_TX_MOD_TIMER_MODE(x) ((x) << S_TX_MOD_TIMER_MODE)
4616 #define G_TX_MOD_TIMER_MODE(x) (((x) >> S_TX_MOD_TIMER_MODE) & M_TX_MOD_TIMER_MODE)
4617 
4618 #define S_TX_MOD_QUEUE_REQ_MAP    0
4619 #define M_TX_MOD_QUEUE_REQ_MAP    0xff
4620 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
4621 #define G_TX_MOD_QUEUE_REQ_MAP(x) (((x) >> S_TX_MOD_QUEUE_REQ_MAP) & M_TX_MOD_QUEUE_REQ_MAP)
4622 
4623 #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x42c
4624 
4625 #define S_TP_TX_MODQ_WGHT7    24
4626 #define M_TP_TX_MODQ_WGHT7    0xff
4627 #define V_TP_TX_MODQ_WGHT7(x) ((x) << S_TP_TX_MODQ_WGHT7)
4628 #define G_TP_TX_MODQ_WGHT7(x) (((x) >> S_TP_TX_MODQ_WGHT7) & M_TP_TX_MODQ_WGHT7)
4629 
4630 #define S_TP_TX_MODQ_WGHT6    16
4631 #define M_TP_TX_MODQ_WGHT6    0xff
4632 #define V_TP_TX_MODQ_WGHT6(x) ((x) << S_TP_TX_MODQ_WGHT6)
4633 #define G_TP_TX_MODQ_WGHT6(x) (((x) >> S_TP_TX_MODQ_WGHT6) & M_TP_TX_MODQ_WGHT6)
4634 
4635 #define S_TP_TX_MODQ_WGHT5    8
4636 #define M_TP_TX_MODQ_WGHT5    0xff
4637 #define V_TP_TX_MODQ_WGHT5(x) ((x) << S_TP_TX_MODQ_WGHT5)
4638 #define G_TP_TX_MODQ_WGHT5(x) (((x) >> S_TP_TX_MODQ_WGHT5) & M_TP_TX_MODQ_WGHT5)
4639 
4640 #define S_TP_TX_MODQ_WGHT4    0
4641 #define M_TP_TX_MODQ_WGHT4    0xff
4642 #define V_TP_TX_MODQ_WGHT4(x) ((x) << S_TP_TX_MODQ_WGHT4)
4643 #define G_TP_TX_MODQ_WGHT4(x) (((x) >> S_TP_TX_MODQ_WGHT4) & M_TP_TX_MODQ_WGHT4)
4644 
4645 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x430
4646 
4647 #define S_TP_TX_MODQ_WGHT3    24
4648 #define M_TP_TX_MODQ_WGHT3    0xff
4649 #define V_TP_TX_MODQ_WGHT3(x) ((x) << S_TP_TX_MODQ_WGHT3)
4650 #define G_TP_TX_MODQ_WGHT3(x) (((x) >> S_TP_TX_MODQ_WGHT3) & M_TP_TX_MODQ_WGHT3)
4651 
4652 #define S_TP_TX_MODQ_WGHT2    16
4653 #define M_TP_TX_MODQ_WGHT2    0xff
4654 #define V_TP_TX_MODQ_WGHT2(x) ((x) << S_TP_TX_MODQ_WGHT2)
4655 #define G_TP_TX_MODQ_WGHT2(x) (((x) >> S_TP_TX_MODQ_WGHT2) & M_TP_TX_MODQ_WGHT2)
4656 
4657 #define S_TP_TX_MODQ_WGHT1    8
4658 #define M_TP_TX_MODQ_WGHT1    0xff
4659 #define V_TP_TX_MODQ_WGHT1(x) ((x) << S_TP_TX_MODQ_WGHT1)
4660 #define G_TP_TX_MODQ_WGHT1(x) (((x) >> S_TP_TX_MODQ_WGHT1) & M_TP_TX_MODQ_WGHT1)
4661 
4662 #define S_TP_TX_MODQ_WGHT0    0
4663 #define M_TP_TX_MODQ_WGHT0    0xff
4664 #define V_TP_TX_MODQ_WGHT0(x) ((x) << S_TP_TX_MODQ_WGHT0)
4665 #define G_TP_TX_MODQ_WGHT0(x) (((x) >> S_TP_TX_MODQ_WGHT0) & M_TP_TX_MODQ_WGHT0)
4666 
4667 #define A_TP_MOD_CHANNEL_WEIGHT 0x434
4668 
4669 #define S_RX_MOD_CHANNEL_WEIGHT1    24
4670 #define M_RX_MOD_CHANNEL_WEIGHT1    0xff
4671 #define V_RX_MOD_CHANNEL_WEIGHT1(x) ((x) << S_RX_MOD_CHANNEL_WEIGHT1)
4672 #define G_RX_MOD_CHANNEL_WEIGHT1(x) (((x) >> S_RX_MOD_CHANNEL_WEIGHT1) & M_RX_MOD_CHANNEL_WEIGHT1)
4673 
4674 #define S_RX_MOD_CHANNEL_WEIGHT0    16
4675 #define M_RX_MOD_CHANNEL_WEIGHT0    0xff
4676 #define V_RX_MOD_CHANNEL_WEIGHT0(x) ((x) << S_RX_MOD_CHANNEL_WEIGHT0)
4677 #define G_RX_MOD_CHANNEL_WEIGHT0(x) (((x) >> S_RX_MOD_CHANNEL_WEIGHT0) & M_RX_MOD_CHANNEL_WEIGHT0)
4678 
4679 #define S_TX_MOD_CHANNEL_WEIGHT1    8
4680 #define M_TX_MOD_CHANNEL_WEIGHT1    0xff
4681 #define V_TX_MOD_CHANNEL_WEIGHT1(x) ((x) << S_TX_MOD_CHANNEL_WEIGHT1)
4682 #define G_TX_MOD_CHANNEL_WEIGHT1(x) (((x) >> S_TX_MOD_CHANNEL_WEIGHT1) & M_TX_MOD_CHANNEL_WEIGHT1)
4683 
4684 #define S_TX_MOD_CHANNEL_WEIGHT0    0
4685 #define M_TX_MOD_CHANNEL_WEIGHT0    0xff
4686 #define V_TX_MOD_CHANNEL_WEIGHT0(x) ((x) << S_TX_MOD_CHANNEL_WEIGHT0)
4687 #define G_TX_MOD_CHANNEL_WEIGHT0(x) (((x) >> S_TX_MOD_CHANNEL_WEIGHT0) & M_TX_MOD_CHANNEL_WEIGHT0)
4688 
4689 #define A_TP_MOD_RATE_LIMIT 0x438
4690 
4691 #define S_RX_MOD_RATE_LIMIT_INC    24
4692 #define M_RX_MOD_RATE_LIMIT_INC    0xff
4693 #define V_RX_MOD_RATE_LIMIT_INC(x) ((x) << S_RX_MOD_RATE_LIMIT_INC)
4694 #define G_RX_MOD_RATE_LIMIT_INC(x) (((x) >> S_RX_MOD_RATE_LIMIT_INC) & M_RX_MOD_RATE_LIMIT_INC)
4695 
4696 #define S_RX_MOD_RATE_LIMIT_TICK    16
4697 #define M_RX_MOD_RATE_LIMIT_TICK    0xff
4698 #define V_RX_MOD_RATE_LIMIT_TICK(x) ((x) << S_RX_MOD_RATE_LIMIT_TICK)
4699 #define G_RX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_RX_MOD_RATE_LIMIT_TICK) & M_RX_MOD_RATE_LIMIT_TICK)
4700 
4701 #define S_TX_MOD_RATE_LIMIT_INC    8
4702 #define M_TX_MOD_RATE_LIMIT_INC    0xff
4703 #define V_TX_MOD_RATE_LIMIT_INC(x) ((x) << S_TX_MOD_RATE_LIMIT_INC)
4704 #define G_TX_MOD_RATE_LIMIT_INC(x) (((x) >> S_TX_MOD_RATE_LIMIT_INC) & M_TX_MOD_RATE_LIMIT_INC)
4705 
4706 #define S_TX_MOD_RATE_LIMIT_TICK    0
4707 #define M_TX_MOD_RATE_LIMIT_TICK    0xff
4708 #define V_TX_MOD_RATE_LIMIT_TICK(x) ((x) << S_TX_MOD_RATE_LIMIT_TICK)
4709 #define G_TX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_TX_MOD_RATE_LIMIT_TICK) & M_TX_MOD_RATE_LIMIT_TICK)
4710 
4711 #define A_TP_PIO_ADDR 0x440
4712 #define A_TP_PIO_DATA 0x444
4713 #define A_TP_RESET 0x44c
4714 
4715 #define S_FLSTINITENABLE    1
4716 #define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE)
4717 #define F_FLSTINITENABLE    V_FLSTINITENABLE(1U)
4718 
4719 #define S_TPRESET    0
4720 #define V_TPRESET(x) ((x) << S_TPRESET)
4721 #define F_TPRESET    V_TPRESET(1U)
4722 
4723 #define A_TP_MIB_INDEX 0x450
4724 #define A_TP_MIB_RDATA 0x454
4725 #define A_TP_SYNC_TIME_HI 0x458
4726 #define A_TP_SYNC_TIME_LO 0x45c
4727 #define A_TP_CMM_MM_RX_FLST_BASE 0x460
4728 
4729 #define S_CMRXFLSTBASE    0
4730 #define M_CMRXFLSTBASE    0xfffffff
4731 #define V_CMRXFLSTBASE(x) ((x) << S_CMRXFLSTBASE)
4732 #define G_CMRXFLSTBASE(x) (((x) >> S_CMRXFLSTBASE) & M_CMRXFLSTBASE)
4733 
4734 #define A_TP_CMM_MM_TX_FLST_BASE 0x464
4735 
4736 #define S_CMTXFLSTBASE    0
4737 #define M_CMTXFLSTBASE    0xfffffff
4738 #define V_CMTXFLSTBASE(x) ((x) << S_CMTXFLSTBASE)
4739 #define G_CMTXFLSTBASE(x) (((x) >> S_CMTXFLSTBASE) & M_CMTXFLSTBASE)
4740 
4741 #define A_TP_CMM_MM_PS_FLST_BASE 0x468
4742 
4743 #define S_CMPSFLSTBASE    0
4744 #define M_CMPSFLSTBASE    0xfffffff
4745 #define V_CMPSFLSTBASE(x) ((x) << S_CMPSFLSTBASE)
4746 #define G_CMPSFLSTBASE(x) (((x) >> S_CMPSFLSTBASE) & M_CMPSFLSTBASE)
4747 
4748 #define A_TP_CMM_MM_MAX_PSTRUCT 0x46c
4749 
4750 #define S_CMMAXPSTRUCT    0
4751 #define M_CMMAXPSTRUCT    0x1fffff
4752 #define V_CMMAXPSTRUCT(x) ((x) << S_CMMAXPSTRUCT)
4753 #define G_CMMAXPSTRUCT(x) (((x) >> S_CMMAXPSTRUCT) & M_CMMAXPSTRUCT)
4754 
4755 #define A_TP_INT_ENABLE 0x470
4756 
4757 #define S_FLMTXFLSTEMPTY    30
4758 #define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY)
4759 #define F_FLMTXFLSTEMPTY    V_FLMTXFLSTEMPTY(1U)
4760 
4761 #define S_FLMRXFLSTEMPTY    29
4762 #define V_FLMRXFLSTEMPTY(x) ((x) << S_FLMRXFLSTEMPTY)
4763 #define F_FLMRXFLSTEMPTY    V_FLMRXFLSTEMPTY(1U)
4764 
4765 #define S_FLMPERRSET    28
4766 #define V_FLMPERRSET(x) ((x) << S_FLMPERRSET)
4767 #define F_FLMPERRSET    V_FLMPERRSET(1U)
4768 
4769 #define S_PROTOCOLSRAMPERR    27
4770 #define V_PROTOCOLSRAMPERR(x) ((x) << S_PROTOCOLSRAMPERR)
4771 #define F_PROTOCOLSRAMPERR    V_PROTOCOLSRAMPERR(1U)
4772 
4773 #define S_ARPLUTPERR    26
4774 #define V_ARPLUTPERR(x) ((x) << S_ARPLUTPERR)
4775 #define F_ARPLUTPERR    V_ARPLUTPERR(1U)
4776 
4777 #define S_CMRCFOPPERR    25
4778 #define V_CMRCFOPPERR(x) ((x) << S_CMRCFOPPERR)
4779 #define F_CMRCFOPPERR    V_CMRCFOPPERR(1U)
4780 
4781 #define S_CMCACHEPERR    24
4782 #define V_CMCACHEPERR(x) ((x) << S_CMCACHEPERR)
4783 #define F_CMCACHEPERR    V_CMCACHEPERR(1U)
4784 
4785 #define S_CMRCFDATAPERR    23
4786 #define V_CMRCFDATAPERR(x) ((x) << S_CMRCFDATAPERR)
4787 #define F_CMRCFDATAPERR    V_CMRCFDATAPERR(1U)
4788 
4789 #define S_DBL2TLUTPERR    22
4790 #define V_DBL2TLUTPERR(x) ((x) << S_DBL2TLUTPERR)
4791 #define F_DBL2TLUTPERR    V_DBL2TLUTPERR(1U)
4792 
4793 #define S_DBTXTIDPERR    21
4794 #define V_DBTXTIDPERR(x) ((x) << S_DBTXTIDPERR)
4795 #define F_DBTXTIDPERR    V_DBTXTIDPERR(1U)
4796 
4797 #define S_DBEXTPERR    20
4798 #define V_DBEXTPERR(x) ((x) << S_DBEXTPERR)
4799 #define F_DBEXTPERR    V_DBEXTPERR(1U)
4800 
4801 #define S_DBOPPERR    19
4802 #define V_DBOPPERR(x) ((x) << S_DBOPPERR)
4803 #define F_DBOPPERR    V_DBOPPERR(1U)
4804 
4805 #define S_TMCACHEPERR    18
4806 #define V_TMCACHEPERR(x) ((x) << S_TMCACHEPERR)
4807 #define F_TMCACHEPERR    V_TMCACHEPERR(1U)
4808 
4809 #define S_ETPOUTCPLFIFOPERR    17
4810 #define V_ETPOUTCPLFIFOPERR(x) ((x) << S_ETPOUTCPLFIFOPERR)
4811 #define F_ETPOUTCPLFIFOPERR    V_ETPOUTCPLFIFOPERR(1U)
4812 
4813 #define S_ETPOUTTCPFIFOPERR    16
4814 #define V_ETPOUTTCPFIFOPERR(x) ((x) << S_ETPOUTTCPFIFOPERR)
4815 #define F_ETPOUTTCPFIFOPERR    V_ETPOUTTCPFIFOPERR(1U)
4816 
4817 #define S_ETPOUTIPFIFOPERR    15
4818 #define V_ETPOUTIPFIFOPERR(x) ((x) << S_ETPOUTIPFIFOPERR)
4819 #define F_ETPOUTIPFIFOPERR    V_ETPOUTIPFIFOPERR(1U)
4820 
4821 #define S_ETPOUTETHFIFOPERR    14
4822 #define V_ETPOUTETHFIFOPERR(x) ((x) << S_ETPOUTETHFIFOPERR)
4823 #define F_ETPOUTETHFIFOPERR    V_ETPOUTETHFIFOPERR(1U)
4824 
4825 #define S_ETPINCPLFIFOPERR    13
4826 #define V_ETPINCPLFIFOPERR(x) ((x) << S_ETPINCPLFIFOPERR)
4827 #define F_ETPINCPLFIFOPERR    V_ETPINCPLFIFOPERR(1U)
4828 
4829 #define S_ETPINTCPOPTFIFOPERR    12
4830 #define V_ETPINTCPOPTFIFOPERR(x) ((x) << S_ETPINTCPOPTFIFOPERR)
4831 #define F_ETPINTCPOPTFIFOPERR    V_ETPINTCPOPTFIFOPERR(1U)
4832 
4833 #define S_ETPINTCPFIFOPERR    11
4834 #define V_ETPINTCPFIFOPERR(x) ((x) << S_ETPINTCPFIFOPERR)
4835 #define F_ETPINTCPFIFOPERR    V_ETPINTCPFIFOPERR(1U)
4836 
4837 #define S_ETPINIPFIFOPERR    10
4838 #define V_ETPINIPFIFOPERR(x) ((x) << S_ETPINIPFIFOPERR)
4839 #define F_ETPINIPFIFOPERR    V_ETPINIPFIFOPERR(1U)
4840 
4841 #define S_ETPINETHFIFOPERR    9
4842 #define V_ETPINETHFIFOPERR(x) ((x) << S_ETPINETHFIFOPERR)
4843 #define F_ETPINETHFIFOPERR    V_ETPINETHFIFOPERR(1U)
4844 
4845 #define S_CTPOUTCPLFIFOPERR    8
4846 #define V_CTPOUTCPLFIFOPERR(x) ((x) << S_CTPOUTCPLFIFOPERR)
4847 #define F_CTPOUTCPLFIFOPERR    V_CTPOUTCPLFIFOPERR(1U)
4848 
4849 #define S_CTPOUTTCPFIFOPERR    7
4850 #define V_CTPOUTTCPFIFOPERR(x) ((x) << S_CTPOUTTCPFIFOPERR)
4851 #define F_CTPOUTTCPFIFOPERR    V_CTPOUTTCPFIFOPERR(1U)
4852 
4853 #define S_CTPOUTIPFIFOPERR    6
4854 #define V_CTPOUTIPFIFOPERR(x) ((x) << S_CTPOUTIPFIFOPERR)
4855 #define F_CTPOUTIPFIFOPERR    V_CTPOUTIPFIFOPERR(1U)
4856 
4857 #define S_CTPOUTETHFIFOPERR    5
4858 #define V_CTPOUTETHFIFOPERR(x) ((x) << S_CTPOUTETHFIFOPERR)
4859 #define F_CTPOUTETHFIFOPERR    V_CTPOUTETHFIFOPERR(1U)
4860 
4861 #define S_CTPINCPLFIFOPERR    4
4862 #define V_CTPINCPLFIFOPERR(x) ((x) << S_CTPINCPLFIFOPERR)
4863 #define F_CTPINCPLFIFOPERR    V_CTPINCPLFIFOPERR(1U)
4864 
4865 #define S_CTPINTCPOPFIFOPERR    3
4866 #define V_CTPINTCPOPFIFOPERR(x) ((x) << S_CTPINTCPOPFIFOPERR)
4867 #define F_CTPINTCPOPFIFOPERR    V_CTPINTCPOPFIFOPERR(1U)
4868 
4869 #define S_CTPINTCPFIFOPERR    2
4870 #define V_CTPINTCPFIFOPERR(x) ((x) << S_CTPINTCPFIFOPERR)
4871 #define F_CTPINTCPFIFOPERR    V_CTPINTCPFIFOPERR(1U)
4872 
4873 #define S_CTPINIPFIFOPERR    1
4874 #define V_CTPINIPFIFOPERR(x) ((x) << S_CTPINIPFIFOPERR)
4875 #define F_CTPINIPFIFOPERR    V_CTPINIPFIFOPERR(1U)
4876 
4877 #define S_CTPINETHFIFOPERR    0
4878 #define V_CTPINETHFIFOPERR(x) ((x) << S_CTPINETHFIFOPERR)
4879 #define F_CTPINETHFIFOPERR    V_CTPINETHFIFOPERR(1U)
4880 
4881 #define A_TP_INT_CAUSE 0x474
4882 #define A_TP_FLM_FREE_PS_CNT 0x480
4883 
4884 #define S_FREEPSTRUCTCOUNT    0
4885 #define M_FREEPSTRUCTCOUNT    0x1fffff
4886 #define V_FREEPSTRUCTCOUNT(x) ((x) << S_FREEPSTRUCTCOUNT)
4887 #define G_FREEPSTRUCTCOUNT(x) (((x) >> S_FREEPSTRUCTCOUNT) & M_FREEPSTRUCTCOUNT)
4888 
4889 #define A_TP_FLM_FREE_RX_CNT 0x484
4890 
4891 #define S_FREERXPAGECOUNT    0
4892 #define M_FREERXPAGECOUNT    0x1fffff
4893 #define V_FREERXPAGECOUNT(x) ((x) << S_FREERXPAGECOUNT)
4894 #define G_FREERXPAGECOUNT(x) (((x) >> S_FREERXPAGECOUNT) & M_FREERXPAGECOUNT)
4895 
4896 #define A_TP_FLM_FREE_TX_CNT 0x488
4897 
4898 #define S_FREETXPAGECOUNT    0
4899 #define M_FREETXPAGECOUNT    0x1fffff
4900 #define V_FREETXPAGECOUNT(x) ((x) << S_FREETXPAGECOUNT)
4901 #define G_FREETXPAGECOUNT(x) (((x) >> S_FREETXPAGECOUNT) & M_FREETXPAGECOUNT)
4902 
4903 #define A_TP_TM_HEAP_PUSH_CNT 0x48c
4904 #define A_TP_TM_HEAP_POP_CNT 0x490
4905 #define A_TP_TM_DACK_PUSH_CNT 0x494
4906 #define A_TP_TM_DACK_POP_CNT 0x498
4907 #define A_TP_TM_MOD_PUSH_CNT 0x49c
4908 #define A_TP_MOD_POP_CNT 0x4a0
4909 #define A_TP_TIMER_SEPARATOR 0x4a4
4910 #define A_TP_DEBUG_SEL 0x4a8
4911 #define A_TP_DEBUG_FLAGS 0x4ac
4912 
4913 #define S_RXTIMERDACKFIRST    26
4914 #define V_RXTIMERDACKFIRST(x) ((x) << S_RXTIMERDACKFIRST)
4915 #define F_RXTIMERDACKFIRST    V_RXTIMERDACKFIRST(1U)
4916 
4917 #define S_RXTIMERDACK    25
4918 #define V_RXTIMERDACK(x) ((x) << S_RXTIMERDACK)
4919 #define F_RXTIMERDACK    V_RXTIMERDACK(1U)
4920 
4921 #define S_RXTIMERHEARTBEAT    24
4922 #define V_RXTIMERHEARTBEAT(x) ((x) << S_RXTIMERHEARTBEAT)
4923 #define F_RXTIMERHEARTBEAT    V_RXTIMERHEARTBEAT(1U)
4924 
4925 #define S_RXPAWSDROP    23
4926 #define V_RXPAWSDROP(x) ((x) << S_RXPAWSDROP)
4927 #define F_RXPAWSDROP    V_RXPAWSDROP(1U)
4928 
4929 #define S_RXURGDATADROP    22
4930 #define V_RXURGDATADROP(x) ((x) << S_RXURGDATADROP)
4931 #define F_RXURGDATADROP    V_RXURGDATADROP(1U)
4932 
4933 #define S_RXFUTUREDATA    21
4934 #define V_RXFUTUREDATA(x) ((x) << S_RXFUTUREDATA)
4935 #define F_RXFUTUREDATA    V_RXFUTUREDATA(1U)
4936 
4937 #define S_RXRCVRXMDATA    20
4938 #define V_RXRCVRXMDATA(x) ((x) << S_RXRCVRXMDATA)
4939 #define F_RXRCVRXMDATA    V_RXRCVRXMDATA(1U)
4940 
4941 #define S_RXRCVOOODATAFIN    19
4942 #define V_RXRCVOOODATAFIN(x) ((x) << S_RXRCVOOODATAFIN)
4943 #define F_RXRCVOOODATAFIN    V_RXRCVOOODATAFIN(1U)
4944 
4945 #define S_RXRCVOOODATA    18
4946 #define V_RXRCVOOODATA(x) ((x) << S_RXRCVOOODATA)
4947 #define F_RXRCVOOODATA    V_RXRCVOOODATA(1U)
4948 
4949 #define S_RXRCVWNDZERO    17
4950 #define V_RXRCVWNDZERO(x) ((x) << S_RXRCVWNDZERO)
4951 #define F_RXRCVWNDZERO    V_RXRCVWNDZERO(1U)
4952 
4953 #define S_RXRCVWNDLTMSS    16
4954 #define V_RXRCVWNDLTMSS(x) ((x) << S_RXRCVWNDLTMSS)
4955 #define F_RXRCVWNDLTMSS    V_RXRCVWNDLTMSS(1U)
4956 
4957 #define S_TXDUPACKINC    11
4958 #define V_TXDUPACKINC(x) ((x) << S_TXDUPACKINC)
4959 #define F_TXDUPACKINC    V_TXDUPACKINC(1U)
4960 
4961 #define S_TXRXMURG    10
4962 #define V_TXRXMURG(x) ((x) << S_TXRXMURG)
4963 #define F_TXRXMURG    V_TXRXMURG(1U)
4964 
4965 #define S_TXRXMFIN    9
4966 #define V_TXRXMFIN(x) ((x) << S_TXRXMFIN)
4967 #define F_TXRXMFIN    V_TXRXMFIN(1U)
4968 
4969 #define S_TXRXMSYN    8
4970 #define V_TXRXMSYN(x) ((x) << S_TXRXMSYN)
4971 #define F_TXRXMSYN    V_TXRXMSYN(1U)
4972 
4973 #define S_TXRXMNEWRENO    7
4974 #define V_TXRXMNEWRENO(x) ((x) << S_TXRXMNEWRENO)
4975 #define F_TXRXMNEWRENO    V_TXRXMNEWRENO(1U)
4976 
4977 #define S_TXRXMFAST    6
4978 #define V_TXRXMFAST(x) ((x) << S_TXRXMFAST)
4979 #define F_TXRXMFAST    V_TXRXMFAST(1U)
4980 
4981 #define S_TXRXMTIMER    5
4982 #define V_TXRXMTIMER(x) ((x) << S_TXRXMTIMER)
4983 #define F_TXRXMTIMER    V_TXRXMTIMER(1U)
4984 
4985 #define S_TXRXMTIMERKEEPALIVE    4
4986 #define V_TXRXMTIMERKEEPALIVE(x) ((x) << S_TXRXMTIMERKEEPALIVE)
4987 #define F_TXRXMTIMERKEEPALIVE    V_TXRXMTIMERKEEPALIVE(1U)
4988 
4989 #define S_TXRXMTIMERPERSIST    3
4990 #define V_TXRXMTIMERPERSIST(x) ((x) << S_TXRXMTIMERPERSIST)
4991 #define F_TXRXMTIMERPERSIST    V_TXRXMTIMERPERSIST(1U)
4992 
4993 #define S_TXRCVADVSHRUNK    2
4994 #define V_TXRCVADVSHRUNK(x) ((x) << S_TXRCVADVSHRUNK)
4995 #define F_TXRCVADVSHRUNK    V_TXRCVADVSHRUNK(1U)
4996 
4997 #define S_TXRCVADVZERO    1
4998 #define V_TXRCVADVZERO(x) ((x) << S_TXRCVADVZERO)
4999 #define F_TXRCVADVZERO    V_TXRCVADVZERO(1U)
5000 
5001 #define S_TXRCVADVLTMSS    0
5002 #define V_TXRCVADVLTMSS(x) ((x) << S_TXRCVADVLTMSS)
5003 #define F_TXRCVADVLTMSS    V_TXRCVADVLTMSS(1U)
5004 
5005 #define S_RXDEBUGFLAGS    16
5006 #define M_RXDEBUGFLAGS    0xffff
5007 #define V_RXDEBUGFLAGS(x) ((x) << S_RXDEBUGFLAGS)
5008 #define G_RXDEBUGFLAGS(x) (((x) >> S_RXDEBUGFLAGS) & M_RXDEBUGFLAGS)
5009 
5010 #define S_TXDEBUGFLAGS    0
5011 #define M_TXDEBUGFLAGS    0xffff
5012 #define V_TXDEBUGFLAGS(x) ((x) << S_TXDEBUGFLAGS)
5013 #define G_TXDEBUGFLAGS(x) (((x) >> S_TXDEBUGFLAGS) & M_TXDEBUGFLAGS)
5014 
5015 #define A_TP_PROXY_FLOW_CNTL 0x4b0
5016 #define A_TP_CM_FLOW_CNTL_MODE 0x4b0
5017 
5018 #define S_CMFLOWCACHEDISABLE    0
5019 #define V_CMFLOWCACHEDISABLE(x) ((x) << S_CMFLOWCACHEDISABLE)
5020 #define F_CMFLOWCACHEDISABLE    V_CMFLOWCACHEDISABLE(1U)
5021 
5022 #define A_TP_PC_CONGESTION_CNTL 0x4b4
5023 
5024 #define S_EDROPTUNNEL    19
5025 #define V_EDROPTUNNEL(x) ((x) << S_EDROPTUNNEL)
5026 #define F_EDROPTUNNEL    V_EDROPTUNNEL(1U)
5027 
5028 #define S_CDROPTUNNEL    18
5029 #define V_CDROPTUNNEL(x) ((x) << S_CDROPTUNNEL)
5030 #define F_CDROPTUNNEL    V_CDROPTUNNEL(1U)
5031 
5032 #define S_ETHRESHOLD    12
5033 #define M_ETHRESHOLD    0x3f
5034 #define V_ETHRESHOLD(x) ((x) << S_ETHRESHOLD)
5035 #define G_ETHRESHOLD(x) (((x) >> S_ETHRESHOLD) & M_ETHRESHOLD)
5036 
5037 #define S_CTHRESHOLD    6
5038 #define M_CTHRESHOLD    0x3f
5039 #define V_CTHRESHOLD(x) ((x) << S_CTHRESHOLD)
5040 #define G_CTHRESHOLD(x) (((x) >> S_CTHRESHOLD) & M_CTHRESHOLD)
5041 
5042 #define S_TXTHRESHOLD    0
5043 #define M_TXTHRESHOLD    0x3f
5044 #define V_TXTHRESHOLD(x) ((x) << S_TXTHRESHOLD)
5045 #define G_TXTHRESHOLD(x) (((x) >> S_TXTHRESHOLD) & M_TXTHRESHOLD)
5046 
5047 #define A_TP_TX_DROP_COUNT 0x4bc
5048 #define A_TP_CLEAR_DEBUG 0x4c0
5049 
5050 #define S_CLRDEBUG    0
5051 #define V_CLRDEBUG(x) ((x) << S_CLRDEBUG)
5052 #define F_CLRDEBUG    V_CLRDEBUG(1U)
5053 
5054 #define A_TP_DEBUG_VEC 0x4c4
5055 #define A_TP_DEBUG_VEC2 0x4c8
5056 #define A_TP_DEBUG_REG_SEL 0x4cc
5057 #define A_TP_DEBUG 0x4d0
5058 #define A_TP_DBG_LA_CONFIG 0x4d4
5059 #define A_TP_DBG_LA_DATAH 0x4d8
5060 #define A_TP_DBG_LA_DATAL 0x4dc
5061 #define A_TP_EMBED_OP_FIELD0 0x4e8
5062 #define A_TP_EMBED_OP_FIELD1 0x4ec
5063 #define A_TP_EMBED_OP_FIELD2 0x4f0
5064 #define A_TP_EMBED_OP_FIELD3 0x4f4
5065 #define A_TP_EMBED_OP_FIELD4 0x4f8
5066 #define A_TP_EMBED_OP_FIELD5 0x4fc
5067 #define A_TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR 0x0
5068 #define A_TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR 0x1
5069 #define A_TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR 0x2
5070 #define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR 0x3
5071 #define A_TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR 0x4
5072 #define A_TP_TX_MOD_Q7_Q6_RATE_LIMIT 0x5
5073 #define A_TP_TX_MOD_Q5_Q4_RATE_LIMIT 0x6
5074 #define A_TP_TX_MOD_Q3_Q2_RATE_LIMIT 0x7
5075 #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
5076 #define A_TP_RX_MOD_Q1_Q0_RATE_LIMIT 0x9
5077 #define A_TP_TX_TRC_KEY0 0x20
5078 #define A_TP_TX_TRC_MASK0 0x21
5079 #define A_TP_TX_TRC_KEY1 0x22
5080 #define A_TP_TX_TRC_MASK1 0x23
5081 #define A_TP_TX_TRC_KEY2 0x24
5082 #define A_TP_TX_TRC_MASK2 0x25
5083 #define A_TP_TX_TRC_KEY3 0x26
5084 #define A_TP_TX_TRC_MASK3 0x27
5085 #define A_TP_IPMI_CFG1 0x28
5086 
5087 #define S_VLANENABLE    31
5088 #define V_VLANENABLE(x) ((x) << S_VLANENABLE)
5089 #define F_VLANENABLE    V_VLANENABLE(1U)
5090 
5091 #define S_PRIMARYPORTENABLE    30
5092 #define V_PRIMARYPORTENABLE(x) ((x) << S_PRIMARYPORTENABLE)
5093 #define F_PRIMARYPORTENABLE    V_PRIMARYPORTENABLE(1U)
5094 
5095 #define S_SECUREPORTENABLE    29
5096 #define V_SECUREPORTENABLE(x) ((x) << S_SECUREPORTENABLE)
5097 #define F_SECUREPORTENABLE    V_SECUREPORTENABLE(1U)
5098 
5099 #define S_ARPENABLE    28
5100 #define V_ARPENABLE(x) ((x) << S_ARPENABLE)
5101 #define F_ARPENABLE    V_ARPENABLE(1U)
5102 
5103 #define S_VLAN    0
5104 #define M_VLAN    0xffff
5105 #define V_VLAN(x) ((x) << S_VLAN)
5106 #define G_VLAN(x) (((x) >> S_VLAN) & M_VLAN)
5107 
5108 #define A_TP_IPMI_CFG2 0x29
5109 
5110 #define S_SECUREPORT    16
5111 #define M_SECUREPORT    0xffff
5112 #define V_SECUREPORT(x) ((x) << S_SECUREPORT)
5113 #define G_SECUREPORT(x) (((x) >> S_SECUREPORT) & M_SECUREPORT)
5114 
5115 #define S_PRIMARYPORT    0
5116 #define M_PRIMARYPORT    0xffff
5117 #define V_PRIMARYPORT(x) ((x) << S_PRIMARYPORT)
5118 #define G_PRIMARYPORT(x) (((x) >> S_PRIMARYPORT) & M_PRIMARYPORT)
5119 
5120 #define A_TP_RX_TRC_KEY0 0x120
5121 #define A_TP_RX_TRC_MASK0 0x121
5122 #define A_TP_RX_TRC_KEY1 0x122
5123 #define A_TP_RX_TRC_MASK1 0x123
5124 #define A_TP_RX_TRC_KEY2 0x124
5125 #define A_TP_RX_TRC_MASK2 0x125
5126 #define A_TP_RX_TRC_KEY3 0x126
5127 #define A_TP_RX_TRC_MASK3 0x127
5128 #define A_TP_QOS_RX_TOS_MAP_H 0x128
5129 #define A_TP_QOS_RX_TOS_MAP_L 0x129
5130 #define A_TP_QOS_RX_MAP_MODE 0x12a
5131 
5132 #define S_DEFAULTCH    11
5133 #define V_DEFAULTCH(x) ((x) << S_DEFAULTCH)
5134 #define F_DEFAULTCH    V_DEFAULTCH(1U)
5135 
5136 #define S_RXMAPMODE    8
5137 #define M_RXMAPMODE    0x7
5138 #define V_RXMAPMODE(x) ((x) << S_RXMAPMODE)
5139 #define G_RXMAPMODE(x) (((x) >> S_RXMAPMODE) & M_RXMAPMODE)
5140 
5141 #define S_RXVLANMAP    7
5142 #define V_RXVLANMAP(x) ((x) << S_RXVLANMAP)
5143 #define F_RXVLANMAP    V_RXVLANMAP(1U)
5144 
5145 #define A_TP_TX_DROP_CFG_CH0 0x12b
5146 
5147 #define S_TIMERENABLED    31
5148 #define V_TIMERENABLED(x) ((x) << S_TIMERENABLED)
5149 #define F_TIMERENABLED    V_TIMERENABLED(1U)
5150 
5151 #define S_TIMERERRORENABLE    30
5152 #define V_TIMERERRORENABLE(x) ((x) << S_TIMERERRORENABLE)
5153 #define F_TIMERERRORENABLE    V_TIMERERRORENABLE(1U)
5154 
5155 #define S_TIMERTHRESHOLD    4
5156 #define M_TIMERTHRESHOLD    0x3ffffff
5157 #define V_TIMERTHRESHOLD(x) ((x) << S_TIMERTHRESHOLD)
5158 #define G_TIMERTHRESHOLD(x) (((x) >> S_TIMERTHRESHOLD) & M_TIMERTHRESHOLD)
5159 
5160 #define S_PACKETDROPS    0
5161 #define M_PACKETDROPS    0xf
5162 #define V_PACKETDROPS(x) ((x) << S_PACKETDROPS)
5163 #define G_PACKETDROPS(x) (((x) >> S_PACKETDROPS) & M_PACKETDROPS)
5164 
5165 #define A_TP_TX_DROP_CFG_CH1 0x12c
5166 #define A_TP_TX_DROP_CNT_CH0 0x12d
5167 
5168 #define S_TXDROPCNTCH0SENT    16
5169 #define M_TXDROPCNTCH0SENT    0xffff
5170 #define V_TXDROPCNTCH0SENT(x) ((x) << S_TXDROPCNTCH0SENT)
5171 #define G_TXDROPCNTCH0SENT(x) (((x) >> S_TXDROPCNTCH0SENT) & M_TXDROPCNTCH0SENT)
5172 
5173 #define S_TXDROPCNTCH0RCVD    0
5174 #define M_TXDROPCNTCH0RCVD    0xffff
5175 #define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD)
5176 #define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & M_TXDROPCNTCH0RCVD)
5177 
5178 #define A_TP_TX_DROP_CNT_CH1 0x12e
5179 
5180 #define S_TXDROPCNTCH1SENT    16
5181 #define M_TXDROPCNTCH1SENT    0xffff
5182 #define V_TXDROPCNTCH1SENT(x) ((x) << S_TXDROPCNTCH1SENT)
5183 #define G_TXDROPCNTCH1SENT(x) (((x) >> S_TXDROPCNTCH1SENT) & M_TXDROPCNTCH1SENT)
5184 
5185 #define S_TXDROPCNTCH1RCVD    0
5186 #define M_TXDROPCNTCH1RCVD    0xffff
5187 #define V_TXDROPCNTCH1RCVD(x) ((x) << S_TXDROPCNTCH1RCVD)
5188 #define G_TXDROPCNTCH1RCVD(x) (((x) >> S_TXDROPCNTCH1RCVD) & M_TXDROPCNTCH1RCVD)
5189 
5190 #define A_TP_TX_DROP_MODE 0x12f
5191 
5192 #define S_TXDROPMODECH1    1
5193 #define V_TXDROPMODECH1(x) ((x) << S_TXDROPMODECH1)
5194 #define F_TXDROPMODECH1    V_TXDROPMODECH1(1U)
5195 
5196 #define S_TXDROPMODECH0    0
5197 #define V_TXDROPMODECH0(x) ((x) << S_TXDROPMODECH0)
5198 #define F_TXDROPMODECH0    V_TXDROPMODECH0(1U)
5199 
5200 #define A_TP_VLAN_PRI_MAP 0x137
5201 
5202 #define S_VLANPRIMAP7    14
5203 #define M_VLANPRIMAP7    0x3
5204 #define V_VLANPRIMAP7(x) ((x) << S_VLANPRIMAP7)
5205 #define G_VLANPRIMAP7(x) (((x) >> S_VLANPRIMAP7) & M_VLANPRIMAP7)
5206 
5207 #define S_VLANPRIMAP6    12
5208 #define M_VLANPRIMAP6    0x3
5209 #define V_VLANPRIMAP6(x) ((x) << S_VLANPRIMAP6)
5210 #define G_VLANPRIMAP6(x) (((x) >> S_VLANPRIMAP6) & M_VLANPRIMAP6)
5211 
5212 #define S_VLANPRIMAP5    10
5213 #define M_VLANPRIMAP5    0x3
5214 #define V_VLANPRIMAP5(x) ((x) << S_VLANPRIMAP5)
5215 #define G_VLANPRIMAP5(x) (((x) >> S_VLANPRIMAP5) & M_VLANPRIMAP5)
5216 
5217 #define S_VLANPRIMAP4    8
5218 #define M_VLANPRIMAP4    0x3
5219 #define V_VLANPRIMAP4(x) ((x) << S_VLANPRIMAP4)
5220 #define G_VLANPRIMAP4(x) (((x) >> S_VLANPRIMAP4) & M_VLANPRIMAP4)
5221 
5222 #define S_VLANPRIMAP3    6
5223 #define M_VLANPRIMAP3    0x3
5224 #define V_VLANPRIMAP3(x) ((x) << S_VLANPRIMAP3)
5225 #define G_VLANPRIMAP3(x) (((x) >> S_VLANPRIMAP3) & M_VLANPRIMAP3)
5226 
5227 #define S_VLANPRIMAP2    4
5228 #define M_VLANPRIMAP2    0x3
5229 #define V_VLANPRIMAP2(x) ((x) << S_VLANPRIMAP2)
5230 #define G_VLANPRIMAP2(x) (((x) >> S_VLANPRIMAP2) & M_VLANPRIMAP2)
5231 
5232 #define S_VLANPRIMAP1    2
5233 #define M_VLANPRIMAP1    0x3
5234 #define V_VLANPRIMAP1(x) ((x) << S_VLANPRIMAP1)
5235 #define G_VLANPRIMAP1(x) (((x) >> S_VLANPRIMAP1) & M_VLANPRIMAP1)
5236 
5237 #define S_VLANPRIMAP0    0
5238 #define M_VLANPRIMAP0    0x3
5239 #define V_VLANPRIMAP0(x) ((x) << S_VLANPRIMAP0)
5240 #define G_VLANPRIMAP0(x) (((x) >> S_VLANPRIMAP0) & M_VLANPRIMAP0)
5241 
5242 #define A_TP_MAC_MATCH_MAP0 0x138
5243 
5244 #define S_MACMATCHMAP7    21
5245 #define M_MACMATCHMAP7    0x7
5246 #define V_MACMATCHMAP7(x) ((x) << S_MACMATCHMAP7)
5247 #define G_MACMATCHMAP7(x) (((x) >> S_MACMATCHMAP7) & M_MACMATCHMAP7)
5248 
5249 #define S_MACMATCHMAP6    18
5250 #define M_MACMATCHMAP6    0x7
5251 #define V_MACMATCHMAP6(x) ((x) << S_MACMATCHMAP6)
5252 #define G_MACMATCHMAP6(x) (((x) >> S_MACMATCHMAP6) & M_MACMATCHMAP6)
5253 
5254 #define S_MACMATCHMAP5    15
5255 #define M_MACMATCHMAP5    0x7
5256 #define V_MACMATCHMAP5(x) ((x) << S_MACMATCHMAP5)
5257 #define G_MACMATCHMAP5(x) (((x) >> S_MACMATCHMAP5) & M_MACMATCHMAP5)
5258 
5259 #define S_MACMATCHMAP4    12
5260 #define M_MACMATCHMAP4    0x7
5261 #define V_MACMATCHMAP4(x) ((x) << S_MACMATCHMAP4)
5262 #define G_MACMATCHMAP4(x) (((x) >> S_MACMATCHMAP4) & M_MACMATCHMAP4)
5263 
5264 #define S_MACMATCHMAP3    9
5265 #define M_MACMATCHMAP3    0x7
5266 #define V_MACMATCHMAP3(x) ((x) << S_MACMATCHMAP3)
5267 #define G_MACMATCHMAP3(x) (((x) >> S_MACMATCHMAP3) & M_MACMATCHMAP3)
5268 
5269 #define S_MACMATCHMAP2    6
5270 #define M_MACMATCHMAP2    0x7
5271 #define V_MACMATCHMAP2(x) ((x) << S_MACMATCHMAP2)
5272 #define G_MACMATCHMAP2(x) (((x) >> S_MACMATCHMAP2) & M_MACMATCHMAP2)
5273 
5274 #define S_MACMATCHMAP1    3
5275 #define M_MACMATCHMAP1    0x7
5276 #define V_MACMATCHMAP1(x) ((x) << S_MACMATCHMAP1)
5277 #define G_MACMATCHMAP1(x) (((x) >> S_MACMATCHMAP1) & M_MACMATCHMAP1)
5278 
5279 #define S_MACMATCHMAP0    0
5280 #define M_MACMATCHMAP0    0x7
5281 #define V_MACMATCHMAP0(x) ((x) << S_MACMATCHMAP0)
5282 #define G_MACMATCHMAP0(x) (((x) >> S_MACMATCHMAP0) & M_MACMATCHMAP0)
5283 
5284 #define A_TP_MAC_MATCH_MAP1 0x139
5285 #define A_TP_INGRESS_CONFIG 0x141
5286 
5287 #define S_LOOKUPEVERYPKT    28
5288 #define V_LOOKUPEVERYPKT(x) ((x) << S_LOOKUPEVERYPKT)
5289 #define F_LOOKUPEVERYPKT    V_LOOKUPEVERYPKT(1U)
5290 
5291 #define S_ENABLEINSERTIONSFD    27
5292 #define V_ENABLEINSERTIONSFD(x) ((x) << S_ENABLEINSERTIONSFD)
5293 #define F_ENABLEINSERTIONSFD    V_ENABLEINSERTIONSFD(1U)
5294 
5295 #define S_ENABLEINSERTION    26
5296 #define V_ENABLEINSERTION(x) ((x) << S_ENABLEINSERTION)
5297 #define F_ENABLEINSERTION    V_ENABLEINSERTION(1U)
5298 
5299 #define S_ENABLEEXTRACTIONSFD    25
5300 #define V_ENABLEEXTRACTIONSFD(x) ((x) << S_ENABLEEXTRACTIONSFD)
5301 #define F_ENABLEEXTRACTIONSFD    V_ENABLEEXTRACTIONSFD(1U)
5302 
5303 #define S_ENABLEEXTRACT    24
5304 #define V_ENABLEEXTRACT(x) ((x) << S_ENABLEEXTRACT)
5305 #define F_ENABLEEXTRACT    V_ENABLEEXTRACT(1U)
5306 
5307 #define S_BITPOS3    18
5308 #define M_BITPOS3    0x3f
5309 #define V_BITPOS3(x) ((x) << S_BITPOS3)
5310 #define G_BITPOS3(x) (((x) >> S_BITPOS3) & M_BITPOS3)
5311 
5312 #define S_BITPOS2    12
5313 #define M_BITPOS2    0x3f
5314 #define V_BITPOS2(x) ((x) << S_BITPOS2)
5315 #define G_BITPOS2(x) (((x) >> S_BITPOS2) & M_BITPOS2)
5316 
5317 #define S_BITPOS1    6
5318 #define M_BITPOS1    0x3f
5319 #define V_BITPOS1(x) ((x) << S_BITPOS1)
5320 #define G_BITPOS1(x) (((x) >> S_BITPOS1) & M_BITPOS1)
5321 
5322 #define S_BITPOS0    0
5323 #define M_BITPOS0    0x3f
5324 #define V_BITPOS0(x) ((x) << S_BITPOS0)
5325 #define G_BITPOS0(x) (((x) >> S_BITPOS0) & M_BITPOS0)
5326 
5327 #define A_TP_PREAMBLE_MSB 0x142
5328 #define A_TP_PREAMBLE_LSB 0x143
5329 #define A_TP_EGRESS_CONFIG 0x145
5330 
5331 #define S_REWRITEFORCETOSIZE    0
5332 #define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE)
5333 #define F_REWRITEFORCETOSIZE    V_REWRITEFORCETOSIZE(1U)
5334 
5335 #define A_TP_INTF_FROM_TX_PKT 0x244
5336 
5337 #define S_INTFFROMTXPKT    0
5338 #define V_INTFFROMTXPKT(x) ((x) << S_INTFFROMTXPKT)
5339 #define F_INTFFROMTXPKT    V_INTFFROMTXPKT(1U)
5340 
5341 #define A_TP_FIFO_CONFIG 0x8c0
5342 
5343 #define S_RXFIFOCONFIG    10
5344 #define M_RXFIFOCONFIG    0x3f
5345 #define V_RXFIFOCONFIG(x) ((x) << S_RXFIFOCONFIG)
5346 #define G_RXFIFOCONFIG(x) (((x) >> S_RXFIFOCONFIG) & M_RXFIFOCONFIG)
5347 
5348 #define S_TXFIFOCONFIG    2
5349 #define M_TXFIFOCONFIG    0x3f
5350 #define V_TXFIFOCONFIG(x) ((x) << S_TXFIFOCONFIG)
5351 #define G_TXFIFOCONFIG(x) (((x) >> S_TXFIFOCONFIG) & M_TXFIFOCONFIG)
5352 
5353 /* registers for module ULP2_RX */
5354 #define ULP2_RX_BASE_ADDR 0x500
5355 
5356 #define A_ULPRX_CTL 0x500
5357 
5358 #define S_PCMD1THRESHOLD    24
5359 #define M_PCMD1THRESHOLD    0xff
5360 #define V_PCMD1THRESHOLD(x) ((x) << S_PCMD1THRESHOLD)
5361 #define G_PCMD1THRESHOLD(x) (((x) >> S_PCMD1THRESHOLD) & M_PCMD1THRESHOLD)
5362 
5363 #define S_PCMD0THRESHOLD    16
5364 #define M_PCMD0THRESHOLD    0xff
5365 #define V_PCMD0THRESHOLD(x) ((x) << S_PCMD0THRESHOLD)
5366 #define G_PCMD0THRESHOLD(x) (((x) >> S_PCMD0THRESHOLD) & M_PCMD0THRESHOLD)
5367 
5368 #define S_ROUND_ROBIN    4
5369 #define V_ROUND_ROBIN(x) ((x) << S_ROUND_ROBIN)
5370 #define F_ROUND_ROBIN    V_ROUND_ROBIN(1U)
5371 
5372 #define S_RDMA_PERMISSIVE_MODE    3
5373 #define V_RDMA_PERMISSIVE_MODE(x) ((x) << S_RDMA_PERMISSIVE_MODE)
5374 #define F_RDMA_PERMISSIVE_MODE    V_RDMA_PERMISSIVE_MODE(1U)
5375 
5376 #define S_PAGEPODME    2
5377 #define V_PAGEPODME(x) ((x) << S_PAGEPODME)
5378 #define F_PAGEPODME    V_PAGEPODME(1U)
5379 
5380 #define S_ISCSITAGTCB    1
5381 #define V_ISCSITAGTCB(x) ((x) << S_ISCSITAGTCB)
5382 #define F_ISCSITAGTCB    V_ISCSITAGTCB(1U)
5383 
5384 #define S_TDDPTAGTCB    0
5385 #define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB)
5386 #define F_TDDPTAGTCB    V_TDDPTAGTCB(1U)
5387 
5388 #define A_ULPRX_INT_ENABLE 0x504
5389 
5390 #define S_DATASELFRAMEERR0    7
5391 #define V_DATASELFRAMEERR0(x) ((x) << S_DATASELFRAMEERR0)
5392 #define F_DATASELFRAMEERR0    V_DATASELFRAMEERR0(1U)
5393 
5394 #define S_DATASELFRAMEERR1    6
5395 #define V_DATASELFRAMEERR1(x) ((x) << S_DATASELFRAMEERR1)
5396 #define F_DATASELFRAMEERR1    V_DATASELFRAMEERR1(1U)
5397 
5398 #define S_PCMDMUXPERR    5
5399 #define V_PCMDMUXPERR(x) ((x) << S_PCMDMUXPERR)
5400 #define F_PCMDMUXPERR    V_PCMDMUXPERR(1U)
5401 
5402 #define S_ARBFPERR    4
5403 #define V_ARBFPERR(x) ((x) << S_ARBFPERR)
5404 #define F_ARBFPERR    V_ARBFPERR(1U)
5405 
5406 #define S_ARBPF0PERR    3
5407 #define V_ARBPF0PERR(x) ((x) << S_ARBPF0PERR)
5408 #define F_ARBPF0PERR    V_ARBPF0PERR(1U)
5409 
5410 #define S_ARBPF1PERR    2
5411 #define V_ARBPF1PERR(x) ((x) << S_ARBPF1PERR)
5412 #define F_ARBPF1PERR    V_ARBPF1PERR(1U)
5413 
5414 #define S_PARERRPCMD    1
5415 #define V_PARERRPCMD(x) ((x) << S_PARERRPCMD)
5416 #define F_PARERRPCMD    V_PARERRPCMD(1U)
5417 
5418 #define S_PARERRDATA    0
5419 #define V_PARERRDATA(x) ((x) << S_PARERRDATA)
5420 #define F_PARERRDATA    V_PARERRDATA(1U)
5421 
5422 #define S_PARERR    0
5423 #define V_PARERR(x) ((x) << S_PARERR)
5424 #define F_PARERR    V_PARERR(1U)
5425 
5426 #define A_ULPRX_INT_CAUSE 0x508
5427 #define A_ULPRX_ISCSI_LLIMIT 0x50c
5428 
5429 #define S_ISCSILLIMIT    6
5430 #define M_ISCSILLIMIT    0x3ffffff
5431 #define V_ISCSILLIMIT(x) ((x) << S_ISCSILLIMIT)
5432 #define G_ISCSILLIMIT(x) (((x) >> S_ISCSILLIMIT) & M_ISCSILLIMIT)
5433 
5434 #define A_ULPRX_ISCSI_ULIMIT 0x510
5435 
5436 #define S_ISCSIULIMIT    6
5437 #define M_ISCSIULIMIT    0x3ffffff
5438 #define V_ISCSIULIMIT(x) ((x) << S_ISCSIULIMIT)
5439 #define G_ISCSIULIMIT(x) (((x) >> S_ISCSIULIMIT) & M_ISCSIULIMIT)
5440 
5441 #define A_ULPRX_ISCSI_TAGMASK 0x514
5442 
5443 #define S_ISCSITAGMASK    6
5444 #define M_ISCSITAGMASK    0x3ffffff
5445 #define V_ISCSITAGMASK(x) ((x) << S_ISCSITAGMASK)
5446 #define G_ISCSITAGMASK(x) (((x) >> S_ISCSITAGMASK) & M_ISCSITAGMASK)
5447 
5448 #define A_ULPRX_ISCSI_PSZ 0x518
5449 
5450 #define S_HPZ3    24
5451 #define M_HPZ3    0xf
5452 #define V_HPZ3(x) ((x) << S_HPZ3)
5453 #define G_HPZ3(x) (((x) >> S_HPZ3) & M_HPZ3)
5454 
5455 #define S_HPZ2    16
5456 #define M_HPZ2    0xf
5457 #define V_HPZ2(x) ((x) << S_HPZ2)
5458 #define G_HPZ2(x) (((x) >> S_HPZ2) & M_HPZ2)
5459 
5460 #define S_HPZ1    8
5461 #define M_HPZ1    0xf
5462 #define V_HPZ1(x) ((x) << S_HPZ1)
5463 #define G_HPZ1(x) (((x) >> S_HPZ1) & M_HPZ1)
5464 
5465 #define S_HPZ0    0
5466 #define M_HPZ0    0xf
5467 #define V_HPZ0(x) ((x) << S_HPZ0)
5468 #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
5469 
5470 #define A_ULPRX_TDDP_LLIMIT 0x51c
5471 
5472 #define S_TDDPLLIMIT    6
5473 #define M_TDDPLLIMIT    0x3ffffff
5474 #define V_TDDPLLIMIT(x) ((x) << S_TDDPLLIMIT)
5475 #define G_TDDPLLIMIT(x) (((x) >> S_TDDPLLIMIT) & M_TDDPLLIMIT)
5476 
5477 #define A_ULPRX_TDDP_ULIMIT 0x520
5478 
5479 #define S_TDDPULIMIT    6
5480 #define M_TDDPULIMIT    0x3ffffff
5481 #define V_TDDPULIMIT(x) ((x) << S_TDDPULIMIT)
5482 #define G_TDDPULIMIT(x) (((x) >> S_TDDPULIMIT) & M_TDDPULIMIT)
5483 
5484 #define A_ULPRX_TDDP_TAGMASK 0x524
5485 
5486 #define S_TDDPTAGMASK    6
5487 #define M_TDDPTAGMASK    0x3ffffff
5488 #define V_TDDPTAGMASK(x) ((x) << S_TDDPTAGMASK)
5489 #define G_TDDPTAGMASK(x) (((x) >> S_TDDPTAGMASK) & M_TDDPTAGMASK)
5490 
5491 #define A_ULPRX_TDDP_PSZ 0x528
5492 #define A_ULPRX_STAG_LLIMIT 0x52c
5493 #define A_ULPRX_STAG_ULIMIT 0x530
5494 #define A_ULPRX_RQ_LLIMIT 0x534
5495 #define A_ULPRX_RQ_ULIMIT 0x538
5496 #define A_ULPRX_PBL_LLIMIT 0x53c
5497 #define A_ULPRX_PBL_ULIMIT 0x540
5498 
5499 /* registers for module ULP2_TX */
5500 #define ULP2_TX_BASE_ADDR 0x580
5501 
5502 #define A_ULPTX_CONFIG 0x580
5503 
5504 #define S_CFG_CQE_SOP_MASK    1
5505 #define V_CFG_CQE_SOP_MASK(x) ((x) << S_CFG_CQE_SOP_MASK)
5506 #define F_CFG_CQE_SOP_MASK    V_CFG_CQE_SOP_MASK(1U)
5507 
5508 #define S_CFG_RR_ARB    0
5509 #define V_CFG_RR_ARB(x) ((x) << S_CFG_RR_ARB)
5510 #define F_CFG_RR_ARB    V_CFG_RR_ARB(1U)
5511 
5512 #define A_ULPTX_INT_ENABLE 0x584
5513 
5514 #define S_CMD_FIFO_PERR_SET1    7
5515 #define V_CMD_FIFO_PERR_SET1(x) ((x) << S_CMD_FIFO_PERR_SET1)
5516 #define F_CMD_FIFO_PERR_SET1    V_CMD_FIFO_PERR_SET1(1U)
5517 
5518 #define S_CMD_FIFO_PERR_SET0    6
5519 #define V_CMD_FIFO_PERR_SET0(x) ((x) << S_CMD_FIFO_PERR_SET0)
5520 #define F_CMD_FIFO_PERR_SET0    V_CMD_FIFO_PERR_SET0(1U)
5521 
5522 #define S_LSO_HDR_SRAM_PERR_SET1    5
5523 #define V_LSO_HDR_SRAM_PERR_SET1(x) ((x) << S_LSO_HDR_SRAM_PERR_SET1)
5524 #define F_LSO_HDR_SRAM_PERR_SET1    V_LSO_HDR_SRAM_PERR_SET1(1U)
5525 
5526 #define S_LSO_HDR_SRAM_PERR_SET0    4
5527 #define V_LSO_HDR_SRAM_PERR_SET0(x) ((x) << S_LSO_HDR_SRAM_PERR_SET0)
5528 #define F_LSO_HDR_SRAM_PERR_SET0    V_LSO_HDR_SRAM_PERR_SET0(1U)
5529 
5530 #define S_IMM_DATA_PERR_SET_CH1    3
5531 #define V_IMM_DATA_PERR_SET_CH1(x) ((x) << S_IMM_DATA_PERR_SET_CH1)
5532 #define F_IMM_DATA_PERR_SET_CH1    V_IMM_DATA_PERR_SET_CH1(1U)
5533 
5534 #define S_IMM_DATA_PERR_SET_CH0    2
5535 #define V_IMM_DATA_PERR_SET_CH0(x) ((x) << S_IMM_DATA_PERR_SET_CH0)
5536 #define F_IMM_DATA_PERR_SET_CH0    V_IMM_DATA_PERR_SET_CH0(1U)
5537 
5538 #define S_PBL_BOUND_ERR_CH1    1
5539 #define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1)
5540 #define F_PBL_BOUND_ERR_CH1    V_PBL_BOUND_ERR_CH1(1U)
5541 
5542 #define S_PBL_BOUND_ERR_CH0    0
5543 #define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0)
5544 #define F_PBL_BOUND_ERR_CH0    V_PBL_BOUND_ERR_CH0(1U)
5545 
5546 #define A_ULPTX_INT_CAUSE 0x588
5547 #define A_ULPTX_TPT_LLIMIT 0x58c
5548 #define A_ULPTX_TPT_ULIMIT 0x590
5549 #define A_ULPTX_PBL_LLIMIT 0x594
5550 #define A_ULPTX_PBL_ULIMIT 0x598
5551 #define A_ULPTX_CPL_ERR_OFFSET 0x59c
5552 #define A_ULPTX_CPL_ERR_MASK 0x5a0
5553 #define A_ULPTX_CPL_ERR_VALUE 0x5a4
5554 #define A_ULPTX_CPL_PACK_SIZE 0x5a8
5555 
5556 #define S_VALUE    24
5557 #define M_VALUE    0xff
5558 #define V_VALUE(x) ((x) << S_VALUE)
5559 #define G_VALUE(x) (((x) >> S_VALUE) & M_VALUE)
5560 
5561 #define S_CH1SIZE2    24
5562 #define M_CH1SIZE2    0xff
5563 #define V_CH1SIZE2(x) ((x) << S_CH1SIZE2)
5564 #define G_CH1SIZE2(x) (((x) >> S_CH1SIZE2) & M_CH1SIZE2)
5565 
5566 #define S_CH1SIZE1    16
5567 #define M_CH1SIZE1    0xff
5568 #define V_CH1SIZE1(x) ((x) << S_CH1SIZE1)
5569 #define G_CH1SIZE1(x) (((x) >> S_CH1SIZE1) & M_CH1SIZE1)
5570 
5571 #define S_CH0SIZE2    8
5572 #define M_CH0SIZE2    0xff
5573 #define V_CH0SIZE2(x) ((x) << S_CH0SIZE2)
5574 #define G_CH0SIZE2(x) (((x) >> S_CH0SIZE2) & M_CH0SIZE2)
5575 
5576 #define S_CH0SIZE1    0
5577 #define M_CH0SIZE1    0xff
5578 #define V_CH0SIZE1(x) ((x) << S_CH0SIZE1)
5579 #define G_CH0SIZE1(x) (((x) >> S_CH0SIZE1) & M_CH0SIZE1)
5580 
5581 #define A_ULPTX_DMA_WEIGHT 0x5ac
5582 
5583 #define S_D1_WEIGHT    16
5584 #define M_D1_WEIGHT    0xffff
5585 #define V_D1_WEIGHT(x) ((x) << S_D1_WEIGHT)
5586 #define G_D1_WEIGHT(x) (((x) >> S_D1_WEIGHT) & M_D1_WEIGHT)
5587 
5588 #define S_D0_WEIGHT    0
5589 #define M_D0_WEIGHT    0xffff
5590 #define V_D0_WEIGHT(x) ((x) << S_D0_WEIGHT)
5591 #define G_D0_WEIGHT(x) (((x) >> S_D0_WEIGHT) & M_D0_WEIGHT)
5592 
5593 /* registers for module PM1_RX */
5594 #define PM1_RX_BASE_ADDR 0x5c0
5595 
5596 #define A_PM1_RX_CFG 0x5c0
5597 #define A_PM1_RX_MODE 0x5c4
5598 
5599 #define S_STAT_CHANNEL    1
5600 #define V_STAT_CHANNEL(x) ((x) << S_STAT_CHANNEL)
5601 #define F_STAT_CHANNEL    V_STAT_CHANNEL(1U)
5602 
5603 #define S_PRIORITY_CH    0
5604 #define V_PRIORITY_CH(x) ((x) << S_PRIORITY_CH)
5605 #define F_PRIORITY_CH    V_PRIORITY_CH(1U)
5606 
5607 #define A_PM1_RX_STAT_CONFIG 0x5c8
5608 #define A_PM1_RX_STAT_COUNT 0x5cc
5609 #define A_PM1_RX_STAT_MSB 0x5d0
5610 #define A_PM1_RX_STAT_LSB 0x5d4
5611 #define A_PM1_RX_INT_ENABLE 0x5d8
5612 
5613 #define S_ZERO_E_CMD_ERROR    18
5614 #define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR)
5615 #define F_ZERO_E_CMD_ERROR    V_ZERO_E_CMD_ERROR(1U)
5616 
5617 #define S_IESPI0_FIFO2X_RX_FRAMING_ERROR    17
5618 #define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR)
5619 #define F_IESPI0_FIFO2X_RX_FRAMING_ERROR    V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U)
5620 
5621 #define S_IESPI1_FIFO2X_RX_FRAMING_ERROR    16
5622 #define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR)
5623 #define F_IESPI1_FIFO2X_RX_FRAMING_ERROR    V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U)
5624 
5625 #define S_IESPI0_RX_FRAMING_ERROR    15
5626 #define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR)
5627 #define F_IESPI0_RX_FRAMING_ERROR    V_IESPI0_RX_FRAMING_ERROR(1U)
5628 
5629 #define S_IESPI1_RX_FRAMING_ERROR    14
5630 #define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR)
5631 #define F_IESPI1_RX_FRAMING_ERROR    V_IESPI1_RX_FRAMING_ERROR(1U)
5632 
5633 #define S_IESPI0_TX_FRAMING_ERROR    13
5634 #define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR)
5635 #define F_IESPI0_TX_FRAMING_ERROR    V_IESPI0_TX_FRAMING_ERROR(1U)
5636 
5637 #define S_IESPI1_TX_FRAMING_ERROR    12
5638 #define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR)
5639 #define F_IESPI1_TX_FRAMING_ERROR    V_IESPI1_TX_FRAMING_ERROR(1U)
5640 
5641 #define S_OCSPI0_RX_FRAMING_ERROR    11
5642 #define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR)
5643 #define F_OCSPI0_RX_FRAMING_ERROR    V_OCSPI0_RX_FRAMING_ERROR(1U)
5644 
5645 #define S_OCSPI1_RX_FRAMING_ERROR    10
5646 #define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR)
5647 #define F_OCSPI1_RX_FRAMING_ERROR    V_OCSPI1_RX_FRAMING_ERROR(1U)
5648 
5649 #define S_OCSPI0_TX_FRAMING_ERROR    9
5650 #define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR)
5651 #define F_OCSPI0_TX_FRAMING_ERROR    V_OCSPI0_TX_FRAMING_ERROR(1U)
5652 
5653 #define S_OCSPI1_TX_FRAMING_ERROR    8
5654 #define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR)
5655 #define F_OCSPI1_TX_FRAMING_ERROR    V_OCSPI1_TX_FRAMING_ERROR(1U)
5656 
5657 #define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    7
5658 #define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR)
5659 #define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
5660 
5661 #define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    6
5662 #define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
5663 #define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
5664 
5665 #define S_IESPI_PAR_ERROR    3
5666 #define M_IESPI_PAR_ERROR    0x7
5667 #define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR)
5668 #define G_IESPI_PAR_ERROR(x) (((x) >> S_IESPI_PAR_ERROR) & M_IESPI_PAR_ERROR)
5669 
5670 #define S_OCSPI_PAR_ERROR    0
5671 #define M_OCSPI_PAR_ERROR    0x7
5672 #define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR)
5673 #define G_OCSPI_PAR_ERROR(x) (((x) >> S_OCSPI_PAR_ERROR) & M_OCSPI_PAR_ERROR)
5674 
5675 #define A_PM1_RX_INT_CAUSE 0x5dc
5676 
5677 /* registers for module PM1_TX */
5678 #define PM1_TX_BASE_ADDR 0x5e0
5679 
5680 #define A_PM1_TX_CFG 0x5e0
5681 #define A_PM1_TX_MODE 0x5e4
5682 #define A_PM1_TX_STAT_CONFIG 0x5e8
5683 #define A_PM1_TX_STAT_COUNT 0x5ec
5684 #define A_PM1_TX_STAT_MSB 0x5f0
5685 #define A_PM1_TX_STAT_LSB 0x5f4
5686 #define A_PM1_TX_INT_ENABLE 0x5f8
5687 
5688 #define S_ZERO_C_CMD_ERROR    18
5689 #define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR)
5690 #define F_ZERO_C_CMD_ERROR    V_ZERO_C_CMD_ERROR(1U)
5691 
5692 #define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR    17
5693 #define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
5694 #define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR    V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
5695 
5696 #define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR    16
5697 #define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
5698 #define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR    V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
5699 
5700 #define S_ICSPI0_RX_FRAMING_ERROR    15
5701 #define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR)
5702 #define F_ICSPI0_RX_FRAMING_ERROR    V_ICSPI0_RX_FRAMING_ERROR(1U)
5703 
5704 #define S_ICSPI1_RX_FRAMING_ERROR    14
5705 #define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR)
5706 #define F_ICSPI1_RX_FRAMING_ERROR    V_ICSPI1_RX_FRAMING_ERROR(1U)
5707 
5708 #define S_ICSPI0_TX_FRAMING_ERROR    13
5709 #define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR)
5710 #define F_ICSPI0_TX_FRAMING_ERROR    V_ICSPI0_TX_FRAMING_ERROR(1U)
5711 
5712 #define S_ICSPI1_TX_FRAMING_ERROR    12
5713 #define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR)
5714 #define F_ICSPI1_TX_FRAMING_ERROR    V_ICSPI1_TX_FRAMING_ERROR(1U)
5715 
5716 #define S_OESPI0_RX_FRAMING_ERROR    11
5717 #define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR)
5718 #define F_OESPI0_RX_FRAMING_ERROR    V_OESPI0_RX_FRAMING_ERROR(1U)
5719 
5720 #define S_OESPI1_RX_FRAMING_ERROR    10
5721 #define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR)
5722 #define F_OESPI1_RX_FRAMING_ERROR    V_OESPI1_RX_FRAMING_ERROR(1U)
5723 
5724 #define S_OESPI0_TX_FRAMING_ERROR    9
5725 #define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR)
5726 #define F_OESPI0_TX_FRAMING_ERROR    V_OESPI0_TX_FRAMING_ERROR(1U)
5727 
5728 #define S_OESPI1_TX_FRAMING_ERROR    8
5729 #define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR)
5730 #define F_OESPI1_TX_FRAMING_ERROR    V_OESPI1_TX_FRAMING_ERROR(1U)
5731 
5732 #define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR    7
5733 #define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
5734 #define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR    V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
5735 
5736 #define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR    6
5737 #define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
5738 #define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR    V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
5739 
5740 #define S_ICSPI_PAR_ERROR    3
5741 #define M_ICSPI_PAR_ERROR    0x7
5742 #define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR)
5743 #define G_ICSPI_PAR_ERROR(x) (((x) >> S_ICSPI_PAR_ERROR) & M_ICSPI_PAR_ERROR)
5744 
5745 #define S_OESPI_PAR_ERROR    0
5746 #define M_OESPI_PAR_ERROR    0x7
5747 #define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR)
5748 #define G_OESPI_PAR_ERROR(x) (((x) >> S_OESPI_PAR_ERROR) & M_OESPI_PAR_ERROR)
5749 
5750 #define A_PM1_TX_INT_CAUSE 0x5fc
5751 
5752 /* registers for module MPS0 */
5753 #define MPS0_BASE_ADDR 0x600
5754 
5755 #define A_MPS_CFG 0x600
5756 
5757 #define S_ENFORCEPKT    11
5758 #define V_ENFORCEPKT(x) ((x) << S_ENFORCEPKT)
5759 #define F_ENFORCEPKT    V_ENFORCEPKT(1U)
5760 
5761 #define S_SGETPQID    8
5762 #define M_SGETPQID    0x7
5763 #define V_SGETPQID(x) ((x) << S_SGETPQID)
5764 #define G_SGETPQID(x) (((x) >> S_SGETPQID) & M_SGETPQID)
5765 
5766 #define S_TPRXPORTSIZE    7
5767 #define V_TPRXPORTSIZE(x) ((x) << S_TPRXPORTSIZE)
5768 #define F_TPRXPORTSIZE    V_TPRXPORTSIZE(1U)
5769 
5770 #define S_TPTXPORT1SIZE    6
5771 #define V_TPTXPORT1SIZE(x) ((x) << S_TPTXPORT1SIZE)
5772 #define F_TPTXPORT1SIZE    V_TPTXPORT1SIZE(1U)
5773 
5774 #define S_TPTXPORT0SIZE    5
5775 #define V_TPTXPORT0SIZE(x) ((x) << S_TPTXPORT0SIZE)
5776 #define F_TPTXPORT0SIZE    V_TPTXPORT0SIZE(1U)
5777 
5778 #define S_TPRXPORTEN    4
5779 #define V_TPRXPORTEN(x) ((x) << S_TPRXPORTEN)
5780 #define F_TPRXPORTEN    V_TPRXPORTEN(1U)
5781 
5782 #define S_TPTXPORT1EN    3
5783 #define V_TPTXPORT1EN(x) ((x) << S_TPTXPORT1EN)
5784 #define F_TPTXPORT1EN    V_TPTXPORT1EN(1U)
5785 
5786 #define S_TPTXPORT0EN    2
5787 #define V_TPTXPORT0EN(x) ((x) << S_TPTXPORT0EN)
5788 #define F_TPTXPORT0EN    V_TPTXPORT0EN(1U)
5789 
5790 #define S_PORT1ACTIVE    1
5791 #define V_PORT1ACTIVE(x) ((x) << S_PORT1ACTIVE)
5792 #define F_PORT1ACTIVE    V_PORT1ACTIVE(1U)
5793 
5794 #define S_PORT0ACTIVE    0
5795 #define V_PORT0ACTIVE(x) ((x) << S_PORT0ACTIVE)
5796 #define F_PORT0ACTIVE    V_PORT0ACTIVE(1U)
5797 
5798 #define A_MPS_DRR_CFG1 0x604
5799 
5800 #define S_RLDWTTPD1    11
5801 #define M_RLDWTTPD1    0x7ff
5802 #define V_RLDWTTPD1(x) ((x) << S_RLDWTTPD1)
5803 #define G_RLDWTTPD1(x) (((x) >> S_RLDWTTPD1) & M_RLDWTTPD1)
5804 
5805 #define S_RLDWTTPD0    0
5806 #define M_RLDWTTPD0    0x7ff
5807 #define V_RLDWTTPD0(x) ((x) << S_RLDWTTPD0)
5808 #define G_RLDWTTPD0(x) (((x) >> S_RLDWTTPD0) & M_RLDWTTPD0)
5809 
5810 #define A_MPS_DRR_CFG2 0x608
5811 
5812 #define S_RLDWTTOTAL    0
5813 #define M_RLDWTTOTAL    0xfff
5814 #define V_RLDWTTOTAL(x) ((x) << S_RLDWTTOTAL)
5815 #define G_RLDWTTOTAL(x) (((x) >> S_RLDWTTOTAL) & M_RLDWTTOTAL)
5816 
5817 #define A_MPS_MCA_STATUS 0x60c
5818 
5819 #define S_MCAPKTCNT    12
5820 #define M_MCAPKTCNT    0xfffff
5821 #define V_MCAPKTCNT(x) ((x) << S_MCAPKTCNT)
5822 #define G_MCAPKTCNT(x) (((x) >> S_MCAPKTCNT) & M_MCAPKTCNT)
5823 
5824 #define S_MCADEPTH    0
5825 #define M_MCADEPTH    0xfff
5826 #define V_MCADEPTH(x) ((x) << S_MCADEPTH)
5827 #define G_MCADEPTH(x) (((x) >> S_MCADEPTH) & M_MCADEPTH)
5828 
5829 #define A_MPS_TX0_TP_CNT 0x610
5830 
5831 #define S_TX0TPDISCNT    24
5832 #define M_TX0TPDISCNT    0xff
5833 #define V_TX0TPDISCNT(x) ((x) << S_TX0TPDISCNT)
5834 #define G_TX0TPDISCNT(x) (((x) >> S_TX0TPDISCNT) & M_TX0TPDISCNT)
5835 
5836 #define S_TX0TPCNT    0
5837 #define M_TX0TPCNT    0xffffff
5838 #define V_TX0TPCNT(x) ((x) << S_TX0TPCNT)
5839 #define G_TX0TPCNT(x) (((x) >> S_TX0TPCNT) & M_TX0TPCNT)
5840 
5841 #define A_MPS_TX1_TP_CNT 0x614
5842 
5843 #define S_TX1TPDISCNT    24
5844 #define M_TX1TPDISCNT    0xff
5845 #define V_TX1TPDISCNT(x) ((x) << S_TX1TPDISCNT)
5846 #define G_TX1TPDISCNT(x) (((x) >> S_TX1TPDISCNT) & M_TX1TPDISCNT)
5847 
5848 #define S_TX1TPCNT    0
5849 #define M_TX1TPCNT    0xffffff
5850 #define V_TX1TPCNT(x) ((x) << S_TX1TPCNT)
5851 #define G_TX1TPCNT(x) (((x) >> S_TX1TPCNT) & M_TX1TPCNT)
5852 
5853 #define A_MPS_RX_TP_CNT 0x618
5854 
5855 #define S_RXTPDISCNT    24
5856 #define M_RXTPDISCNT    0xff
5857 #define V_RXTPDISCNT(x) ((x) << S_RXTPDISCNT)
5858 #define G_RXTPDISCNT(x) (((x) >> S_RXTPDISCNT) & M_RXTPDISCNT)
5859 
5860 #define S_RXTPCNT    0
5861 #define M_RXTPCNT    0xffffff
5862 #define V_RXTPCNT(x) ((x) << S_RXTPCNT)
5863 #define G_RXTPCNT(x) (((x) >> S_RXTPCNT) & M_RXTPCNT)
5864 
5865 #define A_MPS_INT_ENABLE 0x61c
5866 
5867 #define S_MCAPARERRENB    6
5868 #define M_MCAPARERRENB    0x7
5869 #define V_MCAPARERRENB(x) ((x) << S_MCAPARERRENB)
5870 #define G_MCAPARERRENB(x) (((x) >> S_MCAPARERRENB) & M_MCAPARERRENB)
5871 
5872 #define S_RXTPPARERRENB    4
5873 #define M_RXTPPARERRENB    0x3
5874 #define V_RXTPPARERRENB(x) ((x) << S_RXTPPARERRENB)
5875 #define G_RXTPPARERRENB(x) (((x) >> S_RXTPPARERRENB) & M_RXTPPARERRENB)
5876 
5877 #define S_TX1TPPARERRENB    2
5878 #define M_TX1TPPARERRENB    0x3
5879 #define V_TX1TPPARERRENB(x) ((x) << S_TX1TPPARERRENB)
5880 #define G_TX1TPPARERRENB(x) (((x) >> S_TX1TPPARERRENB) & M_TX1TPPARERRENB)
5881 
5882 #define S_TX0TPPARERRENB    0
5883 #define M_TX0TPPARERRENB    0x3
5884 #define V_TX0TPPARERRENB(x) ((x) << S_TX0TPPARERRENB)
5885 #define G_TX0TPPARERRENB(x) (((x) >> S_TX0TPPARERRENB) & M_TX0TPPARERRENB)
5886 
5887 #define A_MPS_INT_CAUSE 0x620
5888 
5889 #define S_MCAPARERR    6
5890 #define M_MCAPARERR    0x7
5891 #define V_MCAPARERR(x) ((x) << S_MCAPARERR)
5892 #define G_MCAPARERR(x) (((x) >> S_MCAPARERR) & M_MCAPARERR)
5893 
5894 #define S_RXTPPARERR    4
5895 #define M_RXTPPARERR    0x3
5896 #define V_RXTPPARERR(x) ((x) << S_RXTPPARERR)
5897 #define G_RXTPPARERR(x) (((x) >> S_RXTPPARERR) & M_RXTPPARERR)
5898 
5899 #define S_TX1TPPARERR    2
5900 #define M_TX1TPPARERR    0x3
5901 #define V_TX1TPPARERR(x) ((x) << S_TX1TPPARERR)
5902 #define G_TX1TPPARERR(x) (((x) >> S_TX1TPPARERR) & M_TX1TPPARERR)
5903 
5904 #define S_TX0TPPARERR    0
5905 #define M_TX0TPPARERR    0x3
5906 #define V_TX0TPPARERR(x) ((x) << S_TX0TPPARERR)
5907 #define G_TX0TPPARERR(x) (((x) >> S_TX0TPPARERR) & M_TX0TPPARERR)
5908 
5909 /* registers for module CPL_SWITCH */
5910 #define CPL_SWITCH_BASE_ADDR 0x640
5911 
5912 #define A_CPL_SWITCH_CNTRL 0x640
5913 
5914 #define S_CPL_PKT_TID    8
5915 #define M_CPL_PKT_TID    0xffffff
5916 #define V_CPL_PKT_TID(x) ((x) << S_CPL_PKT_TID)
5917 #define G_CPL_PKT_TID(x) (((x) >> S_CPL_PKT_TID) & M_CPL_PKT_TID)
5918 
5919 #define S_CIM_TO_UP_FULL_SIZE    4
5920 #define V_CIM_TO_UP_FULL_SIZE(x) ((x) << S_CIM_TO_UP_FULL_SIZE)
5921 #define F_CIM_TO_UP_FULL_SIZE    V_CIM_TO_UP_FULL_SIZE(1U)
5922 
5923 #define S_CPU_NO_3F_CIM_ENABLE    3
5924 #define V_CPU_NO_3F_CIM_ENABLE(x) ((x) << S_CPU_NO_3F_CIM_ENABLE)
5925 #define F_CPU_NO_3F_CIM_ENABLE    V_CPU_NO_3F_CIM_ENABLE(1U)
5926 
5927 #define S_SWITCH_TABLE_ENABLE    2
5928 #define V_SWITCH_TABLE_ENABLE(x) ((x) << S_SWITCH_TABLE_ENABLE)
5929 #define F_SWITCH_TABLE_ENABLE    V_SWITCH_TABLE_ENABLE(1U)
5930 
5931 #define S_SGE_ENABLE    1
5932 #define V_SGE_ENABLE(x) ((x) << S_SGE_ENABLE)
5933 #define F_SGE_ENABLE    V_SGE_ENABLE(1U)
5934 
5935 #define S_CIM_ENABLE    0
5936 #define V_CIM_ENABLE(x) ((x) << S_CIM_ENABLE)
5937 #define F_CIM_ENABLE    V_CIM_ENABLE(1U)
5938 
5939 #define A_CPL_SWITCH_TBL_IDX 0x644
5940 
5941 #define S_SWITCH_TBL_IDX    0
5942 #define M_SWITCH_TBL_IDX    0xf
5943 #define V_SWITCH_TBL_IDX(x) ((x) << S_SWITCH_TBL_IDX)
5944 #define G_SWITCH_TBL_IDX(x) (((x) >> S_SWITCH_TBL_IDX) & M_SWITCH_TBL_IDX)
5945 
5946 #define A_CPL_SWITCH_TBL_DATA 0x648
5947 #define A_CPL_SWITCH_ZERO_ERROR 0x64c
5948 
5949 #define S_ZERO_CMD    0
5950 #define M_ZERO_CMD    0xff
5951 #define V_ZERO_CMD(x) ((x) << S_ZERO_CMD)
5952 #define G_ZERO_CMD(x) (((x) >> S_ZERO_CMD) & M_ZERO_CMD)
5953 
5954 #define A_CPL_INTR_ENABLE 0x650
5955 
5956 #define S_CIM_OP_MAP_PERR    5
5957 #define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR)
5958 #define F_CIM_OP_MAP_PERR    V_CIM_OP_MAP_PERR(1U)
5959 
5960 #define S_CIM_OVFL_ERROR    4
5961 #define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR)
5962 #define F_CIM_OVFL_ERROR    V_CIM_OVFL_ERROR(1U)
5963 
5964 #define S_TP_FRAMING_ERROR    3
5965 #define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR)
5966 #define F_TP_FRAMING_ERROR    V_TP_FRAMING_ERROR(1U)
5967 
5968 #define S_SGE_FRAMING_ERROR    2
5969 #define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR)
5970 #define F_SGE_FRAMING_ERROR    V_SGE_FRAMING_ERROR(1U)
5971 
5972 #define S_CIM_FRAMING_ERROR    1
5973 #define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR)
5974 #define F_CIM_FRAMING_ERROR    V_CIM_FRAMING_ERROR(1U)
5975 
5976 #define S_ZERO_SWITCH_ERROR    0
5977 #define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR)
5978 #define F_ZERO_SWITCH_ERROR    V_ZERO_SWITCH_ERROR(1U)
5979 
5980 #define A_CPL_INTR_CAUSE 0x654
5981 #define A_CPL_MAP_TBL_IDX 0x658
5982 
5983 #define S_CPL_MAP_TBL_IDX    0
5984 #define M_CPL_MAP_TBL_IDX    0xff
5985 #define V_CPL_MAP_TBL_IDX(x) ((x) << S_CPL_MAP_TBL_IDX)
5986 #define G_CPL_MAP_TBL_IDX(x) (((x) >> S_CPL_MAP_TBL_IDX) & M_CPL_MAP_TBL_IDX)
5987 
5988 #define A_CPL_MAP_TBL_DATA 0x65c
5989 
5990 #define S_CPL_MAP_TBL_DATA    0
5991 #define M_CPL_MAP_TBL_DATA    0xff
5992 #define V_CPL_MAP_TBL_DATA(x) ((x) << S_CPL_MAP_TBL_DATA)
5993 #define G_CPL_MAP_TBL_DATA(x) (((x) >> S_CPL_MAP_TBL_DATA) & M_CPL_MAP_TBL_DATA)
5994 
5995 /* registers for module SMB0 */
5996 #define SMB0_BASE_ADDR 0x660
5997 
5998 #define A_SMB_GLOBAL_TIME_CFG 0x660
5999 
6000 #define S_LADBGWRPTR    24
6001 #define M_LADBGWRPTR    0xff
6002 #define V_LADBGWRPTR(x) ((x) << S_LADBGWRPTR)
6003 #define G_LADBGWRPTR(x) (((x) >> S_LADBGWRPTR) & M_LADBGWRPTR)
6004 
6005 #define S_LADBGRDPTR    16
6006 #define M_LADBGRDPTR    0xff
6007 #define V_LADBGRDPTR(x) ((x) << S_LADBGRDPTR)
6008 #define G_LADBGRDPTR(x) (((x) >> S_LADBGRDPTR) & M_LADBGRDPTR)
6009 
6010 #define S_LADBGEN    13
6011 #define V_LADBGEN(x) ((x) << S_LADBGEN)
6012 #define F_LADBGEN    V_LADBGEN(1U)
6013 
6014 #define S_MACROCNTCFG    8
6015 #define M_MACROCNTCFG    0x1f
6016 #define V_MACROCNTCFG(x) ((x) << S_MACROCNTCFG)
6017 #define G_MACROCNTCFG(x) (((x) >> S_MACROCNTCFG) & M_MACROCNTCFG)
6018 
6019 #define S_MICROCNTCFG    0
6020 #define M_MICROCNTCFG    0xff
6021 #define V_MICROCNTCFG(x) ((x) << S_MICROCNTCFG)
6022 #define G_MICROCNTCFG(x) (((x) >> S_MICROCNTCFG) & M_MICROCNTCFG)
6023 
6024 #define A_SMB_MST_TIMEOUT_CFG 0x664
6025 
6026 #define S_DEBUGSELH    28
6027 #define M_DEBUGSELH    0xf
6028 #define V_DEBUGSELH(x) ((x) << S_DEBUGSELH)
6029 #define G_DEBUGSELH(x) (((x) >> S_DEBUGSELH) & M_DEBUGSELH)
6030 
6031 #define S_DEBUGSELL    24
6032 #define M_DEBUGSELL    0xf
6033 #define V_DEBUGSELL(x) ((x) << S_DEBUGSELL)
6034 #define G_DEBUGSELL(x) (((x) >> S_DEBUGSELL) & M_DEBUGSELL)
6035 
6036 #define S_MSTTIMEOUTCFG    0
6037 #define M_MSTTIMEOUTCFG    0xffffff
6038 #define V_MSTTIMEOUTCFG(x) ((x) << S_MSTTIMEOUTCFG)
6039 #define G_MSTTIMEOUTCFG(x) (((x) >> S_MSTTIMEOUTCFG) & M_MSTTIMEOUTCFG)
6040 
6041 #define A_SMB_MST_CTL_CFG 0x668
6042 
6043 #define S_MSTFIFODBG    31
6044 #define V_MSTFIFODBG(x) ((x) << S_MSTFIFODBG)
6045 #define F_MSTFIFODBG    V_MSTFIFODBG(1U)
6046 
6047 #define S_MSTFIFODBGCLR    30
6048 #define V_MSTFIFODBGCLR(x) ((x) << S_MSTFIFODBGCLR)
6049 #define F_MSTFIFODBGCLR    V_MSTFIFODBGCLR(1U)
6050 
6051 #define S_MSTRXBYTECFG    12
6052 #define M_MSTRXBYTECFG    0x3f
6053 #define V_MSTRXBYTECFG(x) ((x) << S_MSTRXBYTECFG)
6054 #define G_MSTRXBYTECFG(x) (((x) >> S_MSTRXBYTECFG) & M_MSTRXBYTECFG)
6055 
6056 #define S_MSTTXBYTECFG    6
6057 #define M_MSTTXBYTECFG    0x3f
6058 #define V_MSTTXBYTECFG(x) ((x) << S_MSTTXBYTECFG)
6059 #define G_MSTTXBYTECFG(x) (((x) >> S_MSTTXBYTECFG) & M_MSTTXBYTECFG)
6060 
6061 #define S_MSTRESET    1
6062 #define V_MSTRESET(x) ((x) << S_MSTRESET)
6063 #define F_MSTRESET    V_MSTRESET(1U)
6064 
6065 #define S_MSTCTLEN    0
6066 #define V_MSTCTLEN(x) ((x) << S_MSTCTLEN)
6067 #define F_MSTCTLEN    V_MSTCTLEN(1U)
6068 
6069 #define A_SMB_MST_CTL_STS 0x66c
6070 
6071 #define S_MSTRXBYTECNT    12
6072 #define M_MSTRXBYTECNT    0x3f
6073 #define V_MSTRXBYTECNT(x) ((x) << S_MSTRXBYTECNT)
6074 #define G_MSTRXBYTECNT(x) (((x) >> S_MSTRXBYTECNT) & M_MSTRXBYTECNT)
6075 
6076 #define S_MSTTXBYTECNT    6
6077 #define M_MSTTXBYTECNT    0x3f
6078 #define V_MSTTXBYTECNT(x) ((x) << S_MSTTXBYTECNT)
6079 #define G_MSTTXBYTECNT(x) (((x) >> S_MSTTXBYTECNT) & M_MSTTXBYTECNT)
6080 
6081 #define S_MSTBUSYSTS    0
6082 #define V_MSTBUSYSTS(x) ((x) << S_MSTBUSYSTS)
6083 #define F_MSTBUSYSTS    V_MSTBUSYSTS(1U)
6084 
6085 #define A_SMB_MST_TX_FIFO_RDWR 0x670
6086 #define A_SMB_MST_RX_FIFO_RDWR 0x674
6087 #define A_SMB_SLV_TIMEOUT_CFG 0x678
6088 
6089 #define S_SLVTIMEOUTCFG    0
6090 #define M_SLVTIMEOUTCFG    0xffffff
6091 #define V_SLVTIMEOUTCFG(x) ((x) << S_SLVTIMEOUTCFG)
6092 #define G_SLVTIMEOUTCFG(x) (((x) >> S_SLVTIMEOUTCFG) & M_SLVTIMEOUTCFG)
6093 
6094 #define A_SMB_SLV_CTL_CFG 0x67c
6095 
6096 #define S_SLVFIFODBG    31
6097 #define V_SLVFIFODBG(x) ((x) << S_SLVFIFODBG)
6098 #define F_SLVFIFODBG    V_SLVFIFODBG(1U)
6099 
6100 #define S_SLVFIFODBGCLR    30
6101 #define V_SLVFIFODBGCLR(x) ((x) << S_SLVFIFODBGCLR)
6102 #define F_SLVFIFODBGCLR    V_SLVFIFODBGCLR(1U)
6103 
6104 #define S_SLVADDRCFG    4
6105 #define M_SLVADDRCFG    0x7f
6106 #define V_SLVADDRCFG(x) ((x) << S_SLVADDRCFG)
6107 #define G_SLVADDRCFG(x) (((x) >> S_SLVADDRCFG) & M_SLVADDRCFG)
6108 
6109 #define S_SLVALRTSET    2
6110 #define V_SLVALRTSET(x) ((x) << S_SLVALRTSET)
6111 #define F_SLVALRTSET    V_SLVALRTSET(1U)
6112 
6113 #define S_SLVRESET    1
6114 #define V_SLVRESET(x) ((x) << S_SLVRESET)
6115 #define F_SLVRESET    V_SLVRESET(1U)
6116 
6117 #define S_SLVCTLEN    0
6118 #define V_SLVCTLEN(x) ((x) << S_SLVCTLEN)
6119 #define F_SLVCTLEN    V_SLVCTLEN(1U)
6120 
6121 #define A_SMB_SLV_CTL_STS 0x680
6122 
6123 #define S_SLVFIFOTXCNT    12
6124 #define M_SLVFIFOTXCNT    0x3f
6125 #define V_SLVFIFOTXCNT(x) ((x) << S_SLVFIFOTXCNT)
6126 #define G_SLVFIFOTXCNT(x) (((x) >> S_SLVFIFOTXCNT) & M_SLVFIFOTXCNT)
6127 
6128 #define S_SLVFIFOCNT    6
6129 #define M_SLVFIFOCNT    0x3f
6130 #define V_SLVFIFOCNT(x) ((x) << S_SLVFIFOCNT)
6131 #define G_SLVFIFOCNT(x) (((x) >> S_SLVFIFOCNT) & M_SLVFIFOCNT)
6132 
6133 #define S_SLVALRTSTS    2
6134 #define V_SLVALRTSTS(x) ((x) << S_SLVALRTSTS)
6135 #define F_SLVALRTSTS    V_SLVALRTSTS(1U)
6136 
6137 #define S_SLVBUSYSTS    0
6138 #define V_SLVBUSYSTS(x) ((x) << S_SLVBUSYSTS)
6139 #define F_SLVBUSYSTS    V_SLVBUSYSTS(1U)
6140 
6141 #define A_SMB_SLV_FIFO_RDWR 0x684
6142 #define A_SMB_SLV_CMD_FIFO_RDWR 0x688
6143 #define A_SMB_INT_ENABLE 0x68c
6144 
6145 #define S_SLVTIMEOUTINTEN    7
6146 #define V_SLVTIMEOUTINTEN(x) ((x) << S_SLVTIMEOUTINTEN)
6147 #define F_SLVTIMEOUTINTEN    V_SLVTIMEOUTINTEN(1U)
6148 
6149 #define S_SLVERRINTEN    6
6150 #define V_SLVERRINTEN(x) ((x) << S_SLVERRINTEN)
6151 #define F_SLVERRINTEN    V_SLVERRINTEN(1U)
6152 
6153 #define S_SLVDONEINTEN    5
6154 #define V_SLVDONEINTEN(x) ((x) << S_SLVDONEINTEN)
6155 #define F_SLVDONEINTEN    V_SLVDONEINTEN(1U)
6156 
6157 #define S_SLVRXRDYINTEN    4
6158 #define V_SLVRXRDYINTEN(x) ((x) << S_SLVRXRDYINTEN)
6159 #define F_SLVRXRDYINTEN    V_SLVRXRDYINTEN(1U)
6160 
6161 #define S_MSTTIMEOUTINTEN    3
6162 #define V_MSTTIMEOUTINTEN(x) ((x) << S_MSTTIMEOUTINTEN)
6163 #define F_MSTTIMEOUTINTEN    V_MSTTIMEOUTINTEN(1U)
6164 
6165 #define S_MSTNACKINTEN    2
6166 #define V_MSTNACKINTEN(x) ((x) << S_MSTNACKINTEN)
6167 #define F_MSTNACKINTEN    V_MSTNACKINTEN(1U)
6168 
6169 #define S_MSTLOSTARBINTEN    1
6170 #define V_MSTLOSTARBINTEN(x) ((x) << S_MSTLOSTARBINTEN)
6171 #define F_MSTLOSTARBINTEN    V_MSTLOSTARBINTEN(1U)
6172 
6173 #define S_MSTDONEINTEN    0
6174 #define V_MSTDONEINTEN(x) ((x) << S_MSTDONEINTEN)
6175 #define F_MSTDONEINTEN    V_MSTDONEINTEN(1U)
6176 
6177 #define A_SMB_INT_CAUSE 0x690
6178 
6179 #define S_SLVTIMEOUTINT    7
6180 #define V_SLVTIMEOUTINT(x) ((x) << S_SLVTIMEOUTINT)
6181 #define F_SLVTIMEOUTINT    V_SLVTIMEOUTINT(1U)
6182 
6183 #define S_SLVERRINT    6
6184 #define V_SLVERRINT(x) ((x) << S_SLVERRINT)
6185 #define F_SLVERRINT    V_SLVERRINT(1U)
6186 
6187 #define S_SLVDONEINT    5
6188 #define V_SLVDONEINT(x) ((x) << S_SLVDONEINT)
6189 #define F_SLVDONEINT    V_SLVDONEINT(1U)
6190 
6191 #define S_SLVRXRDYINT    4
6192 #define V_SLVRXRDYINT(x) ((x) << S_SLVRXRDYINT)
6193 #define F_SLVRXRDYINT    V_SLVRXRDYINT(1U)
6194 
6195 #define S_MSTTIMEOUTINT    3
6196 #define V_MSTTIMEOUTINT(x) ((x) << S_MSTTIMEOUTINT)
6197 #define F_MSTTIMEOUTINT    V_MSTTIMEOUTINT(1U)
6198 
6199 #define S_MSTNACKINT    2
6200 #define V_MSTNACKINT(x) ((x) << S_MSTNACKINT)
6201 #define F_MSTNACKINT    V_MSTNACKINT(1U)
6202 
6203 #define S_MSTLOSTARBINT    1
6204 #define V_MSTLOSTARBINT(x) ((x) << S_MSTLOSTARBINT)
6205 #define F_MSTLOSTARBINT    V_MSTLOSTARBINT(1U)
6206 
6207 #define S_MSTDONEINT    0
6208 #define V_MSTDONEINT(x) ((x) << S_MSTDONEINT)
6209 #define F_MSTDONEINT    V_MSTDONEINT(1U)
6210 
6211 #define A_SMB_DEBUG_DATA 0x694
6212 
6213 #define S_DEBUGDATAH    16
6214 #define M_DEBUGDATAH    0xffff
6215 #define V_DEBUGDATAH(x) ((x) << S_DEBUGDATAH)
6216 #define G_DEBUGDATAH(x) (((x) >> S_DEBUGDATAH) & M_DEBUGDATAH)
6217 
6218 #define S_DEBUGDATAL    0
6219 #define M_DEBUGDATAL    0xffff
6220 #define V_DEBUGDATAL(x) ((x) << S_DEBUGDATAL)
6221 #define G_DEBUGDATAL(x) (((x) >> S_DEBUGDATAL) & M_DEBUGDATAL)
6222 
6223 #define A_SMB_DEBUG_LA 0x69c
6224 
6225 #define S_DEBUGLAREQADDR    0
6226 #define M_DEBUGLAREQADDR    0x3ff
6227 #define V_DEBUGLAREQADDR(x) ((x) << S_DEBUGLAREQADDR)
6228 #define G_DEBUGLAREQADDR(x) (((x) >> S_DEBUGLAREQADDR) & M_DEBUGLAREQADDR)
6229 
6230 /* registers for module I2CM0 */
6231 #define I2CM0_BASE_ADDR 0x6a0
6232 
6233 #define A_I2C_CFG 0x6a0
6234 
6235 #define S_I2C_CLKDIV    0
6236 #define M_I2C_CLKDIV    0xfff
6237 #define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV)
6238 #define G_I2C_CLKDIV(x) (((x) >> S_I2C_CLKDIV) & M_I2C_CLKDIV)
6239 
6240 #define A_I2C_DATA 0x6a4
6241 #define A_I2C_OP 0x6a8
6242 
6243 #define S_ACK    30
6244 #define V_ACK(x) ((x) << S_ACK)
6245 #define F_ACK    V_ACK(1U)
6246 
6247 #define S_I2C_DATA    0
6248 #define M_I2C_DATA    0xff
6249 #define V_I2C_DATA(x) ((x) << S_I2C_DATA)
6250 #define G_I2C_DATA(x) (((x) >> S_I2C_DATA) & M_I2C_DATA)
6251 
6252 #define S_I2C_BUSY    31
6253 #define V_I2C_BUSY(x) ((x) << S_I2C_BUSY)
6254 #define F_I2C_BUSY    V_I2C_BUSY(1U)
6255 
6256 #define S_I2C_ACK     30
6257 #define V_I2C_ACK(x)  ((x) << S_I2C_ACK)
6258 #define F_I2C_ACK     V_I2C_ACK(1U)
6259 
6260 #define S_I2C_CONT    1
6261 #define V_I2C_CONT(x) ((x) << S_I2C_CONT)
6262 #define F_I2C_CONT    V_I2C_CONT(1U)
6263 
6264 #define S_I2C_RDWR    0
6265 #define V_I2C_RDWR(x) ((x) << S_I2C_RDWR)
6266 #define F_I2C_READ    V_I2C_RDWR(0U)
6267 #define F_I2C_WRITE   V_I2C_RDWR(1U)
6268 
6269 /* registers for module MI1 */
6270 #define MI1_BASE_ADDR 0x6b0
6271 
6272 #define A_MI1_CFG 0x6b0
6273 
6274 #define S_CLKDIV    5
6275 #define M_CLKDIV    0xff
6276 #define V_CLKDIV(x) ((x) << S_CLKDIV)
6277 #define G_CLKDIV(x) (((x) >> S_CLKDIV) & M_CLKDIV)
6278 
6279 #define S_ST    3
6280 #define M_ST    0x3
6281 #define V_ST(x) ((x) << S_ST)
6282 #define G_ST(x) (((x) >> S_ST) & M_ST)
6283 
6284 #define S_PREEN    2
6285 #define V_PREEN(x) ((x) << S_PREEN)
6286 #define F_PREEN    V_PREEN(1U)
6287 
6288 #define S_MDIINV    1
6289 #define V_MDIINV(x) ((x) << S_MDIINV)
6290 #define F_MDIINV    V_MDIINV(1U)
6291 
6292 #define S_MDIEN    0
6293 #define V_MDIEN(x) ((x) << S_MDIEN)
6294 #define F_MDIEN    V_MDIEN(1U)
6295 
6296 #define A_MI1_ADDR 0x6b4
6297 
6298 #define S_PHYADDR    5
6299 #define M_PHYADDR    0x1f
6300 #define V_PHYADDR(x) ((x) << S_PHYADDR)
6301 #define G_PHYADDR(x) (((x) >> S_PHYADDR) & M_PHYADDR)
6302 
6303 #define S_REGADDR    0
6304 #define M_REGADDR    0x1f
6305 #define V_REGADDR(x) ((x) << S_REGADDR)
6306 #define G_REGADDR(x) (((x) >> S_REGADDR) & M_REGADDR)
6307 
6308 #define A_MI1_DATA 0x6b8
6309 
6310 #define S_MDI_DATA    0
6311 #define M_MDI_DATA    0xffff
6312 #define V_MDI_DATA(x) ((x) << S_MDI_DATA)
6313 #define G_MDI_DATA(x) (((x) >> S_MDI_DATA) & M_MDI_DATA)
6314 
6315 #define A_MI1_OP 0x6bc
6316 
6317 #define S_INC    2
6318 #define V_INC(x) ((x) << S_INC)
6319 #define F_INC    V_INC(1U)
6320 
6321 #define S_MDI_OP    0
6322 #define M_MDI_OP    0x3
6323 #define V_MDI_OP(x) ((x) << S_MDI_OP)
6324 #define G_MDI_OP(x) (((x) >> S_MDI_OP) & M_MDI_OP)
6325 
6326 /* registers for module JM1 */
6327 #define JM1_BASE_ADDR 0x6c0
6328 
6329 #define A_JM_CFG 0x6c0
6330 
6331 #define S_JM_CLKDIV    2
6332 #define M_JM_CLKDIV    0xff
6333 #define V_JM_CLKDIV(x) ((x) << S_JM_CLKDIV)
6334 #define G_JM_CLKDIV(x) (((x) >> S_JM_CLKDIV) & M_JM_CLKDIV)
6335 
6336 #define S_TRST    1
6337 #define V_TRST(x) ((x) << S_TRST)
6338 #define F_TRST    V_TRST(1U)
6339 
6340 #define S_EN    0
6341 #define V_EN(x) ((x) << S_EN)
6342 #define F_EN    V_EN(1U)
6343 
6344 #define A_JM_MODE 0x6c4
6345 #define A_JM_DATA 0x6c8
6346 #define A_JM_OP 0x6cc
6347 
6348 #define S_CNT    0
6349 #define M_CNT    0x1f
6350 #define V_CNT(x) ((x) << S_CNT)
6351 #define G_CNT(x) (((x) >> S_CNT) & M_CNT)
6352 
6353 /* registers for module SF1 */
6354 #define SF1_BASE_ADDR 0x6d8
6355 
6356 #define A_SF_DATA 0x6d8
6357 #define A_SF_OP 0x6dc
6358 
6359 #define S_BYTECNT    1
6360 #define M_BYTECNT    0x3
6361 #define V_BYTECNT(x) ((x) << S_BYTECNT)
6362 #define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT)
6363 
6364 /* registers for module PL3 */
6365 #define PL3_BASE_ADDR 0x6e0
6366 
6367 #define A_PL_INT_ENABLE0 0x6e0
6368 
6369 #define S_SW    25
6370 #define V_SW(x) ((x) << S_SW)
6371 #define F_SW    V_SW(1U)
6372 
6373 #define S_EXT    24
6374 #define V_EXT(x) ((x) << S_EXT)
6375 #define F_EXT    V_EXT(1U)
6376 
6377 #define S_T3DBG    23
6378 #define V_T3DBG(x) ((x) << S_T3DBG)
6379 #define F_T3DBG    V_T3DBG(1U)
6380 
6381 #define S_XGMAC0_1    20
6382 #define V_XGMAC0_1(x) ((x) << S_XGMAC0_1)
6383 #define F_XGMAC0_1    V_XGMAC0_1(1U)
6384 
6385 #define S_XGMAC0_0    19
6386 #define V_XGMAC0_0(x) ((x) << S_XGMAC0_0)
6387 #define F_XGMAC0_0    V_XGMAC0_0(1U)
6388 
6389 #define S_MC5A    18
6390 #define V_MC5A(x) ((x) << S_MC5A)
6391 #define F_MC5A    V_MC5A(1U)
6392 
6393 #define S_SF1    17
6394 #define V_SF1(x) ((x) << S_SF1)
6395 #define F_SF1    V_SF1(1U)
6396 
6397 #define S_SMB0    15
6398 #define V_SMB0(x) ((x) << S_SMB0)
6399 #define F_SMB0    V_SMB0(1U)
6400 
6401 #define S_I2CM0    14
6402 #define V_I2CM0(x) ((x) << S_I2CM0)
6403 #define F_I2CM0    V_I2CM0(1U)
6404 
6405 #define S_MI1    13
6406 #define V_MI1(x) ((x) << S_MI1)
6407 #define F_MI1    V_MI1(1U)
6408 
6409 #define S_CPL_SWITCH    12
6410 #define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH)
6411 #define F_CPL_SWITCH    V_CPL_SWITCH(1U)
6412 
6413 #define S_MPS0    11
6414 #define V_MPS0(x) ((x) << S_MPS0)
6415 #define F_MPS0    V_MPS0(1U)
6416 
6417 #define S_PM1_TX    10
6418 #define V_PM1_TX(x) ((x) << S_PM1_TX)
6419 #define F_PM1_TX    V_PM1_TX(1U)
6420 
6421 #define S_PM1_RX    9
6422 #define V_PM1_RX(x) ((x) << S_PM1_RX)
6423 #define F_PM1_RX    V_PM1_RX(1U)
6424 
6425 #define S_ULP2_TX    8
6426 #define V_ULP2_TX(x) ((x) << S_ULP2_TX)
6427 #define F_ULP2_TX    V_ULP2_TX(1U)
6428 
6429 #define S_ULP2_RX    7
6430 #define V_ULP2_RX(x) ((x) << S_ULP2_RX)
6431 #define F_ULP2_RX    V_ULP2_RX(1U)
6432 
6433 #define S_TP1    6
6434 #define V_TP1(x) ((x) << S_TP1)
6435 #define F_TP1    V_TP1(1U)
6436 
6437 #define S_CIM    5
6438 #define V_CIM(x) ((x) << S_CIM)
6439 #define F_CIM    V_CIM(1U)
6440 
6441 #define S_MC7_CM    4
6442 #define V_MC7_CM(x) ((x) << S_MC7_CM)
6443 #define F_MC7_CM    V_MC7_CM(1U)
6444 
6445 #define S_MC7_PMTX    3
6446 #define V_MC7_PMTX(x) ((x) << S_MC7_PMTX)
6447 #define F_MC7_PMTX    V_MC7_PMTX(1U)
6448 
6449 #define S_MC7_PMRX    2
6450 #define V_MC7_PMRX(x) ((x) << S_MC7_PMRX)
6451 #define F_MC7_PMRX    V_MC7_PMRX(1U)
6452 
6453 #define S_PCIM0    1
6454 #define V_PCIM0(x) ((x) << S_PCIM0)
6455 #define F_PCIM0    V_PCIM0(1U)
6456 
6457 #define S_SGE3    0
6458 #define V_SGE3(x) ((x) << S_SGE3)
6459 #define F_SGE3    V_SGE3(1U)
6460 
6461 #define A_PL_INT_CAUSE0 0x6e4
6462 #define A_PL_INT_ENABLE1 0x6e8
6463 #define A_PL_INT_CAUSE1 0x6ec
6464 #define A_PL_RST 0x6f0
6465 
6466 #define S_FATALPERREN    4
6467 #define V_FATALPERREN(x) ((x) << S_FATALPERREN)
6468 #define F_FATALPERREN    V_FATALPERREN(1U)
6469 
6470 #define S_SWINT1    3
6471 #define V_SWINT1(x) ((x) << S_SWINT1)
6472 #define F_SWINT1    V_SWINT1(1U)
6473 
6474 #define S_SWINT0    2
6475 #define V_SWINT0(x) ((x) << S_SWINT0)
6476 #define F_SWINT0    V_SWINT0(1U)
6477 
6478 #define S_CRSTWRM    1
6479 #define V_CRSTWRM(x) ((x) << S_CRSTWRM)
6480 #define F_CRSTWRM    V_CRSTWRM(1U)
6481 
6482 #define A_PL_REV 0x6f4
6483 
6484 #define S_REV    0
6485 #define M_REV    0xf
6486 #define V_REV(x) ((x) << S_REV)
6487 #define G_REV(x) (((x) >> S_REV) & M_REV)
6488 
6489 #define A_PL_CLI 0x6f8
6490 #define A_PL_LCK 0x6fc
6491 
6492 #define S_LCK    0
6493 #define M_LCK    0x3
6494 #define V_LCK(x) ((x) << S_LCK)
6495 #define G_LCK(x) (((x) >> S_LCK) & M_LCK)
6496 
6497 /* registers for module MC5A */
6498 #define MC5A_BASE_ADDR 0x700
6499 
6500 #define A_MC5_BUF_CONFIG 0x700
6501 
6502 #define S_TERM300_240    31
6503 #define V_TERM300_240(x) ((x) << S_TERM300_240)
6504 #define F_TERM300_240    V_TERM300_240(1U)
6505 
6506 #define S_MC5_TERM150    30
6507 #define V_MC5_TERM150(x) ((x) << S_MC5_TERM150)
6508 #define F_MC5_TERM150    V_MC5_TERM150(1U)
6509 
6510 #define S_TERM60    29
6511 #define V_TERM60(x) ((x) << S_TERM60)
6512 #define F_TERM60    V_TERM60(1U)
6513 
6514 #define S_GDDRIII    28
6515 #define V_GDDRIII(x) ((x) << S_GDDRIII)
6516 #define F_GDDRIII    V_GDDRIII(1U)
6517 
6518 #define S_GDDRII    27
6519 #define V_GDDRII(x) ((x) << S_GDDRII)
6520 #define F_GDDRII    V_GDDRII(1U)
6521 
6522 #define S_GDDRI    26
6523 #define V_GDDRI(x) ((x) << S_GDDRI)
6524 #define F_GDDRI    V_GDDRI(1U)
6525 
6526 #define S_READ    25
6527 #define V_READ(x) ((x) << S_READ)
6528 #define F_READ    V_READ(1U)
6529 
6530 #define S_IMP_SET_UPDATE    24
6531 #define V_IMP_SET_UPDATE(x) ((x) << S_IMP_SET_UPDATE)
6532 #define F_IMP_SET_UPDATE    V_IMP_SET_UPDATE(1U)
6533 
6534 #define S_CAL_UPDATE    23
6535 #define V_CAL_UPDATE(x) ((x) << S_CAL_UPDATE)
6536 #define F_CAL_UPDATE    V_CAL_UPDATE(1U)
6537 
6538 #define S_CAL_BUSY    22
6539 #define V_CAL_BUSY(x) ((x) << S_CAL_BUSY)
6540 #define F_CAL_BUSY    V_CAL_BUSY(1U)
6541 
6542 #define S_CAL_ERROR    21
6543 #define V_CAL_ERROR(x) ((x) << S_CAL_ERROR)
6544 #define F_CAL_ERROR    V_CAL_ERROR(1U)
6545 
6546 #define S_SGL_CAL_EN    20
6547 #define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN)
6548 #define F_SGL_CAL_EN    V_SGL_CAL_EN(1U)
6549 
6550 #define S_IMP_UPD_MODE    19
6551 #define V_IMP_UPD_MODE(x) ((x) << S_IMP_UPD_MODE)
6552 #define F_IMP_UPD_MODE    V_IMP_UPD_MODE(1U)
6553 
6554 #define S_IMP_SEL    18
6555 #define V_IMP_SEL(x) ((x) << S_IMP_SEL)
6556 #define F_IMP_SEL    V_IMP_SEL(1U)
6557 
6558 #define S_MAN_PU    15
6559 #define M_MAN_PU    0x7
6560 #define V_MAN_PU(x) ((x) << S_MAN_PU)
6561 #define G_MAN_PU(x) (((x) >> S_MAN_PU) & M_MAN_PU)
6562 
6563 #define S_MAN_PD    12
6564 #define M_MAN_PD    0x7
6565 #define V_MAN_PD(x) ((x) << S_MAN_PD)
6566 #define G_MAN_PD(x) (((x) >> S_MAN_PD) & M_MAN_PD)
6567 
6568 #define S_CAL_PU    9
6569 #define M_CAL_PU    0x7
6570 #define V_CAL_PU(x) ((x) << S_CAL_PU)
6571 #define G_CAL_PU(x) (((x) >> S_CAL_PU) & M_CAL_PU)
6572 
6573 #define S_CAL_PD    6
6574 #define M_CAL_PD    0x7
6575 #define V_CAL_PD(x) ((x) << S_CAL_PD)
6576 #define G_CAL_PD(x) (((x) >> S_CAL_PD) & M_CAL_PD)
6577 
6578 #define S_SET_PU    3
6579 #define M_SET_PU    0x7
6580 #define V_SET_PU(x) ((x) << S_SET_PU)
6581 #define G_SET_PU(x) (((x) >> S_SET_PU) & M_SET_PU)
6582 
6583 #define S_SET_PD    0
6584 #define M_SET_PD    0x7
6585 #define V_SET_PD(x) ((x) << S_SET_PD)
6586 #define G_SET_PD(x) (((x) >> S_SET_PD) & M_SET_PD)
6587 
6588 #define S_CAL_IMP_UPD    23
6589 #define V_CAL_IMP_UPD(x) ((x) << S_CAL_IMP_UPD)
6590 #define F_CAL_IMP_UPD    V_CAL_IMP_UPD(1U)
6591 
6592 #define A_MC5_DB_CONFIG 0x704
6593 
6594 #define S_TMCFGWRLOCK    31
6595 #define V_TMCFGWRLOCK(x) ((x) << S_TMCFGWRLOCK)
6596 #define F_TMCFGWRLOCK    V_TMCFGWRLOCK(1U)
6597 
6598 #define S_TMTYPEHI    30
6599 #define V_TMTYPEHI(x) ((x) << S_TMTYPEHI)
6600 #define F_TMTYPEHI    V_TMTYPEHI(1U)
6601 
6602 #define S_TMPARTSIZE    28
6603 #define M_TMPARTSIZE    0x3
6604 #define V_TMPARTSIZE(x) ((x) << S_TMPARTSIZE)
6605 #define G_TMPARTSIZE(x) (((x) >> S_TMPARTSIZE) & M_TMPARTSIZE)
6606 
6607 #define S_TMTYPE    26
6608 #define M_TMTYPE    0x3
6609 #define V_TMTYPE(x) ((x) << S_TMTYPE)
6610 #define G_TMTYPE(x) (((x) >> S_TMTYPE) & M_TMTYPE)
6611 
6612 #define S_TMPARTCOUNT    24
6613 #define M_TMPARTCOUNT    0x3
6614 #define V_TMPARTCOUNT(x) ((x) << S_TMPARTCOUNT)
6615 #define G_TMPARTCOUNT(x) (((x) >> S_TMPARTCOUNT) & M_TMPARTCOUNT)
6616 
6617 #define S_NLIP    18
6618 #define M_NLIP    0x3f
6619 #define V_NLIP(x) ((x) << S_NLIP)
6620 #define G_NLIP(x) (((x) >> S_NLIP) & M_NLIP)
6621 
6622 #define S_COMPEN    17
6623 #define V_COMPEN(x) ((x) << S_COMPEN)
6624 #define F_COMPEN    V_COMPEN(1U)
6625 
6626 #define S_BUILD    16
6627 #define V_BUILD(x) ((x) << S_BUILD)
6628 #define F_BUILD    V_BUILD(1U)
6629 
6630 #define S_FILTEREN    11
6631 #define V_FILTEREN(x) ((x) << S_FILTEREN)
6632 #define F_FILTEREN    V_FILTEREN(1U)
6633 
6634 #define S_CLIPUPDATE    10
6635 #define V_CLIPUPDATE(x) ((x) << S_CLIPUPDATE)
6636 #define F_CLIPUPDATE    V_CLIPUPDATE(1U)
6637 
6638 #define S_TM_IO_PDOWN    9
6639 #define V_TM_IO_PDOWN(x) ((x) << S_TM_IO_PDOWN)
6640 #define F_TM_IO_PDOWN    V_TM_IO_PDOWN(1U)
6641 
6642 #define S_SYNMODE    7
6643 #define M_SYNMODE    0x3
6644 #define V_SYNMODE(x) ((x) << S_SYNMODE)
6645 #define G_SYNMODE(x) (((x) >> S_SYNMODE) & M_SYNMODE)
6646 
6647 #define S_PRTYEN    6
6648 #define V_PRTYEN(x) ((x) << S_PRTYEN)
6649 #define F_PRTYEN    V_PRTYEN(1U)
6650 
6651 #define S_MBUSEN    5
6652 #define V_MBUSEN(x) ((x) << S_MBUSEN)
6653 #define F_MBUSEN    V_MBUSEN(1U)
6654 
6655 #define S_DBGIEN    4
6656 #define V_DBGIEN(x) ((x) << S_DBGIEN)
6657 #define F_DBGIEN    V_DBGIEN(1U)
6658 
6659 #define S_TCMCFGOVR    3
6660 #define V_TCMCFGOVR(x) ((x) << S_TCMCFGOVR)
6661 #define F_TCMCFGOVR    V_TCMCFGOVR(1U)
6662 
6663 #define S_TMRDY    2
6664 #define V_TMRDY(x) ((x) << S_TMRDY)
6665 #define F_TMRDY    V_TMRDY(1U)
6666 
6667 #define S_TMRST    1
6668 #define V_TMRST(x) ((x) << S_TMRST)
6669 #define F_TMRST    V_TMRST(1U)
6670 
6671 #define S_TMMODE    0
6672 #define V_TMMODE(x) ((x) << S_TMMODE)
6673 #define F_TMMODE    V_TMMODE(1U)
6674 
6675 #define A_MC5_MISC 0x708
6676 
6677 #define S_LIP_CMP_UNAVAILABLE    0
6678 #define M_LIP_CMP_UNAVAILABLE    0xf
6679 #define V_LIP_CMP_UNAVAILABLE(x) ((x) << S_LIP_CMP_UNAVAILABLE)
6680 #define G_LIP_CMP_UNAVAILABLE(x) (((x) >> S_LIP_CMP_UNAVAILABLE) & M_LIP_CMP_UNAVAILABLE)
6681 
6682 #define A_MC5_DB_ROUTING_TABLE_INDEX 0x70c
6683 
6684 #define S_RTINDX    0
6685 #define M_RTINDX    0x3fffff
6686 #define V_RTINDX(x) ((x) << S_RTINDX)
6687 #define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX)
6688 
6689 #define A_MC5_DB_FILTER_TABLE 0x710
6690 
6691 #define S_SRINDX    0
6692 #define M_SRINDX    0x3fffff
6693 #define V_SRINDX(x) ((x) << S_SRINDX)
6694 #define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX)
6695 
6696 #define A_MC5_DB_SERVER_INDEX 0x714
6697 #define A_MC5_DB_LIP_RAM_ADDR 0x718
6698 
6699 #define S_RAMWR    8
6700 #define V_RAMWR(x) ((x) << S_RAMWR)
6701 #define F_RAMWR    V_RAMWR(1U)
6702 
6703 #define S_RAMADDR    0
6704 #define M_RAMADDR    0x3f
6705 #define V_RAMADDR(x) ((x) << S_RAMADDR)
6706 #define G_RAMADDR(x) (((x) >> S_RAMADDR) & M_RAMADDR)
6707 
6708 #define A_MC5_DB_LIP_RAM_DATA 0x71c
6709 #define A_MC5_DB_RSP_LATENCY 0x720
6710 
6711 #define S_RDLAT    16
6712 #define M_RDLAT    0x1f
6713 #define V_RDLAT(x) ((x) << S_RDLAT)
6714 #define G_RDLAT(x) (((x) >> S_RDLAT) & M_RDLAT)
6715 
6716 #define S_LRNLAT    8
6717 #define M_LRNLAT    0x1f
6718 #define V_LRNLAT(x) ((x) << S_LRNLAT)
6719 #define G_LRNLAT(x) (((x) >> S_LRNLAT) & M_LRNLAT)
6720 
6721 #define S_SRCHLAT    0
6722 #define M_SRCHLAT    0x1f
6723 #define V_SRCHLAT(x) ((x) << S_SRCHLAT)
6724 #define G_SRCHLAT(x) (((x) >> S_SRCHLAT) & M_SRCHLAT)
6725 
6726 #define A_MC5_DB_PARITY_LATENCY 0x724
6727 
6728 #define S_PARLAT    0
6729 #define M_PARLAT    0xf
6730 #define V_PARLAT(x) ((x) << S_PARLAT)
6731 #define G_PARLAT(x) (((x) >> S_PARLAT) & M_PARLAT)
6732 
6733 #define A_MC5_DB_WR_LRN_VERIFY 0x728
6734 
6735 #define S_VWVEREN    2
6736 #define V_VWVEREN(x) ((x) << S_VWVEREN)
6737 #define F_VWVEREN    V_VWVEREN(1U)
6738 
6739 #define S_LRNVEREN    1
6740 #define V_LRNVEREN(x) ((x) << S_LRNVEREN)
6741 #define F_LRNVEREN    V_LRNVEREN(1U)
6742 
6743 #define S_POVEREN    0
6744 #define V_POVEREN(x) ((x) << S_POVEREN)
6745 #define F_POVEREN    V_POVEREN(1U)
6746 
6747 #define A_MC5_DB_PART_ID_INDEX 0x72c
6748 
6749 #define S_IDINDEX    0
6750 #define M_IDINDEX    0xf
6751 #define V_IDINDEX(x) ((x) << S_IDINDEX)
6752 #define G_IDINDEX(x) (((x) >> S_IDINDEX) & M_IDINDEX)
6753 
6754 #define A_MC5_DB_RESET_MAX 0x730
6755 
6756 #define S_RSTMAX    0
6757 #define M_RSTMAX    0xf
6758 #define V_RSTMAX(x) ((x) << S_RSTMAX)
6759 #define G_RSTMAX(x) (((x) >> S_RSTMAX) & M_RSTMAX)
6760 
6761 #define A_MC5_DB_ACT_CNT 0x734
6762 
6763 #define S_ACTCNT    0
6764 #define M_ACTCNT    0xfffff
6765 #define V_ACTCNT(x) ((x) << S_ACTCNT)
6766 #define G_ACTCNT(x) (((x) >> S_ACTCNT) & M_ACTCNT)
6767 
6768 #define A_MC5_DB_CLIP_MAP 0x738
6769 
6770 #define S_CLIPMAPOP    31
6771 #define V_CLIPMAPOP(x) ((x) << S_CLIPMAPOP)
6772 #define F_CLIPMAPOP    V_CLIPMAPOP(1U)
6773 
6774 #define S_CLIPMAPVAL    16
6775 #define M_CLIPMAPVAL    0x3f
6776 #define V_CLIPMAPVAL(x) ((x) << S_CLIPMAPVAL)
6777 #define G_CLIPMAPVAL(x) (((x) >> S_CLIPMAPVAL) & M_CLIPMAPVAL)
6778 
6779 #define S_CLIPMAPADDR    0
6780 #define M_CLIPMAPADDR    0x3f
6781 #define V_CLIPMAPADDR(x) ((x) << S_CLIPMAPADDR)
6782 #define G_CLIPMAPADDR(x) (((x) >> S_CLIPMAPADDR) & M_CLIPMAPADDR)
6783 
6784 #define A_MC5_DB_SIZE 0x73c
6785 #define A_MC5_DB_INT_ENABLE 0x740
6786 
6787 #define S_MSGSEL    28
6788 #define M_MSGSEL    0xf
6789 #define V_MSGSEL(x) ((x) << S_MSGSEL)
6790 #define G_MSGSEL(x) (((x) >> S_MSGSEL) & M_MSGSEL)
6791 
6792 #define S_DELACTEMPTY    18
6793 #define V_DELACTEMPTY(x) ((x) << S_DELACTEMPTY)
6794 #define F_DELACTEMPTY    V_DELACTEMPTY(1U)
6795 
6796 #define S_DISPQPARERR    17
6797 #define V_DISPQPARERR(x) ((x) << S_DISPQPARERR)
6798 #define F_DISPQPARERR    V_DISPQPARERR(1U)
6799 
6800 #define S_REQQPARERR    16
6801 #define V_REQQPARERR(x) ((x) << S_REQQPARERR)
6802 #define F_REQQPARERR    V_REQQPARERR(1U)
6803 
6804 #define S_UNKNOWNCMD    15
6805 #define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD)
6806 #define F_UNKNOWNCMD    V_UNKNOWNCMD(1U)
6807 
6808 #define S_SYNCOOKIEOFF    11
6809 #define V_SYNCOOKIEOFF(x) ((x) << S_SYNCOOKIEOFF)
6810 #define F_SYNCOOKIEOFF    V_SYNCOOKIEOFF(1U)
6811 
6812 #define S_SYNCOOKIEBAD    10
6813 #define V_SYNCOOKIEBAD(x) ((x) << S_SYNCOOKIEBAD)
6814 #define F_SYNCOOKIEBAD    V_SYNCOOKIEBAD(1U)
6815 
6816 #define S_SYNCOOKIE    9
6817 #define V_SYNCOOKIE(x) ((x) << S_SYNCOOKIE)
6818 #define F_SYNCOOKIE    V_SYNCOOKIE(1U)
6819 
6820 #define S_NFASRCHFAIL    8
6821 #define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL)
6822 #define F_NFASRCHFAIL    V_NFASRCHFAIL(1U)
6823 
6824 #define S_ACTRGNFULL    7
6825 #define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL)
6826 #define F_ACTRGNFULL    V_ACTRGNFULL(1U)
6827 
6828 #define S_PARITYERR    6
6829 #define V_PARITYERR(x) ((x) << S_PARITYERR)
6830 #define F_PARITYERR    V_PARITYERR(1U)
6831 
6832 #define S_LIPMISS    5
6833 #define V_LIPMISS(x) ((x) << S_LIPMISS)
6834 #define F_LIPMISS    V_LIPMISS(1U)
6835 
6836 #define S_LIP0    4
6837 #define V_LIP0(x) ((x) << S_LIP0)
6838 #define F_LIP0    V_LIP0(1U)
6839 
6840 #define S_MISS    3
6841 #define V_MISS(x) ((x) << S_MISS)
6842 #define F_MISS    V_MISS(1U)
6843 
6844 #define S_ROUTINGHIT    2
6845 #define V_ROUTINGHIT(x) ((x) << S_ROUTINGHIT)
6846 #define F_ROUTINGHIT    V_ROUTINGHIT(1U)
6847 
6848 #define S_ACTIVEHIT    1
6849 #define V_ACTIVEHIT(x) ((x) << S_ACTIVEHIT)
6850 #define F_ACTIVEHIT    V_ACTIVEHIT(1U)
6851 
6852 #define S_ACTIVEOUTHIT    0
6853 #define V_ACTIVEOUTHIT(x) ((x) << S_ACTIVEOUTHIT)
6854 #define F_ACTIVEOUTHIT    V_ACTIVEOUTHIT(1U)
6855 
6856 #define A_MC5_DB_INT_CAUSE 0x744
6857 #define A_MC5_DB_INT_TID 0x748
6858 
6859 #define S_INTTID    0
6860 #define M_INTTID    0xfffff
6861 #define V_INTTID(x) ((x) << S_INTTID)
6862 #define G_INTTID(x) (((x) >> S_INTTID) & M_INTTID)
6863 
6864 #define A_MC5_DB_INT_PTID 0x74c
6865 
6866 #define S_INTPTID    0
6867 #define M_INTPTID    0xfffff
6868 #define V_INTPTID(x) ((x) << S_INTPTID)
6869 #define G_INTPTID(x) (((x) >> S_INTPTID) & M_INTPTID)
6870 
6871 #define A_MC5_DB_DBGI_CONFIG 0x774
6872 
6873 #define S_WRREQSIZE    22
6874 #define M_WRREQSIZE    0x3ff
6875 #define V_WRREQSIZE(x) ((x) << S_WRREQSIZE)
6876 #define G_WRREQSIZE(x) (((x) >> S_WRREQSIZE) & M_WRREQSIZE)
6877 
6878 #define S_SADRSEL    4
6879 #define V_SADRSEL(x) ((x) << S_SADRSEL)
6880 #define F_SADRSEL    V_SADRSEL(1U)
6881 
6882 #define S_CMDMODE    0
6883 #define M_CMDMODE    0x7
6884 #define V_CMDMODE(x) ((x) << S_CMDMODE)
6885 #define G_CMDMODE(x) (((x) >> S_CMDMODE) & M_CMDMODE)
6886 
6887 #define A_MC5_DB_DBGI_REQ_CMD 0x778
6888 
6889 #define S_MBUSCMD    0
6890 #define M_MBUSCMD    0xf
6891 #define V_MBUSCMD(x) ((x) << S_MBUSCMD)
6892 #define G_MBUSCMD(x) (((x) >> S_MBUSCMD) & M_MBUSCMD)
6893 
6894 #define S_IDTCMDHI    11
6895 #define M_IDTCMDHI    0x7
6896 #define V_IDTCMDHI(x) ((x) << S_IDTCMDHI)
6897 #define G_IDTCMDHI(x) (((x) >> S_IDTCMDHI) & M_IDTCMDHI)
6898 
6899 #define S_IDTCMDLO    0
6900 #define M_IDTCMDLO    0xf
6901 #define V_IDTCMDLO(x) ((x) << S_IDTCMDLO)
6902 #define G_IDTCMDLO(x) (((x) >> S_IDTCMDLO) & M_IDTCMDLO)
6903 
6904 #define S_IDTCMD    0
6905 #define M_IDTCMD    0xfffff
6906 #define V_IDTCMD(x) ((x) << S_IDTCMD)
6907 #define G_IDTCMD(x) (((x) >> S_IDTCMD) & M_IDTCMD)
6908 
6909 #define S_LCMDB    16
6910 #define M_LCMDB    0x7ff
6911 #define V_LCMDB(x) ((x) << S_LCMDB)
6912 #define G_LCMDB(x) (((x) >> S_LCMDB) & M_LCMDB)
6913 
6914 #define S_LCMDA    0
6915 #define M_LCMDA    0x7ff
6916 #define V_LCMDA(x) ((x) << S_LCMDA)
6917 #define G_LCMDA(x) (((x) >> S_LCMDA) & M_LCMDA)
6918 
6919 #define A_MC5_DB_DBGI_REQ_ADDR0 0x77c
6920 #define A_MC5_DB_DBGI_REQ_ADDR1 0x780
6921 #define A_MC5_DB_DBGI_REQ_ADDR2 0x784
6922 
6923 #define S_DBGIREQADRHI    0
6924 #define M_DBGIREQADRHI    0xff
6925 #define V_DBGIREQADRHI(x) ((x) << S_DBGIREQADRHI)
6926 #define G_DBGIREQADRHI(x) (((x) >> S_DBGIREQADRHI) & M_DBGIREQADRHI)
6927 
6928 #define A_MC5_DB_DBGI_REQ_DATA0 0x788
6929 #define A_MC5_DB_DBGI_REQ_DATA1 0x78c
6930 #define A_MC5_DB_DBGI_REQ_DATA2 0x790
6931 #define A_MC5_DB_DBGI_REQ_DATA3 0x794
6932 #define A_MC5_DB_DBGI_REQ_DATA4 0x798
6933 
6934 #define S_DBGIREQDATA4    0
6935 #define M_DBGIREQDATA4    0xffff
6936 #define V_DBGIREQDATA4(x) ((x) << S_DBGIREQDATA4)
6937 #define G_DBGIREQDATA4(x) (((x) >> S_DBGIREQDATA4) & M_DBGIREQDATA4)
6938 
6939 #define A_MC5_DB_DBGI_REQ_MASK0 0x79c
6940 #define A_MC5_DB_DBGI_REQ_MASK1 0x7a0
6941 #define A_MC5_DB_DBGI_REQ_MASK2 0x7a4
6942 #define A_MC5_DB_DBGI_REQ_MASK3 0x7a8
6943 #define A_MC5_DB_DBGI_REQ_MASK4 0x7ac
6944 
6945 #define S_DBGIREQMSK4    0
6946 #define M_DBGIREQMSK4    0xffff
6947 #define V_DBGIREQMSK4(x) ((x) << S_DBGIREQMSK4)
6948 #define G_DBGIREQMSK4(x) (((x) >> S_DBGIREQMSK4) & M_DBGIREQMSK4)
6949 
6950 #define A_MC5_DB_DBGI_RSP_STATUS 0x7b0
6951 
6952 #define S_DBGIRSPMSG    8
6953 #define M_DBGIRSPMSG    0xf
6954 #define V_DBGIRSPMSG(x) ((x) << S_DBGIRSPMSG)
6955 #define G_DBGIRSPMSG(x) (((x) >> S_DBGIRSPMSG) & M_DBGIRSPMSG)
6956 
6957 #define S_DBGIRSPMSGVLD    2
6958 #define V_DBGIRSPMSGVLD(x) ((x) << S_DBGIRSPMSGVLD)
6959 #define F_DBGIRSPMSGVLD    V_DBGIRSPMSGVLD(1U)
6960 
6961 #define S_DBGIRSPHIT    1
6962 #define V_DBGIRSPHIT(x) ((x) << S_DBGIRSPHIT)
6963 #define F_DBGIRSPHIT    V_DBGIRSPHIT(1U)
6964 
6965 #define S_DBGIRSPVALID    0
6966 #define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID)
6967 #define F_DBGIRSPVALID    V_DBGIRSPVALID(1U)
6968 
6969 #define A_MC5_DB_DBGI_RSP_DATA0 0x7b4
6970 #define A_MC5_DB_DBGI_RSP_DATA1 0x7b8
6971 #define A_MC5_DB_DBGI_RSP_DATA2 0x7bc
6972 #define A_MC5_DB_DBGI_RSP_DATA3 0x7c0
6973 #define A_MC5_DB_DBGI_RSP_DATA4 0x7c4
6974 
6975 #define S_DBGIRSPDATA3    0
6976 #define M_DBGIRSPDATA3    0xffff
6977 #define V_DBGIRSPDATA3(x) ((x) << S_DBGIRSPDATA3)
6978 #define G_DBGIRSPDATA3(x) (((x) >> S_DBGIRSPDATA3) & M_DBGIRSPDATA3)
6979 
6980 #define A_MC5_DB_DBGI_RSP_LAST_CMD 0x7c8
6981 
6982 #define S_LASTCMDB    16
6983 #define M_LASTCMDB    0x7ff
6984 #define V_LASTCMDB(x) ((x) << S_LASTCMDB)
6985 #define G_LASTCMDB(x) (((x) >> S_LASTCMDB) & M_LASTCMDB)
6986 
6987 #define S_LASTCMDA    0
6988 #define M_LASTCMDA    0x7ff
6989 #define V_LASTCMDA(x) ((x) << S_LASTCMDA)
6990 #define G_LASTCMDA(x) (((x) >> S_LASTCMDA) & M_LASTCMDA)
6991 
6992 #define A_MC5_DB_POPEN_DATA_WR_CMD 0x7cc
6993 
6994 #define S_PO_DWR    0
6995 #define M_PO_DWR    0xfffff
6996 #define V_PO_DWR(x) ((x) << S_PO_DWR)
6997 #define G_PO_DWR(x) (((x) >> S_PO_DWR) & M_PO_DWR)
6998 
6999 #define A_MC5_DB_POPEN_MASK_WR_CMD 0x7d0
7000 
7001 #define S_PO_MWR    0
7002 #define M_PO_MWR    0xfffff
7003 #define V_PO_MWR(x) ((x) << S_PO_MWR)
7004 #define G_PO_MWR(x) (((x) >> S_PO_MWR) & M_PO_MWR)
7005 
7006 #define A_MC5_DB_AOPEN_SRCH_CMD 0x7d4
7007 
7008 #define S_AO_SRCH    0
7009 #define M_AO_SRCH    0xfffff
7010 #define V_AO_SRCH(x) ((x) << S_AO_SRCH)
7011 #define G_AO_SRCH(x) (((x) >> S_AO_SRCH) & M_AO_SRCH)
7012 
7013 #define A_MC5_DB_AOPEN_LRN_CMD 0x7d8
7014 
7015 #define S_AO_LRN    0
7016 #define M_AO_LRN    0xfffff
7017 #define V_AO_LRN(x) ((x) << S_AO_LRN)
7018 #define G_AO_LRN(x) (((x) >> S_AO_LRN) & M_AO_LRN)
7019 
7020 #define A_MC5_DB_SYN_SRCH_CMD 0x7dc
7021 
7022 #define S_SYN_SRCH    0
7023 #define M_SYN_SRCH    0xfffff
7024 #define V_SYN_SRCH(x) ((x) << S_SYN_SRCH)
7025 #define G_SYN_SRCH(x) (((x) >> S_SYN_SRCH) & M_SYN_SRCH)
7026 
7027 #define A_MC5_DB_SYN_LRN_CMD 0x7e0
7028 
7029 #define S_SYN_LRN    0
7030 #define M_SYN_LRN    0xfffff
7031 #define V_SYN_LRN(x) ((x) << S_SYN_LRN)
7032 #define G_SYN_LRN(x) (((x) >> S_SYN_LRN) & M_SYN_LRN)
7033 
7034 #define A_MC5_DB_ACK_SRCH_CMD 0x7e4
7035 
7036 #define S_ACK_SRCH    0
7037 #define M_ACK_SRCH    0xfffff
7038 #define V_ACK_SRCH(x) ((x) << S_ACK_SRCH)
7039 #define G_ACK_SRCH(x) (((x) >> S_ACK_SRCH) & M_ACK_SRCH)
7040 
7041 #define A_MC5_DB_ACK_LRN_CMD 0x7e8
7042 
7043 #define S_ACK_LRN    0
7044 #define M_ACK_LRN    0xfffff
7045 #define V_ACK_LRN(x) ((x) << S_ACK_LRN)
7046 #define G_ACK_LRN(x) (((x) >> S_ACK_LRN) & M_ACK_LRN)
7047 
7048 #define A_MC5_DB_ILOOKUP_CMD 0x7ec
7049 
7050 #define S_I_SRCH    0
7051 #define M_I_SRCH    0xfffff
7052 #define V_I_SRCH(x) ((x) << S_I_SRCH)
7053 #define G_I_SRCH(x) (((x) >> S_I_SRCH) & M_I_SRCH)
7054 
7055 #define A_MC5_DB_ELOOKUP_CMD 0x7f0
7056 
7057 #define S_E_SRCH    0
7058 #define M_E_SRCH    0xfffff
7059 #define V_E_SRCH(x) ((x) << S_E_SRCH)
7060 #define G_E_SRCH(x) (((x) >> S_E_SRCH) & M_E_SRCH)
7061 
7062 #define A_MC5_DB_DATA_WRITE_CMD 0x7f4
7063 
7064 #define S_WRITE    0
7065 #define M_WRITE    0xfffff
7066 #define V_WRITE(x) ((x) << S_WRITE)
7067 #define G_WRITE(x) (((x) >> S_WRITE) & M_WRITE)
7068 
7069 #define A_MC5_DB_DATA_READ_CMD 0x7f8
7070 
7071 #define S_READCMD    0
7072 #define M_READCMD    0xfffff
7073 #define V_READCMD(x) ((x) << S_READCMD)
7074 #define G_READCMD(x) (((x) >> S_READCMD) & M_READCMD)
7075 
7076 #define A_MC5_DB_MASK_WRITE_CMD 0x7fc
7077 
7078 #define S_MASKWR    0
7079 #define M_MASKWR    0xffff
7080 #define V_MASKWR(x) ((x) << S_MASKWR)
7081 #define G_MASKWR(x) (((x) >> S_MASKWR) & M_MASKWR)
7082 
7083 /* registers for module XGMAC0_0 */
7084 #define XGMAC0_0_BASE_ADDR 0x800
7085 
7086 #define A_XGM_TX_CTRL 0x800
7087 
7088 #define S_SENDPAUSE    2
7089 #define V_SENDPAUSE(x) ((x) << S_SENDPAUSE)
7090 #define F_SENDPAUSE    V_SENDPAUSE(1U)
7091 
7092 #define S_SENDZEROPAUSE    1
7093 #define V_SENDZEROPAUSE(x) ((x) << S_SENDZEROPAUSE)
7094 #define F_SENDZEROPAUSE    V_SENDZEROPAUSE(1U)
7095 
7096 #define S_TXEN    0
7097 #define V_TXEN(x) ((x) << S_TXEN)
7098 #define F_TXEN    V_TXEN(1U)
7099 
7100 #define A_XGM_TX_CFG 0x804
7101 
7102 #define S_CFGCLKSPEED    2
7103 #define M_CFGCLKSPEED    0x7
7104 #define V_CFGCLKSPEED(x) ((x) << S_CFGCLKSPEED)
7105 #define G_CFGCLKSPEED(x) (((x) >> S_CFGCLKSPEED) & M_CFGCLKSPEED)
7106 
7107 #define S_STRETCHMODE    1
7108 #define V_STRETCHMODE(x) ((x) << S_STRETCHMODE)
7109 #define F_STRETCHMODE    V_STRETCHMODE(1U)
7110 
7111 #define S_TXPAUSEEN    0
7112 #define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN)
7113 #define F_TXPAUSEEN    V_TXPAUSEEN(1U)
7114 
7115 #define A_XGM_TX_PAUSE_QUANTA 0x808
7116 
7117 #define S_TXPAUSEQUANTA    0
7118 #define M_TXPAUSEQUANTA    0xffff
7119 #define V_TXPAUSEQUANTA(x) ((x) << S_TXPAUSEQUANTA)
7120 #define G_TXPAUSEQUANTA(x) (((x) >> S_TXPAUSEQUANTA) & M_TXPAUSEQUANTA)
7121 
7122 #define A_XGM_RX_CTRL 0x80c
7123 
7124 #define S_RXEN    0
7125 #define V_RXEN(x) ((x) << S_RXEN)
7126 #define F_RXEN    V_RXEN(1U)
7127 
7128 #define A_XGM_RX_CFG 0x810
7129 
7130 #define S_CON802_3PREAMBLE    12
7131 #define V_CON802_3PREAMBLE(x) ((x) << S_CON802_3PREAMBLE)
7132 #define F_CON802_3PREAMBLE    V_CON802_3PREAMBLE(1U)
7133 
7134 #define S_ENNON802_3PREAMBLE    11
7135 #define V_ENNON802_3PREAMBLE(x) ((x) << S_ENNON802_3PREAMBLE)
7136 #define F_ENNON802_3PREAMBLE    V_ENNON802_3PREAMBLE(1U)
7137 
7138 #define S_COPYPREAMBLE    10
7139 #define V_COPYPREAMBLE(x) ((x) << S_COPYPREAMBLE)
7140 #define F_COPYPREAMBLE    V_COPYPREAMBLE(1U)
7141 
7142 #define S_DISPAUSEFRAMES    9
7143 #define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES)
7144 #define F_DISPAUSEFRAMES    V_DISPAUSEFRAMES(1U)
7145 
7146 #define S_EN1536BFRAMES    8
7147 #define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES)
7148 #define F_EN1536BFRAMES    V_EN1536BFRAMES(1U)
7149 
7150 #define S_ENJUMBO    7
7151 #define V_ENJUMBO(x) ((x) << S_ENJUMBO)
7152 #define F_ENJUMBO    V_ENJUMBO(1U)
7153 
7154 #define S_RMFCS    6
7155 #define V_RMFCS(x) ((x) << S_RMFCS)
7156 #define F_RMFCS    V_RMFCS(1U)
7157 
7158 #define S_DISNONVLAN    5
7159 #define V_DISNONVLAN(x) ((x) << S_DISNONVLAN)
7160 #define F_DISNONVLAN    V_DISNONVLAN(1U)
7161 
7162 #define S_ENEXTMATCH    4
7163 #define V_ENEXTMATCH(x) ((x) << S_ENEXTMATCH)
7164 #define F_ENEXTMATCH    V_ENEXTMATCH(1U)
7165 
7166 #define S_ENHASHUCAST    3
7167 #define V_ENHASHUCAST(x) ((x) << S_ENHASHUCAST)
7168 #define F_ENHASHUCAST    V_ENHASHUCAST(1U)
7169 
7170 #define S_ENHASHMCAST    2
7171 #define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST)
7172 #define F_ENHASHMCAST    V_ENHASHMCAST(1U)
7173 
7174 #define S_DISBCAST    1
7175 #define V_DISBCAST(x) ((x) << S_DISBCAST)
7176 #define F_DISBCAST    V_DISBCAST(1U)
7177 
7178 #define S_COPYALLFRAMES    0
7179 #define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES)
7180 #define F_COPYALLFRAMES    V_COPYALLFRAMES(1U)
7181 
7182 #define A_XGM_RX_HASH_LOW 0x814
7183 #define A_XGM_RX_HASH_HIGH 0x818
7184 #define A_XGM_RX_EXACT_MATCH_LOW_1 0x81c
7185 #define A_XGM_RX_EXACT_MATCH_HIGH_1 0x820
7186 
7187 #define S_ADDRESS_HIGH    0
7188 #define M_ADDRESS_HIGH    0xffff
7189 #define V_ADDRESS_HIGH(x) ((x) << S_ADDRESS_HIGH)
7190 #define G_ADDRESS_HIGH(x) (((x) >> S_ADDRESS_HIGH) & M_ADDRESS_HIGH)
7191 
7192 #define A_XGM_RX_EXACT_MATCH_LOW_2 0x824
7193 #define A_XGM_RX_EXACT_MATCH_HIGH_2 0x828
7194 #define A_XGM_RX_EXACT_MATCH_LOW_3 0x82c
7195 #define A_XGM_RX_EXACT_MATCH_HIGH_3 0x830
7196 #define A_XGM_RX_EXACT_MATCH_LOW_4 0x834
7197 #define A_XGM_RX_EXACT_MATCH_HIGH_4 0x838
7198 #define A_XGM_RX_EXACT_MATCH_LOW_5 0x83c
7199 #define A_XGM_RX_EXACT_MATCH_HIGH_5 0x840
7200 #define A_XGM_RX_EXACT_MATCH_LOW_6 0x844
7201 #define A_XGM_RX_EXACT_MATCH_HIGH_6 0x848
7202 #define A_XGM_RX_EXACT_MATCH_LOW_7 0x84c
7203 #define A_XGM_RX_EXACT_MATCH_HIGH_7 0x850
7204 #define A_XGM_RX_EXACT_MATCH_LOW_8 0x854
7205 #define A_XGM_RX_EXACT_MATCH_HIGH_8 0x858
7206 #define A_XGM_RX_TYPE_MATCH_1 0x85c
7207 
7208 #define S_ENTYPEMATCH    31
7209 #define V_ENTYPEMATCH(x) ((x) << S_ENTYPEMATCH)
7210 #define F_ENTYPEMATCH    V_ENTYPEMATCH(1U)
7211 
7212 #define S_TYPE    0
7213 #define M_TYPE    0xffff
7214 #define V_TYPE(x) ((x) << S_TYPE)
7215 #define G_TYPE(x) (((x) >> S_TYPE) & M_TYPE)
7216 
7217 #define A_XGM_RX_TYPE_MATCH_2 0x860
7218 #define A_XGM_RX_TYPE_MATCH_3 0x864
7219 #define A_XGM_RX_TYPE_MATCH_4 0x868
7220 #define A_XGM_INT_STATUS 0x86c
7221 
7222 #define S_XGMIIEXTINT    10
7223 #define V_XGMIIEXTINT(x) ((x) << S_XGMIIEXTINT)
7224 #define F_XGMIIEXTINT    V_XGMIIEXTINT(1U)
7225 
7226 #define S_LINKFAULTCHANGE    9
7227 #define V_LINKFAULTCHANGE(x) ((x) << S_LINKFAULTCHANGE)
7228 #define F_LINKFAULTCHANGE    V_LINKFAULTCHANGE(1U)
7229 
7230 #define S_PHYFRAMECOMPLETE    8
7231 #define V_PHYFRAMECOMPLETE(x) ((x) << S_PHYFRAMECOMPLETE)
7232 #define F_PHYFRAMECOMPLETE    V_PHYFRAMECOMPLETE(1U)
7233 
7234 #define S_PAUSEFRAMETXMT    7
7235 #define V_PAUSEFRAMETXMT(x) ((x) << S_PAUSEFRAMETXMT)
7236 #define F_PAUSEFRAMETXMT    V_PAUSEFRAMETXMT(1U)
7237 
7238 #define S_PAUSECNTRTIMEOUT    6
7239 #define V_PAUSECNTRTIMEOUT(x) ((x) << S_PAUSECNTRTIMEOUT)
7240 #define F_PAUSECNTRTIMEOUT    V_PAUSECNTRTIMEOUT(1U)
7241 
7242 #define S_NON0PAUSERCVD    5
7243 #define V_NON0PAUSERCVD(x) ((x) << S_NON0PAUSERCVD)
7244 #define F_NON0PAUSERCVD    V_NON0PAUSERCVD(1U)
7245 
7246 #define S_STATOFLOW    4
7247 #define V_STATOFLOW(x) ((x) << S_STATOFLOW)
7248 #define F_STATOFLOW    V_STATOFLOW(1U)
7249 
7250 #define S_TXERRFIFO    3
7251 #define V_TXERRFIFO(x) ((x) << S_TXERRFIFO)
7252 #define F_TXERRFIFO    V_TXERRFIFO(1U)
7253 
7254 #define S_TXUFLOW    2
7255 #define V_TXUFLOW(x) ((x) << S_TXUFLOW)
7256 #define F_TXUFLOW    V_TXUFLOW(1U)
7257 
7258 #define S_FRAMETXMT    1
7259 #define V_FRAMETXMT(x) ((x) << S_FRAMETXMT)
7260 #define F_FRAMETXMT    V_FRAMETXMT(1U)
7261 
7262 #define S_FRAMERCVD    0
7263 #define V_FRAMERCVD(x) ((x) << S_FRAMERCVD)
7264 #define F_FRAMERCVD    V_FRAMERCVD(1U)
7265 
7266 #define A_XGM_XGM_INT_MASK 0x870
7267 #define A_XGM_XGM_INT_ENABLE 0x874
7268 #define A_XGM_XGM_INT_DISABLE 0x878
7269 #define A_XGM_TX_PAUSE_TIMER 0x87c
7270 
7271 #define S_CURPAUSETIMER    0
7272 #define M_CURPAUSETIMER    0xffff
7273 #define V_CURPAUSETIMER(x) ((x) << S_CURPAUSETIMER)
7274 #define G_CURPAUSETIMER(x) (((x) >> S_CURPAUSETIMER) & M_CURPAUSETIMER)
7275 
7276 #define A_XGM_STAT_CTRL 0x880
7277 
7278 #define S_READSNPSHOT    4
7279 #define V_READSNPSHOT(x) ((x) << S_READSNPSHOT)
7280 #define F_READSNPSHOT    V_READSNPSHOT(1U)
7281 
7282 #define S_TAKESNPSHOT    3
7283 #define V_TAKESNPSHOT(x) ((x) << S_TAKESNPSHOT)
7284 #define F_TAKESNPSHOT    V_TAKESNPSHOT(1U)
7285 
7286 #define S_CLRSTATS    2
7287 #define V_CLRSTATS(x) ((x) << S_CLRSTATS)
7288 #define F_CLRSTATS    V_CLRSTATS(1U)
7289 
7290 #define S_INCRSTATS    1
7291 #define V_INCRSTATS(x) ((x) << S_INCRSTATS)
7292 #define F_INCRSTATS    V_INCRSTATS(1U)
7293 
7294 #define S_ENTESTMODEWR    0
7295 #define V_ENTESTMODEWR(x) ((x) << S_ENTESTMODEWR)
7296 #define F_ENTESTMODEWR    V_ENTESTMODEWR(1U)
7297 
7298 #define A_XGM_RXFIFO_CFG 0x884
7299 
7300 #define S_RXFIFO_EMPTY    31
7301 #define V_RXFIFO_EMPTY(x) ((x) << S_RXFIFO_EMPTY)
7302 #define F_RXFIFO_EMPTY    V_RXFIFO_EMPTY(1U)
7303 
7304 #define S_RXFIFO_FULL    30
7305 #define V_RXFIFO_FULL(x) ((x) << S_RXFIFO_FULL)
7306 #define F_RXFIFO_FULL    V_RXFIFO_FULL(1U)
7307 
7308 #define S_RXFIFOPAUSEHWM    17
7309 #define M_RXFIFOPAUSEHWM    0xfff
7310 #define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM)
7311 #define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM)
7312 
7313 #define S_RXFIFOPAUSELWM    5
7314 #define M_RXFIFOPAUSELWM    0xfff
7315 #define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM)
7316 #define G_RXFIFOPAUSELWM(x) (((x) >> S_RXFIFOPAUSELWM) & M_RXFIFOPAUSELWM)
7317 
7318 #define S_FORCEDPAUSE    4
7319 #define V_FORCEDPAUSE(x) ((x) << S_FORCEDPAUSE)
7320 #define F_FORCEDPAUSE    V_FORCEDPAUSE(1U)
7321 
7322 #define S_EXTERNLOOPBACK    3
7323 #define V_EXTERNLOOPBACK(x) ((x) << S_EXTERNLOOPBACK)
7324 #define F_EXTERNLOOPBACK    V_EXTERNLOOPBACK(1U)
7325 
7326 #define S_RXBYTESWAP    2
7327 #define V_RXBYTESWAP(x) ((x) << S_RXBYTESWAP)
7328 #define F_RXBYTESWAP    V_RXBYTESWAP(1U)
7329 
7330 #define S_RXSTRFRWRD    1
7331 #define V_RXSTRFRWRD(x) ((x) << S_RXSTRFRWRD)
7332 #define F_RXSTRFRWRD    V_RXSTRFRWRD(1U)
7333 
7334 #define S_DISERRFRAMES    0
7335 #define V_DISERRFRAMES(x) ((x) << S_DISERRFRAMES)
7336 #define F_DISERRFRAMES    V_DISERRFRAMES(1U)
7337 
7338 #define A_XGM_TXFIFO_CFG 0x888
7339 
7340 #define S_TXFIFO_EMPTY    31
7341 #define V_TXFIFO_EMPTY(x) ((x) << S_TXFIFO_EMPTY)
7342 #define F_TXFIFO_EMPTY    V_TXFIFO_EMPTY(1U)
7343 
7344 #define S_TXFIFO_FULL    30
7345 #define V_TXFIFO_FULL(x) ((x) << S_TXFIFO_FULL)
7346 #define F_TXFIFO_FULL    V_TXFIFO_FULL(1U)
7347 
7348 #define S_UNDERUNFIX    22
7349 #define V_UNDERUNFIX(x) ((x) << S_UNDERUNFIX)
7350 #define F_UNDERUNFIX    V_UNDERUNFIX(1U)
7351 
7352 #define S_ENDROPPKT    21
7353 #define V_ENDROPPKT(x) ((x) << S_ENDROPPKT)
7354 #define F_ENDROPPKT    V_ENDROPPKT(1U)
7355 
7356 #define S_TXIPG    13
7357 #define M_TXIPG    0xff
7358 #define V_TXIPG(x) ((x) << S_TXIPG)
7359 #define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG)
7360 
7361 #define S_TXFIFOTHRESH    4
7362 #define M_TXFIFOTHRESH    0x1ff
7363 #define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH)
7364 #define G_TXFIFOTHRESH(x) (((x) >> S_TXFIFOTHRESH) & M_TXFIFOTHRESH)
7365 
7366 #define S_INTERNLOOPBACK    3
7367 #define V_INTERNLOOPBACK(x) ((x) << S_INTERNLOOPBACK)
7368 #define F_INTERNLOOPBACK    V_INTERNLOOPBACK(1U)
7369 
7370 #define S_TXBYTESWAP    2
7371 #define V_TXBYTESWAP(x) ((x) << S_TXBYTESWAP)
7372 #define F_TXBYTESWAP    V_TXBYTESWAP(1U)
7373 
7374 #define S_DISCRC    1
7375 #define V_DISCRC(x) ((x) << S_DISCRC)
7376 #define F_DISCRC    V_DISCRC(1U)
7377 
7378 #define S_DISPREAMBLE    0
7379 #define V_DISPREAMBLE(x) ((x) << S_DISPREAMBLE)
7380 #define F_DISPREAMBLE    V_DISPREAMBLE(1U)
7381 
7382 #define A_XGM_SLOW_TIMER 0x88c
7383 
7384 #define S_PAUSESLOWTIMEREN    31
7385 #define V_PAUSESLOWTIMEREN(x) ((x) << S_PAUSESLOWTIMEREN)
7386 #define F_PAUSESLOWTIMEREN    V_PAUSESLOWTIMEREN(1U)
7387 
7388 #define S_PAUSESLOWTIMER    0
7389 #define M_PAUSESLOWTIMER    0xfffff
7390 #define V_PAUSESLOWTIMER(x) ((x) << S_PAUSESLOWTIMER)
7391 #define G_PAUSESLOWTIMER(x) (((x) >> S_PAUSESLOWTIMER) & M_PAUSESLOWTIMER)
7392 
7393 #define A_XGM_PAUSE_TIMER 0x890
7394 
7395 #define S_PAUSETIMER    0
7396 #define M_PAUSETIMER    0xfffff
7397 #define V_PAUSETIMER(x) ((x) << S_PAUSETIMER)
7398 #define G_PAUSETIMER(x) (((x) >> S_PAUSETIMER) & M_PAUSETIMER)
7399 
7400 #define A_XGM_SERDES_CTRL 0x890
7401 
7402 #define S_SERDESEN    25
7403 #define V_SERDESEN(x) ((x) << S_SERDESEN)
7404 #define F_SERDESEN    V_SERDESEN(1U)
7405 
7406 #define S_SERDESRESET_    24
7407 #define V_SERDESRESET_(x) ((x) << S_SERDESRESET_)
7408 #define F_SERDESRESET_    V_SERDESRESET_(1U)
7409 
7410 #define S_CMURANGE    21
7411 #define M_CMURANGE    0x7
7412 #define V_CMURANGE(x) ((x) << S_CMURANGE)
7413 #define G_CMURANGE(x) (((x) >> S_CMURANGE) & M_CMURANGE)
7414 
7415 #define S_BGENB    20
7416 #define V_BGENB(x) ((x) << S_BGENB)
7417 #define F_BGENB    V_BGENB(1U)
7418 
7419 #define S_ENSKPDROP    19
7420 #define V_ENSKPDROP(x) ((x) << S_ENSKPDROP)
7421 #define F_ENSKPDROP    V_ENSKPDROP(1U)
7422 
7423 #define S_ENCOMMA    18
7424 #define V_ENCOMMA(x) ((x) << S_ENCOMMA)
7425 #define F_ENCOMMA    V_ENCOMMA(1U)
7426 
7427 #define S_EN8B10B    17
7428 #define V_EN8B10B(x) ((x) << S_EN8B10B)
7429 #define F_EN8B10B    V_EN8B10B(1U)
7430 
7431 #define S_ENELBUF    16
7432 #define V_ENELBUF(x) ((x) << S_ENELBUF)
7433 #define F_ENELBUF    V_ENELBUF(1U)
7434 
7435 #define S_GAIN    11
7436 #define M_GAIN    0x1f
7437 #define V_GAIN(x) ((x) << S_GAIN)
7438 #define G_GAIN(x) (((x) >> S_GAIN) & M_GAIN)
7439 
7440 #define S_BANDGAP    7
7441 #define M_BANDGAP    0xf
7442 #define V_BANDGAP(x) ((x) << S_BANDGAP)
7443 #define G_BANDGAP(x) (((x) >> S_BANDGAP) & M_BANDGAP)
7444 
7445 #define S_LPBKEN    5
7446 #define M_LPBKEN    0x3
7447 #define V_LPBKEN(x) ((x) << S_LPBKEN)
7448 #define G_LPBKEN(x) (((x) >> S_LPBKEN) & M_LPBKEN)
7449 
7450 #define S_RXENABLE    4
7451 #define V_RXENABLE(x) ((x) << S_RXENABLE)
7452 #define F_RXENABLE    V_RXENABLE(1U)
7453 
7454 #define S_TXENABLE    3
7455 #define V_TXENABLE(x) ((x) << S_TXENABLE)
7456 #define F_TXENABLE    V_TXENABLE(1U)
7457 
7458 #define A_XGM_XAUI_PCS_TEST 0x894
7459 
7460 #define S_TESTPATTERN    1
7461 #define M_TESTPATTERN    0x3
7462 #define V_TESTPATTERN(x) ((x) << S_TESTPATTERN)
7463 #define G_TESTPATTERN(x) (((x) >> S_TESTPATTERN) & M_TESTPATTERN)
7464 
7465 #define S_ENTEST    0
7466 #define V_ENTEST(x) ((x) << S_ENTEST)
7467 #define F_ENTEST    V_ENTEST(1U)
7468 
7469 #define A_XGM_RGMII_CTRL 0x898
7470 
7471 #define S_PHALIGNFIFOTHRESH    1
7472 #define M_PHALIGNFIFOTHRESH    0x3
7473 #define V_PHALIGNFIFOTHRESH(x) ((x) << S_PHALIGNFIFOTHRESH)
7474 #define G_PHALIGNFIFOTHRESH(x) (((x) >> S_PHALIGNFIFOTHRESH) & M_PHALIGNFIFOTHRESH)
7475 
7476 #define S_TXCLK90SHIFT    0
7477 #define V_TXCLK90SHIFT(x) ((x) << S_TXCLK90SHIFT)
7478 #define F_TXCLK90SHIFT    V_TXCLK90SHIFT(1U)
7479 
7480 #define A_XGM_RGMII_IMP 0x89c
7481 
7482 #define S_CALRESET    8
7483 #define V_CALRESET(x) ((x) << S_CALRESET)
7484 #define F_CALRESET    V_CALRESET(1U)
7485 
7486 #define S_CALUPDATE    7
7487 #define V_CALUPDATE(x) ((x) << S_CALUPDATE)
7488 #define F_CALUPDATE    V_CALUPDATE(1U)
7489 
7490 #define S_XGM_IMPSETUPDATE    6
7491 #define V_XGM_IMPSETUPDATE(x) ((x) << S_XGM_IMPSETUPDATE)
7492 #define F_XGM_IMPSETUPDATE    V_XGM_IMPSETUPDATE(1U)
7493 
7494 #define S_RGMIIIMPPD    3
7495 #define M_RGMIIIMPPD    0x7
7496 #define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD)
7497 #define G_RGMIIIMPPD(x) (((x) >> S_RGMIIIMPPD) & M_RGMIIIMPPD)
7498 
7499 #define S_RGMIIIMPPU    0
7500 #define M_RGMIIIMPPU    0x7
7501 #define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU)
7502 #define G_RGMIIIMPPU(x) (((x) >> S_RGMIIIMPPU) & M_RGMIIIMPPU)
7503 
7504 #define A_XGM_XAUI_IMP 0x8a0
7505 
7506 #define S_XGM_CALFAULT    29
7507 #define V_XGM_CALFAULT(x) ((x) << S_XGM_CALFAULT)
7508 #define F_XGM_CALFAULT    V_XGM_CALFAULT(1U)
7509 
7510 #define S_CALIMP    24
7511 #define M_CALIMP    0x1f
7512 #define V_CALIMP(x) ((x) << S_CALIMP)
7513 #define G_CALIMP(x) (((x) >> S_CALIMP) & M_CALIMP)
7514 
7515 #define S_XAUIIMP    0
7516 #define M_XAUIIMP    0x7
7517 #define V_XAUIIMP(x) ((x) << S_XAUIIMP)
7518 #define G_XAUIIMP(x) (((x) >> S_XAUIIMP) & M_XAUIIMP)
7519 
7520 #define A_XGM_SERDES_BIST 0x8a4
7521 
7522 #define S_BISTDONE    28
7523 #define M_BISTDONE    0xf
7524 #define V_BISTDONE(x) ((x) << S_BISTDONE)
7525 #define G_BISTDONE(x) (((x) >> S_BISTDONE) & M_BISTDONE)
7526 
7527 #define S_BISTCYCLETHRESH    3
7528 #define M_BISTCYCLETHRESH    0x1ffff
7529 #define V_BISTCYCLETHRESH(x) ((x) << S_BISTCYCLETHRESH)
7530 #define G_BISTCYCLETHRESH(x) (((x) >> S_BISTCYCLETHRESH) & M_BISTCYCLETHRESH)
7531 
7532 #define A_XGM_RX_MAX_PKT_SIZE 0x8a8
7533 
7534 #define S_RXMAXFRAMERSIZE    17
7535 #define M_RXMAXFRAMERSIZE    0x3fff
7536 #define V_RXMAXFRAMERSIZE(x) ((x) << S_RXMAXFRAMERSIZE)
7537 #define G_RXMAXFRAMERSIZE(x) (((x) >> S_RXMAXFRAMERSIZE) & M_RXMAXFRAMERSIZE)
7538 
7539 #define S_RXENERRORGATHER    16
7540 #define V_RXENERRORGATHER(x) ((x) << S_RXENERRORGATHER)
7541 #define F_RXENERRORGATHER    V_RXENERRORGATHER(1U)
7542 
7543 #define S_RXENSINGLEFLIT    15
7544 #define V_RXENSINGLEFLIT(x) ((x) << S_RXENSINGLEFLIT)
7545 #define F_RXENSINGLEFLIT    V_RXENSINGLEFLIT(1U)
7546 
7547 #define S_RXENFRAMER    14
7548 #define V_RXENFRAMER(x) ((x) << S_RXENFRAMER)
7549 #define F_RXENFRAMER    V_RXENFRAMER(1U)
7550 
7551 #define S_RXMAXPKTSIZE    0
7552 #define M_RXMAXPKTSIZE    0x3fff
7553 #define V_RXMAXPKTSIZE(x) ((x) << S_RXMAXPKTSIZE)
7554 #define G_RXMAXPKTSIZE(x) (((x) >> S_RXMAXPKTSIZE) & M_RXMAXPKTSIZE)
7555 
7556 #define A_XGM_RESET_CTRL 0x8ac
7557 
7558 #define S_XGMAC_STOP_EN    4
7559 #define V_XGMAC_STOP_EN(x) ((x) << S_XGMAC_STOP_EN)
7560 #define F_XGMAC_STOP_EN    V_XGMAC_STOP_EN(1U)
7561 
7562 #define S_XG2G_RESET_    3
7563 #define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_)
7564 #define F_XG2G_RESET_    V_XG2G_RESET_(1U)
7565 
7566 #define S_RGMII_RESET_    2
7567 #define V_RGMII_RESET_(x) ((x) << S_RGMII_RESET_)
7568 #define F_RGMII_RESET_    V_RGMII_RESET_(1U)
7569 
7570 #define S_PCS_RESET_    1
7571 #define V_PCS_RESET_(x) ((x) << S_PCS_RESET_)
7572 #define F_PCS_RESET_    V_PCS_RESET_(1U)
7573 
7574 #define S_MAC_RESET_    0
7575 #define V_MAC_RESET_(x) ((x) << S_MAC_RESET_)
7576 #define F_MAC_RESET_    V_MAC_RESET_(1U)
7577 
7578 #define A_XGM_XAUI1G_CTRL 0x8b0
7579 
7580 #define S_XAUI1GLINKID    0
7581 #define M_XAUI1GLINKID    0x3
7582 #define V_XAUI1GLINKID(x) ((x) << S_XAUI1GLINKID)
7583 #define G_XAUI1GLINKID(x) (((x) >> S_XAUI1GLINKID) & M_XAUI1GLINKID)
7584 
7585 #define A_XGM_SERDES_LANE_CTRL 0x8b4
7586 
7587 #define S_LANEREVERSAL    8
7588 #define V_LANEREVERSAL(x) ((x) << S_LANEREVERSAL)
7589 #define F_LANEREVERSAL    V_LANEREVERSAL(1U)
7590 
7591 #define S_TXPOLARITY    4
7592 #define M_TXPOLARITY    0xf
7593 #define V_TXPOLARITY(x) ((x) << S_TXPOLARITY)
7594 #define G_TXPOLARITY(x) (((x) >> S_TXPOLARITY) & M_TXPOLARITY)
7595 
7596 #define S_RXPOLARITY    0
7597 #define M_RXPOLARITY    0xf
7598 #define V_RXPOLARITY(x) ((x) << S_RXPOLARITY)
7599 #define G_RXPOLARITY(x) (((x) >> S_RXPOLARITY) & M_RXPOLARITY)
7600 
7601 #define A_XGM_PORT_CFG 0x8b8
7602 
7603 #define S_SAFESPEEDCHANGE    4
7604 #define V_SAFESPEEDCHANGE(x) ((x) << S_SAFESPEEDCHANGE)
7605 #define F_SAFESPEEDCHANGE    V_SAFESPEEDCHANGE(1U)
7606 
7607 #define S_CLKDIVRESET_    3
7608 #define V_CLKDIVRESET_(x) ((x) << S_CLKDIVRESET_)
7609 #define F_CLKDIVRESET_    V_CLKDIVRESET_(1U)
7610 
7611 #define S_PORTSPEED    1
7612 #define M_PORTSPEED    0x3
7613 #define V_PORTSPEED(x) ((x) << S_PORTSPEED)
7614 #define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED)
7615 
7616 #define S_ENRGMII    0
7617 #define V_ENRGMII(x) ((x) << S_ENRGMII)
7618 #define F_ENRGMII    V_ENRGMII(1U)
7619 
7620 #define A_XGM_EPIO_DATA0 0x8c0
7621 #define A_XGM_EPIO_DATA1 0x8c4
7622 #define A_XGM_EPIO_DATA2 0x8c8
7623 #define A_XGM_EPIO_DATA3 0x8cc
7624 #define A_XGM_EPIO_OP 0x8d0
7625 
7626 #define S_PIO_READY    31
7627 #define V_PIO_READY(x) ((x) << S_PIO_READY)
7628 #define F_PIO_READY    V_PIO_READY(1U)
7629 
7630 #define S_PIO_WRRD    24
7631 #define V_PIO_WRRD(x) ((x) << S_PIO_WRRD)
7632 #define F_PIO_WRRD    V_PIO_WRRD(1U)
7633 
7634 #define S_PIO_ADDRESS    0
7635 #define M_PIO_ADDRESS    0xff
7636 #define V_PIO_ADDRESS(x) ((x) << S_PIO_ADDRESS)
7637 #define G_PIO_ADDRESS(x) (((x) >> S_PIO_ADDRESS) & M_PIO_ADDRESS)
7638 
7639 #define A_XGM_INT_ENABLE 0x8d4
7640 
7641 #define S_XAUIPCSDECERR    24
7642 #define V_XAUIPCSDECERR(x) ((x) << S_XAUIPCSDECERR)
7643 #define F_XAUIPCSDECERR    V_XAUIPCSDECERR(1U)
7644 
7645 #define S_RGMIIRXFIFOOVERFLOW    23
7646 #define V_RGMIIRXFIFOOVERFLOW(x) ((x) << S_RGMIIRXFIFOOVERFLOW)
7647 #define F_RGMIIRXFIFOOVERFLOW    V_RGMIIRXFIFOOVERFLOW(1U)
7648 
7649 #define S_RGMIIRXFIFOUNDERFLOW    22
7650 #define V_RGMIIRXFIFOUNDERFLOW(x) ((x) << S_RGMIIRXFIFOUNDERFLOW)
7651 #define F_RGMIIRXFIFOUNDERFLOW    V_RGMIIRXFIFOUNDERFLOW(1U)
7652 
7653 #define S_RXPKTSIZEERROR    21
7654 #define V_RXPKTSIZEERROR(x) ((x) << S_RXPKTSIZEERROR)
7655 #define F_RXPKTSIZEERROR    V_RXPKTSIZEERROR(1U)
7656 
7657 #define S_WOLPATDETECTED    20
7658 #define V_WOLPATDETECTED(x) ((x) << S_WOLPATDETECTED)
7659 #define F_WOLPATDETECTED    V_WOLPATDETECTED(1U)
7660 
7661 #define S_TXFIFO_PRTY_ERR    17
7662 #define M_TXFIFO_PRTY_ERR    0x7
7663 #define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR)
7664 #define G_TXFIFO_PRTY_ERR(x) (((x) >> S_TXFIFO_PRTY_ERR) & M_TXFIFO_PRTY_ERR)
7665 
7666 #define S_RXFIFO_PRTY_ERR    14
7667 #define M_RXFIFO_PRTY_ERR    0x7
7668 #define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR)
7669 #define G_RXFIFO_PRTY_ERR(x) (((x) >> S_RXFIFO_PRTY_ERR) & M_RXFIFO_PRTY_ERR)
7670 
7671 #define S_TXFIFO_UNDERRUN    13
7672 #define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN)
7673 #define F_TXFIFO_UNDERRUN    V_TXFIFO_UNDERRUN(1U)
7674 
7675 #define S_RXFIFO_OVERFLOW    12
7676 #define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW)
7677 #define F_RXFIFO_OVERFLOW    V_RXFIFO_OVERFLOW(1U)
7678 
7679 #define S_SERDESBISTERR    8
7680 #define M_SERDESBISTERR    0xf
7681 #define V_SERDESBISTERR(x) ((x) << S_SERDESBISTERR)
7682 #define G_SERDESBISTERR(x) (((x) >> S_SERDESBISTERR) & M_SERDESBISTERR)
7683 
7684 #define S_SERDESLOWSIGCHANGE    4
7685 #define M_SERDESLOWSIGCHANGE    0xf
7686 #define V_SERDESLOWSIGCHANGE(x) ((x) << S_SERDESLOWSIGCHANGE)
7687 #define G_SERDESLOWSIGCHANGE(x) (((x) >> S_SERDESLOWSIGCHANGE) & M_SERDESLOWSIGCHANGE)
7688 
7689 #define S_XAUIPCSCTCERR    3
7690 #define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR)
7691 #define F_XAUIPCSCTCERR    V_XAUIPCSCTCERR(1U)
7692 
7693 #define S_XAUIPCSALIGNCHANGE    2
7694 #define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE)
7695 #define F_XAUIPCSALIGNCHANGE    V_XAUIPCSALIGNCHANGE(1U)
7696 
7697 #define S_RGMIILINKSTSCHANGE    1
7698 #define V_RGMIILINKSTSCHANGE(x) ((x) << S_RGMIILINKSTSCHANGE)
7699 #define F_RGMIILINKSTSCHANGE    V_RGMIILINKSTSCHANGE(1U)
7700 
7701 #define S_XGM_INT    0
7702 #define V_XGM_INT(x) ((x) << S_XGM_INT)
7703 #define F_XGM_INT    V_XGM_INT(1U)
7704 
7705 #define S_SERDESCMULOCK_LOSS    24
7706 #define V_SERDESCMULOCK_LOSS(x) ((x) << S_SERDESCMULOCK_LOSS)
7707 #define F_SERDESCMULOCK_LOSS    V_SERDESCMULOCK_LOSS(1U)
7708 
7709 #define S_SERDESBIST_ERR    8
7710 #define M_SERDESBIST_ERR    0xf
7711 #define V_SERDESBIST_ERR(x) ((x) << S_SERDESBIST_ERR)
7712 #define G_SERDESBIST_ERR(x) (((x) >> S_SERDESBIST_ERR) & M_SERDESBIST_ERR)
7713 
7714 #define S_SERDES_LOS    4
7715 #define M_SERDES_LOS    0xf
7716 #define V_SERDES_LOS(x) ((x) << S_SERDES_LOS)
7717 #define G_SERDES_LOS(x) (((x) >> S_SERDES_LOS) & M_SERDES_LOS)
7718 
7719 #define A_XGM_INT_CAUSE 0x8d8
7720 #define A_XGM_XAUI_ACT_CTRL 0x8dc
7721 
7722 #define S_TXACTENABLE    1
7723 #define V_TXACTENABLE(x) ((x) << S_TXACTENABLE)
7724 #define F_TXACTENABLE    V_TXACTENABLE(1U)
7725 
7726 #define A_XGM_SERDES_CTRL0 0x8e0
7727 
7728 #define S_INTSERLPBK3    27
7729 #define V_INTSERLPBK3(x) ((x) << S_INTSERLPBK3)
7730 #define F_INTSERLPBK3    V_INTSERLPBK3(1U)
7731 
7732 #define S_INTSERLPBK2    26
7733 #define V_INTSERLPBK2(x) ((x) << S_INTSERLPBK2)
7734 #define F_INTSERLPBK2    V_INTSERLPBK2(1U)
7735 
7736 #define S_INTSERLPBK1    25
7737 #define V_INTSERLPBK1(x) ((x) << S_INTSERLPBK1)
7738 #define F_INTSERLPBK1    V_INTSERLPBK1(1U)
7739 
7740 #define S_INTSERLPBK0    24
7741 #define V_INTSERLPBK0(x) ((x) << S_INTSERLPBK0)
7742 #define F_INTSERLPBK0    V_INTSERLPBK0(1U)
7743 
7744 #define S_RESET3    23
7745 #define V_RESET3(x) ((x) << S_RESET3)
7746 #define F_RESET3    V_RESET3(1U)
7747 
7748 #define S_RESET2    22
7749 #define V_RESET2(x) ((x) << S_RESET2)
7750 #define F_RESET2    V_RESET2(1U)
7751 
7752 #define S_RESET1    21
7753 #define V_RESET1(x) ((x) << S_RESET1)
7754 #define F_RESET1    V_RESET1(1U)
7755 
7756 #define S_RESET0    20
7757 #define V_RESET0(x) ((x) << S_RESET0)
7758 #define F_RESET0    V_RESET0(1U)
7759 
7760 #define S_PWRDN3    19
7761 #define V_PWRDN3(x) ((x) << S_PWRDN3)
7762 #define F_PWRDN3    V_PWRDN3(1U)
7763 
7764 #define S_PWRDN2    18
7765 #define V_PWRDN2(x) ((x) << S_PWRDN2)
7766 #define F_PWRDN2    V_PWRDN2(1U)
7767 
7768 #define S_PWRDN1    17
7769 #define V_PWRDN1(x) ((x) << S_PWRDN1)
7770 #define F_PWRDN1    V_PWRDN1(1U)
7771 
7772 #define S_PWRDN0    16
7773 #define V_PWRDN0(x) ((x) << S_PWRDN0)
7774 #define F_PWRDN0    V_PWRDN0(1U)
7775 
7776 #define S_RESETPLL23    15
7777 #define V_RESETPLL23(x) ((x) << S_RESETPLL23)
7778 #define F_RESETPLL23    V_RESETPLL23(1U)
7779 
7780 #define S_RESETPLL01    14
7781 #define V_RESETPLL01(x) ((x) << S_RESETPLL01)
7782 #define F_RESETPLL01    V_RESETPLL01(1U)
7783 
7784 #define S_PW23    12
7785 #define M_PW23    0x3
7786 #define V_PW23(x) ((x) << S_PW23)
7787 #define G_PW23(x) (((x) >> S_PW23) & M_PW23)
7788 
7789 #define S_PW01    10
7790 #define M_PW01    0x3
7791 #define V_PW01(x) ((x) << S_PW01)
7792 #define G_PW01(x) (((x) >> S_PW01) & M_PW01)
7793 
7794 #define S_XGM_DEQ    6
7795 #define M_XGM_DEQ    0xf
7796 #define V_XGM_DEQ(x) ((x) << S_XGM_DEQ)
7797 #define G_XGM_DEQ(x) (((x) >> S_XGM_DEQ) & M_XGM_DEQ)
7798 
7799 #define S_XGM_DTX    2
7800 #define M_XGM_DTX    0xf
7801 #define V_XGM_DTX(x) ((x) << S_XGM_DTX)
7802 #define G_XGM_DTX(x) (((x) >> S_XGM_DTX) & M_XGM_DTX)
7803 
7804 #define S_XGM_LODRV    1
7805 #define V_XGM_LODRV(x) ((x) << S_XGM_LODRV)
7806 #define F_XGM_LODRV    V_XGM_LODRV(1U)
7807 
7808 #define S_XGM_HIDRV    0
7809 #define V_XGM_HIDRV(x) ((x) << S_XGM_HIDRV)
7810 #define F_XGM_HIDRV    V_XGM_HIDRV(1U)
7811 
7812 #define A_XGM_SERDES_CTRL1 0x8e4
7813 
7814 #define S_FMOFFSET3    19
7815 #define M_FMOFFSET3    0x1f
7816 #define V_FMOFFSET3(x) ((x) << S_FMOFFSET3)
7817 #define G_FMOFFSET3(x) (((x) >> S_FMOFFSET3) & M_FMOFFSET3)
7818 
7819 #define S_FMOFFSETEN3    18
7820 #define V_FMOFFSETEN3(x) ((x) << S_FMOFFSETEN3)
7821 #define F_FMOFFSETEN3    V_FMOFFSETEN3(1U)
7822 
7823 #define S_FMOFFSET2    13
7824 #define M_FMOFFSET2    0x1f
7825 #define V_FMOFFSET2(x) ((x) << S_FMOFFSET2)
7826 #define G_FMOFFSET2(x) (((x) >> S_FMOFFSET2) & M_FMOFFSET2)
7827 
7828 #define S_FMOFFSETEN2    12
7829 #define V_FMOFFSETEN2(x) ((x) << S_FMOFFSETEN2)
7830 #define F_FMOFFSETEN2    V_FMOFFSETEN2(1U)
7831 
7832 #define S_FMOFFSET1    7
7833 #define M_FMOFFSET1    0x1f
7834 #define V_FMOFFSET1(x) ((x) << S_FMOFFSET1)
7835 #define G_FMOFFSET1(x) (((x) >> S_FMOFFSET1) & M_FMOFFSET1)
7836 
7837 #define S_FMOFFSETEN1    6
7838 #define V_FMOFFSETEN1(x) ((x) << S_FMOFFSETEN1)
7839 #define F_FMOFFSETEN1    V_FMOFFSETEN1(1U)
7840 
7841 #define S_FMOFFSET0    1
7842 #define M_FMOFFSET0    0x1f
7843 #define V_FMOFFSET0(x) ((x) << S_FMOFFSET0)
7844 #define G_FMOFFSET0(x) (((x) >> S_FMOFFSET0) & M_FMOFFSET0)
7845 
7846 #define S_FMOFFSETEN0    0
7847 #define V_FMOFFSETEN0(x) ((x) << S_FMOFFSETEN0)
7848 #define F_FMOFFSETEN0    V_FMOFFSETEN0(1U)
7849 
7850 #define A_XGM_SERDES_CTRL2 0x8e8
7851 
7852 #define S_DNIN3    11
7853 #define V_DNIN3(x) ((x) << S_DNIN3)
7854 #define F_DNIN3    V_DNIN3(1U)
7855 
7856 #define S_UPIN3    10
7857 #define V_UPIN3(x) ((x) << S_UPIN3)
7858 #define F_UPIN3    V_UPIN3(1U)
7859 
7860 #define S_RXSLAVE3    9
7861 #define V_RXSLAVE3(x) ((x) << S_RXSLAVE3)
7862 #define F_RXSLAVE3    V_RXSLAVE3(1U)
7863 
7864 #define S_DNIN2    8
7865 #define V_DNIN2(x) ((x) << S_DNIN2)
7866 #define F_DNIN2    V_DNIN2(1U)
7867 
7868 #define S_UPIN2    7
7869 #define V_UPIN2(x) ((x) << S_UPIN2)
7870 #define F_UPIN2    V_UPIN2(1U)
7871 
7872 #define S_RXSLAVE2    6
7873 #define V_RXSLAVE2(x) ((x) << S_RXSLAVE2)
7874 #define F_RXSLAVE2    V_RXSLAVE2(1U)
7875 
7876 #define S_DNIN1    5
7877 #define V_DNIN1(x) ((x) << S_DNIN1)
7878 #define F_DNIN1    V_DNIN1(1U)
7879 
7880 #define S_UPIN1    4
7881 #define V_UPIN1(x) ((x) << S_UPIN1)
7882 #define F_UPIN1    V_UPIN1(1U)
7883 
7884 #define S_RXSLAVE1    3
7885 #define V_RXSLAVE1(x) ((x) << S_RXSLAVE1)
7886 #define F_RXSLAVE1    V_RXSLAVE1(1U)
7887 
7888 #define S_DNIN0    2
7889 #define V_DNIN0(x) ((x) << S_DNIN0)
7890 #define F_DNIN0    V_DNIN0(1U)
7891 
7892 #define S_UPIN0    1
7893 #define V_UPIN0(x) ((x) << S_UPIN0)
7894 #define F_UPIN0    V_UPIN0(1U)
7895 
7896 #define S_RXSLAVE0    0
7897 #define V_RXSLAVE0(x) ((x) << S_RXSLAVE0)
7898 #define F_RXSLAVE0    V_RXSLAVE0(1U)
7899 
7900 #define A_XGM_SERDES_CTRL3 0x8ec
7901 
7902 #define S_EXTBISTCHKERRCLR3    31
7903 #define V_EXTBISTCHKERRCLR3(x) ((x) << S_EXTBISTCHKERRCLR3)
7904 #define F_EXTBISTCHKERRCLR3    V_EXTBISTCHKERRCLR3(1U)
7905 
7906 #define S_EXTBISTCHKEN3    30
7907 #define V_EXTBISTCHKEN3(x) ((x) << S_EXTBISTCHKEN3)
7908 #define F_EXTBISTCHKEN3    V_EXTBISTCHKEN3(1U)
7909 
7910 #define S_EXTBISTGENEN3    29
7911 #define V_EXTBISTGENEN3(x) ((x) << S_EXTBISTGENEN3)
7912 #define F_EXTBISTGENEN3    V_EXTBISTGENEN3(1U)
7913 
7914 #define S_EXTBISTPAT3    26
7915 #define M_EXTBISTPAT3    0x7
7916 #define V_EXTBISTPAT3(x) ((x) << S_EXTBISTPAT3)
7917 #define G_EXTBISTPAT3(x) (((x) >> S_EXTBISTPAT3) & M_EXTBISTPAT3)
7918 
7919 #define S_EXTPARRESET3    25
7920 #define V_EXTPARRESET3(x) ((x) << S_EXTPARRESET3)
7921 #define F_EXTPARRESET3    V_EXTPARRESET3(1U)
7922 
7923 #define S_EXTPARLPBK3    24
7924 #define V_EXTPARLPBK3(x) ((x) << S_EXTPARLPBK3)
7925 #define F_EXTPARLPBK3    V_EXTPARLPBK3(1U)
7926 
7927 #define S_EXTBISTCHKERRCLR2    23
7928 #define V_EXTBISTCHKERRCLR2(x) ((x) << S_EXTBISTCHKERRCLR2)
7929 #define F_EXTBISTCHKERRCLR2    V_EXTBISTCHKERRCLR2(1U)
7930 
7931 #define S_EXTBISTCHKEN2    22
7932 #define V_EXTBISTCHKEN2(x) ((x) << S_EXTBISTCHKEN2)
7933 #define F_EXTBISTCHKEN2    V_EXTBISTCHKEN2(1U)
7934 
7935 #define S_EXTBISTGENEN2    21
7936 #define V_EXTBISTGENEN2(x) ((x) << S_EXTBISTGENEN2)
7937 #define F_EXTBISTGENEN2    V_EXTBISTGENEN2(1U)
7938 
7939 #define S_EXTBISTPAT2    18
7940 #define M_EXTBISTPAT2    0x7
7941 #define V_EXTBISTPAT2(x) ((x) << S_EXTBISTPAT2)
7942 #define G_EXTBISTPAT2(x) (((x) >> S_EXTBISTPAT2) & M_EXTBISTPAT2)
7943 
7944 #define S_EXTPARRESET2    17
7945 #define V_EXTPARRESET2(x) ((x) << S_EXTPARRESET2)
7946 #define F_EXTPARRESET2    V_EXTPARRESET2(1U)
7947 
7948 #define S_EXTPARLPBK2    16
7949 #define V_EXTPARLPBK2(x) ((x) << S_EXTPARLPBK2)
7950 #define F_EXTPARLPBK2    V_EXTPARLPBK2(1U)
7951 
7952 #define S_EXTBISTCHKERRCLR1    15
7953 #define V_EXTBISTCHKERRCLR1(x) ((x) << S_EXTBISTCHKERRCLR1)
7954 #define F_EXTBISTCHKERRCLR1    V_EXTBISTCHKERRCLR1(1U)
7955 
7956 #define S_EXTBISTCHKEN1    14
7957 #define V_EXTBISTCHKEN1(x) ((x) << S_EXTBISTCHKEN1)
7958 #define F_EXTBISTCHKEN1    V_EXTBISTCHKEN1(1U)
7959 
7960 #define S_EXTBISTGENEN1    13
7961 #define V_EXTBISTGENEN1(x) ((x) << S_EXTBISTGENEN1)
7962 #define F_EXTBISTGENEN1    V_EXTBISTGENEN1(1U)
7963 
7964 #define S_EXTBISTPAT1    10
7965 #define M_EXTBISTPAT1    0x7
7966 #define V_EXTBISTPAT1(x) ((x) << S_EXTBISTPAT1)
7967 #define G_EXTBISTPAT1(x) (((x) >> S_EXTBISTPAT1) & M_EXTBISTPAT1)
7968 
7969 #define S_EXTPARRESET1    9
7970 #define V_EXTPARRESET1(x) ((x) << S_EXTPARRESET1)
7971 #define F_EXTPARRESET1    V_EXTPARRESET1(1U)
7972 
7973 #define S_EXTPARLPBK1    8
7974 #define V_EXTPARLPBK1(x) ((x) << S_EXTPARLPBK1)
7975 #define F_EXTPARLPBK1    V_EXTPARLPBK1(1U)
7976 
7977 #define S_EXTBISTCHKERRCLR0    7
7978 #define V_EXTBISTCHKERRCLR0(x) ((x) << S_EXTBISTCHKERRCLR0)
7979 #define F_EXTBISTCHKERRCLR0    V_EXTBISTCHKERRCLR0(1U)
7980 
7981 #define S_EXTBISTCHKEN0    6
7982 #define V_EXTBISTCHKEN0(x) ((x) << S_EXTBISTCHKEN0)
7983 #define F_EXTBISTCHKEN0    V_EXTBISTCHKEN0(1U)
7984 
7985 #define S_EXTBISTGENEN0    5
7986 #define V_EXTBISTGENEN0(x) ((x) << S_EXTBISTGENEN0)
7987 #define F_EXTBISTGENEN0    V_EXTBISTGENEN0(1U)
7988 
7989 #define S_EXTBISTPAT0    2
7990 #define M_EXTBISTPAT0    0x7
7991 #define V_EXTBISTPAT0(x) ((x) << S_EXTBISTPAT0)
7992 #define G_EXTBISTPAT0(x) (((x) >> S_EXTBISTPAT0) & M_EXTBISTPAT0)
7993 
7994 #define S_EXTPARRESET0    1
7995 #define V_EXTPARRESET0(x) ((x) << S_EXTPARRESET0)
7996 #define F_EXTPARRESET0    V_EXTPARRESET0(1U)
7997 
7998 #define S_EXTPARLPBK0    0
7999 #define V_EXTPARLPBK0(x) ((x) << S_EXTPARLPBK0)
8000 #define F_EXTPARLPBK0    V_EXTPARLPBK0(1U)
8001 
8002 #define A_XGM_SERDES_STAT0 0x8f0
8003 
8004 #define S_EXTBISTCHKERRCNT0    4
8005 #define M_EXTBISTCHKERRCNT0    0xffffff
8006 #define V_EXTBISTCHKERRCNT0(x) ((x) << S_EXTBISTCHKERRCNT0)
8007 #define G_EXTBISTCHKERRCNT0(x) (((x) >> S_EXTBISTCHKERRCNT0) & M_EXTBISTCHKERRCNT0)
8008 
8009 #define S_EXTBISTCHKFMD0    3
8010 #define V_EXTBISTCHKFMD0(x) ((x) << S_EXTBISTCHKFMD0)
8011 #define F_EXTBISTCHKFMD0    V_EXTBISTCHKFMD0(1U)
8012 
8013 #define S_LOWSIGFORCEEN0    2
8014 #define V_LOWSIGFORCEEN0(x) ((x) << S_LOWSIGFORCEEN0)
8015 #define F_LOWSIGFORCEEN0    V_LOWSIGFORCEEN0(1U)
8016 
8017 #define S_LOWSIGFORCEVALUE0    1
8018 #define V_LOWSIGFORCEVALUE0(x) ((x) << S_LOWSIGFORCEVALUE0)
8019 #define F_LOWSIGFORCEVALUE0    V_LOWSIGFORCEVALUE0(1U)
8020 
8021 #define S_LOWSIG0    0
8022 #define V_LOWSIG0(x) ((x) << S_LOWSIG0)
8023 #define F_LOWSIG0    V_LOWSIG0(1U)
8024 
8025 #define A_XGM_SERDES_STAT1 0x8f4
8026 
8027 #define S_EXTBISTCHKERRCNT1    4
8028 #define M_EXTBISTCHKERRCNT1    0xffffff
8029 #define V_EXTBISTCHKERRCNT1(x) ((x) << S_EXTBISTCHKERRCNT1)
8030 #define G_EXTBISTCHKERRCNT1(x) (((x) >> S_EXTBISTCHKERRCNT1) & M_EXTBISTCHKERRCNT1)
8031 
8032 #define S_EXTBISTCHKFMD1    3
8033 #define V_EXTBISTCHKFMD1(x) ((x) << S_EXTBISTCHKFMD1)
8034 #define F_EXTBISTCHKFMD1    V_EXTBISTCHKFMD1(1U)
8035 
8036 #define S_LOWSIGFORCEEN1    2
8037 #define V_LOWSIGFORCEEN1(x) ((x) << S_LOWSIGFORCEEN1)
8038 #define F_LOWSIGFORCEEN1    V_LOWSIGFORCEEN1(1U)
8039 
8040 #define S_LOWSIGFORCEVALUE1    1
8041 #define V_LOWSIGFORCEVALUE1(x) ((x) << S_LOWSIGFORCEVALUE1)
8042 #define F_LOWSIGFORCEVALUE1    V_LOWSIGFORCEVALUE1(1U)
8043 
8044 #define S_LOWSIG1    0
8045 #define V_LOWSIG1(x) ((x) << S_LOWSIG1)
8046 #define F_LOWSIG1    V_LOWSIG1(1U)
8047 
8048 #define A_XGM_SERDES_STAT2 0x8f8
8049 
8050 #define S_EXTBISTCHKERRCNT2    4
8051 #define M_EXTBISTCHKERRCNT2    0xffffff
8052 #define V_EXTBISTCHKERRCNT2(x) ((x) << S_EXTBISTCHKERRCNT2)
8053 #define G_EXTBISTCHKERRCNT2(x) (((x) >> S_EXTBISTCHKERRCNT2) & M_EXTBISTCHKERRCNT2)
8054 
8055 #define S_EXTBISTCHKFMD2    3
8056 #define V_EXTBISTCHKFMD2(x) ((x) << S_EXTBISTCHKFMD2)
8057 #define F_EXTBISTCHKFMD2    V_EXTBISTCHKFMD2(1U)
8058 
8059 #define S_LOWSIGFORCEEN2    2
8060 #define V_LOWSIGFORCEEN2(x) ((x) << S_LOWSIGFORCEEN2)
8061 #define F_LOWSIGFORCEEN2    V_LOWSIGFORCEEN2(1U)
8062 
8063 #define S_LOWSIGFORCEVALUE2    1
8064 #define V_LOWSIGFORCEVALUE2(x) ((x) << S_LOWSIGFORCEVALUE2)
8065 #define F_LOWSIGFORCEVALUE2    V_LOWSIGFORCEVALUE2(1U)
8066 
8067 #define S_LOWSIG2    0
8068 #define V_LOWSIG2(x) ((x) << S_LOWSIG2)
8069 #define F_LOWSIG2    V_LOWSIG2(1U)
8070 
8071 #define A_XGM_SERDES_STAT3 0x8fc
8072 
8073 #define S_EXTBISTCHKERRCNT3    4
8074 #define M_EXTBISTCHKERRCNT3    0xffffff
8075 #define V_EXTBISTCHKERRCNT3(x) ((x) << S_EXTBISTCHKERRCNT3)
8076 #define G_EXTBISTCHKERRCNT3(x) (((x) >> S_EXTBISTCHKERRCNT3) & M_EXTBISTCHKERRCNT3)
8077 
8078 #define S_EXTBISTCHKFMD3    3
8079 #define V_EXTBISTCHKFMD3(x) ((x) << S_EXTBISTCHKFMD3)
8080 #define F_EXTBISTCHKFMD3    V_EXTBISTCHKFMD3(1U)
8081 
8082 #define S_LOWSIGFORCEEN3    2
8083 #define V_LOWSIGFORCEEN3(x) ((x) << S_LOWSIGFORCEEN3)
8084 #define F_LOWSIGFORCEEN3    V_LOWSIGFORCEEN3(1U)
8085 
8086 #define S_LOWSIGFORCEVALUE3    1
8087 #define V_LOWSIGFORCEVALUE3(x) ((x) << S_LOWSIGFORCEVALUE3)
8088 #define F_LOWSIGFORCEVALUE3    V_LOWSIGFORCEVALUE3(1U)
8089 
8090 #define S_LOWSIG3    0
8091 #define V_LOWSIG3(x) ((x) << S_LOWSIG3)
8092 #define F_LOWSIG3    V_LOWSIG3(1U)
8093 
8094 #define A_XGM_STAT_TX_BYTE_LOW 0x900
8095 #define A_XGM_STAT_TX_BYTE_HIGH 0x904
8096 
8097 #define S_TXBYTES_HIGH    0
8098 #define M_TXBYTES_HIGH    0x1fff
8099 #define V_TXBYTES_HIGH(x) ((x) << S_TXBYTES_HIGH)
8100 #define G_TXBYTES_HIGH(x) (((x) >> S_TXBYTES_HIGH) & M_TXBYTES_HIGH)
8101 
8102 #define A_XGM_STAT_TX_FRAME_LOW 0x908
8103 #define A_XGM_STAT_TX_FRAME_HIGH 0x90c
8104 
8105 #define S_TXFRAMES_HIGH    0
8106 #define M_TXFRAMES_HIGH    0xf
8107 #define V_TXFRAMES_HIGH(x) ((x) << S_TXFRAMES_HIGH)
8108 #define G_TXFRAMES_HIGH(x) (((x) >> S_TXFRAMES_HIGH) & M_TXFRAMES_HIGH)
8109 
8110 #define A_XGM_STAT_TX_BCAST 0x910
8111 #define A_XGM_STAT_TX_MCAST 0x914
8112 #define A_XGM_STAT_TX_PAUSE 0x918
8113 #define A_XGM_STAT_TX_64B_FRAMES 0x91c
8114 #define A_XGM_STAT_TX_65_127B_FRAMES 0x920
8115 #define A_XGM_STAT_TX_128_255B_FRAMES 0x924
8116 #define A_XGM_STAT_TX_256_511B_FRAMES 0x928
8117 #define A_XGM_STAT_TX_512_1023B_FRAMES 0x92c
8118 #define A_XGM_STAT_TX_1024_1518B_FRAMES 0x930
8119 #define A_XGM_STAT_TX_1519_MAXB_FRAMES 0x934
8120 #define A_XGM_STAT_TX_ERR_FRAMES 0x938
8121 #define A_XGM_STAT_RX_BYTES_LOW 0x93c
8122 #define A_XGM_STAT_RX_BYTES_HIGH 0x940
8123 
8124 #define S_RXBYTES_HIGH    0
8125 #define M_RXBYTES_HIGH    0x1fff
8126 #define V_RXBYTES_HIGH(x) ((x) << S_RXBYTES_HIGH)
8127 #define G_RXBYTES_HIGH(x) (((x) >> S_RXBYTES_HIGH) & M_RXBYTES_HIGH)
8128 
8129 #define A_XGM_STAT_RX_FRAMES_LOW 0x944
8130 #define A_XGM_STAT_RX_FRAMES_HIGH 0x948
8131 
8132 #define S_RXFRAMES_HIGH    0
8133 #define M_RXFRAMES_HIGH    0xf
8134 #define V_RXFRAMES_HIGH(x) ((x) << S_RXFRAMES_HIGH)
8135 #define G_RXFRAMES_HIGH(x) (((x) >> S_RXFRAMES_HIGH) & M_RXFRAMES_HIGH)
8136 
8137 #define A_XGM_STAT_RX_BCAST_FRAMES 0x94c
8138 #define A_XGM_STAT_RX_MCAST_FRAMES 0x950
8139 #define A_XGM_STAT_RX_PAUSE_FRAMES 0x954
8140 
8141 #define S_RXPAUSEFRAMES    0
8142 #define M_RXPAUSEFRAMES    0xffff
8143 #define V_RXPAUSEFRAMES(x) ((x) << S_RXPAUSEFRAMES)
8144 #define G_RXPAUSEFRAMES(x) (((x) >> S_RXPAUSEFRAMES) & M_RXPAUSEFRAMES)
8145 
8146 #define A_XGM_STAT_RX_64B_FRAMES 0x958
8147 #define A_XGM_STAT_RX_65_127B_FRAMES 0x95c
8148 #define A_XGM_STAT_RX_128_255B_FRAMES 0x960
8149 #define A_XGM_STAT_RX_256_511B_FRAMES 0x964
8150 #define A_XGM_STAT_RX_512_1023B_FRAMES 0x968
8151 #define A_XGM_STAT_RX_1024_1518B_FRAMES 0x96c
8152 #define A_XGM_STAT_RX_1519_MAXB_FRAMES 0x970
8153 #define A_XGM_STAT_RX_SHORT_FRAMES 0x974
8154 
8155 #define S_RXSHORTFRAMES    0
8156 #define M_RXSHORTFRAMES    0xffff
8157 #define V_RXSHORTFRAMES(x) ((x) << S_RXSHORTFRAMES)
8158 #define G_RXSHORTFRAMES(x) (((x) >> S_RXSHORTFRAMES) & M_RXSHORTFRAMES)
8159 
8160 #define A_XGM_STAT_RX_OVERSIZE_FRAMES 0x978
8161 
8162 #define S_RXOVERSIZEFRAMES    0
8163 #define M_RXOVERSIZEFRAMES    0xffff
8164 #define V_RXOVERSIZEFRAMES(x) ((x) << S_RXOVERSIZEFRAMES)
8165 #define G_RXOVERSIZEFRAMES(x) (((x) >> S_RXOVERSIZEFRAMES) & M_RXOVERSIZEFRAMES)
8166 
8167 #define A_XGM_STAT_RX_JABBER_FRAMES 0x97c
8168 
8169 #define S_RXJABBERFRAMES    0
8170 #define M_RXJABBERFRAMES    0xffff
8171 #define V_RXJABBERFRAMES(x) ((x) << S_RXJABBERFRAMES)
8172 #define G_RXJABBERFRAMES(x) (((x) >> S_RXJABBERFRAMES) & M_RXJABBERFRAMES)
8173 
8174 #define A_XGM_STAT_RX_CRC_ERR_FRAMES 0x980
8175 
8176 #define S_RXCRCERRFRAMES    0
8177 #define M_RXCRCERRFRAMES    0xffff
8178 #define V_RXCRCERRFRAMES(x) ((x) << S_RXCRCERRFRAMES)
8179 #define G_RXCRCERRFRAMES(x) (((x) >> S_RXCRCERRFRAMES) & M_RXCRCERRFRAMES)
8180 
8181 #define A_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x984
8182 
8183 #define S_RXLENGTHERRFRAMES    0
8184 #define M_RXLENGTHERRFRAMES    0xffff
8185 #define V_RXLENGTHERRFRAMES(x) ((x) << S_RXLENGTHERRFRAMES)
8186 #define G_RXLENGTHERRFRAMES(x) (((x) >> S_RXLENGTHERRFRAMES) & M_RXLENGTHERRFRAMES)
8187 
8188 #define A_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x988
8189 
8190 #define S_RXSYMCODEERRFRAMES    0
8191 #define M_RXSYMCODEERRFRAMES    0xffff
8192 #define V_RXSYMCODEERRFRAMES(x) ((x) << S_RXSYMCODEERRFRAMES)
8193 #define G_RXSYMCODEERRFRAMES(x) (((x) >> S_RXSYMCODEERRFRAMES) & M_RXSYMCODEERRFRAMES)
8194 
8195 #define A_XGM_SERDES_STATUS0 0x98c
8196 
8197 #define S_RXERRLANE3    9
8198 #define M_RXERRLANE3    0x7
8199 #define V_RXERRLANE3(x) ((x) << S_RXERRLANE3)
8200 #define G_RXERRLANE3(x) (((x) >> S_RXERRLANE3) & M_RXERRLANE3)
8201 
8202 #define S_RXERRLANE2    6
8203 #define M_RXERRLANE2    0x7
8204 #define V_RXERRLANE2(x) ((x) << S_RXERRLANE2)
8205 #define G_RXERRLANE2(x) (((x) >> S_RXERRLANE2) & M_RXERRLANE2)
8206 
8207 #define S_RXERRLANE1    3
8208 #define M_RXERRLANE1    0x7
8209 #define V_RXERRLANE1(x) ((x) << S_RXERRLANE1)
8210 #define G_RXERRLANE1(x) (((x) >> S_RXERRLANE1) & M_RXERRLANE1)
8211 
8212 #define S_RXERRLANE0    0
8213 #define M_RXERRLANE0    0x7
8214 #define V_RXERRLANE0(x) ((x) << S_RXERRLANE0)
8215 #define G_RXERRLANE0(x) (((x) >> S_RXERRLANE0) & M_RXERRLANE0)
8216 
8217 #define A_XGM_SERDES_STATUS1 0x990
8218 
8219 #define S_RXKLOCKLANE3    11
8220 #define V_RXKLOCKLANE3(x) ((x) << S_RXKLOCKLANE3)
8221 #define F_RXKLOCKLANE3    V_RXKLOCKLANE3(1U)
8222 
8223 #define S_RXKLOCKLANE2    10
8224 #define V_RXKLOCKLANE2(x) ((x) << S_RXKLOCKLANE2)
8225 #define F_RXKLOCKLANE2    V_RXKLOCKLANE2(1U)
8226 
8227 #define S_RXKLOCKLANE1    9
8228 #define V_RXKLOCKLANE1(x) ((x) << S_RXKLOCKLANE1)
8229 #define F_RXKLOCKLANE1    V_RXKLOCKLANE1(1U)
8230 
8231 #define S_RXKLOCKLANE0    8
8232 #define V_RXKLOCKLANE0(x) ((x) << S_RXKLOCKLANE0)
8233 #define F_RXKLOCKLANE0    V_RXKLOCKLANE0(1U)
8234 
8235 #define S_RXUFLOWLANE3    7
8236 #define V_RXUFLOWLANE3(x) ((x) << S_RXUFLOWLANE3)
8237 #define F_RXUFLOWLANE3    V_RXUFLOWLANE3(1U)
8238 
8239 #define S_RXUFLOWLANE2    6
8240 #define V_RXUFLOWLANE2(x) ((x) << S_RXUFLOWLANE2)
8241 #define F_RXUFLOWLANE2    V_RXUFLOWLANE2(1U)
8242 
8243 #define S_RXUFLOWLANE1    5
8244 #define V_RXUFLOWLANE1(x) ((x) << S_RXUFLOWLANE1)
8245 #define F_RXUFLOWLANE1    V_RXUFLOWLANE1(1U)
8246 
8247 #define S_RXUFLOWLANE0    4
8248 #define V_RXUFLOWLANE0(x) ((x) << S_RXUFLOWLANE0)
8249 #define F_RXUFLOWLANE0    V_RXUFLOWLANE0(1U)
8250 
8251 #define S_RXOFLOWLANE3    3
8252 #define V_RXOFLOWLANE3(x) ((x) << S_RXOFLOWLANE3)
8253 #define F_RXOFLOWLANE3    V_RXOFLOWLANE3(1U)
8254 
8255 #define S_RXOFLOWLANE2    2
8256 #define V_RXOFLOWLANE2(x) ((x) << S_RXOFLOWLANE2)
8257 #define F_RXOFLOWLANE2    V_RXOFLOWLANE2(1U)
8258 
8259 #define S_RXOFLOWLANE1    1
8260 #define V_RXOFLOWLANE1(x) ((x) << S_RXOFLOWLANE1)
8261 #define F_RXOFLOWLANE1    V_RXOFLOWLANE1(1U)
8262 
8263 #define S_RXOFLOWLANE0    0
8264 #define V_RXOFLOWLANE0(x) ((x) << S_RXOFLOWLANE0)
8265 #define F_RXOFLOWLANE0    V_RXOFLOWLANE0(1U)
8266 
8267 #define A_XGM_SERDES_STATUS2 0x994
8268 
8269 #define S_XGM_RXEIDLANE3    11
8270 #define V_XGM_RXEIDLANE3(x) ((x) << S_XGM_RXEIDLANE3)
8271 #define F_XGM_RXEIDLANE3    V_XGM_RXEIDLANE3(1U)
8272 
8273 #define S_XGM_RXEIDLANE2    10
8274 #define V_XGM_RXEIDLANE2(x) ((x) << S_XGM_RXEIDLANE2)
8275 #define F_XGM_RXEIDLANE2    V_XGM_RXEIDLANE2(1U)
8276 
8277 #define S_XGM_RXEIDLANE1    9
8278 #define V_XGM_RXEIDLANE1(x) ((x) << S_XGM_RXEIDLANE1)
8279 #define F_XGM_RXEIDLANE1    V_XGM_RXEIDLANE1(1U)
8280 
8281 #define S_XGM_RXEIDLANE0    8
8282 #define V_XGM_RXEIDLANE0(x) ((x) << S_XGM_RXEIDLANE0)
8283 #define F_XGM_RXEIDLANE0    V_XGM_RXEIDLANE0(1U)
8284 
8285 #define S_RXREMSKIPLANE3    7
8286 #define V_RXREMSKIPLANE3(x) ((x) << S_RXREMSKIPLANE3)
8287 #define F_RXREMSKIPLANE3    V_RXREMSKIPLANE3(1U)
8288 
8289 #define S_RXREMSKIPLANE2    6
8290 #define V_RXREMSKIPLANE2(x) ((x) << S_RXREMSKIPLANE2)
8291 #define F_RXREMSKIPLANE2    V_RXREMSKIPLANE2(1U)
8292 
8293 #define S_RXREMSKIPLANE1    5
8294 #define V_RXREMSKIPLANE1(x) ((x) << S_RXREMSKIPLANE1)
8295 #define F_RXREMSKIPLANE1    V_RXREMSKIPLANE1(1U)
8296 
8297 #define S_RXREMSKIPLANE0    4
8298 #define V_RXREMSKIPLANE0(x) ((x) << S_RXREMSKIPLANE0)
8299 #define F_RXREMSKIPLANE0    V_RXREMSKIPLANE0(1U)
8300 
8301 #define S_RXADDSKIPLANE3    3
8302 #define V_RXADDSKIPLANE3(x) ((x) << S_RXADDSKIPLANE3)
8303 #define F_RXADDSKIPLANE3    V_RXADDSKIPLANE3(1U)
8304 
8305 #define S_RXADDSKIPLANE2    2
8306 #define V_RXADDSKIPLANE2(x) ((x) << S_RXADDSKIPLANE2)
8307 #define F_RXADDSKIPLANE2    V_RXADDSKIPLANE2(1U)
8308 
8309 #define S_RXADDSKIPLANE1    1
8310 #define V_RXADDSKIPLANE1(x) ((x) << S_RXADDSKIPLANE1)
8311 #define F_RXADDSKIPLANE1    V_RXADDSKIPLANE1(1U)
8312 
8313 #define S_RXADDSKIPLANE0    0
8314 #define V_RXADDSKIPLANE0(x) ((x) << S_RXADDSKIPLANE0)
8315 #define F_RXADDSKIPLANE0    V_RXADDSKIPLANE0(1U)
8316 
8317 #define A_XGM_XAUI_PCS_ERR 0x998
8318 
8319 #define S_PCS_SYNCSTATUS    5
8320 #define M_PCS_SYNCSTATUS    0xf
8321 #define V_PCS_SYNCSTATUS(x) ((x) << S_PCS_SYNCSTATUS)
8322 #define G_PCS_SYNCSTATUS(x) (((x) >> S_PCS_SYNCSTATUS) & M_PCS_SYNCSTATUS)
8323 
8324 #define S_PCS_CTCFIFOERR    1
8325 #define M_PCS_CTCFIFOERR    0xf
8326 #define V_PCS_CTCFIFOERR(x) ((x) << S_PCS_CTCFIFOERR)
8327 #define G_PCS_CTCFIFOERR(x) (((x) >> S_PCS_CTCFIFOERR) & M_PCS_CTCFIFOERR)
8328 
8329 #define S_PCS_NOTALIGNED    0
8330 #define V_PCS_NOTALIGNED(x) ((x) << S_PCS_NOTALIGNED)
8331 #define F_PCS_NOTALIGNED    V_PCS_NOTALIGNED(1U)
8332 
8333 #define A_XGM_RGMII_STATUS 0x99c
8334 
8335 #define S_GMIIDUPLEX    3
8336 #define V_GMIIDUPLEX(x) ((x) << S_GMIIDUPLEX)
8337 #define F_GMIIDUPLEX    V_GMIIDUPLEX(1U)
8338 
8339 #define S_GMIISPEED    1
8340 #define M_GMIISPEED    0x3
8341 #define V_GMIISPEED(x) ((x) << S_GMIISPEED)
8342 #define G_GMIISPEED(x) (((x) >> S_GMIISPEED) & M_GMIISPEED)
8343 
8344 #define S_GMIILINKSTATUS    0
8345 #define V_GMIILINKSTATUS(x) ((x) << S_GMIILINKSTATUS)
8346 #define F_GMIILINKSTATUS    V_GMIILINKSTATUS(1U)
8347 
8348 #define A_XGM_WOL_STATUS 0x9a0
8349 
8350 #define S_PATDETECTED    31
8351 #define V_PATDETECTED(x) ((x) << S_PATDETECTED)
8352 #define F_PATDETECTED    V_PATDETECTED(1U)
8353 
8354 #define S_MATCHEDFILTER    0
8355 #define M_MATCHEDFILTER    0x7
8356 #define V_MATCHEDFILTER(x) ((x) << S_MATCHEDFILTER)
8357 #define G_MATCHEDFILTER(x) (((x) >> S_MATCHEDFILTER) & M_MATCHEDFILTER)
8358 
8359 #define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4
8360 #define A_XGM_TX_SPI4_SOP_EOP_CNT 0x9a8
8361 
8362 #define S_TXSPI4SOPCNT    16
8363 #define M_TXSPI4SOPCNT    0xffff
8364 #define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT)
8365 #define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT)
8366 
8367 #define S_TXSPI4EOPCNT    0
8368 #define M_TXSPI4EOPCNT    0xffff
8369 #define V_TXSPI4EOPCNT(x) ((x) << S_TXSPI4EOPCNT)
8370 #define G_TXSPI4EOPCNT(x) (((x) >> S_TXSPI4EOPCNT) & M_TXSPI4EOPCNT)
8371 
8372 #define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac
8373 
8374 #define S_RXSPI4SOPCNT    16
8375 #define M_RXSPI4SOPCNT    0xffff
8376 #define V_RXSPI4SOPCNT(x) ((x) << S_RXSPI4SOPCNT)
8377 #define G_RXSPI4SOPCNT(x) (((x) >> S_RXSPI4SOPCNT) & M_RXSPI4SOPCNT)
8378 
8379 #define S_RXSPI4EOPCNT    0
8380 #define M_RXSPI4EOPCNT    0xffff
8381 #define V_RXSPI4EOPCNT(x) ((x) << S_RXSPI4EOPCNT)
8382 #define G_RXSPI4EOPCNT(x) (((x) >> S_RXSPI4EOPCNT) & M_RXSPI4EOPCNT)
8383 
8384 /* registers for module XGMAC0_1 */
8385 #define XGMAC0_1_BASE_ADDR 0xa00
8386