1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011, 2016, 2025 Chelsio Communications. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /* This file is automatically generated --- changes will be lost */ 30 31 #ifndef _T4_TCB_DEFS_H 32 #define _T4_TCB_DEFS_H 33 34 /* 3:0 */ 35 #define W_TCB_ULP_TYPE 0 36 #define S_TCB_ULP_TYPE 0 37 #define M_TCB_ULP_TYPE 0xfULL 38 #define V_TCB_ULP_TYPE(x) ((x) << S_TCB_ULP_TYPE) 39 40 /* 11:4 */ 41 #define W_TCB_ULP_RAW 0 42 #define S_TCB_ULP_RAW 4 43 #define M_TCB_ULP_RAW 0xffULL 44 #define V_TCB_ULP_RAW(x) ((x) << S_TCB_ULP_RAW) 45 46 /* 23:12 */ 47 #define W_TCB_L2T_IX 0 48 #define S_TCB_L2T_IX 12 49 #define M_TCB_L2T_IX 0xfffULL 50 #define V_TCB_L2T_IX(x) ((x) << S_TCB_L2T_IX) 51 52 /* 31:24 */ 53 #define W_TCB_SMAC_SEL 0 54 #define S_TCB_SMAC_SEL 24 55 #define M_TCB_SMAC_SEL 0xffULL 56 #define V_TCB_SMAC_SEL(x) ((x) << S_TCB_SMAC_SEL) 57 58 /* 95:32 */ 59 #define W_TCB_T_FLAGS 1 60 #define S_TCB_T_FLAGS 0 61 #define M_TCB_T_FLAGS 0xffffffffffffffffULL 62 #define V_TCB_T_FLAGS(x) ((__u64)(x) << S_TCB_T_FLAGS) 63 64 /* 105:96 */ 65 #define W_TCB_RSS_INFO 3 66 #define S_TCB_RSS_INFO 0 67 #define M_TCB_RSS_INFO 0x3ffULL 68 #define V_TCB_RSS_INFO(x) ((x) << S_TCB_RSS_INFO) 69 70 /* 111:106 */ 71 #define W_TCB_TOS 3 72 #define S_TCB_TOS 10 73 #define M_TCB_TOS 0x3fULL 74 #define V_TCB_TOS(x) ((x) << S_TCB_TOS) 75 76 /* 115:112 */ 77 #define W_TCB_T_STATE 3 78 #define S_TCB_T_STATE 16 79 #define M_TCB_T_STATE 0xfULL 80 #define V_TCB_T_STATE(x) ((x) << S_TCB_T_STATE) 81 82 /* 119:116 */ 83 #define W_TCB_MAX_RT 3 84 #define S_TCB_MAX_RT 20 85 #define M_TCB_MAX_RT 0xfULL 86 #define V_TCB_MAX_RT(x) ((x) << S_TCB_MAX_RT) 87 88 /* 123:120 */ 89 #define W_TCB_T_MAXSEG 3 90 #define S_TCB_T_MAXSEG 24 91 #define M_TCB_T_MAXSEG 0xfULL 92 #define V_TCB_T_MAXSEG(x) ((x) << S_TCB_T_MAXSEG) 93 94 /* 127:124 */ 95 #define W_TCB_SND_SCALE 3 96 #define S_TCB_SND_SCALE 28 97 #define M_TCB_SND_SCALE 0xfULL 98 #define V_TCB_SND_SCALE(x) ((x) << S_TCB_SND_SCALE) 99 100 /* 131:128 */ 101 #define W_TCB_RCV_SCALE 4 102 #define S_TCB_RCV_SCALE 0 103 #define M_TCB_RCV_SCALE 0xfULL 104 #define V_TCB_RCV_SCALE(x) ((x) << S_TCB_RCV_SCALE) 105 106 /* 135:132 */ 107 #define W_TCB_T_RXTSHIFT 4 108 #define S_TCB_T_RXTSHIFT 4 109 #define M_TCB_T_RXTSHIFT 0xfULL 110 #define V_TCB_T_RXTSHIFT(x) ((x) << S_TCB_T_RXTSHIFT) 111 112 /* 139:136 */ 113 #define W_TCB_T_DUPACKS 4 114 #define S_TCB_T_DUPACKS 8 115 #define M_TCB_T_DUPACKS 0xfULL 116 #define V_TCB_T_DUPACKS(x) ((x) << S_TCB_T_DUPACKS) 117 118 /* 143:140 */ 119 #define W_TCB_TIMESTAMP_OFFSET 4 120 #define S_TCB_TIMESTAMP_OFFSET 12 121 #define M_TCB_TIMESTAMP_OFFSET 0xfULL 122 #define V_TCB_TIMESTAMP_OFFSET(x) ((x) << S_TCB_TIMESTAMP_OFFSET) 123 124 /* 159:144 */ 125 #define W_TCB_RCV_ADV 4 126 #define S_TCB_RCV_ADV 16 127 #define M_TCB_RCV_ADV 0xffffULL 128 #define V_TCB_RCV_ADV(x) ((x) << S_TCB_RCV_ADV) 129 130 /* 191:160 */ 131 #define W_TCB_TIMESTAMP 5 132 #define S_TCB_TIMESTAMP 0 133 #define M_TCB_TIMESTAMP 0xffffffffULL 134 #define V_TCB_TIMESTAMP(x) ((x) << S_TCB_TIMESTAMP) 135 136 /* 223:192 */ 137 #define W_TCB_T_RTT_TS_RECENT_AGE 6 138 #define S_TCB_T_RTT_TS_RECENT_AGE 0 139 #define M_TCB_T_RTT_TS_RECENT_AGE 0xffffffffULL 140 #define V_TCB_T_RTT_TS_RECENT_AGE(x) ((x) << S_TCB_T_RTT_TS_RECENT_AGE) 141 142 /* 255:224 */ 143 #define W_TCB_T_RTSEQ_RECENT 7 144 #define S_TCB_T_RTSEQ_RECENT 0 145 #define M_TCB_T_RTSEQ_RECENT 0xffffffffULL 146 #define V_TCB_T_RTSEQ_RECENT(x) ((x) << S_TCB_T_RTSEQ_RECENT) 147 148 /* 271:256 */ 149 #define W_TCB_T_SRTT 8 150 #define S_TCB_T_SRTT 0 151 #define M_TCB_T_SRTT 0xffffULL 152 #define V_TCB_T_SRTT(x) ((x) << S_TCB_T_SRTT) 153 154 /* 287:272 */ 155 #define W_TCB_T_RTTVAR 8 156 #define S_TCB_T_RTTVAR 16 157 #define M_TCB_T_RTTVAR 0xffffULL 158 #define V_TCB_T_RTTVAR(x) ((x) << S_TCB_T_RTTVAR) 159 160 /* 319:288 */ 161 #define W_TCB_TX_MAX 9 162 #define S_TCB_TX_MAX 0 163 #define M_TCB_TX_MAX 0xffffffffULL 164 #define V_TCB_TX_MAX(x) ((x) << S_TCB_TX_MAX) 165 166 /* 347:320 */ 167 #define W_TCB_SND_UNA_RAW 10 168 #define S_TCB_SND_UNA_RAW 0 169 #define M_TCB_SND_UNA_RAW 0xfffffffULL 170 #define V_TCB_SND_UNA_RAW(x) ((x) << S_TCB_SND_UNA_RAW) 171 172 /* 375:348 */ 173 #define W_TCB_SND_NXT_RAW 10 174 #define S_TCB_SND_NXT_RAW 28 175 #define M_TCB_SND_NXT_RAW 0xfffffffULL 176 #define V_TCB_SND_NXT_RAW(x) ((__u64)(x) << S_TCB_SND_NXT_RAW) 177 178 /* 403:376 */ 179 #define W_TCB_SND_MAX_RAW 11 180 #define S_TCB_SND_MAX_RAW 24 181 #define M_TCB_SND_MAX_RAW 0xfffffffULL 182 #define V_TCB_SND_MAX_RAW(x) ((__u64)(x) << S_TCB_SND_MAX_RAW) 183 184 /* 431:404 */ 185 #define W_TCB_SND_REC_RAW 12 186 #define S_TCB_SND_REC_RAW 20 187 #define M_TCB_SND_REC_RAW 0xfffffffULL 188 #define V_TCB_SND_REC_RAW(x) ((__u64)(x) << S_TCB_SND_REC_RAW) 189 190 /* 459:432 */ 191 #define W_TCB_SND_CWND 13 192 #define S_TCB_SND_CWND 16 193 #define M_TCB_SND_CWND 0xfffffffULL 194 #define V_TCB_SND_CWND(x) ((__u64)(x) << S_TCB_SND_CWND) 195 196 /* 487:460 */ 197 #define W_TCB_SND_SSTHRESH 14 198 #define S_TCB_SND_SSTHRESH 12 199 #define M_TCB_SND_SSTHRESH 0xfffffffULL 200 #define V_TCB_SND_SSTHRESH(x) ((__u64)(x) << S_TCB_SND_SSTHRESH) 201 202 /* 504:488 */ 203 #define W_TCB_TX_HDR_PTR_RAW 15 204 #define S_TCB_TX_HDR_PTR_RAW 8 205 #define M_TCB_TX_HDR_PTR_RAW 0x1ffffULL 206 #define V_TCB_TX_HDR_PTR_RAW(x) ((x) << S_TCB_TX_HDR_PTR_RAW) 207 208 /* 521:505 */ 209 #define W_TCB_TX_LAST_PTR_RAW 15 210 #define S_TCB_TX_LAST_PTR_RAW 25 211 #define M_TCB_TX_LAST_PTR_RAW 0x1ffffULL 212 #define V_TCB_TX_LAST_PTR_RAW(x) ((__u64)(x) << S_TCB_TX_LAST_PTR_RAW) 213 214 /* 553:522 */ 215 #define W_TCB_RCV_NXT 16 216 #define S_TCB_RCV_NXT 10 217 #define M_TCB_RCV_NXT 0xffffffffULL 218 #define V_TCB_RCV_NXT(x) ((__u64)(x) << S_TCB_RCV_NXT) 219 220 /* 581:554 */ 221 #define W_TCB_RCV_WND 17 222 #define S_TCB_RCV_WND 10 223 #define M_TCB_RCV_WND 0xfffffffULL 224 #define V_TCB_RCV_WND(x) ((__u64)(x) << S_TCB_RCV_WND) 225 226 /* 609:582 */ 227 #define W_TCB_RX_HDR_OFFSET 18 228 #define S_TCB_RX_HDR_OFFSET 6 229 #define M_TCB_RX_HDR_OFFSET 0xfffffffULL 230 #define V_TCB_RX_HDR_OFFSET(x) ((__u64)(x) << S_TCB_RX_HDR_OFFSET) 231 232 /* 637:610 */ 233 #define W_TCB_TS_LAST_ACK_SENT_RAW 19 234 #define S_TCB_TS_LAST_ACK_SENT_RAW 2 235 #define M_TCB_TS_LAST_ACK_SENT_RAW 0xfffffffULL 236 #define V_TCB_TS_LAST_ACK_SENT_RAW(x) ((x) << S_TCB_TS_LAST_ACK_SENT_RAW) 237 238 /* 665:638 */ 239 #define W_TCB_RX_FRAG0_START_IDX_RAW 19 240 #define S_TCB_RX_FRAG0_START_IDX_RAW 30 241 #define M_TCB_RX_FRAG0_START_IDX_RAW 0xfffffffULL 242 #define V_TCB_RX_FRAG0_START_IDX_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG0_START_IDX_RAW) 243 244 /* 693:666 */ 245 #define W_TCB_RX_FRAG1_START_IDX_OFFSET 20 246 #define S_TCB_RX_FRAG1_START_IDX_OFFSET 26 247 #define M_TCB_RX_FRAG1_START_IDX_OFFSET 0xfffffffULL 248 #define V_TCB_RX_FRAG1_START_IDX_OFFSET(x) ((__u64)(x) << S_TCB_RX_FRAG1_START_IDX_OFFSET) 249 250 /* 721:694 */ 251 #define W_TCB_RX_FRAG0_LEN 21 252 #define S_TCB_RX_FRAG0_LEN 22 253 #define M_TCB_RX_FRAG0_LEN 0xfffffffULL 254 #define V_TCB_RX_FRAG0_LEN(x) ((__u64)(x) << S_TCB_RX_FRAG0_LEN) 255 256 /* 749:722 */ 257 #define W_TCB_RX_FRAG1_LEN 22 258 #define S_TCB_RX_FRAG1_LEN 18 259 #define M_TCB_RX_FRAG1_LEN 0xfffffffULL 260 #define V_TCB_RX_FRAG1_LEN(x) ((__u64)(x) << S_TCB_RX_FRAG1_LEN) 261 262 /* 765:750 */ 263 #define W_TCB_PDU_LEN 23 264 #define S_TCB_PDU_LEN 14 265 #define M_TCB_PDU_LEN 0xffffULL 266 #define V_TCB_PDU_LEN(x) ((x) << S_TCB_PDU_LEN) 267 268 /* 782:766 */ 269 #define W_TCB_RX_PTR_RAW 23 270 #define S_TCB_RX_PTR_RAW 30 271 #define M_TCB_RX_PTR_RAW 0x1ffffULL 272 #define V_TCB_RX_PTR_RAW(x) ((__u64)(x) << S_TCB_RX_PTR_RAW) 273 274 /* 799:783 */ 275 #define W_TCB_RX_FRAG1_PTR_RAW 24 276 #define S_TCB_RX_FRAG1_PTR_RAW 15 277 #define M_TCB_RX_FRAG1_PTR_RAW 0x1ffffULL 278 #define V_TCB_RX_FRAG1_PTR_RAW(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW) 279 280 /* 831:800 */ 281 #define W_TCB_MAIN_SLUSH 25 282 #define S_TCB_MAIN_SLUSH 0 283 #define M_TCB_MAIN_SLUSH 0xffffffffULL 284 #define V_TCB_MAIN_SLUSH(x) ((x) << S_TCB_MAIN_SLUSH) 285 286 /* 846:832 */ 287 #define W_TCB_AUX1_SLUSH0 26 288 #define S_TCB_AUX1_SLUSH0 0 289 #define M_TCB_AUX1_SLUSH0 0x7fffULL 290 #define V_TCB_AUX1_SLUSH0(x) ((x) << S_TCB_AUX1_SLUSH0) 291 292 /* 874:847 */ 293 #define W_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 26 294 #define S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 15 295 #define M_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 0xfffffffULL 296 #define V_TCB_RX_FRAG2_START_IDX_OFFSET_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW) 297 298 /* 891:875 */ 299 #define W_TCB_RX_FRAG2_PTR_RAW 27 300 #define S_TCB_RX_FRAG2_PTR_RAW 11 301 #define M_TCB_RX_FRAG2_PTR_RAW 0x1ffffULL 302 #define V_TCB_RX_FRAG2_PTR_RAW(x) ((x) << S_TCB_RX_FRAG2_PTR_RAW) 303 304 /* 919:892 */ 305 #define W_TCB_RX_FRAG2_LEN_RAW 27 306 #define S_TCB_RX_FRAG2_LEN_RAW 28 307 #define M_TCB_RX_FRAG2_LEN_RAW 0xfffffffULL 308 #define V_TCB_RX_FRAG2_LEN_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG2_LEN_RAW) 309 310 /* 936:920 */ 311 #define W_TCB_RX_FRAG3_PTR_RAW 28 312 #define S_TCB_RX_FRAG3_PTR_RAW 24 313 #define M_TCB_RX_FRAG3_PTR_RAW 0x1ffffULL 314 #define V_TCB_RX_FRAG3_PTR_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG3_PTR_RAW) 315 316 /* 964:937 */ 317 #define W_TCB_RX_FRAG3_LEN_RAW 29 318 #define S_TCB_RX_FRAG3_LEN_RAW 9 319 #define M_TCB_RX_FRAG3_LEN_RAW 0xfffffffULL 320 #define V_TCB_RX_FRAG3_LEN_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG3_LEN_RAW) 321 322 /* 992:965 */ 323 #define W_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 30 324 #define S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 5 325 #define M_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 0xfffffffULL 326 #define V_TCB_RX_FRAG3_START_IDX_OFFSET_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW) 327 328 /* 1000:993 */ 329 #define W_TCB_PDU_HDR_LEN 31 330 #define S_TCB_PDU_HDR_LEN 1 331 #define M_TCB_PDU_HDR_LEN 0xffULL 332 #define V_TCB_PDU_HDR_LEN(x) ((x) << S_TCB_PDU_HDR_LEN) 333 334 /* 1019:1001 */ 335 #define W_TCB_AUX1_SLUSH1 31 336 #define S_TCB_AUX1_SLUSH1 9 337 #define M_TCB_AUX1_SLUSH1 0x7ffffULL 338 #define V_TCB_AUX1_SLUSH1(x) ((x) << S_TCB_AUX1_SLUSH1) 339 340 /* 1023:1020 */ 341 #define W_TCB_ULP_EXT 31 342 #define S_TCB_ULP_EXT 28 343 #define M_TCB_ULP_EXT 0xfULL 344 #define V_TCB_ULP_EXT(x) ((x) << S_TCB_ULP_EXT) 345 346 /* 840:832 */ 347 #define W_TCB_IRS_ULP 26 348 #define S_TCB_IRS_ULP 0 349 #define M_TCB_IRS_ULP 0x1ffULL 350 #define V_TCB_IRS_ULP(x) ((x) << S_TCB_IRS_ULP) 351 352 /* 849:841 */ 353 #define W_TCB_ISS_ULP 26 354 #define S_TCB_ISS_ULP 9 355 #define M_TCB_ISS_ULP 0x1ffULL 356 #define V_TCB_ISS_ULP(x) ((x) << S_TCB_ISS_ULP) 357 358 /* 863:850 */ 359 #define W_TCB_TX_PDU_LEN 26 360 #define S_TCB_TX_PDU_LEN 18 361 #define M_TCB_TX_PDU_LEN 0x3fffULL 362 #define V_TCB_TX_PDU_LEN(x) ((x) << S_TCB_TX_PDU_LEN) 363 364 /* 879:864 */ 365 #define W_TCB_CQ_IDX_SQ 27 366 #define S_TCB_CQ_IDX_SQ 0 367 #define M_TCB_CQ_IDX_SQ 0xffffULL 368 #define V_TCB_CQ_IDX_SQ(x) ((x) << S_TCB_CQ_IDX_SQ) 369 370 /* 895:880 */ 371 #define W_TCB_CQ_IDX_RQ 27 372 #define S_TCB_CQ_IDX_RQ 16 373 #define M_TCB_CQ_IDX_RQ 0xffffULL 374 #define V_TCB_CQ_IDX_RQ(x) ((x) << S_TCB_CQ_IDX_RQ) 375 376 /* 911:896 */ 377 #define W_TCB_QP_ID 28 378 #define S_TCB_QP_ID 0 379 #define M_TCB_QP_ID 0xffffULL 380 #define V_TCB_QP_ID(x) ((x) << S_TCB_QP_ID) 381 382 /* 927:912 */ 383 #define W_TCB_PD_ID 28 384 #define S_TCB_PD_ID 16 385 #define M_TCB_PD_ID 0xffffULL 386 #define V_TCB_PD_ID(x) ((x) << S_TCB_PD_ID) 387 388 /* 959:928 */ 389 #define W_TCB_STAG 29 390 #define S_TCB_STAG 0 391 #define M_TCB_STAG 0xffffffffULL 392 #define V_TCB_STAG(x) ((x) << S_TCB_STAG) 393 394 /* 985:960 */ 395 #define W_TCB_RQ_START 30 396 #define S_TCB_RQ_START 0 397 #define M_TCB_RQ_START 0x3ffffffULL 398 #define V_TCB_RQ_START(x) ((x) << S_TCB_RQ_START) 399 400 /* 998:986 */ 401 #define W_TCB_RQ_MSN 30 402 #define S_TCB_RQ_MSN 26 403 #define M_TCB_RQ_MSN 0x1fffULL 404 #define V_TCB_RQ_MSN(x) ((__u64)(x) << S_TCB_RQ_MSN) 405 406 /* 1002:999 */ 407 #define W_TCB_RQ_MAX_OFFSET 31 408 #define S_TCB_RQ_MAX_OFFSET 7 409 #define M_TCB_RQ_MAX_OFFSET 0xfULL 410 #define V_TCB_RQ_MAX_OFFSET(x) ((x) << S_TCB_RQ_MAX_OFFSET) 411 412 /* 1015:1003 */ 413 #define W_TCB_RQ_WRITE_PTR 31 414 #define S_TCB_RQ_WRITE_PTR 11 415 #define M_TCB_RQ_WRITE_PTR 0x1fffULL 416 #define V_TCB_RQ_WRITE_PTR(x) ((x) << S_TCB_RQ_WRITE_PTR) 417 418 /* 1019:1016 */ 419 #define W_TCB_RDMAP_OPCODE 31 420 #define S_TCB_RDMAP_OPCODE 24 421 #define M_TCB_RDMAP_OPCODE 0xfULL 422 #define V_TCB_RDMAP_OPCODE(x) ((x) << S_TCB_RDMAP_OPCODE) 423 424 /* 1020:1020 */ 425 #define W_TCB_ORD_L_BIT_VLD 31 426 #define S_TCB_ORD_L_BIT_VLD 28 427 #define M_TCB_ORD_L_BIT_VLD 0x1ULL 428 #define V_TCB_ORD_L_BIT_VLD(x) ((x) << S_TCB_ORD_L_BIT_VLD) 429 430 /* 1021:1021 */ 431 #define W_TCB_TX_FLUSH 31 432 #define S_TCB_TX_FLUSH 29 433 #define M_TCB_TX_FLUSH 0x1ULL 434 #define V_TCB_TX_FLUSH(x) ((x) << S_TCB_TX_FLUSH) 435 436 /* 1022:1022 */ 437 #define W_TCB_TX_OOS_RXMT 31 438 #define S_TCB_TX_OOS_RXMT 30 439 #define M_TCB_TX_OOS_RXMT 0x1ULL 440 #define V_TCB_TX_OOS_RXMT(x) ((x) << S_TCB_TX_OOS_RXMT) 441 442 /* 1023:1023 */ 443 #define W_TCB_TX_OOS_TXMT 31 444 #define S_TCB_TX_OOS_TXMT 31 445 #define M_TCB_TX_OOS_TXMT 0x1ULL 446 #define V_TCB_TX_OOS_TXMT(x) ((x) << S_TCB_TX_OOS_TXMT) 447 448 /* 855:832 */ 449 #define W_TCB_RX_DDP_BUF0_OFFSET 26 450 #define S_TCB_RX_DDP_BUF0_OFFSET 0 451 #define M_TCB_RX_DDP_BUF0_OFFSET 0xffffffULL 452 #define V_TCB_RX_DDP_BUF0_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF0_OFFSET) 453 454 /* 879:856 */ 455 #define W_TCB_RX_DDP_BUF0_LEN 26 456 #define S_TCB_RX_DDP_BUF0_LEN 24 457 #define M_TCB_RX_DDP_BUF0_LEN 0xffffffULL 458 #define V_TCB_RX_DDP_BUF0_LEN(x) ((__u64)(x) << S_TCB_RX_DDP_BUF0_LEN) 459 460 /* 903:880 */ 461 #define W_TCB_RX_DDP_FLAGS 27 462 #define S_TCB_RX_DDP_FLAGS 16 463 #define M_TCB_RX_DDP_FLAGS 0xffffffULL 464 #define V_TCB_RX_DDP_FLAGS(x) ((__u64)(x) << S_TCB_RX_DDP_FLAGS) 465 466 /* 927:904 */ 467 #define W_TCB_RX_DDP_BUF1_OFFSET 28 468 #define S_TCB_RX_DDP_BUF1_OFFSET 8 469 #define M_TCB_RX_DDP_BUF1_OFFSET 0xffffffULL 470 #define V_TCB_RX_DDP_BUF1_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF1_OFFSET) 471 472 /* 951:928 */ 473 #define W_TCB_RX_DDP_BUF1_LEN 29 474 #define S_TCB_RX_DDP_BUF1_LEN 0 475 #define M_TCB_RX_DDP_BUF1_LEN 0xffffffULL 476 #define V_TCB_RX_DDP_BUF1_LEN(x) ((x) << S_TCB_RX_DDP_BUF1_LEN) 477 478 /* 959:952 */ 479 #define W_TCB_AUX3_SLUSH 29 480 #define S_TCB_AUX3_SLUSH 24 481 #define M_TCB_AUX3_SLUSH 0xffULL 482 #define V_TCB_AUX3_SLUSH(x) ((x) << S_TCB_AUX3_SLUSH) 483 484 /* 991:960 */ 485 #define W_TCB_RX_DDP_BUF0_TAG 30 486 #define S_TCB_RX_DDP_BUF0_TAG 0 487 #define M_TCB_RX_DDP_BUF0_TAG 0xffffffffULL 488 #define V_TCB_RX_DDP_BUF0_TAG(x) ((x) << S_TCB_RX_DDP_BUF0_TAG) 489 490 /* 1023:992 */ 491 #define W_TCB_RX_DDP_BUF1_TAG 31 492 #define S_TCB_RX_DDP_BUF1_TAG 0 493 #define M_TCB_RX_DDP_BUF1_TAG 0xffffffffULL 494 #define V_TCB_RX_DDP_BUF1_TAG(x) ((x) << S_TCB_RX_DDP_BUF1_TAG) 495 496 /* 855:832 */ 497 #define W_TCB_RX_TLS_BUF_OFFSET 26 498 #define S_TCB_RX_TLS_BUF_OFFSET 0 499 #define M_TCB_RX_TLS_BUF_OFFSET 0xffffffULL 500 #define V_TCB_RX_TLS_BUF_OFFSET(x) ((x) << S_TCB_RX_TLS_BUF_OFFSET) 501 502 /* 879:856 */ 503 #define W_TCB_RX_TLS_BUF_LEN 26 504 #define S_TCB_RX_TLS_BUF_LEN 24 505 #define M_TCB_RX_TLS_BUF_LEN 0xffffffULL 506 #define V_TCB_RX_TLS_BUF_LEN(x) ((__u64)(x) << S_TCB_RX_TLS_BUF_LEN) 507 508 /* 895:880 */ 509 #define W_TCB_RX_TLS_FLAGS 27 510 #define S_TCB_RX_TLS_FLAGS 16 511 #define M_TCB_RX_TLS_FLAGS 0xffffULL 512 #define V_TCB_RX_TLS_FLAGS(x) ((__u64)(x) << S_TCB_RX_TLS_FLAGS) 513 514 /* 959:896 */ 515 #define W_TCB_RX_TLS_SEQ 28 516 #define S_TCB_RX_TLS_SEQ 0 517 #define M_TCB_RX_TLS_SEQ 0xffffffffffffffffULL 518 #define V_TCB_RX_TLS_SEQ(x) ((__u64)(x) << S_TCB_RX_TLS_SEQ) 519 520 /* 991:960 */ 521 #define W_TCB_RX_TLS_BUF_TAG 30 522 #define S_TCB_RX_TLS_BUF_TAG 0 523 #define M_TCB_RX_TLS_BUF_TAG 0xffffffffULL 524 #define V_TCB_RX_TLS_BUF_TAG(x) ((x) << S_TCB_RX_TLS_BUF_TAG) 525 526 /* 1023:992 */ 527 #define W_TCB_RX_TLS_KEY_TAG 31 528 #define S_TCB_RX_TLS_KEY_TAG 0 529 #define M_TCB_RX_TLS_KEY_TAG 0xffffffffULL 530 #define V_TCB_RX_TLS_KEY_TAG(x) ((x) << S_TCB_RX_TLS_KEY_TAG) 531 532 #define S_TF_TLS_ENABLE 0 533 #define V_TF_TLS_ENABLE(x) ((x) << S_TF_TLS_ENABLE) 534 535 #define S_TF_TLS_ACTIVE 1 536 #define V_TF_TLS_ACTIVE(x) ((x) << S_TF_TLS_ACTIVE) 537 538 #define S_TF_TLS_CONTROL 2 539 #define V_TF_TLS_CONTROL(x) ((x) << S_TF_TLS_CONTROL) 540 541 #define S_TF_TLS_KEY_SIZE 7 542 #define V_TF_TLS_KEY_SIZE(x) ((x) << S_TF_TLS_KEY_SIZE) 543 544 /* 853:832 */ 545 #define W_TCB_TPT_OFFSET 26 546 #define S_TCB_TPT_OFFSET 0 547 #define M_TCB_TPT_OFFSET 0x3fffffULL 548 #define V_TCB_TPT_OFFSET(x) ((x) << S_TCB_TPT_OFFSET) 549 550 /* 863:854 */ 551 #define W_TCB_T10_CONFIG 26 552 #define S_TCB_T10_CONFIG 22 553 #define M_TCB_T10_CONFIG 0x3ffULL 554 #define V_TCB_T10_CONFIG(x) ((x) << S_TCB_T10_CONFIG) 555 556 /* 871:864 */ 557 #define W_TCB_PDU_HLEN 27 558 #define S_TCB_PDU_HLEN 0 559 #define M_TCB_PDU_HLEN 0xffULL 560 #define V_TCB_PDU_HLEN(x) ((x) << S_TCB_PDU_HLEN) 561 562 /* 879:872 */ 563 #define W_TCB_PDU_PDO 27 564 #define S_TCB_PDU_PDO 8 565 #define M_TCB_PDU_PDO 0xffULL 566 #define V_TCB_PDU_PDO(x) ((x) << S_TCB_PDU_PDO) 567 568 /* 895:880 */ 569 #define W_TCB_N_CQ_IDX_RQ 27 570 #define S_TCB_N_CQ_IDX_RQ 16 571 #define M_TCB_N_CQ_IDX_RQ 0xffffULL 572 #define V_TCB_N_CQ_IDX_RQ(x) ((x) << S_TCB_N_CQ_IDX_RQ) 573 574 /* 900:896 */ 575 #define W_TCB_NVMT_PDA 28 576 #define S_TCB_NVMT_PDA 0 577 #define M_TCB_NVMT_PDA 0x1fULL 578 #define V_TCB_NVMT_PDA(x) ((x) << S_TCB_NVMT_PDA) 579 580 /* 911:901 */ 581 #define W_TCB_RSVD 28 582 #define S_TCB_RSVD 5 583 #define M_TCB_RSVD 0x7ffULL 584 #define V_TCB_RSVD(x) ((x) << S_TCB_RSVD) 585 586 /* 927:912 */ 587 #define W_TCB_N_PD_ID 28 588 #define S_TCB_N_PD_ID 16 589 #define M_TCB_N_PD_ID 0xffffULL 590 #define V_TCB_N_PD_ID(x) ((x) << S_TCB_N_PD_ID) 591 592 /* 929:928 */ 593 #define W_TCB_CMP_IMM_SZ 29 594 #define S_TCB_CMP_IMM_SZ 0 595 #define M_TCB_CMP_IMM_SZ 0x3ULL 596 #define V_TCB_CMP_IMM_SZ(x) ((x) << S_TCB_CMP_IMM_SZ) 597 598 /* 931:930 */ 599 #define W_TCB_PDU_DGST_FLAGS 29 600 #define S_TCB_PDU_DGST_FLAGS 2 601 #define M_TCB_PDU_DGST_FLAGS 0x3ULL 602 #define V_TCB_PDU_DGST_FLAGS(x) ((x) << S_TCB_PDU_DGST_FLAGS) 603 604 /* 959:932 */ 605 #define W_TCB_RSVD1 29 606 #define S_TCB_RSVD1 4 607 #define M_TCB_RSVD1 0xfffffffULL 608 #define V_TCB_RSVD1(x) ((x) << S_TCB_RSVD1) 609 610 /* 985:960 */ 611 #define W_TCB_N_RQ_START 30 612 #define S_TCB_N_RQ_START 0 613 #define M_TCB_N_RQ_START 0x3ffffffULL 614 #define V_TCB_N_RQ_START(x) ((x) << S_TCB_N_RQ_START) 615 616 /* 998:986 */ 617 #define W_TCB_N_RQ_MSN 30 618 #define S_TCB_N_RQ_MSN 26 619 #define M_TCB_N_RQ_MSN 0x1fffULL 620 #define V_TCB_N_RQ_MSN(x) ((__u64)(x) << S_TCB_N_RQ_MSN) 621 622 /* 1002:999 */ 623 #define W_TCB_N_RQ_MAX_OFFSET 31 624 #define S_TCB_N_RQ_MAX_OFFSET 7 625 #define M_TCB_N_RQ_MAX_OFFSET 0xfULL 626 #define V_TCB_N_RQ_MAX_OFFSET(x) ((x) << S_TCB_N_RQ_MAX_OFFSET) 627 628 /* 1015:1003 */ 629 #define W_TCB_N_RQ_WRITE_PTR 31 630 #define S_TCB_N_RQ_WRITE_PTR 11 631 #define M_TCB_N_RQ_WRITE_PTR 0x1fffULL 632 #define V_TCB_N_RQ_WRITE_PTR(x) ((x) << S_TCB_N_RQ_WRITE_PTR) 633 634 /* 1023:1016 */ 635 #define W_TCB_N_PDU_TYPE 31 636 #define S_TCB_N_PDU_TYPE 24 637 #define M_TCB_N_PDU_TYPE 0xffULL 638 #define V_TCB_N_PDU_TYPE(x) ((x) << S_TCB_N_PDU_TYPE) 639 640 #define S_TF_MIGRATING 0 641 #define V_TF_MIGRATING(x) ((x) << S_TF_MIGRATING) 642 643 #define S_TF_NON_OFFLOAD 1 644 #define V_TF_NON_OFFLOAD(x) ((x) << S_TF_NON_OFFLOAD) 645 646 #define S_TF_FILTER 1 647 #define V_TF_FILTER(x) ((x) << S_TF_FILTER) 648 649 #define S_TF_LOCK_TID 2 650 #define V_TF_LOCK_TID(x) ((x) << S_TF_LOCK_TID) 651 652 #define S_TF_KEEPALIVE 3 653 #define V_TF_KEEPALIVE(x) ((x) << S_TF_KEEPALIVE) 654 655 #define S_TF_DROP_ENCAPS_HDR 3 656 #define V_TF_DROP_ENCAPS_HDR(x) ((x) << S_TF_DROP_ENCAPS_HDR) 657 658 #define S_TF_DACK 4 659 #define V_TF_DACK(x) ((x) << S_TF_DACK) 660 661 #define S_TF_COUNT_HITS 4 662 #define V_TF_COUNT_HITS(x) ((x) << S_TF_COUNT_HITS) 663 664 #define S_TF_DACK_MSS 5 665 #define V_TF_DACK_MSS(x) ((x) << S_TF_DACK_MSS) 666 667 #define S_TF_DACK_NOT_ACKED 6 668 #define V_TF_DACK_NOT_ACKED(x) ((x) << S_TF_DACK_NOT_ACKED) 669 670 #define S_TF_NAGLE 7 671 #define V_TF_NAGLE(x) ((x) << S_TF_NAGLE) 672 673 #define S_TF_REMOVE_VLAN 7 674 #define V_TF_REMOVE_VLAN(x) ((x) << S_TF_REMOVE_VLAN) 675 676 #define S_TF_SSWS_DISABLED 8 677 #define V_TF_SSWS_DISABLED(x) ((x) << S_TF_SSWS_DISABLED) 678 679 #define S_TF_RX_FLOW_CONTROL_DDP 9 680 #define V_TF_RX_FLOW_CONTROL_DDP(x) ((x) << S_TF_RX_FLOW_CONTROL_DDP) 681 682 #define S_TF_RX_FLOW_CONTROL_DISABLE 10 683 #define V_TF_RX_FLOW_CONTROL_DISABLE(x) ((x) << S_TF_RX_FLOW_CONTROL_DISABLE) 684 685 #define S_TF_NAT_SEQ_CHECK 10 686 #define V_TF_NAT_SEQ_CHECK(x) ((x) << S_TF_NAT_SEQ_CHECK) 687 688 #define S_TF_RX_CHANNEL 11 689 #define V_TF_RX_CHANNEL(x) ((x) << S_TF_RX_CHANNEL) 690 691 #define S_TF_TX_CHANNEL0 12 692 #define V_TF_TX_CHANNEL0(x) ((x) << S_TF_TX_CHANNEL0) 693 694 #define S_TF_LPBK_TX_CHANNEL0 12 695 #define V_TF_LPBK_TX_CHANNEL0(x) ((x) << S_TF_LPBK_TX_CHANNEL0) 696 697 #define S_TF_TX_CHANNEL1 13 698 #define V_TF_TX_CHANNEL1(x) ((x) << S_TF_TX_CHANNEL1) 699 700 #define S_TF_LPBK_TX_CHANNEL1 13 701 #define V_TF_LPBK_TX_CHANNEL1(x) ((x) << S_TF_LPBK_TX_CHANNEL1) 702 703 #define S_TF_TX_QUIESCE 14 704 #define V_TF_TX_QUIESCE(x) ((x) << S_TF_TX_QUIESCE) 705 706 #define S_TF_RX_QUIESCE 15 707 #define V_TF_RX_QUIESCE(x) ((x) << S_TF_RX_QUIESCE) 708 709 #define S_TF_TX_PACE_AUTO 16 710 #define V_TF_TX_PACE_AUTO(x) ((x) << S_TF_TX_PACE_AUTO) 711 712 #define S_TF_MASK_HASH 16 713 #define V_TF_MASK_HASH(x) ((x) << S_TF_MASK_HASH) 714 715 #define S_TF_TX_PACE_FIXED 17 716 #define V_TF_TX_PACE_FIXED(x) ((x) << S_TF_TX_PACE_FIXED) 717 718 #define S_TF_DIRECT_STEER_HASH 17 719 #define V_TF_DIRECT_STEER_HASH(x) ((x) << S_TF_DIRECT_STEER_HASH) 720 721 #define S_TF_TX_QUEUE 18 722 #define M_TF_TX_QUEUE 0x7ULL 723 #define V_TF_TX_QUEUE(x) ((x) << S_TF_TX_QUEUE) 724 725 #define S_TF_NAT_MODE 18 726 #define M_TF_NAT_MODE 0x7ULL 727 #define V_TF_NAT_MODE(x) ((x) << S_TF_NAT_MODE) 728 729 #define S_TF_TURBO 21 730 #define V_TF_TURBO(x) ((x) << S_TF_TURBO) 731 732 #define S_TF_REPORT_TID 21 733 #define V_TF_REPORT_TID(x) ((x) << S_TF_REPORT_TID) 734 735 #define S_TF_CCTRL_SEL0 22 736 #define V_TF_CCTRL_SEL0(x) ((x) << S_TF_CCTRL_SEL0) 737 738 #define S_TF_DROP 22 739 #define V_TF_DROP(x) ((x) << S_TF_DROP) 740 741 #define S_TF_CCTRL_SEL1 23 742 #define V_TF_CCTRL_SEL1(x) ((x) << S_TF_CCTRL_SEL1) 743 744 #define S_TF_DIRECT_STEER 23 745 #define V_TF_DIRECT_STEER(x) ((x) << S_TF_DIRECT_STEER) 746 747 #define S_TF_CORE_FIN 24 748 #define V_TF_CORE_FIN(x) ((x) << S_TF_CORE_FIN) 749 750 #define S_TF_CORE_URG 25 751 #define V_TF_CORE_URG(x) ((x) << S_TF_CORE_URG) 752 753 #define S_TF_CORE_MORE 26 754 #define V_TF_CORE_MORE(x) ((x) << S_TF_CORE_MORE) 755 756 #define S_TF_CORE_PUSH 27 757 #define V_TF_CORE_PUSH(x) ((x) << S_TF_CORE_PUSH) 758 759 #define S_TF_CORE_FLUSH 28 760 #define V_TF_CORE_FLUSH(x) ((x) << S_TF_CORE_FLUSH) 761 762 #define S_TF_RCV_COALESCE_ENABLE 29 763 #define V_TF_RCV_COALESCE_ENABLE(x) ((x) << S_TF_RCV_COALESCE_ENABLE) 764 765 #define S_TF_RCV_COALESCE_PUSH 30 766 #define V_TF_RCV_COALESCE_PUSH(x) ((x) << S_TF_RCV_COALESCE_PUSH) 767 768 #define S_TF_RCV_COALESCE_LAST_PSH 31 769 #define V_TF_RCV_COALESCE_LAST_PSH(x) ((x) << S_TF_RCV_COALESCE_LAST_PSH) 770 771 #define S_TF_RCV_COALESCE_HEARTBEAT 32 772 #define V_TF_RCV_COALESCE_HEARTBEAT(x) ((__u64)(x) << S_TF_RCV_COALESCE_HEARTBEAT) 773 774 #define S_TF_RSS_FW 33 775 #define V_TF_RSS_FW(x) ((__u64)(x) << S_TF_RSS_FW) 776 777 #define S_TF_ACTIVE_OPEN 34 778 #define V_TF_ACTIVE_OPEN(x) ((__u64)(x) << S_TF_ACTIVE_OPEN) 779 780 #define S_TF_ASK_MODE 35 781 #define V_TF_ASK_MODE(x) ((__u64)(x) << S_TF_ASK_MODE) 782 783 #define S_TF_MOD_SCHD_REASON0 36 784 #define V_TF_MOD_SCHD_REASON0(x) ((__u64)(x) << S_TF_MOD_SCHD_REASON0) 785 786 #define S_TF_MOD_SCHD_REASON1 37 787 #define V_TF_MOD_SCHD_REASON1(x) ((__u64)(x) << S_TF_MOD_SCHD_REASON1) 788 789 #define S_TF_MOD_SCHD_REASON2 38 790 #define V_TF_MOD_SCHD_REASON2(x) ((__u64)(x) << S_TF_MOD_SCHD_REASON2) 791 792 #define S_TF_MOD_SCHD_TX 39 793 #define V_TF_MOD_SCHD_TX(x) ((__u64)(x) << S_TF_MOD_SCHD_TX) 794 795 #define S_TF_MOD_SCHD_RX 40 796 #define V_TF_MOD_SCHD_RX(x) ((__u64)(x) << S_TF_MOD_SCHD_RX) 797 798 #define S_TF_TIMER 41 799 #define V_TF_TIMER(x) ((__u64)(x) << S_TF_TIMER) 800 801 #define S_TF_DACK_TIMER 42 802 #define V_TF_DACK_TIMER(x) ((__u64)(x) << S_TF_DACK_TIMER) 803 804 #define S_TF_PEER_FIN 43 805 #define V_TF_PEER_FIN(x) ((__u64)(x) << S_TF_PEER_FIN) 806 807 #define S_TF_TX_COMPACT 44 808 #define V_TF_TX_COMPACT(x) ((__u64)(x) << S_TF_TX_COMPACT) 809 810 #define S_TF_RX_COMPACT 45 811 #define V_TF_RX_COMPACT(x) ((__u64)(x) << S_TF_RX_COMPACT) 812 813 #define S_TF_RDMA_ERROR 46 814 #define V_TF_RDMA_ERROR(x) ((__u64)(x) << S_TF_RDMA_ERROR) 815 816 #define S_TF_RDMA_FLM_ERROR 47 817 #define V_TF_RDMA_FLM_ERROR(x) ((__u64)(x) << S_TF_RDMA_FLM_ERROR) 818 819 #define S_TF_TX_PDU_OUT 48 820 #define V_TF_TX_PDU_OUT(x) ((__u64)(x) << S_TF_TX_PDU_OUT) 821 822 #define S_TF_RX_PDU_OUT 49 823 #define V_TF_RX_PDU_OUT(x) ((__u64)(x) << S_TF_RX_PDU_OUT) 824 825 #define S_TF_DUPACK_COUNT_ODD 50 826 #define V_TF_DUPACK_COUNT_ODD(x) ((__u64)(x) << S_TF_DUPACK_COUNT_ODD) 827 828 #define S_TF_FAST_RECOVERY 51 829 #define V_TF_FAST_RECOVERY(x) ((__u64)(x) << S_TF_FAST_RECOVERY) 830 831 #define S_TF_RECV_SCALE 52 832 #define V_TF_RECV_SCALE(x) ((__u64)(x) << S_TF_RECV_SCALE) 833 834 #define S_TF_NAT_FLAG_CHECK 52 835 #define V_TF_NAT_FLAG_CHECK(x) ((__u64)(x) << S_TF_NAT_FLAG_CHECK) 836 837 #define S_TF_RECV_TSTMP 53 838 #define V_TF_RECV_TSTMP(x) ((__u64)(x) << S_TF_RECV_TSTMP) 839 840 #define S_TF_LPBK_TX_LPBK 53 841 #define V_TF_LPBK_TX_LPBK(x) ((__u64)(x) << S_TF_LPBK_TX_LPBK) 842 843 #define S_TF_RECV_SACK 54 844 #define V_TF_RECV_SACK(x) ((__u64)(x) << S_TF_RECV_SACK) 845 846 #define S_TF_SWAP_MAC_ADDR 54 847 #define V_TF_SWAP_MAC_ADDR(x) ((__u64)(x) << S_TF_SWAP_MAC_ADDR) 848 849 #define S_TF_PEND_CTL0 55 850 #define V_TF_PEND_CTL0(x) ((__u64)(x) << S_TF_PEND_CTL0) 851 852 #define S_TF_PEND_CTL1 56 853 #define V_TF_PEND_CTL1(x) ((__u64)(x) << S_TF_PEND_CTL1) 854 855 #define S_TF_PEND_CTL2 57 856 #define V_TF_PEND_CTL2(x) ((__u64)(x) << S_TF_PEND_CTL2) 857 858 #define S_TF_IP_VERSION 58 859 #define V_TF_IP_VERSION(x) ((__u64)(x) << S_TF_IP_VERSION) 860 861 #define S_TF_CCTRL_ECN 59 862 #define V_TF_CCTRL_ECN(x) ((__u64)(x) << S_TF_CCTRL_ECN) 863 864 #define S_TF_LPBK 59 865 #define V_TF_LPBK(x) ((__u64)(x) << S_TF_LPBK) 866 867 #define S_TF_CCTRL_ECE 60 868 #define V_TF_CCTRL_ECE(x) ((__u64)(x) << S_TF_CCTRL_ECE) 869 870 #define S_TF_REWRITE_DMAC 60 871 #define V_TF_REWRITE_DMAC(x) ((__u64)(x) << S_TF_REWRITE_DMAC) 872 873 #define S_TF_CCTRL_CWR 61 874 #define V_TF_CCTRL_CWR(x) ((__u64)(x) << S_TF_CCTRL_CWR) 875 876 #define S_TF_REWRITE_SMAC 61 877 #define V_TF_REWRITE_SMAC(x) ((__u64)(x) << S_TF_REWRITE_SMAC) 878 879 #define S_TF_CCTRL_RFR 62 880 #define V_TF_CCTRL_RFR(x) ((__u64)(x) << S_TF_CCTRL_RFR) 881 882 #define S_TF_INSERT_VLAN 62 883 #define V_TF_INSERT_VLAN(x) ((__u64)(x) << S_TF_INSERT_VLAN) 884 885 #define S_TF_CORE_BYPASS 63 886 #define V_TF_CORE_BYPASS(x) ((__u64)(x) << S_TF_CORE_BYPASS) 887 888 #define S_TF_DDP_INDICATE_OUT 16 889 #define V_TF_DDP_INDICATE_OUT(x) ((x) << S_TF_DDP_INDICATE_OUT) 890 891 #define S_TF_DDP_ACTIVE_BUF 17 892 #define V_TF_DDP_ACTIVE_BUF(x) ((x) << S_TF_DDP_ACTIVE_BUF) 893 894 #define S_TF_DDP_OFF 18 895 #define V_TF_DDP_OFF(x) ((x) << S_TF_DDP_OFF) 896 897 #define S_TF_DDP_WAIT_FRAG 19 898 #define V_TF_DDP_WAIT_FRAG(x) ((x) << S_TF_DDP_WAIT_FRAG) 899 900 #define S_TF_DDP_BUF_INF 20 901 #define V_TF_DDP_BUF_INF(x) ((x) << S_TF_DDP_BUF_INF) 902 903 #define S_TF_DDP_RX2TX 21 904 #define V_TF_DDP_RX2TX(x) ((x) << S_TF_DDP_RX2TX) 905 906 #define S_TF_DDP_INDICATE_FLL 22 907 #define V_TF_DDP_INDICATE_FLL(x) ((x) << S_TF_DDP_INDICATE_FLL) 908 909 #define S_TF_DDP_BUF0_VALID 24 910 #define V_TF_DDP_BUF0_VALID(x) ((x) << S_TF_DDP_BUF0_VALID) 911 912 #define S_TF_DDP_BUF0_INDICATE 25 913 #define V_TF_DDP_BUF0_INDICATE(x) ((x) << S_TF_DDP_BUF0_INDICATE) 914 915 #define S_TF_DDP_BUF0_FLUSH 26 916 #define V_TF_DDP_BUF0_FLUSH(x) ((x) << S_TF_DDP_BUF0_FLUSH) 917 918 #define S_TF_DDP_PSHF_ENABLE_0 27 919 #define V_TF_DDP_PSHF_ENABLE_0(x) ((x) << S_TF_DDP_PSHF_ENABLE_0) 920 921 #define S_TF_DDP_PUSH_DISABLE_0 28 922 #define V_TF_DDP_PUSH_DISABLE_0(x) ((x) << S_TF_DDP_PUSH_DISABLE_0) 923 924 #define S_TF_DDP_PSH_NO_INVALIDATE0 29 925 #define V_TF_DDP_PSH_NO_INVALIDATE0(x) ((x) << S_TF_DDP_PSH_NO_INVALIDATE0) 926 927 #define S_TF_DDP_BUF1_VALID 32 928 #define V_TF_DDP_BUF1_VALID(x) ((__u64)(x) << S_TF_DDP_BUF1_VALID) 929 930 #define S_TF_DDP_BUF1_INDICATE 33 931 #define V_TF_DDP_BUF1_INDICATE(x) ((__u64)(x) << S_TF_DDP_BUF1_INDICATE) 932 933 #define S_TF_DDP_BUF1_FLUSH 34 934 #define V_TF_DDP_BUF1_FLUSH(x) ((__u64)(x) << S_TF_DDP_BUF1_FLUSH) 935 936 #define S_TF_DDP_PSHF_ENABLE_1 35 937 #define V_TF_DDP_PSHF_ENABLE_1(x) ((__u64)(x) << S_TF_DDP_PSHF_ENABLE_1) 938 939 #define S_TF_DDP_PUSH_DISABLE_1 36 940 #define V_TF_DDP_PUSH_DISABLE_1(x) ((__u64)(x) << S_TF_DDP_PUSH_DISABLE_1) 941 942 #define S_TF_DDP_PSH_NO_INVALIDATE1 37 943 #define V_TF_DDP_PSH_NO_INVALIDATE1(x) ((__u64)(x) << S_TF_DDP_PSH_NO_INVALIDATE1) 944 945 #endif /* _T4_TCB_DEFS_H */ 946