xref: /linux/tools/arch/arm64/include/asm/sysreg.h (revision 43db1111073049220381944af4a3b8a5400eda71)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Macros for accessing system registers with older binutils.
4  *
5  * Copyright (C) 2014 ARM Ltd.
6  * Author: Catalin Marinas <catalin.marinas@arm.com>
7  */
8 
9 #ifndef __ASM_SYSREG_H
10 #define __ASM_SYSREG_H
11 
12 #include <linux/bits.h>
13 #include <linux/stringify.h>
14 #include <linux/kasan-tags.h>
15 
16 #include <asm/gpr-num.h>
17 
18 /*
19  * ARMv8 ARM reserves the following encoding for system registers:
20  * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
21  *  C5.2, version:ARM DDI 0487A.f)
22  *	[20-19] : Op0
23  *	[18-16] : Op1
24  *	[15-12] : CRn
25  *	[11-8]  : CRm
26  *	[7-5]   : Op2
27  */
28 #define Op0_shift	19
29 #define Op0_mask	0x3
30 #define Op1_shift	16
31 #define Op1_mask	0x7
32 #define CRn_shift	12
33 #define CRn_mask	0xf
34 #define CRm_shift	8
35 #define CRm_mask	0xf
36 #define Op2_shift	5
37 #define Op2_mask	0x7
38 
39 #define sys_reg(op0, op1, crn, crm, op2) \
40 	(((op0) << Op0_shift) | ((op1) << Op1_shift) | \
41 	 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
42 	 ((op2) << Op2_shift))
43 
44 #define sys_insn	sys_reg
45 
46 #define sys_reg_Op0(id)	(((id) >> Op0_shift) & Op0_mask)
47 #define sys_reg_Op1(id)	(((id) >> Op1_shift) & Op1_mask)
48 #define sys_reg_CRn(id)	(((id) >> CRn_shift) & CRn_mask)
49 #define sys_reg_CRm(id)	(((id) >> CRm_shift) & CRm_mask)
50 #define sys_reg_Op2(id)	(((id) >> Op2_shift) & Op2_mask)
51 
52 #ifndef CONFIG_BROKEN_GAS_INST
53 
54 #ifdef __ASSEMBLY__
55 // The space separator is omitted so that __emit_inst(x) can be parsed as
56 // either an assembler directive or an assembler macro argument.
57 #define __emit_inst(x)			.inst(x)
58 #else
59 #define __emit_inst(x)			".inst " __stringify((x)) "\n\t"
60 #endif
61 
62 #else  /* CONFIG_BROKEN_GAS_INST */
63 
64 #ifndef CONFIG_CPU_BIG_ENDIAN
65 #define __INSTR_BSWAP(x)		(x)
66 #else  /* CONFIG_CPU_BIG_ENDIAN */
67 #define __INSTR_BSWAP(x)		((((x) << 24) & 0xff000000)	| \
68 					 (((x) <<  8) & 0x00ff0000)	| \
69 					 (((x) >>  8) & 0x0000ff00)	| \
70 					 (((x) >> 24) & 0x000000ff))
71 #endif	/* CONFIG_CPU_BIG_ENDIAN */
72 
73 #ifdef __ASSEMBLY__
74 #define __emit_inst(x)			.long __INSTR_BSWAP(x)
75 #else  /* __ASSEMBLY__ */
76 #define __emit_inst(x)			".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
77 #endif	/* __ASSEMBLY__ */
78 
79 #endif	/* CONFIG_BROKEN_GAS_INST */
80 
81 /*
82  * Instructions for modifying PSTATE fields.
83  * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
84  * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
85  * for accessing PSTATE fields have the following encoding:
86  *	Op0 = 0, CRn = 4
87  *	Op1, Op2 encodes the PSTATE field modified and defines the constraints.
88  *	CRm = Imm4 for the instruction.
89  *	Rt = 0x1f
90  */
91 #define pstate_field(op1, op2)		((op1) << Op1_shift | (op2) << Op2_shift)
92 #define PSTATE_Imm_shift		CRm_shift
93 #define SET_PSTATE(x, r)		__emit_inst(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift))
94 
95 #define PSTATE_PAN			pstate_field(0, 4)
96 #define PSTATE_UAO			pstate_field(0, 3)
97 #define PSTATE_SSBS			pstate_field(3, 1)
98 #define PSTATE_DIT			pstate_field(3, 2)
99 #define PSTATE_TCO			pstate_field(3, 4)
100 
101 #define SET_PSTATE_PAN(x)		SET_PSTATE((x), PAN)
102 #define SET_PSTATE_UAO(x)		SET_PSTATE((x), UAO)
103 #define SET_PSTATE_SSBS(x)		SET_PSTATE((x), SSBS)
104 #define SET_PSTATE_DIT(x)		SET_PSTATE((x), DIT)
105 #define SET_PSTATE_TCO(x)		SET_PSTATE((x), TCO)
106 
107 #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
108 #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
109 #define set_pstate_ssbs(x)		asm volatile(SET_PSTATE_SSBS(x))
110 #define set_pstate_dit(x)		asm volatile(SET_PSTATE_DIT(x))
111 
112 /* Register-based PAN access, for save/restore purposes */
113 #define SYS_PSTATE_PAN			sys_reg(3, 0, 4, 2, 3)
114 
115 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \
116 	__emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
117 
118 #define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 7, 31)
119 
120 /* Data cache zero operations */
121 #define SYS_DC_ISW			sys_insn(1, 0, 7, 6, 2)
122 #define SYS_DC_IGSW			sys_insn(1, 0, 7, 6, 4)
123 #define SYS_DC_IGDSW			sys_insn(1, 0, 7, 6, 6)
124 #define SYS_DC_CSW			sys_insn(1, 0, 7, 10, 2)
125 #define SYS_DC_CGSW			sys_insn(1, 0, 7, 10, 4)
126 #define SYS_DC_CGDSW			sys_insn(1, 0, 7, 10, 6)
127 #define SYS_DC_CISW			sys_insn(1, 0, 7, 14, 2)
128 #define SYS_DC_CIGSW			sys_insn(1, 0, 7, 14, 4)
129 #define SYS_DC_CIGDSW			sys_insn(1, 0, 7, 14, 6)
130 
131 #define SYS_IC_IALLUIS			sys_insn(1, 0, 7, 1, 0)
132 #define SYS_IC_IALLU			sys_insn(1, 0, 7, 5, 0)
133 #define SYS_IC_IVAU			sys_insn(1, 3, 7, 5, 1)
134 
135 #define SYS_DC_IVAC			sys_insn(1, 0, 7, 6, 1)
136 #define SYS_DC_IGVAC			sys_insn(1, 0, 7, 6, 3)
137 #define SYS_DC_IGDVAC			sys_insn(1, 0, 7, 6, 5)
138 
139 #define SYS_DC_CVAC			sys_insn(1, 3, 7, 10, 1)
140 #define SYS_DC_CGVAC			sys_insn(1, 3, 7, 10, 3)
141 #define SYS_DC_CGDVAC			sys_insn(1, 3, 7, 10, 5)
142 
143 #define SYS_DC_CVAU			sys_insn(1, 3, 7, 11, 1)
144 
145 #define SYS_DC_CVAP			sys_insn(1, 3, 7, 12, 1)
146 #define SYS_DC_CGVAP			sys_insn(1, 3, 7, 12, 3)
147 #define SYS_DC_CGDVAP			sys_insn(1, 3, 7, 12, 5)
148 
149 #define SYS_DC_CVADP			sys_insn(1, 3, 7, 13, 1)
150 #define SYS_DC_CGVADP			sys_insn(1, 3, 7, 13, 3)
151 #define SYS_DC_CGDVADP			sys_insn(1, 3, 7, 13, 5)
152 
153 #define SYS_DC_CIVAC			sys_insn(1, 3, 7, 14, 1)
154 #define SYS_DC_CIGVAC			sys_insn(1, 3, 7, 14, 3)
155 #define SYS_DC_CIGDVAC			sys_insn(1, 3, 7, 14, 5)
156 
157 #define SYS_DC_ZVA			sys_insn(1, 3, 7, 4, 1)
158 #define SYS_DC_GVA			sys_insn(1, 3, 7, 4, 3)
159 #define SYS_DC_GZVA			sys_insn(1, 3, 7, 4, 4)
160 
161 #define SYS_DC_CIVAPS			sys_insn(1, 0, 7, 15, 1)
162 #define SYS_DC_CIGDVAPS			sys_insn(1, 0, 7, 15, 5)
163 
164 /*
165  * Automatically generated definitions for system registers, the
166  * manual encodings below are in the process of being converted to
167  * come from here. The header relies on the definition of sys_reg()
168  * earlier in this file.
169  */
170 #include "asm/sysreg-defs.h"
171 
172 /*
173  * System registers, organised loosely by encoding but grouped together
174  * where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
175  */
176 #define SYS_SVCR_SMSTOP_SM_EL0		sys_reg(0, 3, 4, 2, 3)
177 #define SYS_SVCR_SMSTART_SM_EL0		sys_reg(0, 3, 4, 3, 3)
178 #define SYS_SVCR_SMSTOP_SMZA_EL0	sys_reg(0, 3, 4, 6, 3)
179 
180 #define SYS_DBGBVRn_EL1(n)		sys_reg(2, 0, 0, n, 4)
181 #define SYS_DBGBCRn_EL1(n)		sys_reg(2, 0, 0, n, 5)
182 #define SYS_DBGWVRn_EL1(n)		sys_reg(2, 0, 0, n, 6)
183 #define SYS_DBGWCRn_EL1(n)		sys_reg(2, 0, 0, n, 7)
184 #define SYS_MDRAR_EL1			sys_reg(2, 0, 1, 0, 0)
185 
186 #define SYS_OSLSR_EL1			sys_reg(2, 0, 1, 1, 4)
187 #define OSLSR_EL1_OSLM_MASK		(BIT(3) | BIT(0))
188 #define OSLSR_EL1_OSLM_NI		0
189 #define OSLSR_EL1_OSLM_IMPLEMENTED	BIT(3)
190 #define OSLSR_EL1_OSLK			BIT(1)
191 
192 #define SYS_OSDLR_EL1			sys_reg(2, 0, 1, 3, 4)
193 #define SYS_DBGPRCR_EL1			sys_reg(2, 0, 1, 4, 4)
194 #define SYS_DBGCLAIMSET_EL1		sys_reg(2, 0, 7, 8, 6)
195 #define SYS_DBGCLAIMCLR_EL1		sys_reg(2, 0, 7, 9, 6)
196 #define SYS_DBGAUTHSTATUS_EL1		sys_reg(2, 0, 7, 14, 6)
197 #define SYS_MDCCSR_EL0			sys_reg(2, 3, 0, 1, 0)
198 #define SYS_DBGDTR_EL0			sys_reg(2, 3, 0, 4, 0)
199 #define SYS_DBGDTRRX_EL0		sys_reg(2, 3, 0, 5, 0)
200 #define SYS_DBGDTRTX_EL0		sys_reg(2, 3, 0, 5, 0)
201 #define SYS_DBGVCR32_EL2		sys_reg(2, 4, 0, 7, 0)
202 
203 #define SYS_BRBINF_EL1(n)		sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
204 #define SYS_BRBINFINJ_EL1		sys_reg(2, 1, 9, 1, 0)
205 #define SYS_BRBSRC_EL1(n)		sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
206 #define SYS_BRBSRCINJ_EL1		sys_reg(2, 1, 9, 1, 1)
207 #define SYS_BRBTGT_EL1(n)		sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
208 #define SYS_BRBTGTINJ_EL1		sys_reg(2, 1, 9, 1, 2)
209 #define SYS_BRBTS_EL1			sys_reg(2, 1, 9, 0, 2)
210 
211 #define SYS_BRBCR_EL1			sys_reg(2, 1, 9, 0, 0)
212 #define SYS_BRBFCR_EL1			sys_reg(2, 1, 9, 0, 1)
213 #define SYS_BRBIDR0_EL1			sys_reg(2, 1, 9, 2, 0)
214 
215 #define SYS_TRCITECR_EL1		sys_reg(3, 0, 1, 2, 3)
216 #define SYS_TRCACATR(m)			sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
217 #define SYS_TRCACVR(m)			sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
218 #define SYS_TRCAUTHSTATUS		sys_reg(2, 1, 7, 14, 6)
219 #define SYS_TRCAUXCTLR			sys_reg(2, 1, 0, 6, 0)
220 #define SYS_TRCBBCTLR			sys_reg(2, 1, 0, 15, 0)
221 #define SYS_TRCCCCTLR			sys_reg(2, 1, 0, 14, 0)
222 #define SYS_TRCCIDCCTLR0		sys_reg(2, 1, 3, 0, 2)
223 #define SYS_TRCCIDCCTLR1		sys_reg(2, 1, 3, 1, 2)
224 #define SYS_TRCCIDCVR(m)		sys_reg(2, 1, 3, ((m & 7) << 1), 0)
225 #define SYS_TRCCLAIMCLR			sys_reg(2, 1, 7, 9, 6)
226 #define SYS_TRCCLAIMSET			sys_reg(2, 1, 7, 8, 6)
227 #define SYS_TRCCNTCTLR(m)		sys_reg(2, 1, 0, (4 | (m & 3)), 5)
228 #define SYS_TRCCNTRLDVR(m)		sys_reg(2, 1, 0, (0 | (m & 3)), 5)
229 #define SYS_TRCCNTVR(m)			sys_reg(2, 1, 0, (8 | (m & 3)), 5)
230 #define SYS_TRCCONFIGR			sys_reg(2, 1, 0, 4, 0)
231 #define SYS_TRCDEVARCH			sys_reg(2, 1, 7, 15, 6)
232 #define SYS_TRCDEVID			sys_reg(2, 1, 7, 2, 7)
233 #define SYS_TRCEVENTCTL0R		sys_reg(2, 1, 0, 8, 0)
234 #define SYS_TRCEVENTCTL1R		sys_reg(2, 1, 0, 9, 0)
235 #define SYS_TRCEXTINSELR(m)		sys_reg(2, 1, 0, (8 | (m & 3)), 4)
236 #define SYS_TRCIDR0			sys_reg(2, 1, 0, 8, 7)
237 #define SYS_TRCIDR10			sys_reg(2, 1, 0, 2, 6)
238 #define SYS_TRCIDR11			sys_reg(2, 1, 0, 3, 6)
239 #define SYS_TRCIDR12			sys_reg(2, 1, 0, 4, 6)
240 #define SYS_TRCIDR13			sys_reg(2, 1, 0, 5, 6)
241 #define SYS_TRCIDR1			sys_reg(2, 1, 0, 9, 7)
242 #define SYS_TRCIDR2			sys_reg(2, 1, 0, 10, 7)
243 #define SYS_TRCIDR3			sys_reg(2, 1, 0, 11, 7)
244 #define SYS_TRCIDR4			sys_reg(2, 1, 0, 12, 7)
245 #define SYS_TRCIDR5			sys_reg(2, 1, 0, 13, 7)
246 #define SYS_TRCIDR6			sys_reg(2, 1, 0, 14, 7)
247 #define SYS_TRCIDR7			sys_reg(2, 1, 0, 15, 7)
248 #define SYS_TRCIDR8			sys_reg(2, 1, 0, 0, 6)
249 #define SYS_TRCIDR9			sys_reg(2, 1, 0, 1, 6)
250 #define SYS_TRCIMSPEC(m)		sys_reg(2, 1, 0, (m & 7), 7)
251 #define SYS_TRCITEEDCR			sys_reg(2, 1, 0, 2, 1)
252 #define SYS_TRCOSLSR			sys_reg(2, 1, 1, 1, 4)
253 #define SYS_TRCPRGCTLR			sys_reg(2, 1, 0, 1, 0)
254 #define SYS_TRCQCTLR			sys_reg(2, 1, 0, 1, 1)
255 #define SYS_TRCRSCTLR(m)		sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))
256 #define SYS_TRCRSR			sys_reg(2, 1, 0, 10, 0)
257 #define SYS_TRCSEQEVR(m)		sys_reg(2, 1, 0, (m & 3), 4)
258 #define SYS_TRCSEQRSTEVR		sys_reg(2, 1, 0, 6, 4)
259 #define SYS_TRCSEQSTR			sys_reg(2, 1, 0, 7, 4)
260 #define SYS_TRCSSCCR(m)			sys_reg(2, 1, 1, (m & 7), 2)
261 #define SYS_TRCSSCSR(m)			sys_reg(2, 1, 1, (8 | (m & 7)), 2)
262 #define SYS_TRCSSPCICR(m)		sys_reg(2, 1, 1, (m & 7), 3)
263 #define SYS_TRCSTALLCTLR		sys_reg(2, 1, 0, 11, 0)
264 #define SYS_TRCSTATR			sys_reg(2, 1, 0, 3, 0)
265 #define SYS_TRCSYNCPR			sys_reg(2, 1, 0, 13, 0)
266 #define SYS_TRCTRACEIDR			sys_reg(2, 1, 0, 0, 1)
267 #define SYS_TRCTSCTLR			sys_reg(2, 1, 0, 12, 0)
268 #define SYS_TRCVICTLR			sys_reg(2, 1, 0, 0, 2)
269 #define SYS_TRCVIIECTLR			sys_reg(2, 1, 0, 1, 2)
270 #define SYS_TRCVIPCSSCTLR		sys_reg(2, 1, 0, 3, 2)
271 #define SYS_TRCVISSCTLR			sys_reg(2, 1, 0, 2, 2)
272 #define SYS_TRCVMIDCCTLR0		sys_reg(2, 1, 3, 2, 2)
273 #define SYS_TRCVMIDCCTLR1		sys_reg(2, 1, 3, 3, 2)
274 #define SYS_TRCVMIDCVR(m)		sys_reg(2, 1, 3, ((m & 7) << 1), 1)
275 
276 /* ETM */
277 #define SYS_TRCOSLAR			sys_reg(2, 1, 1, 0, 4)
278 
279 #define SYS_BRBCR_EL2			sys_reg(2, 4, 9, 0, 0)
280 
281 #define SYS_MIDR_EL1			sys_reg(3, 0, 0, 0, 0)
282 #define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)
283 #define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)
284 
285 #define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
286 #define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
287 #define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)
288 
289 #define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
290 
291 #define SYS_APIAKEYLO_EL1		sys_reg(3, 0, 2, 1, 0)
292 #define SYS_APIAKEYHI_EL1		sys_reg(3, 0, 2, 1, 1)
293 #define SYS_APIBKEYLO_EL1		sys_reg(3, 0, 2, 1, 2)
294 #define SYS_APIBKEYHI_EL1		sys_reg(3, 0, 2, 1, 3)
295 
296 #define SYS_APDAKEYLO_EL1		sys_reg(3, 0, 2, 2, 0)
297 #define SYS_APDAKEYHI_EL1		sys_reg(3, 0, 2, 2, 1)
298 #define SYS_APDBKEYLO_EL1		sys_reg(3, 0, 2, 2, 2)
299 #define SYS_APDBKEYHI_EL1		sys_reg(3, 0, 2, 2, 3)
300 
301 #define SYS_APGAKEYLO_EL1		sys_reg(3, 0, 2, 3, 0)
302 #define SYS_APGAKEYHI_EL1		sys_reg(3, 0, 2, 3, 1)
303 
304 #define SYS_SPSR_EL1			sys_reg(3, 0, 4, 0, 0)
305 #define SYS_ELR_EL1			sys_reg(3, 0, 4, 0, 1)
306 
307 #define SYS_ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
308 
309 #define SYS_AFSR0_EL1			sys_reg(3, 0, 5, 1, 0)
310 #define SYS_AFSR1_EL1			sys_reg(3, 0, 5, 1, 1)
311 #define SYS_ESR_EL1			sys_reg(3, 0, 5, 2, 0)
312 
313 #define SYS_ERRIDR_EL1			sys_reg(3, 0, 5, 3, 0)
314 #define SYS_ERRSELR_EL1			sys_reg(3, 0, 5, 3, 1)
315 #define SYS_ERXFR_EL1			sys_reg(3, 0, 5, 4, 0)
316 #define SYS_ERXCTLR_EL1			sys_reg(3, 0, 5, 4, 1)
317 #define SYS_ERXSTATUS_EL1		sys_reg(3, 0, 5, 4, 2)
318 #define SYS_ERXADDR_EL1			sys_reg(3, 0, 5, 4, 3)
319 #define SYS_ERXPFGF_EL1			sys_reg(3, 0, 5, 4, 4)
320 #define SYS_ERXPFGCTL_EL1		sys_reg(3, 0, 5, 4, 5)
321 #define SYS_ERXPFGCDN_EL1		sys_reg(3, 0, 5, 4, 6)
322 #define SYS_ERXMISC0_EL1		sys_reg(3, 0, 5, 5, 0)
323 #define SYS_ERXMISC1_EL1		sys_reg(3, 0, 5, 5, 1)
324 #define SYS_ERXMISC2_EL1		sys_reg(3, 0, 5, 5, 2)
325 #define SYS_ERXMISC3_EL1		sys_reg(3, 0, 5, 5, 3)
326 #define SYS_TFSR_EL1			sys_reg(3, 0, 5, 6, 0)
327 #define SYS_TFSRE0_EL1			sys_reg(3, 0, 5, 6, 1)
328 
329 #define SYS_PAR_EL1			sys_reg(3, 0, 7, 4, 0)
330 
331 #define SYS_PAR_EL1_F			BIT(0)
332 /* When PAR_EL1.F == 1 */
333 #define SYS_PAR_EL1_FST			GENMASK(6, 1)
334 #define SYS_PAR_EL1_PTW			BIT(8)
335 #define SYS_PAR_EL1_S			BIT(9)
336 #define SYS_PAR_EL1_AssuredOnly		BIT(12)
337 #define SYS_PAR_EL1_TopLevel		BIT(13)
338 #define SYS_PAR_EL1_Overlay		BIT(14)
339 #define SYS_PAR_EL1_DirtyBit		BIT(15)
340 #define SYS_PAR_EL1_F1_IMPDEF		GENMASK_ULL(63, 48)
341 #define SYS_PAR_EL1_F1_RES0		(BIT(7) | BIT(10) | GENMASK_ULL(47, 16))
342 #define SYS_PAR_EL1_RES1		BIT(11)
343 /* When PAR_EL1.F == 0 */
344 #define SYS_PAR_EL1_SH			GENMASK_ULL(8, 7)
345 #define SYS_PAR_EL1_NS			BIT(9)
346 #define SYS_PAR_EL1_F0_IMPDEF		BIT(10)
347 #define SYS_PAR_EL1_NSE			BIT(11)
348 #define SYS_PAR_EL1_PA			GENMASK_ULL(51, 12)
349 #define SYS_PAR_EL1_ATTR		GENMASK_ULL(63, 56)
350 #define SYS_PAR_EL1_F0_RES0		(GENMASK_ULL(6, 1) | GENMASK_ULL(55, 52))
351 
352 /*** Statistical Profiling Extension ***/
353 #define PMSEVFR_EL1_RES0_IMP	\
354 	(GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
355 	 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
356 #define PMSEVFR_EL1_RES0_V1P1	\
357 	(PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
358 #define PMSEVFR_EL1_RES0_V1P2	\
359 	(PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6))
360 
361 /* Buffer error reporting */
362 #define PMBSR_EL1_FAULT_FSC_SHIFT	PMBSR_EL1_MSS_SHIFT
363 #define PMBSR_EL1_FAULT_FSC_MASK	PMBSR_EL1_MSS_MASK
364 
365 #define PMBSR_EL1_BUF_BSC_SHIFT		PMBSR_EL1_MSS_SHIFT
366 #define PMBSR_EL1_BUF_BSC_MASK		PMBSR_EL1_MSS_MASK
367 
368 #define PMBSR_EL1_BUF_BSC_FULL		0x1UL
369 
370 /*** End of Statistical Profiling Extension ***/
371 
372 #define TRBSR_EL1_BSC_MASK		GENMASK(5, 0)
373 #define TRBSR_EL1_BSC_SHIFT		0
374 
375 #define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
376 #define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
377 
378 #define SYS_PMMIR_EL1			sys_reg(3, 0, 9, 14, 6)
379 
380 #define SYS_MAIR_EL1			sys_reg(3, 0, 10, 2, 0)
381 #define SYS_AMAIR_EL1			sys_reg(3, 0, 10, 3, 0)
382 
383 #define SYS_VBAR_EL1			sys_reg(3, 0, 12, 0, 0)
384 #define SYS_DISR_EL1			sys_reg(3, 0, 12, 1, 1)
385 
386 #define SYS_ICC_IAR0_EL1		sys_reg(3, 0, 12, 8, 0)
387 #define SYS_ICC_EOIR0_EL1		sys_reg(3, 0, 12, 8, 1)
388 #define SYS_ICC_HPPIR0_EL1		sys_reg(3, 0, 12, 8, 2)
389 #define SYS_ICC_BPR0_EL1		sys_reg(3, 0, 12, 8, 3)
390 #define SYS_ICC_AP0Rn_EL1(n)		sys_reg(3, 0, 12, 8, 4 | n)
391 #define SYS_ICC_AP0R0_EL1		SYS_ICC_AP0Rn_EL1(0)
392 #define SYS_ICC_AP0R1_EL1		SYS_ICC_AP0Rn_EL1(1)
393 #define SYS_ICC_AP0R2_EL1		SYS_ICC_AP0Rn_EL1(2)
394 #define SYS_ICC_AP0R3_EL1		SYS_ICC_AP0Rn_EL1(3)
395 #define SYS_ICC_AP1Rn_EL1(n)		sys_reg(3, 0, 12, 9, n)
396 #define SYS_ICC_AP1R0_EL1		SYS_ICC_AP1Rn_EL1(0)
397 #define SYS_ICC_AP1R1_EL1		SYS_ICC_AP1Rn_EL1(1)
398 #define SYS_ICC_AP1R2_EL1		SYS_ICC_AP1Rn_EL1(2)
399 #define SYS_ICC_AP1R3_EL1		SYS_ICC_AP1Rn_EL1(3)
400 #define SYS_ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
401 #define SYS_ICC_RPR_EL1			sys_reg(3, 0, 12, 11, 3)
402 #define SYS_ICC_SGI1R_EL1		sys_reg(3, 0, 12, 11, 5)
403 #define SYS_ICC_ASGI1R_EL1		sys_reg(3, 0, 12, 11, 6)
404 #define SYS_ICC_SGI0R_EL1		sys_reg(3, 0, 12, 11, 7)
405 #define SYS_ICC_IAR1_EL1		sys_reg(3, 0, 12, 12, 0)
406 #define SYS_ICC_EOIR1_EL1		sys_reg(3, 0, 12, 12, 1)
407 #define SYS_ICC_HPPIR1_EL1		sys_reg(3, 0, 12, 12, 2)
408 #define SYS_ICC_BPR1_EL1		sys_reg(3, 0, 12, 12, 3)
409 #define SYS_ICC_CTLR_EL1		sys_reg(3, 0, 12, 12, 4)
410 #define SYS_ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
411 #define SYS_ICC_IGRPEN0_EL1		sys_reg(3, 0, 12, 12, 6)
412 #define SYS_ICC_IGRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)
413 
414 #define SYS_ACCDATA_EL1			sys_reg(3, 0, 13, 0, 5)
415 
416 #define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)
417 
418 #define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
419 
420 #define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
421 #define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
422 
423 #define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
424 #define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)
425 #define SYS_PMCNTENCLR_EL0		sys_reg(3, 3, 9, 12, 2)
426 #define SYS_PMOVSCLR_EL0		sys_reg(3, 3, 9, 12, 3)
427 #define SYS_PMSWINC_EL0			sys_reg(3, 3, 9, 12, 4)
428 #define SYS_PMCEID0_EL0			sys_reg(3, 3, 9, 12, 6)
429 #define SYS_PMCEID1_EL0			sys_reg(3, 3, 9, 12, 7)
430 #define SYS_PMCCNTR_EL0			sys_reg(3, 3, 9, 13, 0)
431 #define SYS_PMXEVTYPER_EL0		sys_reg(3, 3, 9, 13, 1)
432 #define SYS_PMXEVCNTR_EL0		sys_reg(3, 3, 9, 13, 2)
433 #define SYS_PMUSERENR_EL0		sys_reg(3, 3, 9, 14, 0)
434 #define SYS_PMOVSSET_EL0		sys_reg(3, 3, 9, 14, 3)
435 
436 #define SYS_TPIDR_EL0			sys_reg(3, 3, 13, 0, 2)
437 #define SYS_TPIDRRO_EL0			sys_reg(3, 3, 13, 0, 3)
438 #define SYS_TPIDR2_EL0			sys_reg(3, 3, 13, 0, 5)
439 
440 #define SYS_SCXTNUM_EL0			sys_reg(3, 3, 13, 0, 7)
441 
442 /* Definitions for system register interface to AMU for ARMv8.4 onwards */
443 #define SYS_AM_EL0(crm, op2)		sys_reg(3, 3, 13, (crm), (op2))
444 #define SYS_AMCR_EL0			SYS_AM_EL0(2, 0)
445 #define SYS_AMCFGR_EL0			SYS_AM_EL0(2, 1)
446 #define SYS_AMCGCR_EL0			SYS_AM_EL0(2, 2)
447 #define SYS_AMUSERENR_EL0		SYS_AM_EL0(2, 3)
448 #define SYS_AMCNTENCLR0_EL0		SYS_AM_EL0(2, 4)
449 #define SYS_AMCNTENSET0_EL0		SYS_AM_EL0(2, 5)
450 #define SYS_AMCNTENCLR1_EL0		SYS_AM_EL0(3, 0)
451 #define SYS_AMCNTENSET1_EL0		SYS_AM_EL0(3, 1)
452 
453 /*
454  * Group 0 of activity monitors (architected):
455  *                op0  op1  CRn   CRm       op2
456  * Counter:       11   011  1101  010:n<3>  n<2:0>
457  * Type:          11   011  1101  011:n<3>  n<2:0>
458  * n: 0-15
459  *
460  * Group 1 of activity monitors (auxiliary):
461  *                op0  op1  CRn   CRm       op2
462  * Counter:       11   011  1101  110:n<3>  n<2:0>
463  * Type:          11   011  1101  111:n<3>  n<2:0>
464  * n: 0-15
465  */
466 
467 #define SYS_AMEVCNTR0_EL0(n)		SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
468 #define SYS_AMEVTYPER0_EL0(n)		SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
469 #define SYS_AMEVCNTR1_EL0(n)		SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
470 #define SYS_AMEVTYPER1_EL0(n)		SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
471 
472 /* AMU v1: Fixed (architecturally defined) activity monitors */
473 #define SYS_AMEVCNTR0_CORE_EL0		SYS_AMEVCNTR0_EL0(0)
474 #define SYS_AMEVCNTR0_CONST_EL0		SYS_AMEVCNTR0_EL0(1)
475 #define SYS_AMEVCNTR0_INST_RET_EL0	SYS_AMEVCNTR0_EL0(2)
476 #define SYS_AMEVCNTR0_MEM_STALL		SYS_AMEVCNTR0_EL0(3)
477 
478 #define SYS_CNTFRQ_EL0			sys_reg(3, 3, 14, 0, 0)
479 
480 #define SYS_CNTPCT_EL0			sys_reg(3, 3, 14, 0, 1)
481 #define SYS_CNTVCT_EL0			sys_reg(3, 3, 14, 0, 2)
482 #define SYS_CNTPCTSS_EL0		sys_reg(3, 3, 14, 0, 5)
483 #define SYS_CNTVCTSS_EL0		sys_reg(3, 3, 14, 0, 6)
484 
485 #define SYS_CNTP_TVAL_EL0		sys_reg(3, 3, 14, 2, 0)
486 #define SYS_CNTP_CTL_EL0		sys_reg(3, 3, 14, 2, 1)
487 #define SYS_CNTP_CVAL_EL0		sys_reg(3, 3, 14, 2, 2)
488 
489 #define SYS_CNTV_TVAL_EL0		sys_reg(3, 3, 14, 3, 0)
490 #define SYS_CNTV_CTL_EL0		sys_reg(3, 3, 14, 3, 1)
491 #define SYS_CNTV_CVAL_EL0		sys_reg(3, 3, 14, 3, 2)
492 
493 #define SYS_AARCH32_CNTP_TVAL		sys_reg(0, 0, 14, 2, 0)
494 #define SYS_AARCH32_CNTP_CTL		sys_reg(0, 0, 14, 2, 1)
495 #define SYS_AARCH32_CNTPCT		sys_reg(0, 0, 0, 14, 0)
496 #define SYS_AARCH32_CNTVCT		sys_reg(0, 1, 0, 14, 0)
497 #define SYS_AARCH32_CNTP_CVAL		sys_reg(0, 2, 0, 14, 0)
498 #define SYS_AARCH32_CNTPCTSS		sys_reg(0, 8, 0, 14, 0)
499 #define SYS_AARCH32_CNTVCTSS		sys_reg(0, 9, 0, 14, 0)
500 
501 #define __PMEV_op2(n)			((n) & 0x7)
502 #define __CNTR_CRm(n)			(0x8 | (((n) >> 3) & 0x3))
503 #define SYS_PMEVCNTSVRn_EL1(n)		sys_reg(2, 0, 14, __CNTR_CRm(n), __PMEV_op2(n))
504 #define SYS_PMEVCNTRn_EL0(n)		sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
505 #define __TYPER_CRm(n)			(0xc | (((n) >> 3) & 0x3))
506 #define SYS_PMEVTYPERn_EL0(n)		sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
507 
508 #define SYS_PMCCFILTR_EL0		sys_reg(3, 3, 14, 15, 7)
509 
510 #define	SYS_SPMCGCRn_EL1(n)		sys_reg(2, 0, 9, 13, ((n) & 1))
511 
512 #define __SPMEV_op2(n)			((n) & 0x7)
513 #define __SPMEV_crm(p, n)		((((p) & 7) << 1) | (((n) >> 3) & 1))
514 #define SYS_SPMEVCNTRn_EL0(n)		sys_reg(2, 3, 14, __SPMEV_crm(0b000, n), __SPMEV_op2(n))
515 #define	SYS_SPMEVFILT2Rn_EL0(n)		sys_reg(2, 3, 14, __SPMEV_crm(0b011, n), __SPMEV_op2(n))
516 #define	SYS_SPMEVFILTRn_EL0(n)		sys_reg(2, 3, 14, __SPMEV_crm(0b010, n), __SPMEV_op2(n))
517 #define	SYS_SPMEVTYPERn_EL0(n)		sys_reg(2, 3, 14, __SPMEV_crm(0b001, n), __SPMEV_op2(n))
518 
519 #define SYS_VPIDR_EL2			sys_reg(3, 4, 0, 0, 0)
520 #define SYS_VMPIDR_EL2			sys_reg(3, 4, 0, 0, 5)
521 
522 #define SYS_SCTLR_EL2			sys_reg(3, 4, 1, 0, 0)
523 #define SYS_ACTLR_EL2			sys_reg(3, 4, 1, 0, 1)
524 #define SYS_SCTLR2_EL2			sys_reg(3, 4, 1, 0, 3)
525 #define SYS_HCR_EL2			sys_reg(3, 4, 1, 1, 0)
526 #define SYS_MDCR_EL2			sys_reg(3, 4, 1, 1, 1)
527 #define SYS_CPTR_EL2			sys_reg(3, 4, 1, 1, 2)
528 #define SYS_HSTR_EL2			sys_reg(3, 4, 1, 1, 3)
529 #define SYS_HACR_EL2			sys_reg(3, 4, 1, 1, 7)
530 
531 #define SYS_TTBR0_EL2			sys_reg(3, 4, 2, 0, 0)
532 #define SYS_TTBR1_EL2			sys_reg(3, 4, 2, 0, 1)
533 #define SYS_TCR_EL2			sys_reg(3, 4, 2, 0, 2)
534 #define SYS_VTTBR_EL2			sys_reg(3, 4, 2, 1, 0)
535 #define SYS_VTCR_EL2			sys_reg(3, 4, 2, 1, 2)
536 
537 #define SYS_VNCR_EL2			sys_reg(3, 4, 2, 2, 0)
538 #define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)
539 #define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
540 #define SYS_SP_EL1			sys_reg(3, 4, 4, 1, 0)
541 #define SYS_SPSR_irq			sys_reg(3, 4, 4, 3, 0)
542 #define SYS_SPSR_abt			sys_reg(3, 4, 4, 3, 1)
543 #define SYS_SPSR_und			sys_reg(3, 4, 4, 3, 2)
544 #define SYS_SPSR_fiq			sys_reg(3, 4, 4, 3, 3)
545 #define SYS_IFSR32_EL2			sys_reg(3, 4, 5, 0, 1)
546 #define SYS_AFSR0_EL2			sys_reg(3, 4, 5, 1, 0)
547 #define SYS_AFSR1_EL2			sys_reg(3, 4, 5, 1, 1)
548 #define SYS_ESR_EL2			sys_reg(3, 4, 5, 2, 0)
549 #define SYS_VSESR_EL2			sys_reg(3, 4, 5, 2, 3)
550 #define SYS_FPEXC32_EL2			sys_reg(3, 4, 5, 3, 0)
551 #define SYS_TFSR_EL2			sys_reg(3, 4, 5, 6, 0)
552 
553 #define SYS_FAR_EL2			sys_reg(3, 4, 6, 0, 0)
554 #define SYS_HPFAR_EL2			sys_reg(3, 4, 6, 0, 4)
555 
556 #define SYS_MAIR_EL2			sys_reg(3, 4, 10, 2, 0)
557 #define SYS_AMAIR_EL2			sys_reg(3, 4, 10, 3, 0)
558 
559 #define SYS_VBAR_EL2			sys_reg(3, 4, 12, 0, 0)
560 #define SYS_RVBAR_EL2			sys_reg(3, 4, 12, 0, 1)
561 #define SYS_RMR_EL2			sys_reg(3, 4, 12, 0, 2)
562 #define SYS_VDISR_EL2			sys_reg(3, 4, 12, 1, 1)
563 #define __SYS__AP0Rx_EL2(x)		sys_reg(3, 4, 12, 8, x)
564 #define SYS_ICH_AP0R0_EL2		__SYS__AP0Rx_EL2(0)
565 #define SYS_ICH_AP0R1_EL2		__SYS__AP0Rx_EL2(1)
566 #define SYS_ICH_AP0R2_EL2		__SYS__AP0Rx_EL2(2)
567 #define SYS_ICH_AP0R3_EL2		__SYS__AP0Rx_EL2(3)
568 
569 #define __SYS__AP1Rx_EL2(x)		sys_reg(3, 4, 12, 9, x)
570 #define SYS_ICH_AP1R0_EL2		__SYS__AP1Rx_EL2(0)
571 #define SYS_ICH_AP1R1_EL2		__SYS__AP1Rx_EL2(1)
572 #define SYS_ICH_AP1R2_EL2		__SYS__AP1Rx_EL2(2)
573 #define SYS_ICH_AP1R3_EL2		__SYS__AP1Rx_EL2(3)
574 
575 #define SYS_ICH_VSEIR_EL2		sys_reg(3, 4, 12, 9, 4)
576 #define SYS_ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)
577 #define SYS_ICH_EISR_EL2		sys_reg(3, 4, 12, 11, 3)
578 #define SYS_ICH_ELRSR_EL2		sys_reg(3, 4, 12, 11, 5)
579 #define SYS_ICH_VMCR_EL2		sys_reg(3, 4, 12, 11, 7)
580 
581 #define __SYS__LR0_EL2(x)		sys_reg(3, 4, 12, 12, x)
582 #define SYS_ICH_LR0_EL2			__SYS__LR0_EL2(0)
583 #define SYS_ICH_LR1_EL2			__SYS__LR0_EL2(1)
584 #define SYS_ICH_LR2_EL2			__SYS__LR0_EL2(2)
585 #define SYS_ICH_LR3_EL2			__SYS__LR0_EL2(3)
586 #define SYS_ICH_LR4_EL2			__SYS__LR0_EL2(4)
587 #define SYS_ICH_LR5_EL2			__SYS__LR0_EL2(5)
588 #define SYS_ICH_LR6_EL2			__SYS__LR0_EL2(6)
589 #define SYS_ICH_LR7_EL2			__SYS__LR0_EL2(7)
590 
591 #define __SYS__LR8_EL2(x)		sys_reg(3, 4, 12, 13, x)
592 #define SYS_ICH_LR8_EL2			__SYS__LR8_EL2(0)
593 #define SYS_ICH_LR9_EL2			__SYS__LR8_EL2(1)
594 #define SYS_ICH_LR10_EL2		__SYS__LR8_EL2(2)
595 #define SYS_ICH_LR11_EL2		__SYS__LR8_EL2(3)
596 #define SYS_ICH_LR12_EL2		__SYS__LR8_EL2(4)
597 #define SYS_ICH_LR13_EL2		__SYS__LR8_EL2(5)
598 #define SYS_ICH_LR14_EL2		__SYS__LR8_EL2(6)
599 #define SYS_ICH_LR15_EL2		__SYS__LR8_EL2(7)
600 
601 #define SYS_CONTEXTIDR_EL2		sys_reg(3, 4, 13, 0, 1)
602 #define SYS_TPIDR_EL2			sys_reg(3, 4, 13, 0, 2)
603 #define SYS_SCXTNUM_EL2			sys_reg(3, 4, 13, 0, 7)
604 
605 #define __AMEV_op2(m)			(m & 0x7)
606 #define __AMEV_CRm(n, m)		(n | ((m & 0x8) >> 3))
607 #define __SYS__AMEVCNTVOFF0n_EL2(m)	sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m))
608 #define SYS_AMEVCNTVOFF0n_EL2(m)	__SYS__AMEVCNTVOFF0n_EL2(m)
609 #define __SYS__AMEVCNTVOFF1n_EL2(m)	sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m))
610 #define SYS_AMEVCNTVOFF1n_EL2(m)	__SYS__AMEVCNTVOFF1n_EL2(m)
611 
612 #define SYS_CNTVOFF_EL2			sys_reg(3, 4, 14, 0, 3)
613 #define SYS_CNTHCTL_EL2			sys_reg(3, 4, 14, 1, 0)
614 #define SYS_CNTHP_TVAL_EL2		sys_reg(3, 4, 14, 2, 0)
615 #define SYS_CNTHP_CTL_EL2		sys_reg(3, 4, 14, 2, 1)
616 #define SYS_CNTHP_CVAL_EL2		sys_reg(3, 4, 14, 2, 2)
617 #define SYS_CNTHV_TVAL_EL2		sys_reg(3, 4, 14, 3, 0)
618 #define SYS_CNTHV_CTL_EL2		sys_reg(3, 4, 14, 3, 1)
619 #define SYS_CNTHV_CVAL_EL2		sys_reg(3, 4, 14, 3, 2)
620 
621 /* VHE encodings for architectural EL0/1 system registers */
622 #define SYS_BRBCR_EL12			sys_reg(2, 5, 9, 0, 0)
623 #define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
624 #define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
625 #define SYS_SPSR_EL12			sys_reg(3, 5, 4, 0, 0)
626 #define SYS_ELR_EL12			sys_reg(3, 5, 4, 0, 1)
627 #define SYS_AFSR0_EL12			sys_reg(3, 5, 5, 1, 0)
628 #define SYS_AFSR1_EL12			sys_reg(3, 5, 5, 1, 1)
629 #define SYS_ESR_EL12			sys_reg(3, 5, 5, 2, 0)
630 #define SYS_TFSR_EL12			sys_reg(3, 5, 5, 6, 0)
631 #define SYS_PMSCR_EL12			sys_reg(3, 5, 9, 9, 0)
632 #define SYS_MAIR_EL12			sys_reg(3, 5, 10, 2, 0)
633 #define SYS_AMAIR_EL12			sys_reg(3, 5, 10, 3, 0)
634 #define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)
635 #define SYS_SCXTNUM_EL12		sys_reg(3, 5, 13, 0, 7)
636 #define SYS_CNTKCTL_EL12		sys_reg(3, 5, 14, 1, 0)
637 #define SYS_CNTP_TVAL_EL02		sys_reg(3, 5, 14, 2, 0)
638 #define SYS_CNTP_CTL_EL02		sys_reg(3, 5, 14, 2, 1)
639 #define SYS_CNTP_CVAL_EL02		sys_reg(3, 5, 14, 2, 2)
640 #define SYS_CNTV_TVAL_EL02		sys_reg(3, 5, 14, 3, 0)
641 #define SYS_CNTV_CTL_EL02		sys_reg(3, 5, 14, 3, 1)
642 #define SYS_CNTV_CVAL_EL02		sys_reg(3, 5, 14, 3, 2)
643 
644 #define SYS_SP_EL2			sys_reg(3, 6,  4, 1, 0)
645 
646 /* AT instructions */
647 #define AT_Op0 1
648 #define AT_CRn 7
649 
650 #define OP_AT_S1E1R	sys_insn(AT_Op0, 0, AT_CRn, 8, 0)
651 #define OP_AT_S1E1W	sys_insn(AT_Op0, 0, AT_CRn, 8, 1)
652 #define OP_AT_S1E0R	sys_insn(AT_Op0, 0, AT_CRn, 8, 2)
653 #define OP_AT_S1E0W	sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
654 #define OP_AT_S1E1RP	sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
655 #define OP_AT_S1E1WP	sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
656 #define OP_AT_S1E1A	sys_insn(AT_Op0, 0, AT_CRn, 9, 2)
657 #define OP_AT_S1E2R	sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
658 #define OP_AT_S1E2W	sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
659 #define OP_AT_S12E1R	sys_insn(AT_Op0, 4, AT_CRn, 8, 4)
660 #define OP_AT_S12E1W	sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
661 #define OP_AT_S12E0R	sys_insn(AT_Op0, 4, AT_CRn, 8, 6)
662 #define OP_AT_S12E0W	sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
663 #define OP_AT_S1E2A	sys_insn(AT_Op0, 4, AT_CRn, 9, 2)
664 
665 /* TLBI instructions */
666 #define TLBI_Op0	1
667 
668 #define TLBI_Op1_EL1	0	/* Accessible from EL1 or higher */
669 #define TLBI_Op1_EL2	4	/* Accessible from EL2 or higher */
670 
671 #define TLBI_CRn_XS	8	/* Extra Slow (the common one) */
672 #define TLBI_CRn_nXS	9	/* not Extra Slow (which nobody uses)*/
673 
674 #define TLBI_CRm_IPAIS	0	/* S2 Inner-Shareable */
675 #define TLBI_CRm_nROS	1	/* non-Range, Outer-Sharable */
676 #define TLBI_CRm_RIS	2	/* Range, Inner-Sharable */
677 #define TLBI_CRm_nRIS	3	/* non-Range, Inner-Sharable */
678 #define TLBI_CRm_IPAONS	4	/* S2 Outer and Non-Shareable */
679 #define TLBI_CRm_ROS	5	/* Range, Outer-Sharable */
680 #define TLBI_CRm_RNS	6	/* Range, Non-Sharable */
681 #define TLBI_CRm_nRNS	7	/* non-Range, Non-Sharable */
682 
683 #define OP_TLBI_VMALLE1OS		sys_insn(1, 0, 8, 1, 0)
684 #define OP_TLBI_VAE1OS			sys_insn(1, 0, 8, 1, 1)
685 #define OP_TLBI_ASIDE1OS		sys_insn(1, 0, 8, 1, 2)
686 #define OP_TLBI_VAAE1OS			sys_insn(1, 0, 8, 1, 3)
687 #define OP_TLBI_VALE1OS			sys_insn(1, 0, 8, 1, 5)
688 #define OP_TLBI_VAALE1OS		sys_insn(1, 0, 8, 1, 7)
689 #define OP_TLBI_RVAE1IS			sys_insn(1, 0, 8, 2, 1)
690 #define OP_TLBI_RVAAE1IS		sys_insn(1, 0, 8, 2, 3)
691 #define OP_TLBI_RVALE1IS		sys_insn(1, 0, 8, 2, 5)
692 #define OP_TLBI_RVAALE1IS		sys_insn(1, 0, 8, 2, 7)
693 #define OP_TLBI_VMALLE1IS		sys_insn(1, 0, 8, 3, 0)
694 #define OP_TLBI_VAE1IS			sys_insn(1, 0, 8, 3, 1)
695 #define OP_TLBI_ASIDE1IS		sys_insn(1, 0, 8, 3, 2)
696 #define OP_TLBI_VAAE1IS			sys_insn(1, 0, 8, 3, 3)
697 #define OP_TLBI_VALE1IS			sys_insn(1, 0, 8, 3, 5)
698 #define OP_TLBI_VAALE1IS		sys_insn(1, 0, 8, 3, 7)
699 #define OP_TLBI_RVAE1OS			sys_insn(1, 0, 8, 5, 1)
700 #define OP_TLBI_RVAAE1OS		sys_insn(1, 0, 8, 5, 3)
701 #define OP_TLBI_RVALE1OS		sys_insn(1, 0, 8, 5, 5)
702 #define OP_TLBI_RVAALE1OS		sys_insn(1, 0, 8, 5, 7)
703 #define OP_TLBI_RVAE1			sys_insn(1, 0, 8, 6, 1)
704 #define OP_TLBI_RVAAE1			sys_insn(1, 0, 8, 6, 3)
705 #define OP_TLBI_RVALE1			sys_insn(1, 0, 8, 6, 5)
706 #define OP_TLBI_RVAALE1			sys_insn(1, 0, 8, 6, 7)
707 #define OP_TLBI_VMALLE1			sys_insn(1, 0, 8, 7, 0)
708 #define OP_TLBI_VAE1			sys_insn(1, 0, 8, 7, 1)
709 #define OP_TLBI_ASIDE1			sys_insn(1, 0, 8, 7, 2)
710 #define OP_TLBI_VAAE1			sys_insn(1, 0, 8, 7, 3)
711 #define OP_TLBI_VALE1			sys_insn(1, 0, 8, 7, 5)
712 #define OP_TLBI_VAALE1			sys_insn(1, 0, 8, 7, 7)
713 #define OP_TLBI_VMALLE1OSNXS		sys_insn(1, 0, 9, 1, 0)
714 #define OP_TLBI_VAE1OSNXS		sys_insn(1, 0, 9, 1, 1)
715 #define OP_TLBI_ASIDE1OSNXS		sys_insn(1, 0, 9, 1, 2)
716 #define OP_TLBI_VAAE1OSNXS		sys_insn(1, 0, 9, 1, 3)
717 #define OP_TLBI_VALE1OSNXS		sys_insn(1, 0, 9, 1, 5)
718 #define OP_TLBI_VAALE1OSNXS		sys_insn(1, 0, 9, 1, 7)
719 #define OP_TLBI_RVAE1ISNXS		sys_insn(1, 0, 9, 2, 1)
720 #define OP_TLBI_RVAAE1ISNXS		sys_insn(1, 0, 9, 2, 3)
721 #define OP_TLBI_RVALE1ISNXS		sys_insn(1, 0, 9, 2, 5)
722 #define OP_TLBI_RVAALE1ISNXS		sys_insn(1, 0, 9, 2, 7)
723 #define OP_TLBI_VMALLE1ISNXS		sys_insn(1, 0, 9, 3, 0)
724 #define OP_TLBI_VAE1ISNXS		sys_insn(1, 0, 9, 3, 1)
725 #define OP_TLBI_ASIDE1ISNXS		sys_insn(1, 0, 9, 3, 2)
726 #define OP_TLBI_VAAE1ISNXS		sys_insn(1, 0, 9, 3, 3)
727 #define OP_TLBI_VALE1ISNXS		sys_insn(1, 0, 9, 3, 5)
728 #define OP_TLBI_VAALE1ISNXS		sys_insn(1, 0, 9, 3, 7)
729 #define OP_TLBI_RVAE1OSNXS		sys_insn(1, 0, 9, 5, 1)
730 #define OP_TLBI_RVAAE1OSNXS		sys_insn(1, 0, 9, 5, 3)
731 #define OP_TLBI_RVALE1OSNXS		sys_insn(1, 0, 9, 5, 5)
732 #define OP_TLBI_RVAALE1OSNXS		sys_insn(1, 0, 9, 5, 7)
733 #define OP_TLBI_RVAE1NXS		sys_insn(1, 0, 9, 6, 1)
734 #define OP_TLBI_RVAAE1NXS		sys_insn(1, 0, 9, 6, 3)
735 #define OP_TLBI_RVALE1NXS		sys_insn(1, 0, 9, 6, 5)
736 #define OP_TLBI_RVAALE1NXS		sys_insn(1, 0, 9, 6, 7)
737 #define OP_TLBI_VMALLE1NXS		sys_insn(1, 0, 9, 7, 0)
738 #define OP_TLBI_VAE1NXS			sys_insn(1, 0, 9, 7, 1)
739 #define OP_TLBI_ASIDE1NXS		sys_insn(1, 0, 9, 7, 2)
740 #define OP_TLBI_VAAE1NXS		sys_insn(1, 0, 9, 7, 3)
741 #define OP_TLBI_VALE1NXS		sys_insn(1, 0, 9, 7, 5)
742 #define OP_TLBI_VAALE1NXS		sys_insn(1, 0, 9, 7, 7)
743 #define OP_TLBI_IPAS2E1IS		sys_insn(1, 4, 8, 0, 1)
744 #define OP_TLBI_RIPAS2E1IS		sys_insn(1, 4, 8, 0, 2)
745 #define OP_TLBI_IPAS2LE1IS		sys_insn(1, 4, 8, 0, 5)
746 #define OP_TLBI_RIPAS2LE1IS		sys_insn(1, 4, 8, 0, 6)
747 #define OP_TLBI_ALLE2OS			sys_insn(1, 4, 8, 1, 0)
748 #define OP_TLBI_VAE2OS			sys_insn(1, 4, 8, 1, 1)
749 #define OP_TLBI_ALLE1OS			sys_insn(1, 4, 8, 1, 4)
750 #define OP_TLBI_VALE2OS			sys_insn(1, 4, 8, 1, 5)
751 #define OP_TLBI_VMALLS12E1OS		sys_insn(1, 4, 8, 1, 6)
752 #define OP_TLBI_RVAE2IS			sys_insn(1, 4, 8, 2, 1)
753 #define OP_TLBI_RVALE2IS		sys_insn(1, 4, 8, 2, 5)
754 #define OP_TLBI_ALLE2IS			sys_insn(1, 4, 8, 3, 0)
755 #define OP_TLBI_VAE2IS			sys_insn(1, 4, 8, 3, 1)
756 #define OP_TLBI_ALLE1IS			sys_insn(1, 4, 8, 3, 4)
757 #define OP_TLBI_VALE2IS			sys_insn(1, 4, 8, 3, 5)
758 #define OP_TLBI_VMALLS12E1IS		sys_insn(1, 4, 8, 3, 6)
759 #define OP_TLBI_IPAS2E1OS		sys_insn(1, 4, 8, 4, 0)
760 #define OP_TLBI_IPAS2E1			sys_insn(1, 4, 8, 4, 1)
761 #define OP_TLBI_RIPAS2E1		sys_insn(1, 4, 8, 4, 2)
762 #define OP_TLBI_RIPAS2E1OS		sys_insn(1, 4, 8, 4, 3)
763 #define OP_TLBI_IPAS2LE1OS		sys_insn(1, 4, 8, 4, 4)
764 #define OP_TLBI_IPAS2LE1		sys_insn(1, 4, 8, 4, 5)
765 #define OP_TLBI_RIPAS2LE1		sys_insn(1, 4, 8, 4, 6)
766 #define OP_TLBI_RIPAS2LE1OS		sys_insn(1, 4, 8, 4, 7)
767 #define OP_TLBI_RVAE2OS			sys_insn(1, 4, 8, 5, 1)
768 #define OP_TLBI_RVALE2OS		sys_insn(1, 4, 8, 5, 5)
769 #define OP_TLBI_RVAE2			sys_insn(1, 4, 8, 6, 1)
770 #define OP_TLBI_RVALE2			sys_insn(1, 4, 8, 6, 5)
771 #define OP_TLBI_ALLE2			sys_insn(1, 4, 8, 7, 0)
772 #define OP_TLBI_VAE2			sys_insn(1, 4, 8, 7, 1)
773 #define OP_TLBI_ALLE1			sys_insn(1, 4, 8, 7, 4)
774 #define OP_TLBI_VALE2			sys_insn(1, 4, 8, 7, 5)
775 #define OP_TLBI_VMALLS12E1		sys_insn(1, 4, 8, 7, 6)
776 #define OP_TLBI_IPAS2E1ISNXS		sys_insn(1, 4, 9, 0, 1)
777 #define OP_TLBI_RIPAS2E1ISNXS		sys_insn(1, 4, 9, 0, 2)
778 #define OP_TLBI_IPAS2LE1ISNXS		sys_insn(1, 4, 9, 0, 5)
779 #define OP_TLBI_RIPAS2LE1ISNXS		sys_insn(1, 4, 9, 0, 6)
780 #define OP_TLBI_ALLE2OSNXS		sys_insn(1, 4, 9, 1, 0)
781 #define OP_TLBI_VAE2OSNXS		sys_insn(1, 4, 9, 1, 1)
782 #define OP_TLBI_ALLE1OSNXS		sys_insn(1, 4, 9, 1, 4)
783 #define OP_TLBI_VALE2OSNXS		sys_insn(1, 4, 9, 1, 5)
784 #define OP_TLBI_VMALLS12E1OSNXS		sys_insn(1, 4, 9, 1, 6)
785 #define OP_TLBI_RVAE2ISNXS		sys_insn(1, 4, 9, 2, 1)
786 #define OP_TLBI_RVALE2ISNXS		sys_insn(1, 4, 9, 2, 5)
787 #define OP_TLBI_ALLE2ISNXS		sys_insn(1, 4, 9, 3, 0)
788 #define OP_TLBI_VAE2ISNXS		sys_insn(1, 4, 9, 3, 1)
789 #define OP_TLBI_ALLE1ISNXS		sys_insn(1, 4, 9, 3, 4)
790 #define OP_TLBI_VALE2ISNXS		sys_insn(1, 4, 9, 3, 5)
791 #define OP_TLBI_VMALLS12E1ISNXS		sys_insn(1, 4, 9, 3, 6)
792 #define OP_TLBI_IPAS2E1OSNXS		sys_insn(1, 4, 9, 4, 0)
793 #define OP_TLBI_IPAS2E1NXS		sys_insn(1, 4, 9, 4, 1)
794 #define OP_TLBI_RIPAS2E1NXS		sys_insn(1, 4, 9, 4, 2)
795 #define OP_TLBI_RIPAS2E1OSNXS		sys_insn(1, 4, 9, 4, 3)
796 #define OP_TLBI_IPAS2LE1OSNXS		sys_insn(1, 4, 9, 4, 4)
797 #define OP_TLBI_IPAS2LE1NXS		sys_insn(1, 4, 9, 4, 5)
798 #define OP_TLBI_RIPAS2LE1NXS		sys_insn(1, 4, 9, 4, 6)
799 #define OP_TLBI_RIPAS2LE1OSNXS		sys_insn(1, 4, 9, 4, 7)
800 #define OP_TLBI_RVAE2OSNXS		sys_insn(1, 4, 9, 5, 1)
801 #define OP_TLBI_RVALE2OSNXS		sys_insn(1, 4, 9, 5, 5)
802 #define OP_TLBI_RVAE2NXS		sys_insn(1, 4, 9, 6, 1)
803 #define OP_TLBI_RVALE2NXS		sys_insn(1, 4, 9, 6, 5)
804 #define OP_TLBI_ALLE2NXS		sys_insn(1, 4, 9, 7, 0)
805 #define OP_TLBI_VAE2NXS			sys_insn(1, 4, 9, 7, 1)
806 #define OP_TLBI_ALLE1NXS		sys_insn(1, 4, 9, 7, 4)
807 #define OP_TLBI_VALE2NXS		sys_insn(1, 4, 9, 7, 5)
808 #define OP_TLBI_VMALLS12E1NXS		sys_insn(1, 4, 9, 7, 6)
809 
810 /* Misc instructions */
811 #define OP_GCSPUSHX			sys_insn(1, 0, 7, 7, 4)
812 #define OP_GCSPOPCX			sys_insn(1, 0, 7, 7, 5)
813 #define OP_GCSPOPX			sys_insn(1, 0, 7, 7, 6)
814 #define OP_GCSPUSHM			sys_insn(1, 3, 7, 7, 0)
815 
816 #define OP_BRB_IALL			sys_insn(1, 1, 7, 2, 4)
817 #define OP_BRB_INJ			sys_insn(1, 1, 7, 2, 5)
818 #define OP_CFP_RCTX			sys_insn(1, 3, 7, 3, 4)
819 #define OP_DVP_RCTX			sys_insn(1, 3, 7, 3, 5)
820 #define OP_COSP_RCTX			sys_insn(1, 3, 7, 3, 6)
821 #define OP_CPP_RCTX			sys_insn(1, 3, 7, 3, 7)
822 
823 /* Common SCTLR_ELx flags. */
824 #define SCTLR_ELx_ENTP2	(BIT(60))
825 #define SCTLR_ELx_DSSBS	(BIT(44))
826 #define SCTLR_ELx_ATA	(BIT(43))
827 
828 #define SCTLR_ELx_EE_SHIFT	25
829 #define SCTLR_ELx_ENIA_SHIFT	31
830 
831 #define SCTLR_ELx_ITFSB	 (BIT(37))
832 #define SCTLR_ELx_ENIA	 (BIT(SCTLR_ELx_ENIA_SHIFT))
833 #define SCTLR_ELx_ENIB	 (BIT(30))
834 #define SCTLR_ELx_LSMAOE (BIT(29))
835 #define SCTLR_ELx_nTLSMD (BIT(28))
836 #define SCTLR_ELx_ENDA	 (BIT(27))
837 #define SCTLR_ELx_EE     (BIT(SCTLR_ELx_EE_SHIFT))
838 #define SCTLR_ELx_EIS	 (BIT(22))
839 #define SCTLR_ELx_IESB	 (BIT(21))
840 #define SCTLR_ELx_TSCXT	 (BIT(20))
841 #define SCTLR_ELx_WXN	 (BIT(19))
842 #define SCTLR_ELx_ENDB	 (BIT(13))
843 #define SCTLR_ELx_I	 (BIT(12))
844 #define SCTLR_ELx_EOS	 (BIT(11))
845 #define SCTLR_ELx_SA	 (BIT(3))
846 #define SCTLR_ELx_C	 (BIT(2))
847 #define SCTLR_ELx_A	 (BIT(1))
848 #define SCTLR_ELx_M	 (BIT(0))
849 
850 /* SCTLR_EL2 specific flags. */
851 #define SCTLR_EL2_RES1	((BIT(4))  | (BIT(5))  | (BIT(11)) | (BIT(16)) | \
852 			 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
853 			 (BIT(29)))
854 
855 #define SCTLR_EL2_BT	(BIT(36))
856 #ifdef CONFIG_CPU_BIG_ENDIAN
857 #define ENDIAN_SET_EL2		SCTLR_ELx_EE
858 #else
859 #define ENDIAN_SET_EL2		0
860 #endif
861 
862 #define INIT_SCTLR_EL2_MMU_ON						\
863 	(SCTLR_ELx_M  | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I |	\
864 	 SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 |		\
865 	 SCTLR_ELx_ITFSB | SCTLR_EL2_RES1)
866 
867 #define INIT_SCTLR_EL2_MMU_OFF \
868 	(SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
869 
870 /* SCTLR_EL1 specific flags. */
871 #ifdef CONFIG_CPU_BIG_ENDIAN
872 #define ENDIAN_SET_EL1		(SCTLR_EL1_E0E | SCTLR_ELx_EE)
873 #else
874 #define ENDIAN_SET_EL1		0
875 #endif
876 
877 #define INIT_SCTLR_EL1_MMU_OFF \
878 	(ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | \
879 	 SCTLR_EL1_EIS  | SCTLR_EL1_TSCXT  | SCTLR_EL1_EOS)
880 
881 #define INIT_SCTLR_EL1_MMU_ON \
882 	(SCTLR_ELx_M      | SCTLR_ELx_C      | SCTLR_ELx_SA    | \
883 	 SCTLR_EL1_SA0    | SCTLR_EL1_SED    | SCTLR_ELx_I     | \
884 	 SCTLR_EL1_DZE    | SCTLR_EL1_UCT    | SCTLR_EL1_nTWE  | \
885 	 SCTLR_ELx_IESB   | SCTLR_EL1_SPAN   | SCTLR_ELx_ITFSB | \
886 	 ENDIAN_SET_EL1   | SCTLR_EL1_UCI    | SCTLR_EL1_EPAN  | \
887 	 SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS   | \
888 	 SCTLR_EL1_TSCXT  | SCTLR_EL1_EOS)
889 
890 /* MAIR_ELx memory attributes (used by Linux) */
891 #define MAIR_ATTR_DEVICE_nGnRnE		UL(0x00)
892 #define MAIR_ATTR_DEVICE_nGnRE		UL(0x04)
893 #define MAIR_ATTR_NORMAL_NC		UL(0x44)
894 #define MAIR_ATTR_NORMAL_TAGGED		UL(0xf0)
895 #define MAIR_ATTR_NORMAL		UL(0xff)
896 #define MAIR_ATTR_MASK			UL(0xff)
897 
898 /* Position the attr at the correct index */
899 #define MAIR_ATTRIDX(attr, idx)		((attr) << ((idx) * 8))
900 
901 /* id_aa64mmfr0 */
902 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN	0x0
903 #define ID_AA64MMFR0_EL1_TGRAN4_LPA2		ID_AA64MMFR0_EL1_TGRAN4_52_BIT
904 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX	0x7
905 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN	0x0
906 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX	0x7
907 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN	0x1
908 #define ID_AA64MMFR0_EL1_TGRAN16_LPA2		ID_AA64MMFR0_EL1_TGRAN16_52_BIT
909 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX	0xf
910 
911 #define ARM64_MIN_PARANGE_BITS		32
912 
913 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT	0x0
914 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE		0x1
915 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN		0x2
916 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2		0x3
917 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX		0x7
918 
919 #ifdef CONFIG_ARM64_PA_BITS_52
920 #define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_52
921 #else
922 #define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_48
923 #endif
924 
925 #if defined(CONFIG_ARM64_4K_PAGES)
926 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_SHIFT
927 #define ID_AA64MMFR0_EL1_TGRAN_LPA2		ID_AA64MMFR0_EL1_TGRAN4_52_BIT
928 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
929 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX
930 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT
931 #elif defined(CONFIG_ARM64_16K_PAGES)
932 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_SHIFT
933 #define ID_AA64MMFR0_EL1_TGRAN_LPA2		ID_AA64MMFR0_EL1_TGRAN16_52_BIT
934 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN
935 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX
936 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT
937 #elif defined(CONFIG_ARM64_64K_PAGES)
938 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN64_SHIFT
939 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN
940 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX
941 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT
942 #endif
943 
944 #define CPACR_EL1_FPEN_EL1EN	(BIT(20)) /* enable EL1 access */
945 #define CPACR_EL1_FPEN_EL0EN	(BIT(21)) /* enable EL0 access, if EL1EN set */
946 
947 #define CPACR_EL1_SMEN_EL1EN	(BIT(24)) /* enable EL1 access */
948 #define CPACR_EL1_SMEN_EL0EN	(BIT(25)) /* enable EL0 access, if EL1EN set */
949 
950 #define CPACR_EL1_ZEN_EL1EN	(BIT(16)) /* enable EL1 access */
951 #define CPACR_EL1_ZEN_EL0EN	(BIT(17)) /* enable EL0 access, if EL1EN set */
952 
953 /* GCR_EL1 Definitions */
954 #define SYS_GCR_EL1_RRND	(BIT(16))
955 #define SYS_GCR_EL1_EXCL_MASK	0xffffUL
956 
957 #ifdef CONFIG_KASAN_HW_TAGS
958 /*
959  * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it
960  * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
961  */
962 #define __MTE_TAG_MIN		(KASAN_TAG_MIN & 0xf)
963 #define __MTE_TAG_MAX		(KASAN_TAG_MAX & 0xf)
964 #define __MTE_TAG_INCL		GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN)
965 #define KERNEL_GCR_EL1_EXCL	(SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL)
966 #else
967 #define KERNEL_GCR_EL1_EXCL	SYS_GCR_EL1_EXCL_MASK
968 #endif
969 
970 #define KERNEL_GCR_EL1		(SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL)
971 
972 /* RGSR_EL1 Definitions */
973 #define SYS_RGSR_EL1_TAG_MASK	0xfUL
974 #define SYS_RGSR_EL1_SEED_SHIFT	8
975 #define SYS_RGSR_EL1_SEED_MASK	0xffffUL
976 
977 /* TFSR{,E0}_EL1 bit definitions */
978 #define SYS_TFSR_EL1_TF0_SHIFT	0
979 #define SYS_TFSR_EL1_TF1_SHIFT	1
980 #define SYS_TFSR_EL1_TF0	(UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
981 #define SYS_TFSR_EL1_TF1	(UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
982 
983 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
984 #define SYS_MPIDR_SAFE_VAL	(BIT(31))
985 
986 /* GIC Hypervisor interface registers */
987 /* ICH_LR*_EL2 bit definitions */
988 #define ICH_LR_VIRTUAL_ID_MASK	((1ULL << 32) - 1)
989 
990 #define ICH_LR_EOI		(1ULL << 41)
991 #define ICH_LR_GROUP		(1ULL << 60)
992 #define ICH_LR_HW		(1ULL << 61)
993 #define ICH_LR_STATE		(3ULL << 62)
994 #define ICH_LR_PENDING_BIT	(1ULL << 62)
995 #define ICH_LR_ACTIVE_BIT	(1ULL << 63)
996 #define ICH_LR_PHYS_ID_SHIFT	32
997 #define ICH_LR_PHYS_ID_MASK	(0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
998 #define ICH_LR_PRIORITY_SHIFT	48
999 #define ICH_LR_PRIORITY_MASK	(0xffULL << ICH_LR_PRIORITY_SHIFT)
1000 
1001 /* ICH_VMCR_EL2 bit definitions */
1002 #define ICH_VMCR_ACK_CTL_SHIFT	2
1003 #define ICH_VMCR_ACK_CTL_MASK	(1 << ICH_VMCR_ACK_CTL_SHIFT)
1004 #define ICH_VMCR_FIQ_EN_SHIFT	3
1005 #define ICH_VMCR_FIQ_EN_MASK	(1 << ICH_VMCR_FIQ_EN_SHIFT)
1006 #define ICH_VMCR_CBPR_SHIFT	4
1007 #define ICH_VMCR_CBPR_MASK	(1 << ICH_VMCR_CBPR_SHIFT)
1008 #define ICH_VMCR_EOIM_SHIFT	9
1009 #define ICH_VMCR_EOIM_MASK	(1 << ICH_VMCR_EOIM_SHIFT)
1010 #define ICH_VMCR_BPR1_SHIFT	18
1011 #define ICH_VMCR_BPR1_MASK	(7 << ICH_VMCR_BPR1_SHIFT)
1012 #define ICH_VMCR_BPR0_SHIFT	21
1013 #define ICH_VMCR_BPR0_MASK	(7 << ICH_VMCR_BPR0_SHIFT)
1014 #define ICH_VMCR_PMR_SHIFT	24
1015 #define ICH_VMCR_PMR_MASK	(0xffUL << ICH_VMCR_PMR_SHIFT)
1016 #define ICH_VMCR_ENG0_SHIFT	0
1017 #define ICH_VMCR_ENG0_MASK	(1 << ICH_VMCR_ENG0_SHIFT)
1018 #define ICH_VMCR_ENG1_SHIFT	1
1019 #define ICH_VMCR_ENG1_MASK	(1 << ICH_VMCR_ENG1_SHIFT)
1020 
1021 /*
1022  * Permission Indirection Extension (PIE) permission encodings.
1023  * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension).
1024  */
1025 #define PIE_NONE_O	UL(0x0)
1026 #define PIE_R_O		UL(0x1)
1027 #define PIE_X_O		UL(0x2)
1028 #define PIE_RX_O	UL(0x3)
1029 #define PIE_RW_O	UL(0x5)
1030 #define PIE_RWnX_O	UL(0x6)
1031 #define PIE_RWX_O	UL(0x7)
1032 #define PIE_R		UL(0x8)
1033 #define PIE_GCS		UL(0x9)
1034 #define PIE_RX		UL(0xa)
1035 #define PIE_RW		UL(0xc)
1036 #define PIE_RWX		UL(0xe)
1037 #define PIE_MASK	UL(0xf)
1038 
1039 #define PIRx_ELx_BITS_PER_IDX		4
1040 #define PIRx_ELx_PERM_SHIFT(idx)	((idx) * PIRx_ELx_BITS_PER_IDX)
1041 #define PIRx_ELx_PERM_PREP(idx, perm)	(((perm) & PIE_MASK) << PIRx_ELx_PERM_SHIFT(idx))
1042 
1043 /*
1044  * Permission Overlay Extension (POE) permission encodings.
1045  */
1046 #define POE_NONE	UL(0x0)
1047 #define POE_R		UL(0x1)
1048 #define POE_X		UL(0x2)
1049 #define POE_RX		UL(0x3)
1050 #define POE_W		UL(0x4)
1051 #define POE_RW		UL(0x5)
1052 #define POE_WX		UL(0x6)
1053 #define POE_RWX		UL(0x7)
1054 #define POE_MASK	UL(0xf)
1055 
1056 #define POR_ELx_BITS_PER_IDX		4
1057 #define POR_ELx_PERM_SHIFT(idx)		((idx) * POR_ELx_BITS_PER_IDX)
1058 #define POR_ELx_PERM_GET(idx, reg)	(((reg) >> POR_ELx_PERM_SHIFT(idx)) & POE_MASK)
1059 #define POR_ELx_PERM_PREP(idx, perm)	(((perm) & POE_MASK) << POR_ELx_PERM_SHIFT(idx))
1060 
1061 /*
1062  * Definitions for Guarded Control Stack
1063  */
1064 
1065 #define GCS_CAP_ADDR_MASK		GENMASK(63, 12)
1066 #define GCS_CAP_ADDR_SHIFT		12
1067 #define GCS_CAP_ADDR_WIDTH		52
1068 #define GCS_CAP_ADDR(x)			FIELD_GET(GCS_CAP_ADDR_MASK, x)
1069 
1070 #define GCS_CAP_TOKEN_MASK		GENMASK(11, 0)
1071 #define GCS_CAP_TOKEN_SHIFT		0
1072 #define GCS_CAP_TOKEN_WIDTH		12
1073 #define GCS_CAP_TOKEN(x)		FIELD_GET(GCS_CAP_TOKEN_MASK, x)
1074 
1075 #define GCS_CAP_VALID_TOKEN		0x1
1076 #define GCS_CAP_IN_PROGRESS_TOKEN	0x5
1077 
1078 #define GCS_CAP(x)	((((unsigned long)x) & GCS_CAP_ADDR_MASK) | \
1079 					       GCS_CAP_VALID_TOKEN)
1080 
1081 #define ARM64_FEATURE_FIELD_BITS	4
1082 
1083 /* Defined for compatibility only, do not add new users. */
1084 #define ARM64_FEATURE_MASK(x)	(x##_MASK)
1085 
1086 #ifdef __ASSEMBLY__
1087 
1088 	.macro	mrs_s, rt, sreg
1089 	 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
1090 	.endm
1091 
1092 	.macro	msr_s, sreg, rt
1093 	__emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt))
1094 	.endm
1095 
1096 #else
1097 
1098 #include <linux/bitfield.h>
1099 #include <linux/build_bug.h>
1100 #include <linux/types.h>
1101 #include <asm/alternative.h>
1102 
1103 #define DEFINE_MRS_S						\
1104 	__DEFINE_ASM_GPR_NUMS					\
1105 "	.macro	mrs_s, rt, sreg\n"				\
1106 	__emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt))	\
1107 "	.endm\n"
1108 
1109 #define DEFINE_MSR_S						\
1110 	__DEFINE_ASM_GPR_NUMS					\
1111 "	.macro	msr_s, sreg, rt\n"				\
1112 	__emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt))	\
1113 "	.endm\n"
1114 
1115 #define UNDEFINE_MRS_S						\
1116 "	.purgem	mrs_s\n"
1117 
1118 #define UNDEFINE_MSR_S						\
1119 "	.purgem	msr_s\n"
1120 
1121 #define __mrs_s(v, r)						\
1122 	DEFINE_MRS_S						\
1123 "	mrs_s " v ", " __stringify(r) "\n"			\
1124 	UNDEFINE_MRS_S
1125 
1126 #define __msr_s(r, v)						\
1127 	DEFINE_MSR_S						\
1128 "	msr_s " __stringify(r) ", " v "\n"			\
1129 	UNDEFINE_MSR_S
1130 
1131 /*
1132  * Unlike read_cpuid, calls to read_sysreg are never expected to be
1133  * optimized away or replaced with synthetic values.
1134  */
1135 #define read_sysreg(r) ({					\
1136 	u64 __val;						\
1137 	asm volatile("mrs %0, " __stringify(r) : "=r" (__val));	\
1138 	__val;							\
1139 })
1140 
1141 /*
1142  * The "Z" constraint normally means a zero immediate, but when combined with
1143  * the "%x0" template means XZR.
1144  */
1145 #define write_sysreg(v, r) do {					\
1146 	u64 __val = (u64)(v);					\
1147 	asm volatile("msr " __stringify(r) ", %x0"		\
1148 		     : : "rZ" (__val));				\
1149 } while (0)
1150 
1151 /*
1152  * For registers without architectural names, or simply unsupported by
1153  * GAS.
1154  *
1155  * __check_r forces warnings to be generated by the compiler when
1156  * evaluating r which wouldn't normally happen due to being passed to
1157  * the assembler via __stringify(r).
1158  */
1159 #define read_sysreg_s(r) ({						\
1160 	u64 __val;							\
1161 	u32 __maybe_unused __check_r = (u32)(r);			\
1162 	asm volatile(__mrs_s("%0", r) : "=r" (__val));			\
1163 	__val;								\
1164 })
1165 
1166 #define write_sysreg_s(v, r) do {					\
1167 	u64 __val = (u64)(v);						\
1168 	u32 __maybe_unused __check_r = (u32)(r);			\
1169 	asm volatile(__msr_s(r, "%x0") : : "rZ" (__val));		\
1170 } while (0)
1171 
1172 /*
1173  * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
1174  * set mask are set. Other bits are left as-is.
1175  */
1176 #define sysreg_clear_set(sysreg, clear, set) do {			\
1177 	u64 __scs_val = read_sysreg(sysreg);				\
1178 	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
1179 	if (__scs_new != __scs_val)					\
1180 		write_sysreg(__scs_new, sysreg);			\
1181 } while (0)
1182 
1183 #define sysreg_clear_set_s(sysreg, clear, set) do {			\
1184 	u64 __scs_val = read_sysreg_s(sysreg);				\
1185 	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
1186 	if (__scs_new != __scs_val)					\
1187 		write_sysreg_s(__scs_new, sysreg);			\
1188 } while (0)
1189 
1190 #define read_sysreg_par() ({						\
1191 	u64 par;							\
1192 	asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));	\
1193 	par = read_sysreg(par_el1);					\
1194 	asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));	\
1195 	par;								\
1196 })
1197 
1198 #define SYS_FIELD_VALUE(reg, field, val)	reg##_##field##_##val
1199 
1200 #define SYS_FIELD_GET(reg, field, val)		\
1201 		 FIELD_GET(reg##_##field##_MASK, val)
1202 
1203 #define SYS_FIELD_PREP(reg, field, val)		\
1204 		 FIELD_PREP(reg##_##field##_MASK, val)
1205 
1206 #define SYS_FIELD_PREP_ENUM(reg, field, val)		\
1207 		 FIELD_PREP(reg##_##field##_MASK,	\
1208 			    SYS_FIELD_VALUE(reg, field, val))
1209 
1210 #endif
1211 
1212 #endif	/* __ASM_SYSREG_H */
1213