xref: /titanic_41/usr/src/uts/sun4v/io/n2piupc/n2piupc_biterr.h (revision ea1a228c80597366447774aa1988868492330eb5)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_N2PIUPC_BITERR_H
28 #define	_N2PIUPC_BITERR_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 /*
33  * "Virtual register" definitions for the bit error performance counters.
34  *
35  * The N2 PIU presents two bit error counters.  Bit 63 on the first counter
36  * serves as an enable for all bit error counters.   Bit 62 serves as a clear
37  * for all the bit error counters.
38  *
39  * Busstat doesn't play well with a register that has counters, enable and
40  * clear, so this module presents to the rest of the driver and to busstat a
41  * new layered set of register interfaces.
42  *
43  * These are:
44  *	SW_N2PIU_BITERR_CNT1_DATA	Biterr counter 1 data (readonly)
45  *						Maps directly to HW biterr
46  *						counter 1.  Returns data for
47  *						bad_dllps, bad_tlps,
48  *						phys_rcvr_errs
49  *
50  *	SW_N2PIU_BITERR_CNT2_DATA	Biterr counter 2 data (readonly)
51  *						Maps to HW biterr counter 2, but
52  *						offers evt select of individual
53  *						lanes 0-7 or all lanes together
54  *
55  *	SW_N2PIU_BITERR_CLR		Setting bit 62 here clears all biterr
56  *						counters (write-only)
57  *
58  *	SW_N2PIU_BITERR_SEL		Bit 63 is overall biterr enable.
59  *					Bits 0-3 are event select for counter 2
60  *					(read-write)
61  *
62  * Note: each is assigned an offset similar to the offset of real performance
63  * counter registers.  Offsets for these registers extend beyond the real reg
64  * set.
65  */
66 
67 #ifdef	__cplusplus
68 extern "C" {
69 #endif
70 
71 #include <sys/sunddi.h>
72 
73 /* SW abstractions for the BITERR counters. */
74 
75 /* Select register.  Select enable for all biterr ctrs, and PIC3 events. */
76 #define	SW_N2PIU_BITERR_SEL		HVIO_N2PIU_PERFREG_NUM_REGS
77 
78 /* Clear register.  This zeros out all biterr ctrs. */
79 #define	SW_N2PIU_BITERR_CLR		(HVIO_N2PIU_PERFREG_NUM_REGS + 1)
80 
81 /* Biterr counter 1.  Same as in the PRM. */
82 #define	SW_N2PIU_BITERR_CNT1_DATA	(HVIO_N2PIU_PERFREG_NUM_REGS + 2)
83 
84 /*
85  * Biterr counter 2.  Reports errors for all lanes, or for any individual lane.
86  * Select what to report with the SELect register above.  Enabled only if the
87  * enable for all biterr counters is enabled.
88  */
89 #define	SW_N2PIU_BITERR_CNT2_DATA	(HVIO_N2PIU_PERFREG_NUM_REGS + 3)
90 
91 /* Biterr counter abstraction functions. */
92 extern int n2piupc_biterr_attach(void **);
93 extern void n2piupc_biterr_detach(void *);
94 extern int n2piupc_biterr_write(n2piupc_t *n2piupc_p, int regid, uint64_t data);
95 extern int n2piupc_biterr_read(n2piupc_t *n2piupc_p, int regid, uint64_t *data);
96 
97 #ifdef	__cplusplus
98 }
99 #endif
100 
101 #endif	/* _N2PIUPC_BITERR_H */
102