1 /* $NetBSD: fpu_div.c,v 1.4 2005/12/11 12:18:42 christos Exp $ */
2
3 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 * Copyright (c) 1992, 1993
7 * The Regents of the University of California. All rights reserved.
8 *
9 * This software was developed by the Computer Systems Engineering group
10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
11 * contributed to Berkeley.
12 *
13 * All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Lawrence Berkeley Laboratory.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions
20 * are met:
21 * 1. Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * 3. Neither the name of the University nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * SUCH DAMAGE.
41 */
42
43 /*
44 * Perform an FPU divide (return x / y).
45 */
46
47 #include <sys/types.h>
48 #include <sys/systm.h>
49
50 #include <machine/fpu.h>
51
52 #include <powerpc/fpu/fpu_arith.h>
53 #include <powerpc/fpu/fpu_emu.h>
54
55 /*
56 * Division of normal numbers is done as follows:
57 *
58 * x and y are floating point numbers, i.e., in the form 1.bbbb * 2^e.
59 * If X and Y are the mantissas (1.bbbb's), the quotient is then:
60 *
61 * q = (X / Y) * 2^((x exponent) - (y exponent))
62 *
63 * Since X and Y are both in [1.0,2.0), the quotient's mantissa (X / Y)
64 * will be in [0.5,2.0). Moreover, it will be less than 1.0 if and only
65 * if X < Y. In that case, it will have to be shifted left one bit to
66 * become a normal number, and the exponent decremented. Thus, the
67 * desired exponent is:
68 *
69 * left_shift = x->fp_mant < y->fp_mant;
70 * result_exp = x->fp_exp - y->fp_exp - left_shift;
71 *
72 * The quotient mantissa X/Y can then be computed one bit at a time
73 * using the following algorithm:
74 *
75 * Q = 0; -- Initial quotient.
76 * R = X; -- Initial remainder,
77 * if (left_shift) -- but fixed up in advance.
78 * R *= 2;
79 * for (bit = FP_NMANT; --bit >= 0; R *= 2) {
80 * if (R >= Y) {
81 * Q |= 1 << bit;
82 * R -= Y;
83 * }
84 * }
85 *
86 * The subtraction R -= Y always removes the uppermost bit from R (and
87 * can sometimes remove additional lower-order 1 bits); this proof is
88 * left to the reader.
89 *
90 * This loop correctly calculates the guard and round bits since they are
91 * included in the expanded internal representation. The sticky bit
92 * is to be set if and only if any other bits beyond guard and round
93 * would be set. From the above it is obvious that this is true if and
94 * only if the remainder R is nonzero when the loop terminates.
95 *
96 * Examining the loop above, we can see that the quotient Q is built
97 * one bit at a time ``from the top down''. This means that we can
98 * dispense with the multi-word arithmetic and just build it one word
99 * at a time, writing each result word when it is done.
100 *
101 * Furthermore, since X and Y are both in [1.0,2.0), we know that,
102 * initially, R >= Y. (Recall that, if X < Y, R is set to X * 2 and
103 * is therefore at in [2.0,4.0).) Thus Q is sure to have bit FP_NMANT-1
104 * set, and R can be set initially to either X - Y (when X >= Y) or
105 * 2X - Y (when X < Y). In addition, comparing R and Y is difficult,
106 * so we will simply calculate R - Y and see if that underflows.
107 * This leads to the following revised version of the algorithm:
108 *
109 * R = X;
110 * bit = FP_1;
111 * D = R - Y;
112 * if (D >= 0) {
113 * result_exp = x->fp_exp - y->fp_exp;
114 * R = D;
115 * q = bit;
116 * bit >>= 1;
117 * } else {
118 * result_exp = x->fp_exp - y->fp_exp - 1;
119 * q = 0;
120 * }
121 * R <<= 1;
122 * do {
123 * D = R - Y;
124 * if (D >= 0) {
125 * q |= bit;
126 * R = D;
127 * }
128 * R <<= 1;
129 * } while ((bit >>= 1) != 0);
130 * Q[0] = q;
131 * for (i = 1; i < 4; i++) {
132 * q = 0, bit = 1 << 31;
133 * do {
134 * D = R - Y;
135 * if (D >= 0) {
136 * q |= bit;
137 * R = D;
138 * }
139 * R <<= 1;
140 * } while ((bit >>= 1) != 0);
141 * Q[i] = q;
142 * }
143 *
144 * This can be refined just a bit further by moving the `R <<= 1'
145 * calculations to the front of the do-loops and eliding the first one.
146 * The process can be terminated immediately whenever R becomes 0, but
147 * this is relatively rare, and we do not bother.
148 */
149
150 struct fpn *
fpu_div(struct fpemu * fe)151 fpu_div(struct fpemu *fe)
152 {
153 struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2;
154 u_int q, bit;
155 u_int r0, r1, r2, r3, d0, d1, d2, d3, y0, y1, y2, y3;
156 FPU_DECL_CARRY
157
158 /*
159 * Since divide is not commutative, we cannot just use ORDER.
160 * Check either operand for NaN first; if there is at least one,
161 * order the signalling one (if only one) onto the right, then
162 * return it. Otherwise we have the following cases:
163 *
164 * Inf / Inf = NaN, plus NV exception
165 * Inf / num = Inf [i.e., return x]
166 * Inf / 0 = Inf [i.e., return x]
167 * 0 / Inf = 0 [i.e., return x]
168 * 0 / num = 0 [i.e., return x]
169 * 0 / 0 = NaN, plus NV exception
170 * num / Inf = 0
171 * num / num = num (do the divide)
172 * num / 0 = Inf, plus DZ exception
173 */
174 DPRINTF(FPE_REG, ("fpu_div:\n"));
175 DUMPFPN(FPE_REG, x);
176 DUMPFPN(FPE_REG, y);
177 DPRINTF(FPE_REG, ("=>\n"));
178 if (ISNAN(x) || ISNAN(y)) {
179 ORDER(x, y);
180 fe->fe_cx |= FPSCR_VXSNAN;
181 DUMPFPN(FPE_REG, y);
182 return (y);
183 }
184 /*
185 * Need to split the following out cause they generate different
186 * exceptions.
187 */
188 if (ISINF(x)) {
189 if (x->fp_class == y->fp_class) {
190 fe->fe_cx |= FPSCR_VXIDI;
191 return (fpu_newnan(fe));
192 }
193 DUMPFPN(FPE_REG, x);
194 return (x);
195 }
196 if (ISZERO(x)) {
197 fe->fe_cx |= FPSCR_ZX;
198 if (x->fp_class == y->fp_class) {
199 fe->fe_cx |= FPSCR_VXZDZ;
200 return (fpu_newnan(fe));
201 }
202 DUMPFPN(FPE_REG, x);
203 return (x);
204 }
205
206 /* all results at this point use XOR of operand signs */
207 x->fp_sign ^= y->fp_sign;
208 if (ISINF(y)) {
209 x->fp_class = FPC_ZERO;
210 DUMPFPN(FPE_REG, x);
211 return (x);
212 }
213 if (ISZERO(y)) {
214 fe->fe_cx = FPSCR_ZX;
215 x->fp_class = FPC_INF;
216 DUMPFPN(FPE_REG, x);
217 return (x);
218 }
219
220 /*
221 * Macros for the divide. See comments at top for algorithm.
222 * Note that we expand R, D, and Y here.
223 */
224
225 #define SUBTRACT /* D = R - Y */ \
226 FPU_SUBS(d3, r3, y3); FPU_SUBCS(d2, r2, y2); \
227 FPU_SUBCS(d1, r1, y1); FPU_SUBC(d0, r0, y0)
228
229 #define NONNEGATIVE /* D >= 0 */ \
230 ((int)d0 >= 0)
231
232 #ifdef FPU_SHL1_BY_ADD
233 #define SHL1 /* R <<= 1 */ \
234 FPU_ADDS(r3, r3, r3); FPU_ADDCS(r2, r2, r2); \
235 FPU_ADDCS(r1, r1, r1); FPU_ADDC(r0, r0, r0)
236 #else
237 #define SHL1 \
238 r0 = (r0 << 1) | (r1 >> 31), r1 = (r1 << 1) | (r2 >> 31), \
239 r2 = (r2 << 1) | (r3 >> 31), r3 <<= 1
240 #endif
241
242 #define LOOP /* do ... while (bit >>= 1) */ \
243 do { \
244 SHL1; \
245 SUBTRACT; \
246 if (NONNEGATIVE) { \
247 q |= bit; \
248 r0 = d0, r1 = d1, r2 = d2, r3 = d3; \
249 } \
250 } while ((bit >>= 1) != 0)
251
252 #define WORD(r, i) /* calculate r->fp_mant[i] */ \
253 q = 0; \
254 bit = 1 << 31; \
255 LOOP; \
256 (x)->fp_mant[i] = q
257
258 /* Setup. Note that we put our result in x. */
259 r0 = x->fp_mant[0];
260 r1 = x->fp_mant[1];
261 r2 = x->fp_mant[2];
262 r3 = x->fp_mant[3];
263 y0 = y->fp_mant[0];
264 y1 = y->fp_mant[1];
265 y2 = y->fp_mant[2];
266 y3 = y->fp_mant[3];
267
268 bit = FP_1;
269 SUBTRACT;
270 if (NONNEGATIVE) {
271 x->fp_exp -= y->fp_exp;
272 r0 = d0, r1 = d1, r2 = d2, r3 = d3;
273 q = bit;
274 bit >>= 1;
275 } else {
276 x->fp_exp -= y->fp_exp + 1;
277 q = 0;
278 }
279 LOOP;
280 x->fp_mant[0] = q;
281 WORD(x, 1);
282 WORD(x, 2);
283 WORD(x, 3);
284 x->fp_sticky = r0 | r1 | r2 | r3;
285
286 DUMPFPN(FPE_REG, x);
287 return (x);
288 }
289