xref: /linux/drivers/clocksource/timer-stm32-lp.c (revision 1ac731c529cd4d6adbce134754b51ff7d822b145)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
4  * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
5  *	    Pascal Paillet <p.paillet@st.com> for STMicroelectronics.
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/clockchips.h>
10 #include <linux/interrupt.h>
11 #include <linux/mfd/stm32-lptimer.h>
12 #include <linux/module.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_wakeirq.h>
17 
18 #define CFGR_PSC_OFFSET		9
19 #define STM32_LP_RATING		1000
20 #define STM32_TARGET_CLKRATE	(32000 * HZ)
21 #define STM32_LP_MAX_PSC	7
22 
23 struct stm32_lp_private {
24 	struct regmap *reg;
25 	struct clock_event_device clkevt;
26 	unsigned long period;
27 	struct device *dev;
28 };
29 
30 static struct stm32_lp_private*
to_priv(struct clock_event_device * clkevt)31 to_priv(struct clock_event_device *clkevt)
32 {
33 	return container_of(clkevt, struct stm32_lp_private, clkevt);
34 }
35 
stm32_clkevent_lp_shutdown(struct clock_event_device * clkevt)36 static int stm32_clkevent_lp_shutdown(struct clock_event_device *clkevt)
37 {
38 	struct stm32_lp_private *priv = to_priv(clkevt);
39 
40 	regmap_write(priv->reg, STM32_LPTIM_CR, 0);
41 	regmap_write(priv->reg, STM32_LPTIM_IER, 0);
42 	/* clear pending flags */
43 	regmap_write(priv->reg, STM32_LPTIM_ICR, STM32_LPTIM_ARRMCF);
44 
45 	return 0;
46 }
47 
stm32_clkevent_lp_set_timer(unsigned long evt,struct clock_event_device * clkevt,int is_periodic)48 static int stm32_clkevent_lp_set_timer(unsigned long evt,
49 				       struct clock_event_device *clkevt,
50 				       int is_periodic)
51 {
52 	struct stm32_lp_private *priv = to_priv(clkevt);
53 
54 	/* disable LPTIMER to be able to write into IER register*/
55 	regmap_write(priv->reg, STM32_LPTIM_CR, 0);
56 	/* enable ARR interrupt */
57 	regmap_write(priv->reg, STM32_LPTIM_IER, STM32_LPTIM_ARRMIE);
58 	/* enable LPTIMER to be able to write into ARR register */
59 	regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE);
60 	/* set next event counter */
61 	regmap_write(priv->reg, STM32_LPTIM_ARR, evt);
62 
63 	/* start counter */
64 	if (is_periodic)
65 		regmap_write(priv->reg, STM32_LPTIM_CR,
66 			     STM32_LPTIM_CNTSTRT | STM32_LPTIM_ENABLE);
67 	else
68 		regmap_write(priv->reg, STM32_LPTIM_CR,
69 			     STM32_LPTIM_SNGSTRT | STM32_LPTIM_ENABLE);
70 
71 	return 0;
72 }
73 
stm32_clkevent_lp_set_next_event(unsigned long evt,struct clock_event_device * clkevt)74 static int stm32_clkevent_lp_set_next_event(unsigned long evt,
75 					    struct clock_event_device *clkevt)
76 {
77 	return stm32_clkevent_lp_set_timer(evt, clkevt,
78 					   clockevent_state_periodic(clkevt));
79 }
80 
stm32_clkevent_lp_set_periodic(struct clock_event_device * clkevt)81 static int stm32_clkevent_lp_set_periodic(struct clock_event_device *clkevt)
82 {
83 	struct stm32_lp_private *priv = to_priv(clkevt);
84 
85 	return stm32_clkevent_lp_set_timer(priv->period, clkevt, true);
86 }
87 
stm32_clkevent_lp_set_oneshot(struct clock_event_device * clkevt)88 static int stm32_clkevent_lp_set_oneshot(struct clock_event_device *clkevt)
89 {
90 	struct stm32_lp_private *priv = to_priv(clkevt);
91 
92 	return stm32_clkevent_lp_set_timer(priv->period, clkevt, false);
93 }
94 
stm32_clkevent_lp_irq_handler(int irq,void * dev_id)95 static irqreturn_t stm32_clkevent_lp_irq_handler(int irq, void *dev_id)
96 {
97 	struct clock_event_device *clkevt = (struct clock_event_device *)dev_id;
98 	struct stm32_lp_private *priv = to_priv(clkevt);
99 
100 	regmap_write(priv->reg, STM32_LPTIM_ICR, STM32_LPTIM_ARRMCF);
101 
102 	if (clkevt->event_handler)
103 		clkevt->event_handler(clkevt);
104 
105 	return IRQ_HANDLED;
106 }
107 
stm32_clkevent_lp_set_prescaler(struct stm32_lp_private * priv,unsigned long * rate)108 static void stm32_clkevent_lp_set_prescaler(struct stm32_lp_private *priv,
109 					    unsigned long *rate)
110 {
111 	int i;
112 
113 	for (i = 0; i <= STM32_LP_MAX_PSC; i++) {
114 		if (DIV_ROUND_CLOSEST(*rate, 1 << i) < STM32_TARGET_CLKRATE)
115 			break;
116 	}
117 
118 	regmap_write(priv->reg, STM32_LPTIM_CFGR, i << CFGR_PSC_OFFSET);
119 
120 	/* Adjust rate and period given the prescaler value */
121 	*rate = DIV_ROUND_CLOSEST(*rate, (1 << i));
122 	priv->period = DIV_ROUND_UP(*rate, HZ);
123 }
124 
stm32_clkevent_lp_init(struct stm32_lp_private * priv,struct device_node * np,unsigned long rate)125 static void stm32_clkevent_lp_init(struct stm32_lp_private *priv,
126 				  struct device_node *np, unsigned long rate)
127 {
128 	priv->clkevt.name = np->full_name;
129 	priv->clkevt.cpumask = cpu_possible_mask;
130 	priv->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
131 				CLOCK_EVT_FEAT_ONESHOT;
132 	priv->clkevt.set_state_shutdown = stm32_clkevent_lp_shutdown;
133 	priv->clkevt.set_state_periodic = stm32_clkevent_lp_set_periodic;
134 	priv->clkevt.set_state_oneshot = stm32_clkevent_lp_set_oneshot;
135 	priv->clkevt.set_next_event = stm32_clkevent_lp_set_next_event;
136 	priv->clkevt.rating = STM32_LP_RATING;
137 
138 	clockevents_config_and_register(&priv->clkevt, rate, 0x1,
139 					STM32_LPTIM_MAX_ARR);
140 }
141 
stm32_clkevent_lp_probe(struct platform_device * pdev)142 static int stm32_clkevent_lp_probe(struct platform_device *pdev)
143 {
144 	struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent);
145 	struct stm32_lp_private *priv;
146 	unsigned long rate;
147 	int ret, irq;
148 
149 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
150 	if (!priv)
151 		return -ENOMEM;
152 
153 	priv->reg = ddata->regmap;
154 	ret = clk_prepare_enable(ddata->clk);
155 	if (ret)
156 		return -EINVAL;
157 
158 	rate = clk_get_rate(ddata->clk);
159 	if (!rate) {
160 		ret = -EINVAL;
161 		goto out_clk_disable;
162 	}
163 
164 	irq = platform_get_irq(to_platform_device(pdev->dev.parent), 0);
165 	if (irq <= 0) {
166 		ret = irq;
167 		goto out_clk_disable;
168 	}
169 
170 	if (of_property_read_bool(pdev->dev.parent->of_node, "wakeup-source")) {
171 		ret = device_init_wakeup(&pdev->dev, true);
172 		if (ret)
173 			goto out_clk_disable;
174 
175 		ret = dev_pm_set_wake_irq(&pdev->dev, irq);
176 		if (ret)
177 			goto out_clk_disable;
178 	}
179 
180 	ret = devm_request_irq(&pdev->dev, irq, stm32_clkevent_lp_irq_handler,
181 			       IRQF_TIMER, pdev->name, &priv->clkevt);
182 	if (ret)
183 		goto out_clk_disable;
184 
185 	stm32_clkevent_lp_set_prescaler(priv, &rate);
186 
187 	stm32_clkevent_lp_init(priv, pdev->dev.parent->of_node, rate);
188 
189 	priv->dev = &pdev->dev;
190 
191 	return 0;
192 
193 out_clk_disable:
194 	clk_disable_unprepare(ddata->clk);
195 	return ret;
196 }
197 
198 static const struct of_device_id stm32_clkevent_lp_of_match[] = {
199 	{ .compatible = "st,stm32-lptimer-timer", },
200 	{},
201 };
202 MODULE_DEVICE_TABLE(of, stm32_clkevent_lp_of_match);
203 
204 static struct platform_driver stm32_clkevent_lp_driver = {
205 	.probe  = stm32_clkevent_lp_probe,
206 	.driver	= {
207 		.name = "stm32-lptimer-timer",
208 		.of_match_table = stm32_clkevent_lp_of_match,
209 		.suppress_bind_attrs = true,
210 	},
211 };
212 module_platform_driver(stm32_clkevent_lp_driver);
213 
214 MODULE_ALIAS("platform:stm32-lptimer-timer");
215 MODULE_DESCRIPTION("STMicroelectronics STM32 clockevent low power driver");
216