1 // ---------------------------------------------------------------------------- 2 // ATMEL Microcontroller Software Support - ROUSSET - 3 // ---------------------------------------------------------------------------- 4 // The software is delivered "AS IS" without warranty or condition of any 5 // kind, either express, implied or statutory. This includes without 6 // limitation any warranty or condition with respect to merchantability or 7 // fitness for any particular purpose, or against the infringements of 8 // intellectual property rights of others. 9 // ---------------------------------------------------------------------------- 10 // $FreeBSD$ 11 // 12 // File Name : AT91RM9200.h 13 // Object : AT91RM9200 definitions 14 // Generated : AT91 SW Application Group 07/04/2003 (11:05:04) 15 // 16 // CVS Reference : /AT91RM9200.pl/1.16/Fri Feb 07 09:29:50 2003// 17 // CVS Reference : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 11:44:36 2003// 18 // CVS Reference : /MC_1760A.pl/1.1/Fri Aug 23 13:38:22 2002// 19 // CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 08:36:46 2002// 20 // CVS Reference : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 08:36:48 2002// 21 // CVS Reference : /ST_1763B.pl/1.1/Fri Aug 23 13:41:42 2002// 22 // CVS Reference : /RTC_1245D.pl/1.2/Fri Jan 31 11:19:06 2003// 23 // CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 08:36:46 2002// 24 // CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 11:18:24 2003// 25 // CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 02 13:45:38 2002// 26 // CVS Reference : /MCI_1764A.pl/1.2/Thu Nov 14 16:48:24 2002// 27 // CVS Reference : /US_1739C.pl/1.2/Fri Jul 12 06:49:24 2002// 28 // CVS Reference : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 09:20:28 2002// 29 // CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 08 12:26:38 2002// 30 // CVS Reference : /TC_1753B.pl/1.2/Fri Jan 31 11:19:54 2003// 31 // CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 07 09:30:06 2003// 32 // CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 15:38:22 2002// 33 // CVS Reference : /UHP_xxxxA.pl/1.1/Mon Jul 22 11:21:58 2002// 34 // CVS Reference : /EMAC_1794A.pl/1.4/Fri Jan 17 11:11:54 2003// 35 // CVS Reference : /EBI_1759B.pl/1.10/Fri Jan 17 11:44:28 2003// 36 // CVS Reference : /SMC_1783A.pl/1.3/Thu Oct 31 13:38:16 2002// 37 // CVS Reference : /SDRC_1758B.pl/1.2/Thu Oct 03 12:04:40 2002// 38 // CVS Reference : /BFC_1757B.pl/1.3/Thu Oct 31 13:38:00 2002// 39 // ---------------------------------------------------------------------------- 40 41 #ifndef AT91RM9200_H 42 #define AT91RM9200_H 43 44 #define ATMEL_ENV 45 46 typedef volatile unsigned int AT91_REG;// Hardware register definition 47 48 // ***************************************************************************** 49 // SOFTWARE API DEFINITION FOR System Peripherals 50 // ***************************************************************************** 51 typedef struct _AT91S_SYS { 52 AT91_REG AIC_SMR[32]; // Source Mode Register 53 AT91_REG AIC_SVR[32]; // Source Vector Register 54 AT91_REG AIC_IVR; // IRQ Vector Register 55 AT91_REG AIC_FVR; // FIQ Vector Register 56 AT91_REG AIC_ISR; // Interrupt Status Register 57 AT91_REG AIC_IPR; // Interrupt Pending Register 58 AT91_REG AIC_IMR; // Interrupt Mask Register 59 AT91_REG AIC_CISR; // Core Interrupt Status Register 60 AT91_REG Reserved0[2]; // 61 AT91_REG AIC_IECR; // Interrupt Enable Command Register 62 AT91_REG AIC_IDCR; // Interrupt Disable Command Register 63 AT91_REG AIC_ICCR; // Interrupt Clear Command Register 64 AT91_REG AIC_ISCR; // Interrupt Set Command Register 65 AT91_REG AIC_EOICR; // End of Interrupt Command Register 66 AT91_REG AIC_SPU; // Spurious Vector Register 67 AT91_REG AIC_DCR; // Debug Control Register (Protect) 68 AT91_REG Reserved1[1]; // 69 AT91_REG AIC_FFER; // Fast Forcing Enable Register 70 AT91_REG AIC_FFDR; // Fast Forcing Disable Register 71 AT91_REG AIC_FFSR; // Fast Forcing Status Register 72 AT91_REG Reserved2[45]; // 73 AT91_REG DBGU_CR; // Control Register 74 AT91_REG DBGU_MR; // Mode Register 75 AT91_REG DBGU_IER; // Interrupt Enable Register 76 AT91_REG DBGU_IDR; // Interrupt Disable Register 77 AT91_REG DBGU_IMR; // Interrupt Mask Register 78 AT91_REG DBGU_CSR; // Channel Status Register 79 AT91_REG DBGU_RHR; // Receiver Holding Register 80 AT91_REG DBGU_THR; // Transmitter Holding Register 81 AT91_REG DBGU_BRGR; // Baud Rate Generator Register 82 AT91_REG Reserved3[7]; // 83 AT91_REG DBGU_C1R; // Chip ID1 Register 84 AT91_REG DBGU_C2R; // Chip ID2 Register 85 AT91_REG DBGU_FNTR; // Force NTRST Register 86 AT91_REG Reserved4[45]; // 87 AT91_REG DBGU_RPR; // Receive Pointer Register 88 AT91_REG DBGU_RCR; // Receive Counter Register 89 AT91_REG DBGU_TPR; // Transmit Pointer Register 90 AT91_REG DBGU_TCR; // Transmit Counter Register 91 AT91_REG DBGU_RNPR; // Receive Next Pointer Register 92 AT91_REG DBGU_RNCR; // Receive Next Counter Register 93 AT91_REG DBGU_TNPR; // Transmit Next Pointer Register 94 AT91_REG DBGU_TNCR; // Transmit Next Counter Register 95 AT91_REG DBGU_PTCR; // PDC Transfer Control Register 96 AT91_REG DBGU_PTSR; // PDC Transfer Status Register 97 AT91_REG Reserved5[54]; // 98 AT91_REG PIOA_PER; // PIO Enable Register 99 AT91_REG PIOA_PDR; // PIO Disable Register 100 AT91_REG PIOA_PSR; // PIO Status Register 101 AT91_REG Reserved6[1]; // 102 AT91_REG PIOA_OER; // Output Enable Register 103 AT91_REG PIOA_ODR; // Output Disable Registerr 104 AT91_REG PIOA_OSR; // Output Status Register 105 AT91_REG Reserved7[1]; // 106 AT91_REG PIOA_IFER; // Input Filter Enable Register 107 AT91_REG PIOA_IFDR; // Input Filter Disable Register 108 AT91_REG PIOA_IFSR; // Input Filter Status Register 109 AT91_REG Reserved8[1]; // 110 AT91_REG PIOA_SODR; // Set Output Data Register 111 AT91_REG PIOA_CODR; // Clear Output Data Register 112 AT91_REG PIOA_ODSR; // Output Data Status Register 113 AT91_REG PIOA_PDSR; // Pin Data Status Register 114 AT91_REG PIOA_IER; // Interrupt Enable Register 115 AT91_REG PIOA_IDR; // Interrupt Disable Register 116 AT91_REG PIOA_IMR; // Interrupt Mask Register 117 AT91_REG PIOA_ISR; // Interrupt Status Register 118 AT91_REG PIOA_MDER; // Multi-driver Enable Register 119 AT91_REG PIOA_MDDR; // Multi-driver Disable Register 120 AT91_REG PIOA_MDSR; // Multi-driver Status Register 121 AT91_REG Reserved9[1]; // 122 AT91_REG PIOA_PPUDR; // Pull-up Disable Register 123 AT91_REG PIOA_PPUER; // Pull-up Enable Register 124 AT91_REG PIOA_PPUSR; // Pad Pull-up Status Register 125 AT91_REG Reserved10[1]; // 126 AT91_REG PIOA_ASR; // Select A Register 127 AT91_REG PIOA_BSR; // Select B Register 128 AT91_REG PIOA_ABSR; // AB Select Status Register 129 AT91_REG Reserved11[9]; // 130 AT91_REG PIOA_OWER; // Output Write Enable Register 131 AT91_REG PIOA_OWDR; // Output Write Disable Register 132 AT91_REG PIOA_OWSR; // Output Write Status Register 133 AT91_REG Reserved12[85]; // 134 AT91_REG PIOB_PER; // PIO Enable Register 135 AT91_REG PIOB_PDR; // PIO Disable Register 136 AT91_REG PIOB_PSR; // PIO Status Register 137 AT91_REG Reserved13[1]; // 138 AT91_REG PIOB_OER; // Output Enable Register 139 AT91_REG PIOB_ODR; // Output Disable Registerr 140 AT91_REG PIOB_OSR; // Output Status Register 141 AT91_REG Reserved14[1]; // 142 AT91_REG PIOB_IFER; // Input Filter Enable Register 143 AT91_REG PIOB_IFDR; // Input Filter Disable Register 144 AT91_REG PIOB_IFSR; // Input Filter Status Register 145 AT91_REG Reserved15[1]; // 146 AT91_REG PIOB_SODR; // Set Output Data Register 147 AT91_REG PIOB_CODR; // Clear Output Data Register 148 AT91_REG PIOB_ODSR; // Output Data Status Register 149 AT91_REG PIOB_PDSR; // Pin Data Status Register 150 AT91_REG PIOB_IER; // Interrupt Enable Register 151 AT91_REG PIOB_IDR; // Interrupt Disable Register 152 AT91_REG PIOB_IMR; // Interrupt Mask Register 153 AT91_REG PIOB_ISR; // Interrupt Status Register 154 AT91_REG PIOB_MDER; // Multi-driver Enable Register 155 AT91_REG PIOB_MDDR; // Multi-driver Disable Register 156 AT91_REG PIOB_MDSR; // Multi-driver Status Register 157 AT91_REG Reserved16[1]; // 158 AT91_REG PIOB_PPUDR; // Pull-up Disable Register 159 AT91_REG PIOB_PPUER; // Pull-up Enable Register 160 AT91_REG PIOB_PPUSR; // Pad Pull-up Status Register 161 AT91_REG Reserved17[1]; // 162 AT91_REG PIOB_ASR; // Select A Register 163 AT91_REG PIOB_BSR; // Select B Register 164 AT91_REG PIOB_ABSR; // AB Select Status Register 165 AT91_REG Reserved18[9]; // 166 AT91_REG PIOB_OWER; // Output Write Enable Register 167 AT91_REG PIOB_OWDR; // Output Write Disable Register 168 AT91_REG PIOB_OWSR; // Output Write Status Register 169 AT91_REG Reserved19[85]; // 170 AT91_REG PIOC_PER; // PIO Enable Register 171 AT91_REG PIOC_PDR; // PIO Disable Register 172 AT91_REG PIOC_PSR; // PIO Status Register 173 AT91_REG Reserved20[1]; // 174 AT91_REG PIOC_OER; // Output Enable Register 175 AT91_REG PIOC_ODR; // Output Disable Registerr 176 AT91_REG PIOC_OSR; // Output Status Register 177 AT91_REG Reserved21[1]; // 178 AT91_REG PIOC_IFER; // Input Filter Enable Register 179 AT91_REG PIOC_IFDR; // Input Filter Disable Register 180 AT91_REG PIOC_IFSR; // Input Filter Status Register 181 AT91_REG Reserved22[1]; // 182 AT91_REG PIOC_SODR; // Set Output Data Register 183 AT91_REG PIOC_CODR; // Clear Output Data Register 184 AT91_REG PIOC_ODSR; // Output Data Status Register 185 AT91_REG PIOC_PDSR; // Pin Data Status Register 186 AT91_REG PIOC_IER; // Interrupt Enable Register 187 AT91_REG PIOC_IDR; // Interrupt Disable Register 188 AT91_REG PIOC_IMR; // Interrupt Mask Register 189 AT91_REG PIOC_ISR; // Interrupt Status Register 190 AT91_REG PIOC_MDER; // Multi-driver Enable Register 191 AT91_REG PIOC_MDDR; // Multi-driver Disable Register 192 AT91_REG PIOC_MDSR; // Multi-driver Status Register 193 AT91_REG Reserved23[1]; // 194 AT91_REG PIOC_PPUDR; // Pull-up Disable Register 195 AT91_REG PIOC_PPUER; // Pull-up Enable Register 196 AT91_REG PIOC_PPUSR; // Pad Pull-up Status Register 197 AT91_REG Reserved24[1]; // 198 AT91_REG PIOC_ASR; // Select A Register 199 AT91_REG PIOC_BSR; // Select B Register 200 AT91_REG PIOC_ABSR; // AB Select Status Register 201 AT91_REG Reserved25[9]; // 202 AT91_REG PIOC_OWER; // Output Write Enable Register 203 AT91_REG PIOC_OWDR; // Output Write Disable Register 204 AT91_REG PIOC_OWSR; // Output Write Status Register 205 AT91_REG Reserved26[85]; // 206 AT91_REG PIOD_PER; // PIO Enable Register 207 AT91_REG PIOD_PDR; // PIO Disable Register 208 AT91_REG PIOD_PSR; // PIO Status Register 209 AT91_REG Reserved27[1]; // 210 AT91_REG PIOD_OER; // Output Enable Register 211 AT91_REG PIOD_ODR; // Output Disable Registerr 212 AT91_REG PIOD_OSR; // Output Status Register 213 AT91_REG Reserved28[1]; // 214 AT91_REG PIOD_IFER; // Input Filter Enable Register 215 AT91_REG PIOD_IFDR; // Input Filter Disable Register 216 AT91_REG PIOD_IFSR; // Input Filter Status Register 217 AT91_REG Reserved29[1]; // 218 AT91_REG PIOD_SODR; // Set Output Data Register 219 AT91_REG PIOD_CODR; // Clear Output Data Register 220 AT91_REG PIOD_ODSR; // Output Data Status Register 221 AT91_REG PIOD_PDSR; // Pin Data Status Register 222 AT91_REG PIOD_IER; // Interrupt Enable Register 223 AT91_REG PIOD_IDR; // Interrupt Disable Register 224 AT91_REG PIOD_IMR; // Interrupt Mask Register 225 AT91_REG PIOD_ISR; // Interrupt Status Register 226 AT91_REG PIOD_MDER; // Multi-driver Enable Register 227 AT91_REG PIOD_MDDR; // Multi-driver Disable Register 228 AT91_REG PIOD_MDSR; // Multi-driver Status Register 229 AT91_REG Reserved30[1]; // 230 AT91_REG PIOD_PPUDR; // Pull-up Disable Register 231 AT91_REG PIOD_PPUER; // Pull-up Enable Register 232 AT91_REG PIOD_PPUSR; // Pad Pull-up Status Register 233 AT91_REG Reserved31[1]; // 234 AT91_REG PIOD_ASR; // Select A Register 235 AT91_REG PIOD_BSR; // Select B Register 236 AT91_REG PIOD_ABSR; // AB Select Status Register 237 AT91_REG Reserved32[9]; // 238 AT91_REG PIOD_OWER; // Output Write Enable Register 239 AT91_REG PIOD_OWDR; // Output Write Disable Register 240 AT91_REG PIOD_OWSR; // Output Write Status Register 241 AT91_REG Reserved33[85]; // 242 AT91_REG PMC_SCER; // System Clock Enable Register 243 AT91_REG PMC_SCDR; // System Clock Disable Register 244 AT91_REG PMC_SCSR; // System Clock Status Register 245 AT91_REG Reserved34[1]; // 246 AT91_REG PMC_PCER; // Peripheral Clock Enable Register 247 AT91_REG PMC_PCDR; // Peripheral Clock Disable Register 248 AT91_REG PMC_PCSR; // Peripheral Clock Status Register 249 AT91_REG Reserved35[1]; // 250 AT91_REG CKGR_MOR; // Main Oscillator Register 251 AT91_REG CKGR_MCFR; // Main Clock Frequency Register 252 AT91_REG CKGR_PLLAR; // PLL A Register 253 AT91_REG CKGR_PLLBR; // PLL B Register 254 AT91_REG PMC_MCKR; // Master Clock Register 255 AT91_REG Reserved36[3]; // 256 AT91_REG PMC_PCKR[8]; // Programmable Clock Register 257 AT91_REG PMC_IER; // Interrupt Enable Register 258 AT91_REG PMC_IDR; // Interrupt Disable Register 259 AT91_REG PMC_SR; // Status Register 260 AT91_REG PMC_IMR; // Interrupt Mask Register 261 AT91_REG Reserved37[36]; // 262 AT91_REG ST_CR; // Control Register 263 AT91_REG ST_PIMR; // Period Interval Mode Register 264 AT91_REG ST_WDMR; // Watchdog Mode Register 265 AT91_REG ST_RTMR; // Real-time Mode Register 266 AT91_REG ST_SR; // Status Register 267 AT91_REG ST_IER; // Interrupt Enable Register 268 AT91_REG ST_IDR; // Interrupt Disable Register 269 AT91_REG ST_IMR; // Interrupt Mask Register 270 AT91_REG ST_RTAR; // Real-time Alarm Register 271 AT91_REG ST_CRTR; // Current Real-time Register 272 AT91_REG Reserved38[54]; // 273 AT91_REG RTC_CR; // Control Register 274 AT91_REG RTC_MR; // Mode Register 275 AT91_REG RTC_TIMR; // Time Register 276 AT91_REG RTC_CALR; // Calendar Register 277 AT91_REG RTC_TIMALR; // Time Alarm Register 278 AT91_REG RTC_CALALR; // Calendar Alarm Register 279 AT91_REG RTC_SR; // Status Register 280 AT91_REG RTC_SCCR; // Status Clear Command Register 281 AT91_REG RTC_IER; // Interrupt Enable Register 282 AT91_REG RTC_IDR; // Interrupt Disable Register 283 AT91_REG RTC_IMR; // Interrupt Mask Register 284 AT91_REG RTC_VER; // Valid Entry Register 285 AT91_REG Reserved39[52]; // 286 AT91_REG MC_RCR; // MC Remap Control Register 287 AT91_REG MC_ASR; // MC Abort Status Register 288 AT91_REG MC_AASR; // MC Abort Address Status Register 289 AT91_REG Reserved40[1]; // 290 AT91_REG MC_PUIA[16]; // MC Protection Unit Area 291 AT91_REG MC_PUP; // MC Protection Unit Peripherals 292 AT91_REG MC_PUER; // MC Protection Unit Enable Register 293 AT91_REG Reserved41[2]; // 294 AT91_REG EBI_CSA; // Chip Select Assignment Register 295 AT91_REG EBI_CFGR; // Configuration Register 296 AT91_REG Reserved42[2]; // 297 AT91_REG EBI_SMC2_CSR[8]; // SMC2 Chip Select Register 298 AT91_REG EBI_SDRC_MR; // SDRAM Controller Mode Register 299 AT91_REG EBI_SDRC_TR; // SDRAM Controller Refresh Timer Register 300 AT91_REG EBI_SDRC_CR; // SDRAM Controller Configuration Register 301 AT91_REG EBI_SDRC_SRR; // SDRAM Controller Self Refresh Register 302 AT91_REG EBI_SDRC_LPR; // SDRAM Controller Low Power Register 303 AT91_REG EBI_SDRC_IER; // SDRAM Controller Interrupt Enable Register 304 AT91_REG EBI_SDRC_IDR; // SDRAM Controller Interrupt Disable Register 305 AT91_REG EBI_SDRC_IMR; // SDRAM Controller Interrupt Mask Register 306 AT91_REG EBI_SDRC_ISR; // SDRAM Controller Interrupt Mask Register 307 AT91_REG Reserved43[3]; // 308 AT91_REG EBI_BFC_MR; // BFC Mode Register 309 } AT91S_SYS, *AT91PS_SYS; 310 311 312 // ***************************************************************************** 313 // SOFTWARE API DEFINITION FOR Memory Controller Interface 314 // ***************************************************************************** 315 typedef struct _AT91S_MC { 316 AT91_REG MC_RCR; // MC Remap Control Register 317 AT91_REG MC_ASR; // MC Abort Status Register 318 AT91_REG MC_AASR; // MC Abort Address Status Register 319 AT91_REG Reserved0[1]; // 320 AT91_REG MC_PUIA[16]; // MC Protection Unit Area 321 AT91_REG MC_PUP; // MC Protection Unit Peripherals 322 AT91_REG MC_PUER; // MC Protection Unit Enable Register 323 } AT91S_MC, *AT91PS_MC; 324 325 // -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 326 #define AT91C_MC_RCB (0x1u << 0) // (MC) Remap Command Bit 327 // -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 328 #define AT91C_MC_UNDADD (0x1u << 0) // (MC) Undefined Addess Abort Status 329 #define AT91C_MC_MISADD (0x1u << 1) // (MC) Misaligned Addess Abort Status 330 #define AT91C_MC_MPU (0x1u << 2) // (MC) Memory protection Unit Abort Status 331 #define AT91C_MC_ABTSZ (0x3u << 8) // (MC) Abort Size Status 332 #define AT91C_MC_ABTSZ_BYTE (0x0u << 8) // (MC) Byte 333 #define AT91C_MC_ABTSZ_HWORD (0x1u << 8) // (MC) Half-word 334 #define AT91C_MC_ABTSZ_WORD (0x2u << 8) // (MC) Word 335 #define AT91C_MC_ABTTYP (0x3u << 10) // (MC) Abort Type Status 336 #define AT91C_MC_ABTTYP_DATAR (0x0u << 10) // (MC) Data Read 337 #define AT91C_MC_ABTTYP_DATAW (0x1u << 10) // (MC) Data Write 338 #define AT91C_MC_ABTTYP_FETCH (0x2u << 10) // (MC) Code Fetch 339 #define AT91C_MC_MST0 (0x1u << 16) // (MC) Master 0 Abort Source 340 #define AT91C_MC_MST1 (0x1u << 17) // (MC) Master 1 Abort Source 341 #define AT91C_MC_SVMST0 (0x1u << 24) // (MC) Saved Master 0 Abort Source 342 #define AT91C_MC_SVMST1 (0x1u << 25) // (MC) Saved Master 1 Abort Source 343 // -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- 344 #define AT91C_MC_PROT (0x3u << 0) // (MC) Protection 345 #define AT91C_MC_PROT_PNAUNA 0x0u // (MC) Privilege: No Access, User: No Access 346 #define AT91C_MC_PROT_PRWUNA 0x1u // (MC) Privilege: Read/Write, User: No Access 347 #define AT91C_MC_PROT_PRWURO 0x2u // (MC) Privilege: Read/Write, User: Read Only 348 #define AT91C_MC_PROT_PRWURW 0x3u // (MC) Privilege: Read/Write, User: Read/Write 349 #define AT91C_MC_SIZE (0xFu << 4) // (MC) Internal Area Size 350 #define AT91C_MC_SIZE_1KB (0x0u << 4) // (MC) Area size 1KByte 351 #define AT91C_MC_SIZE_2KB (0x1u << 4) // (MC) Area size 2KByte 352 #define AT91C_MC_SIZE_4KB (0x2u << 4) // (MC) Area size 4KByte 353 #define AT91C_MC_SIZE_8KB (0x3u << 4) // (MC) Area size 8KByte 354 #define AT91C_MC_SIZE_16KB (0x4u << 4) // (MC) Area size 16KByte 355 #define AT91C_MC_SIZE_32KB (0x5u << 4) // (MC) Area size 32KByte 356 #define AT91C_MC_SIZE_64KB (0x6u << 4) // (MC) Area size 64KByte 357 #define AT91C_MC_SIZE_128KB (0x7u << 4) // (MC) Area size 128KByte 358 #define AT91C_MC_SIZE_256KB (0x8u << 4) // (MC) Area size 256KByte 359 #define AT91C_MC_SIZE_512KB (0x9u << 4) // (MC) Area size 512KByte 360 #define AT91C_MC_SIZE_1MB (0xAu << 4) // (MC) Area size 1MByte 361 #define AT91C_MC_SIZE_2MB (0xBu << 4) // (MC) Area size 2MByte 362 #define AT91C_MC_SIZE_4MB (0xCu << 4) // (MC) Area size 4MByte 363 #define AT91C_MC_SIZE_8MB (0xDu << 4) // (MC) Area size 8MByte 364 #define AT91C_MC_SIZE_16MB (0xEu << 4) // (MC) Area size 16MByte 365 #define AT91C_MC_SIZE_64MB (0xFu << 4) // (MC) Area size 64MByte 366 #define AT91C_MC_BA (0x3FFFFu << 10) // (MC) Internal Area Base Address 367 // -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- 368 // -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- 369 #define AT91C_MC_PUEB (0x1u << 0) // (MC) Protection Unit enable Bit 370 371 // ***************************************************************************** 372 // SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface 373 // ***************************************************************************** 374 typedef struct _AT91S_RTC { 375 AT91_REG RTC_CR; // Control Register 376 AT91_REG RTC_MR; // Mode Register 377 AT91_REG RTC_TIMR; // Time Register 378 AT91_REG RTC_CALR; // Calendar Register 379 AT91_REG RTC_TIMALR; // Time Alarm Register 380 AT91_REG RTC_CALALR; // Calendar Alarm Register 381 AT91_REG RTC_SR; // Status Register 382 AT91_REG RTC_SCCR; // Status Clear Command Register 383 AT91_REG RTC_IER; // Interrupt Enable Register 384 AT91_REG RTC_IDR; // Interrupt Disable Register 385 AT91_REG RTC_IMR; // Interrupt Mask Register 386 AT91_REG RTC_VER; // Valid Entry Register 387 } AT91S_RTC, *AT91PS_RTC; 388 389 // -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- 390 #define AT91C_RTC_UPDTIM (0x1u << 0) // (RTC) Update Request Time Register 391 #define AT91C_RTC_UPDCAL (0x1u << 1) // (RTC) Update Request Calendar Register 392 #define AT91C_RTC_TIMEVSEL (0x3u << 8) // (RTC) Time Event Selection 393 #define AT91C_RTC_TIMEVSEL_MINUTE (0x0u << 8) // (RTC) Minute change. 394 #define AT91C_RTC_TIMEVSEL_HOUR (0x1u << 8) // (RTC) Hour change. 395 #define AT91C_RTC_TIMEVSEL_DAY24 (0x2u << 8) // (RTC) Every day at midnight. 396 #define AT91C_RTC_TIMEVSEL_DAY12 (0x3u << 8) // (RTC) Every day at noon. 397 #define AT91C_RTC_CALEVSEL (0x3u << 16) // (RTC) Calendar Event Selection 398 #define AT91C_RTC_CALEVSEL_WEEK (0x0u << 16) // (RTC) Week change (every Monday at time 00:00:00). 399 #define AT91C_RTC_CALEVSEL_MONTH (0x1u << 16) // (RTC) Month change (every 01 of each month at time 00:00:00). 400 #define AT91C_RTC_CALEVSEL_YEAR (0x2u << 16) // (RTC) Year change (every January 1 at time 00:00:00). 401 // -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- 402 #define AT91C_RTC_HRMOD (0x1u << 0) // (RTC) 12-24 hour Mode 403 // -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- 404 #define AT91C_RTC_SEC (0x7Fu << 0) // (RTC) Current Second 405 #define AT91C_RTC_MIN (0x7Fu << 8) // (RTC) Current Minute 406 #define AT91C_RTC_HOUR (0x1Fu << 16) // (RTC) Current Hour 407 #define AT91C_RTC_AMPM (0x1u << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator 408 // -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- 409 #define AT91C_RTC_CENT (0x3Fu << 0) // (RTC) Current Century 410 #define AT91C_RTC_YEAR (0xFFu << 8) // (RTC) Current Year 411 #define AT91C_RTC_MONTH (0x1Fu << 16) // (RTC) Current Month 412 #define AT91C_RTC_DAY (0x7u << 21) // (RTC) Current Day 413 #define AT91C_RTC_DATE (0x3Fu << 24) // (RTC) Current Date 414 // -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- 415 #define AT91C_RTC_SECEN (0x1u << 7) // (RTC) Second Alarm Enable 416 #define AT91C_RTC_MINEN (0x1u << 15) // (RTC) Minute Alarm 417 #define AT91C_RTC_HOUREN (0x1u << 23) // (RTC) Current Hour 418 // -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- 419 #define AT91C_RTC_MONTHEN (0x1u << 23) // (RTC) Month Alarm Enable 420 #define AT91C_RTC_DATEEN (0x1u << 31) // (RTC) Date Alarm Enable 421 // -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- 422 #define AT91C_RTC_ACKUPD (0x1u << 0) // (RTC) Acknowledge for Update 423 #define AT91C_RTC_ALARM (0x1u << 1) // (RTC) Alarm Flag 424 #define AT91C_RTC_SECEV (0x1u << 2) // (RTC) Second Event 425 #define AT91C_RTC_TIMEV (0x1u << 3) // (RTC) Time Event 426 #define AT91C_RTC_CALEV (0x1u << 4) // (RTC) Calendar event 427 // -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- 428 // -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- 429 // -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- 430 // -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- 431 // -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- 432 #define AT91C_RTC_NVTIM (0x1u << 0) // (RTC) Non valid Time 433 #define AT91C_RTC_NVCAL (0x1u << 1) // (RTC) Non valid Calendar 434 #define AT91C_RTC_NVTIMALR (0x1u << 2) // (RTC) Non valid time Alarm 435 #define AT91C_RTC_NVCALALR (0x1u << 3) // (RTC) Nonvalid Calendar Alarm 436 437 // ***************************************************************************** 438 // SOFTWARE API DEFINITION FOR System Timer Interface 439 // ***************************************************************************** 440 typedef struct _AT91S_ST { 441 AT91_REG ST_CR; // Control Register 442 AT91_REG ST_PIMR; // Period Interval Mode Register 443 AT91_REG ST_WDMR; // Watchdog Mode Register 444 AT91_REG ST_RTMR; // Real-time Mode Register 445 AT91_REG ST_SR; // Status Register 446 AT91_REG ST_IER; // Interrupt Enable Register 447 AT91_REG ST_IDR; // Interrupt Disable Register 448 AT91_REG ST_IMR; // Interrupt Mask Register 449 AT91_REG ST_RTAR; // Real-time Alarm Register 450 AT91_REG ST_CRTR; // Current Real-time Register 451 } AT91S_ST, *AT91PS_ST; 452 453 // -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- 454 #define AT91C_ST_WDRST (0x1u << 0) // (ST) Watchdog Timer Restart 455 // -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- 456 #define AT91C_ST_PIV (0xFFFFu << 0) // (ST) Watchdog Timer Restart 457 // -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- 458 #define AT91C_ST_WDV (0xFFFFu << 0) // (ST) Watchdog Timer Restart 459 #define AT91C_ST_RSTEN (0x1u << 16) // (ST) Reset Enable 460 #define AT91C_ST_EXTEN (0x1u << 17) // (ST) External Signal Assertion Enable 461 // -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- 462 #define AT91C_ST_RTPRES (0xFFFFu << 0) // (ST) Real-time Timer Prescaler Value 463 // -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- 464 #define AT91C_ST_PITS (0x1u << 0) // (ST) Period Interval Timer Interrupt 465 #define AT91C_ST_WDOVF (0x1u << 1) // (ST) Watchdog Overflow 466 #define AT91C_ST_RTTINC (0x1u << 2) // (ST) Real-time Timer Increment 467 #define AT91C_ST_ALMS (0x1u << 3) // (ST) Alarm Status 468 // -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- 469 // -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- 470 // -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- 471 // -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- 472 #define AT91C_ST_ALMV (0xFFFFFu << 0) // (ST) Alarm Value Value 473 // -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- 474 #define AT91C_ST_CRTV (0xFFFFFu << 0) // (ST) Current Real-time Value 475 476 // ***************************************************************************** 477 // SOFTWARE API DEFINITION FOR Power Management Controller 478 // ***************************************************************************** 479 typedef struct _AT91S_PMC { 480 AT91_REG PMC_SCER; // System Clock Enable Register 481 AT91_REG PMC_SCDR; // System Clock Disable Register 482 AT91_REG PMC_SCSR; // System Clock Status Register 483 AT91_REG Reserved0[1]; // 484 AT91_REG PMC_PCER; // Peripheral Clock Enable Register 485 AT91_REG PMC_PCDR; // Peripheral Clock Disable Register 486 AT91_REG PMC_PCSR; // Peripheral Clock Status Register 487 AT91_REG Reserved1[5]; // 488 AT91_REG PMC_MCKR; // Master Clock Register 489 AT91_REG Reserved2[3]; // 490 AT91_REG PMC_PCKR[8]; // Programmable Clock Register 491 AT91_REG PMC_IER; // Interrupt Enable Register 492 AT91_REG PMC_IDR; // Interrupt Disable Register 493 AT91_REG PMC_SR; // Status Register 494 AT91_REG PMC_IMR; // Interrupt Mask Register 495 } AT91S_PMC, *AT91PS_PMC; 496 497 // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 498 #define AT91C_PMC_PCK (0x1u << 0) // (PMC) Processor Clock 499 #define AT91C_PMC_UDP (0x1u << 1) // (PMC) USB Device Port Clock 500 #define AT91C_PMC_MCKUDP (0x1u << 2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend 501 #define AT91C_PMC_UHP (0x1u << 4) // (PMC) USB Host Port Clock 502 #define AT91C_PMC_PCK0 (0x1u << 8) // (PMC) Programmable Clock Output 503 #define AT91C_PMC_PCK1 (0x1u << 9) // (PMC) Programmable Clock Output 504 #define AT91C_PMC_PCK2 (0x1u << 10) // (PMC) Programmable Clock Output 505 #define AT91C_PMC_PCK3 (0x1u << 11) // (PMC) Programmable Clock Output 506 #define AT91C_PMC_PCK4 (0x1u << 12) // (PMC) Programmable Clock Output 507 #define AT91C_PMC_PCK5 (0x1u << 13) // (PMC) Programmable Clock Output 508 #define AT91C_PMC_PCK6 (0x1u << 14) // (PMC) Programmable Clock Output 509 #define AT91C_PMC_PCK7 (0x1u << 15) // (PMC) Programmable Clock Output 510 // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 511 // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 512 // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 513 #define AT91C_PMC_CSS (0x3u << 0) // (PMC) Programmable Clock Selection 514 #define AT91C_PMC_CSS_SLOW_CLK 0x0u // (PMC) Slow Clock is selected 515 #define AT91C_PMC_CSS_MAIN_CLK 0x1u // (PMC) Main Clock is selected 516 #define AT91C_PMC_CSS_PLLA_CLK 0x2u // (PMC) Clock from PLL A is selected 517 #define AT91C_PMC_CSS_PLLB_CLK 0x3u // (PMC) Clock from PLL B is selected 518 #define AT91C_PMC_PRES (0x7u << 2) // (PMC) Programmable Clock Prescaler 519 #define AT91C_PMC_PRES_CLK (0x0u << 2) // (PMC) Selected clock 520 #define AT91C_PMC_PRES_CLK_2 (0x1u << 2) // (PMC) Selected clock divided by 2 521 #define AT91C_PMC_PRES_CLK_4 (0x2u << 2) // (PMC) Selected clock divided by 4 522 #define AT91C_PMC_PRES_CLK_8 (0x3u << 2) // (PMC) Selected clock divided by 8 523 #define AT91C_PMC_PRES_CLK_16 (0x4u << 2) // (PMC) Selected clock divided by 16 524 #define AT91C_PMC_PRES_CLK_32 (0x5u << 2) // (PMC) Selected clock divided by 32 525 #define AT91C_PMC_PRES_CLK_64 (0x6u << 2) // (PMC) Selected clock divided by 64 526 #define AT91C_PMC_MDIV (0x3u << 8) // (PMC) Master Clock Division 527 #define AT91C_PMC_MDIV_1 (0x0u << 8) // (PMC) The master clock and the processor clock are the same 528 #define AT91C_PMC_MDIV_2 (0x1u << 8) // (PMC) The processor clock is twice as fast as the master clock 529 #define AT91C_PMC_MDIV_3 (0x2u << 8) // (PMC) The processor clock is three times faster than the master clock 530 #define AT91C_PMC_MDIV_4 (0x3u << 8) // (PMC) The processor clock is four times faster than the master clock 531 // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 532 // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 533 #define AT91C_PMC_MOSCS (0x1u << 0) // (PMC) MOSC Status/Enable/Disable/Mask 534 #define AT91C_PMC_LOCKA (0x1u << 1) // (PMC) PLL A Status/Enable/Disable/Mask 535 #define AT91C_PMC_LOCKB (0x1u << 2) // (PMC) PLL B Status/Enable/Disable/Mask 536 #define AT91C_PMC_MCKRDY (0x1u << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask 537 #define AT91C_PMC_PCK0RDY (0x1u << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask 538 #define AT91C_PMC_PCK1RDY (0x1u << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask 539 #define AT91C_PMC_PCK2RDY (0x1u << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask 540 #define AT91C_PMC_PCK3RDY (0x1u << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask 541 #define AT91C_PMC_PCK4RDY (0x1u << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask 542 #define AT91C_PMC_PCK5RDY (0x1u << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask 543 #define AT91C_PMC_PCK6RDY (0x1u << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask 544 #define AT91C_PMC_PCK7RDY (0x1u << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask 545 // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 546 // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 547 // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 548 549 // ***************************************************************************** 550 // SOFTWARE API DEFINITION FOR Clock Generator Controller 551 // ***************************************************************************** 552 typedef struct _AT91S_CKGR { 553 AT91_REG CKGR_MOR; // Main Oscillator Register 554 AT91_REG CKGR_MCFR; // Main Clock Frequency Register 555 AT91_REG CKGR_PLLAR; // PLL A Register 556 AT91_REG CKGR_PLLBR; // PLL B Register 557 } AT91S_CKGR, *AT91PS_CKGR; 558 559 // -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 560 #define AT91C_CKGR_MOSCEN (0x1u << 0) // (CKGR) Main Oscillator Enable 561 #define AT91C_CKGR_OSCTEST (0x1u << 1) // (CKGR) Oscillator Test 562 #define AT91C_CKGR_OSCOUNT (0xFFu << 8) // (CKGR) Main Oscillator Start-up Time 563 // -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 564 #define AT91C_CKGR_MAINF (0xFFFFu << 0) // (CKGR) Main Clock Frequency 565 #define AT91C_CKGR_MAINRDY (0x1u << 16) // (CKGR) Main Clock Ready 566 // -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- 567 #define AT91C_CKGR_DIVA (0xFFu << 0) // (CKGR) Divider Selected 568 #define AT91C_CKGR_DIVA_0 0x0u // (CKGR) Divider output is 0 569 #define AT91C_CKGR_DIVA_BYPASS 0x1u // (CKGR) Divider is bypassed 570 #define AT91C_CKGR_PLLACOUNT (0x3Fu << 8) // (CKGR) PLL A Counter 571 #define AT91C_CKGR_OUTA (0x3u << 14) // (CKGR) PLL A Output Frequency Range 572 #define AT91C_CKGR_OUTA_0 (0x0u << 14) // (CKGR) Please refer to the PLLA datasheet 573 #define AT91C_CKGR_OUTA_1 (0x1u << 14) // (CKGR) Please refer to the PLLA datasheet 574 #define AT91C_CKGR_OUTA_2 (0x2u << 14) // (CKGR) Please refer to the PLLA datasheet 575 #define AT91C_CKGR_OUTA_3 (0x3u << 14) // (CKGR) Please refer to the PLLA datasheet 576 #define AT91C_CKGR_MULA (0x7FFu << 16) // (CKGR) PLL A Multiplier 577 #define AT91C_CKGR_SRCA (0x1u << 29) // (CKGR) PLL A Source 578 // -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- 579 #define AT91C_CKGR_DIVB (0xFFu << 0) // (CKGR) Divider Selected 580 #define AT91C_CKGR_DIVB_0 0x0u // (CKGR) Divider output is 0 581 #define AT91C_CKGR_DIVB_BYPASS 0x1u // (CKGR) Divider is bypassed 582 #define AT91C_CKGR_PLLBCOUNT (0x3Fu << 8) // (CKGR) PLL B Counter 583 #define AT91C_CKGR_OUTB (0x3u << 14) // (CKGR) PLL B Output Frequency Range 584 #define AT91C_CKGR_OUTB_0 (0x0u << 14) // (CKGR) Please refer to the PLLB datasheet 585 #define AT91C_CKGR_OUTB_1 (0x1u << 14) // (CKGR) Please refer to the PLLB datasheet 586 #define AT91C_CKGR_OUTB_2 (0x2u << 14) // (CKGR) Please refer to the PLLB datasheet 587 #define AT91C_CKGR_OUTB_3 (0x3u << 14) // (CKGR) Please refer to the PLLB datasheet 588 #define AT91C_CKGR_MULB (0x7FFu << 16) // (CKGR) PLL B Multiplier 589 #define AT91C_CKGR_USB_96M (0x1u << 28) // (CKGR) Divider for USB Ports 590 #define AT91C_CKGR_USB_PLL (0x1u << 29) // (CKGR) PLL Use 591 592 // ***************************************************************************** 593 // SOFTWARE API DEFINITION FOR Parallel Input Output Controller 594 // ***************************************************************************** 595 typedef struct _AT91S_PIO { 596 AT91_REG PIO_PER; // PIO Enable Register 597 AT91_REG PIO_PDR; // PIO Disable Register 598 AT91_REG PIO_PSR; // PIO Status Register 599 AT91_REG Reserved0[1]; // 600 AT91_REG PIO_OER; // Output Enable Register 601 AT91_REG PIO_ODR; // Output Disable Registerr 602 AT91_REG PIO_OSR; // Output Status Register 603 AT91_REG Reserved1[1]; // 604 AT91_REG PIO_IFER; // Input Filter Enable Register 605 AT91_REG PIO_IFDR; // Input Filter Disable Register 606 AT91_REG PIO_IFSR; // Input Filter Status Register 607 AT91_REG Reserved2[1]; // 608 AT91_REG PIO_SODR; // Set Output Data Register 609 AT91_REG PIO_CODR; // Clear Output Data Register 610 AT91_REG PIO_ODSR; // Output Data Status Register 611 AT91_REG PIO_PDSR; // Pin Data Status Register 612 AT91_REG PIO_IER; // Interrupt Enable Register 613 AT91_REG PIO_IDR; // Interrupt Disable Register 614 AT91_REG PIO_IMR; // Interrupt Mask Register 615 AT91_REG PIO_ISR; // Interrupt Status Register 616 AT91_REG PIO_MDER; // Multi-driver Enable Register 617 AT91_REG PIO_MDDR; // Multi-driver Disable Register 618 AT91_REG PIO_MDSR; // Multi-driver Status Register 619 AT91_REG Reserved3[1]; // 620 AT91_REG PIO_PPUDR; // Pull-up Disable Register 621 AT91_REG PIO_PPUER; // Pull-up Enable Register 622 AT91_REG PIO_PPUSR; // Pad Pull-up Status Register 623 AT91_REG Reserved4[1]; // 624 AT91_REG PIO_ASR; // Select A Register 625 AT91_REG PIO_BSR; // Select B Register 626 AT91_REG PIO_ABSR; // AB Select Status Register 627 AT91_REG Reserved5[9]; // 628 AT91_REG PIO_OWER; // Output Write Enable Register 629 AT91_REG PIO_OWDR; // Output Write Disable Register 630 AT91_REG PIO_OWSR; // Output Write Status Register 631 } AT91S_PIO, *AT91PS_PIO; 632 633 634 // ***************************************************************************** 635 // SOFTWARE API DEFINITION FOR Debug Unit 636 // ***************************************************************************** 637 typedef struct _AT91S_DBGU { 638 AT91_REG DBGU_CR; // Control Register 639 AT91_REG DBGU_MR; // Mode Register 640 AT91_REG DBGU_IER; // Interrupt Enable Register 641 AT91_REG DBGU_IDR; // Interrupt Disable Register 642 AT91_REG DBGU_IMR; // Interrupt Mask Register 643 AT91_REG DBGU_CSR; // Channel Status Register 644 AT91_REG DBGU_RHR; // Receiver Holding Register 645 AT91_REG DBGU_THR; // Transmitter Holding Register 646 AT91_REG DBGU_BRGR; // Baud Rate Generator Register 647 AT91_REG Reserved0[7]; // 648 AT91_REG DBGU_C1R; // Chip ID1 Register 649 AT91_REG DBGU_C2R; // Chip ID2 Register 650 AT91_REG DBGU_FNTR; // Force NTRST Register 651 AT91_REG Reserved1[45]; // 652 AT91_REG DBGU_RPR; // Receive Pointer Register 653 AT91_REG DBGU_RCR; // Receive Counter Register 654 AT91_REG DBGU_TPR; // Transmit Pointer Register 655 AT91_REG DBGU_TCR; // Transmit Counter Register 656 AT91_REG DBGU_RNPR; // Receive Next Pointer Register 657 AT91_REG DBGU_RNCR; // Receive Next Counter Register 658 AT91_REG DBGU_TNPR; // Transmit Next Pointer Register 659 AT91_REG DBGU_TNCR; // Transmit Next Counter Register 660 AT91_REG DBGU_PTCR; // PDC Transfer Control Register 661 AT91_REG DBGU_PTSR; // PDC Transfer Status Register 662 } AT91S_DBGU, *AT91PS_DBGU; 663 664 // -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 665 #define AT91C_US_RSTRX (0x1u << 2) // (DBGU) Reset Receiver 666 #define AT91C_US_RSTTX (0x1u << 3) // (DBGU) Reset Transmitter 667 #define AT91C_US_RXEN (0x1u << 4) // (DBGU) Receiver Enable 668 #define AT91C_US_RXDIS (0x1u << 5) // (DBGU) Receiver Disable 669 #define AT91C_US_TXEN (0x1u << 6) // (DBGU) Transmitter Enable 670 #define AT91C_US_TXDIS (0x1u << 7) // (DBGU) Transmitter Disable 671 // -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 672 #define AT91C_US_PAR (0x7u << 9) // (DBGU) Parity type 673 #define AT91C_US_PAR_EVEN (0x0u << 9) // (DBGU) Even Parity 674 #define AT91C_US_PAR_ODD (0x1u << 9) // (DBGU) Odd Parity 675 #define AT91C_US_PAR_SPACE (0x2u << 9) // (DBGU) Parity forced to 0 (Space) 676 #define AT91C_US_PAR_MARK (0x3u << 9) // (DBGU) Parity forced to 1 (Mark) 677 #define AT91C_US_PAR_NONE (0x4u << 9) // (DBGU) No Parity 678 #define AT91C_US_PAR_MULTI_DROP (0x6u << 9) // (DBGU) Multi-drop mode 679 #define AT91C_US_CHMODE (0x3u << 14) // (DBGU) Channel Mode 680 #define AT91C_US_CHMODE_NORMAL (0x0u << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. 681 #define AT91C_US_CHMODE_AUTO (0x1u << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. 682 #define AT91C_US_CHMODE_LOCAL (0x2u << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. 683 #define AT91C_US_CHMODE_REMOTE (0x3u << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. 684 // -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 685 #define AT91C_US_RXRDY (0x1u << 0) // (DBGU) RXRDY Interrupt 686 #define AT91C_US_TXRDY (0x1u << 1) // (DBGU) TXRDY Interrupt 687 #define AT91C_US_ENDRX (0x1u << 3) // (DBGU) End of Receive Transfer Interrupt 688 #define AT91C_US_ENDTX (0x1u << 4) // (DBGU) End of Transmit Interrupt 689 #define AT91C_US_OVRE (0x1u << 5) // (DBGU) Overrun Interrupt 690 #define AT91C_US_FRAME (0x1u << 6) // (DBGU) Framing Error Interrupt 691 #define AT91C_US_PARE (0x1u << 7) // (DBGU) Parity Error Interrupt 692 #define AT91C_US_TXEMPTY (0x1u << 9) // (DBGU) TXEMPTY Interrupt 693 #define AT91C_US_TXBUFE (0x1u << 11) // (DBGU) TXBUFE Interrupt 694 #define AT91C_US_RXBUFF (0x1u << 12) // (DBGU) RXBUFF Interrupt 695 #define AT91C_US_COMM_TX (0x1u << 30) // (DBGU) COMM_TX Interrupt 696 #define AT91C_US_COMM_RX (0x1u << 31) // (DBGU) COMM_RX Interrupt 697 // -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 698 // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 699 // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 700 // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 701 #define AT91C_US_FORCE_NTRST (0x1u << 0) // (DBGU) Force NTRST in JTAG 702 703 // ***************************************************************************** 704 // SOFTWARE API DEFINITION FOR Peripheral Data Controller 705 // ***************************************************************************** 706 typedef struct _AT91S_PDC { 707 AT91_REG PDC_RPR; // Receive Pointer Register 708 AT91_REG PDC_RCR; // Receive Counter Register 709 AT91_REG PDC_TPR; // Transmit Pointer Register 710 AT91_REG PDC_TCR; // Transmit Counter Register 711 AT91_REG PDC_RNPR; // Receive Next Pointer Register 712 AT91_REG PDC_RNCR; // Receive Next Counter Register 713 AT91_REG PDC_TNPR; // Transmit Next Pointer Register 714 AT91_REG PDC_TNCR; // Transmit Next Counter Register 715 AT91_REG PDC_PTCR; // PDC Transfer Control Register 716 AT91_REG PDC_PTSR; // PDC Transfer Status Register 717 } AT91S_PDC, *AT91PS_PDC; 718 719 // -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 720 #define AT91C_PDC_RXTEN (0x1u << 0) // (PDC) Receiver Transfer Enable 721 #define AT91C_PDC_RXTDIS (0x1u << 1) // (PDC) Receiver Transfer Disable 722 #define AT91C_PDC_TXTEN (0x1u << 8) // (PDC) Transmitter Transfer Enable 723 #define AT91C_PDC_TXTDIS (0x1u << 9) // (PDC) Transmitter Transfer Disable 724 // -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 725 726 // ***************************************************************************** 727 // SOFTWARE API DEFINITION FOR Advanced Interrupt Controller 728 // ***************************************************************************** 729 typedef struct _AT91S_AIC { 730 AT91_REG AIC_SMR[32]; // Source Mode Register 731 AT91_REG AIC_SVR[32]; // Source Vector Register 732 AT91_REG AIC_IVR; // IRQ Vector Register 733 AT91_REG AIC_FVR; // FIQ Vector Register 734 AT91_REG AIC_ISR; // Interrupt Status Register 735 AT91_REG AIC_IPR; // Interrupt Pending Register 736 AT91_REG AIC_IMR; // Interrupt Mask Register 737 AT91_REG AIC_CISR; // Core Interrupt Status Register 738 AT91_REG Reserved0[2]; // 739 AT91_REG AIC_IECR; // Interrupt Enable Command Register 740 AT91_REG AIC_IDCR; // Interrupt Disable Command Register 741 AT91_REG AIC_ICCR; // Interrupt Clear Command Register 742 AT91_REG AIC_ISCR; // Interrupt Set Command Register 743 AT91_REG AIC_EOICR; // End of Interrupt Command Register 744 AT91_REG AIC_SPU; // Spurious Vector Register 745 AT91_REG AIC_DCR; // Debug Control Register (Protect) 746 AT91_REG Reserved1[1]; // 747 AT91_REG AIC_FFER; // Fast Forcing Enable Register 748 AT91_REG AIC_FFDR; // Fast Forcing Disable Register 749 AT91_REG AIC_FFSR; // Fast Forcing Status Register 750 } AT91S_AIC, *AT91PS_AIC; 751 752 // -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 753 #define AT91C_AIC_PRIOR (0x7u << 0) // (AIC) Priority Level 754 #define AT91C_AIC_PRIOR_LOWEST 0x0u // (AIC) Lowest priority level 755 #define AT91C_AIC_PRIOR_HIGHEST 0x7u // (AIC) Highest priority level 756 #define AT91C_AIC_SRCTYPE (0x3u << 5) // (AIC) Interrupt Source Type 757 #define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0u << 5) // (AIC) Internal Sources Code Label Level Sensitive 758 #define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1u << 5) // (AIC) Internal Sources Code Label Edge triggered 759 #define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2u << 5) // (AIC) External Sources Code Label High-level Sensitive 760 #define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3u << 5) // (AIC) External Sources Code Label Positive Edge triggered 761 // -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 762 #define AT91C_AIC_NFIQ (0x1u << 0) // (AIC) NFIQ Status 763 #define AT91C_AIC_NIRQ (0x1u << 1) // (AIC) NIRQ Status 764 // -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 765 #define AT91C_AIC_DCR_PROT (0x1u << 0) // (AIC) Protection Mode 766 #define AT91C_AIC_DCR_GMSK (0x1u << 1) // (AIC) General Mask 767 768 // ***************************************************************************** 769 // SOFTWARE API DEFINITION FOR Serial Parallel Interface 770 // ***************************************************************************** 771 typedef struct _AT91S_SPI { 772 AT91_REG SPI_CR; // Control Register 773 AT91_REG SPI_MR; // Mode Register 774 AT91_REG SPI_RDR; // Receive Data Register 775 AT91_REG SPI_TDR; // Transmit Data Register 776 AT91_REG SPI_SR; // Status Register 777 AT91_REG SPI_IER; // Interrupt Enable Register 778 AT91_REG SPI_IDR; // Interrupt Disable Register 779 AT91_REG SPI_IMR; // Interrupt Mask Register 780 AT91_REG Reserved0[4]; // 781 AT91_REG SPI_CSR[4]; // Chip Select Register 782 AT91_REG Reserved1[48]; // 783 AT91_REG SPI_RPR; // Receive Pointer Register 784 AT91_REG SPI_RCR; // Receive Counter Register 785 AT91_REG SPI_TPR; // Transmit Pointer Register 786 AT91_REG SPI_TCR; // Transmit Counter Register 787 AT91_REG SPI_RNPR; // Receive Next Pointer Register 788 AT91_REG SPI_RNCR; // Receive Next Counter Register 789 AT91_REG SPI_TNPR; // Transmit Next Pointer Register 790 AT91_REG SPI_TNCR; // Transmit Next Counter Register 791 AT91_REG SPI_PTCR; // PDC Transfer Control Register 792 AT91_REG SPI_PTSR; // PDC Transfer Status Register 793 } AT91S_SPI, *AT91PS_SPI; 794 795 // -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 796 #define AT91C_SPI_SPIEN (0x1u << 0) // (SPI) SPI Enable 797 #define AT91C_SPI_SPIDIS (0x1u << 1) // (SPI) SPI Disable 798 #define AT91C_SPI_SWRST (0x1u << 7) // (SPI) SPI Software reset 799 // -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 800 #define AT91C_SPI_MSTR (0x1u << 0) // (SPI) Master/Slave Mode 801 #define AT91C_SPI_PS (0x1u << 1) // (SPI) Peripheral Select 802 #define AT91C_SPI_PS_FIXED (0x0u << 1) // (SPI) Fixed Peripheral Select 803 #define AT91C_SPI_PS_VARIABLE (0x1u << 1) // (SPI) Variable Peripheral Select 804 #define AT91C_SPI_PCSDEC (0x1u << 2) // (SPI) Chip Select Decode 805 #define AT91C_SPI_DIV32 (0x1u << 3) // (SPI) Clock Selection 806 #define AT91C_SPI_MODFDIS (0x1u << 4) // (SPI) Mode Fault Detection 807 #define AT91C_SPI_LLB (0x1u << 7) // (SPI) Clock Selection 808 #define AT91C_SPI_PCS (0xFu << 16) // (SPI) Peripheral Chip Select 809 #define AT91C_SPI_DLYBCS (0xFFu << 24) // (SPI) Delay Between Chip Selects 810 // -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 811 #define AT91C_SPI_RD (0xFFFFu << 0) // (SPI) Receive Data 812 #define AT91C_SPI_RPCS (0xFu << 16) // (SPI) Peripheral Chip Select Status 813 // -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 814 #define AT91C_SPI_TD (0xFFFFu << 0) // (SPI) Transmit Data 815 #define AT91C_SPI_TPCS (0xFu << 16) // (SPI) Peripheral Chip Select Status 816 // -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 817 #define AT91C_SPI_RDRF (0x1u << 0) // (SPI) Receive Data Register Full 818 #define AT91C_SPI_TDRE (0x1u << 1) // (SPI) Transmit Data Register Empty 819 #define AT91C_SPI_MODF (0x1u << 2) // (SPI) Mode Fault Error 820 #define AT91C_SPI_OVRES (0x1u << 3) // (SPI) Overrun Error Status 821 #define AT91C_SPI_SPENDRX (0x1u << 4) // (SPI) End of Receiver Transfer 822 #define AT91C_SPI_SPENDTX (0x1u << 5) // (SPI) End of Receiver Transfer 823 #define AT91C_SPI_RXBUFF (0x1u << 6) // (SPI) RXBUFF Interrupt 824 #define AT91C_SPI_TXBUFE (0x1u << 7) // (SPI) TXBUFE Interrupt 825 #define AT91C_SPI_SPIENS (0x1u << 16) // (SPI) Enable Status 826 // -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 827 // -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 828 // -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 829 // -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 830 #define AT91C_SPI_CPOL (0x1u << 0) // (SPI) Clock Polarity 831 #define AT91C_SPI_NCPHA (0x1u << 1) // (SPI) Clock Phase 832 #define AT91C_SPI_BITS (0xFu << 4) // (SPI) Bits Per Transfer 833 #define AT91C_SPI_BITS_8 (0x0u << 4) // (SPI) 8 Bits Per transfer 834 #define AT91C_SPI_BITS_9 (0x1u << 4) // (SPI) 9 Bits Per transfer 835 #define AT91C_SPI_BITS_10 (0x2u << 4) // (SPI) 10 Bits Per transfer 836 #define AT91C_SPI_BITS_11 (0x3u << 4) // (SPI) 11 Bits Per transfer 837 #define AT91C_SPI_BITS_12 (0x4u << 4) // (SPI) 12 Bits Per transfer 838 #define AT91C_SPI_BITS_13 (0x5u << 4) // (SPI) 13 Bits Per transfer 839 #define AT91C_SPI_BITS_14 (0x6u << 4) // (SPI) 14 Bits Per transfer 840 #define AT91C_SPI_BITS_15 (0x7u << 4) // (SPI) 15 Bits Per transfer 841 #define AT91C_SPI_BITS_16 (0x8u << 4) // (SPI) 16 Bits Per transfer 842 #define AT91C_SPI_SCBR (0xFFu << 8) // (SPI) Serial Clock Baud Rate 843 #define AT91C_SPI_DLYBS (0xFFu << 16) // (SPI) Serial Clock Baud Rate 844 #define AT91C_SPI_DLYBCT (0xFFu << 24) // (SPI) Delay Between Consecutive Transfers 845 846 // ***************************************************************************** 847 // SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface 848 // ***************************************************************************** 849 typedef struct _AT91S_SSC { 850 AT91_REG SSC_CR; // Control Register 851 AT91_REG SSC_CMR; // Clock Mode Register 852 AT91_REG Reserved0[2]; // 853 AT91_REG SSC_RCMR; // Receive Clock ModeRegister 854 AT91_REG SSC_RFMR; // Receive Frame Mode Register 855 AT91_REG SSC_TCMR; // Transmit Clock Mode Register 856 AT91_REG SSC_TFMR; // Transmit Frame Mode Register 857 AT91_REG SSC_RHR; // Receive Holding Register 858 AT91_REG SSC_THR; // Transmit Holding Register 859 AT91_REG Reserved1[2]; // 860 AT91_REG SSC_RSHR; // Receive Sync Holding Register 861 AT91_REG SSC_TSHR; // Transmit Sync Holding Register 862 AT91_REG SSC_RC0R; // Receive Compare 0 Register 863 AT91_REG SSC_RC1R; // Receive Compare 1 Register 864 AT91_REG SSC_SR; // Status Register 865 AT91_REG SSC_IER; // Interrupt Enable Register 866 AT91_REG SSC_IDR; // Interrupt Disable Register 867 AT91_REG SSC_IMR; // Interrupt Mask Register 868 AT91_REG Reserved2[44]; // 869 AT91_REG SSC_RPR; // Receive Pointer Register 870 AT91_REG SSC_RCR; // Receive Counter Register 871 AT91_REG SSC_TPR; // Transmit Pointer Register 872 AT91_REG SSC_TCR; // Transmit Counter Register 873 AT91_REG SSC_RNPR; // Receive Next Pointer Register 874 AT91_REG SSC_RNCR; // Receive Next Counter Register 875 AT91_REG SSC_TNPR; // Transmit Next Pointer Register 876 AT91_REG SSC_TNCR; // Transmit Next Counter Register 877 AT91_REG SSC_PTCR; // PDC Transfer Control Register 878 AT91_REG SSC_PTSR; // PDC Transfer Status Register 879 } AT91S_SSC, *AT91PS_SSC; 880 881 // -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 882 #define AT91C_SSC_RXEN (0x1u << 0) // (SSC) Receive Enable 883 #define AT91C_SSC_RXDIS (0x1u << 1) // (SSC) Receive Disable 884 #define AT91C_SSC_TXEN (0x1u << 8) // (SSC) Transmit Enable 885 #define AT91C_SSC_TXDIS (0x1u << 9) // (SSC) Transmit Disable 886 #define AT91C_SSC_SWRST (0x1u << 15) // (SSC) Software Reset 887 // -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 888 #define AT91C_SSC_CKS (0x3u << 0) // (SSC) Receive/Transmit Clock Selection 889 #define AT91C_SSC_CKS_DIV 0x0u // (SSC) Divided Clock 890 #define AT91C_SSC_CKS_TK 0x1u // (SSC) TK Clock signal 891 #define AT91C_SSC_CKS_RK 0x2u // (SSC) RK pin 892 #define AT91C_SSC_CKO (0x7u << 2) // (SSC) Receive/Transmit Clock Output Mode Selection 893 #define AT91C_SSC_CKO_NONE (0x0u << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only 894 #define AT91C_SSC_CKO_CONTINOUS (0x1u << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output 895 #define AT91C_SSC_CKO_DATA_TX (0x2u << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output 896 #define AT91C_SSC_CKI (0x1u << 5) // (SSC) Receive/Transmit Clock Inversion 897 #define AT91C_SSC_CKG (0x3u << 6) // (SSC) Receive/Transmit Clock Gating Selection 898 #define AT91C_SSC_CKG_NONE (0x0u << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock 899 #define AT91C_SSC_CKG_LOW (0x1u << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low 900 #define AT91C_SSC_CKG_HIGH (0x2u << 6) // (SSC) Receive/Transmit Clock enabled only if RF High 901 #define AT91C_SSC_START (0xFu << 8) // (SSC) Receive/Transmit Start Selection 902 #define AT91C_SSC_START_CONTINOUS (0x0u << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 903 #define AT91C_SSC_START_TX (0x1u << 8) // (SSC) Transmit/Receive start 904 #define AT91C_SSC_START_LOW_RF (0x2u << 8) // (SSC) Detection of a low level on RF input 905 #define AT91C_SSC_START_HIGH_RF (0x3u << 8) // (SSC) Detection of a high level on RF input 906 #define AT91C_SSC_START_FALL_RF (0x4u << 8) // (SSC) Detection of a falling edge on RF input 907 #define AT91C_SSC_START_RISE_RF (0x5u << 8) // (SSC) Detection of a rising edge on RF input 908 #define AT91C_SSC_START_LEVEL_RF (0x6u << 8) // (SSC) Detection of any level change on RF input 909 #define AT91C_SSC_START_EDGE_RF (0x7u << 8) // (SSC) Detection of any edge on RF input 910 #define AT91C_SSC_START_0 (0x8u << 8) // (SSC) Compare 0 911 #define AT91C_SSC_STOP (0x1u << 12) // (SSC) Receive Stop Selection 912 #define AT91C_SSC_STTOUT (0x1u << 15) // (SSC) Receive/Transmit Start Output Selection 913 #define AT91C_SSC_STTDLY (0xFFu << 16) // (SSC) Receive/Transmit Start Delay 914 #define AT91C_SSC_PERIOD (0xFFu << 24) // (SSC) Receive/Transmit Period Divider Selection 915 // -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 916 #define AT91C_SSC_DATLEN (0x1Fu << 0) // (SSC) Data Length 917 #define AT91C_SSC_LOOP (0x1u << 5) // (SSC) Loop Mode 918 #define AT91C_SSC_MSBF (0x1u << 7) // (SSC) Most Significant Bit First 919 #define AT91C_SSC_DATNB (0xFu << 8) // (SSC) Data Number per Frame 920 #define AT91C_SSC_FSLEN (0xFu << 16) // (SSC) Receive/Transmit Frame Sync length 921 #define AT91C_SSC_FSOS (0x7u << 20) // (SSC) Receive/Transmit Frame Sync Output Selection 922 #define AT91C_SSC_FSOS_NONE (0x0u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only 923 #define AT91C_SSC_FSOS_NEGATIVE (0x1u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse 924 #define AT91C_SSC_FSOS_POSITIVE (0x2u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse 925 #define AT91C_SSC_FSOS_LOW (0x3u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer 926 #define AT91C_SSC_FSOS_HIGH (0x4u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer 927 #define AT91C_SSC_FSOS_TOGGLE (0x5u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer 928 #define AT91C_SSC_FSEDGE (0x1u << 24) // (SSC) Frame Sync Edge Detection 929 // -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 930 // -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 931 #define AT91C_SSC_DATDEF (0x1u << 5) // (SSC) Data Default Value 932 #define AT91C_SSC_FSDEN (0x1u << 23) // (SSC) Frame Sync Data Enable 933 // -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 934 #define AT91C_SSC_TXRDY (0x1u << 0) // (SSC) Transmit Ready 935 #define AT91C_SSC_TXEMPTY (0x1u << 1) // (SSC) Transmit Empty 936 #define AT91C_SSC_ENDTX (0x1u << 2) // (SSC) End Of Transmission 937 #define AT91C_SSC_TXBUFE (0x1u << 3) // (SSC) Transmit Buffer Empty 938 #define AT91C_SSC_RXRDY (0x1u << 4) // (SSC) Receive Ready 939 #define AT91C_SSC_OVRUN (0x1u << 5) // (SSC) Receive Overrun 940 #define AT91C_SSC_ENDRX (0x1u << 6) // (SSC) End of Reception 941 #define AT91C_SSC_RXBUFF (0x1u << 7) // (SSC) Receive Buffer Full 942 #define AT91C_SSC_CP0 (0x1u << 8) // (SSC) Compare 0 943 #define AT91C_SSC_CP1 (0x1u << 9) // (SSC) Compare 1 944 #define AT91C_SSC_TXSYN (0x1u << 10) // (SSC) Transmit Sync 945 #define AT91C_SSC_RXSYN (0x1u << 11) // (SSC) Receive Sync 946 #define AT91C_SSC_TXENA (0x1u << 16) // (SSC) Transmit Enable 947 #define AT91C_SSC_RXENA (0x1u << 17) // (SSC) Receive Enable 948 // -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 949 // -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 950 // -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 951 952 // ***************************************************************************** 953 // SOFTWARE API DEFINITION FOR Usart 954 // ***************************************************************************** 955 typedef struct _AT91S_USART { 956 AT91_REG US_CR; // Control Register 957 AT91_REG US_MR; // Mode Register 958 AT91_REG US_IER; // Interrupt Enable Register 959 AT91_REG US_IDR; // Interrupt Disable Register 960 AT91_REG US_IMR; // Interrupt Mask Register 961 AT91_REG US_CSR; // Channel Status Register 962 AT91_REG US_RHR; // Receiver Holding Register 963 AT91_REG US_THR; // Transmitter Holding Register 964 AT91_REG US_BRGR; // Baud Rate Generator Register 965 AT91_REG US_RTOR; // Receiver Time-out Register 966 AT91_REG US_TTGR; // Transmitter Time-guard Register 967 AT91_REG Reserved0[5]; // 968 AT91_REG US_FIDI; // FI_DI_Ratio Register 969 AT91_REG US_NER; // Nb Errors Register 970 AT91_REG US_XXR; // XON_XOFF Register 971 AT91_REG US_IF; // IRDA_FILTER Register 972 AT91_REG Reserved1[44]; // 973 AT91_REG US_RPR; // Receive Pointer Register 974 AT91_REG US_RCR; // Receive Counter Register 975 AT91_REG US_TPR; // Transmit Pointer Register 976 AT91_REG US_TCR; // Transmit Counter Register 977 AT91_REG US_RNPR; // Receive Next Pointer Register 978 AT91_REG US_RNCR; // Receive Next Counter Register 979 AT91_REG US_TNPR; // Transmit Next Pointer Register 980 AT91_REG US_TNCR; // Transmit Next Counter Register 981 AT91_REG US_PTCR; // PDC Transfer Control Register 982 AT91_REG US_PTSR; // PDC Transfer Status Register 983 } AT91S_USART, *AT91PS_USART; 984 985 // -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 986 #define AT91C_US_RSTSTA (0x1u << 8) // (USART) Reset Status Bits 987 #define AT91C_US_STTBRK (0x1u << 9) // (USART) Start Break 988 #define AT91C_US_STPBRK (0x1u << 10) // (USART) Stop Break 989 #define AT91C_US_STTTO (0x1u << 11) // (USART) Start Time-out 990 #define AT91C_US_SENDA (0x1u << 12) // (USART) Send Address 991 #define AT91C_US_RSTIT (0x1u << 13) // (USART) Reset Iterations 992 #define AT91C_US_RSTNACK (0x1u << 14) // (USART) Reset Non Acknowledge 993 #define AT91C_US_RETTO (0x1u << 15) // (USART) Rearm Time-out 994 #define AT91C_US_DTREN (0x1u << 16) // (USART) Data Terminal ready Enable 995 #define AT91C_US_DTRDIS (0x1u << 17) // (USART) Data Terminal ready Disable 996 #define AT91C_US_RTSEN (0x1u << 18) // (USART) Request to Send enable 997 #define AT91C_US_RTSDIS (0x1u << 19) // (USART) Request to Send Disable 998 // -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 999 #define AT91C_US_USMODE (0xFu << 0) // (USART) Usart mode 1000 #define AT91C_US_USMODE_NORMAL 0x0u // (USART) Normal 1001 #define AT91C_US_USMODE_RS485 0x1u // (USART) RS485 1002 #define AT91C_US_USMODE_HWHSH 0x2u // (USART) Hardware Handshaking 1003 #define AT91C_US_USMODE_MODEM 0x3u // (USART) Modem 1004 #define AT91C_US_USMODE_ISO7816_0 0x4u // (USART) ISO7816 protocol: T = 0 1005 #define AT91C_US_USMODE_ISO7816_1 0x6u // (USART) ISO7816 protocol: T = 1 1006 #define AT91C_US_USMODE_IRDA 0x8u // (USART) IrDA 1007 #define AT91C_US_USMODE_SWHSH 0xCu // (USART) Software Handshaking 1008 #define AT91C_US_CLKS (0x3u << 4) // (USART) Clock Selection (Baud Rate generator Input Clock 1009 #define AT91C_US_CLKS_CLOCK (0x0u << 4) // (USART) Clock 1010 #define AT91C_US_CLKS_FDIV1 (0x1u << 4) // (USART) fdiv1 1011 #define AT91C_US_CLKS_SLOW (0x2u << 4) // (USART) slow_clock (ARM) 1012 #define AT91C_US_CLKS_EXT (0x3u << 4) // (USART) External (SCK) 1013 #define AT91C_US_CHRL (0x3u << 6) // (USART) Clock Selection (Baud Rate generator Input Clock 1014 #define AT91C_US_CHRL_5_BITS (0x0u << 6) // (USART) Character Length: 5 bits 1015 #define AT91C_US_CHRL_6_BITS (0x1u << 6) // (USART) Character Length: 6 bits 1016 #define AT91C_US_CHRL_7_BITS (0x2u << 6) // (USART) Character Length: 7 bits 1017 #define AT91C_US_CHRL_8_BITS (0x3u << 6) // (USART) Character Length: 8 bits 1018 #define AT91C_US_SYNC (0x1u << 8) // (USART) Synchronous Mode Select 1019 #define AT91C_US_NBSTOP (0x3u << 12) // (USART) Number of Stop bits 1020 #define AT91C_US_NBSTOP_1_BIT (0x0u << 12) // (USART) 1 stop bit 1021 #define AT91C_US_NBSTOP_15_BIT (0x1u << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits 1022 #define AT91C_US_NBSTOP_2_BIT (0x2u << 12) // (USART) 2 stop bits 1023 #define AT91C_US_MSBF (0x1u << 16) // (USART) Bit Order 1024 #define AT91C_US_MODE9 (0x1u << 17) // (USART) 9-bit Character length 1025 #define AT91C_US_CKLO (0x1u << 18) // (USART) Clock Output Select 1026 #define AT91C_US_OVER (0x1u << 19) // (USART) Over Sampling Mode 1027 #define AT91C_US_INACK (0x1u << 20) // (USART) Inhibit Non Acknowledge 1028 #define AT91C_US_DSNACK (0x1u << 21) // (USART) Disable Successive NACK 1029 #define AT91C_US_MAX_ITER (0x1u << 24) // (USART) Number of Repetitions 1030 #define AT91C_US_FILTER (0x1u << 28) // (USART) Receive Line Filter 1031 // -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 1032 #define AT91C_US_RXBRK (0x1u << 2) // (USART) Break Received/End of Break 1033 #define AT91C_US_TIMEOUT (0x1u << 8) // (USART) Receiver Time-out 1034 #define AT91C_US_ITERATION (0x1u << 10) // (USART) Max number of Repetitions Reached 1035 #define AT91C_US_NACK (0x1u << 13) // (USART) Non Acknowledge 1036 #define AT91C_US_RIIC (0x1u << 16) // (USART) Ring INdicator Input Change Flag 1037 #define AT91C_US_DSRIC (0x1u << 17) // (USART) Data Set Ready Input Change Flag 1038 #define AT91C_US_DCDIC (0x1u << 18) // (USART) Data Carrier Flag 1039 #define AT91C_US_CTSIC (0x1u << 19) // (USART) Clear To Send Input Change Flag 1040 // -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 1041 // -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 1042 // -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 1043 #define AT91C_US_RI (0x1u << 20) // (USART) Image of RI Input 1044 #define AT91C_US_DSR (0x1u << 21) // (USART) Image of DSR Input 1045 #define AT91C_US_DCD (0x1u << 22) // (USART) Image of DCD Input 1046 #define AT91C_US_CTS (0x1u << 23) // (USART) Image of CTS Input 1047 1048 // ***************************************************************************** 1049 // SOFTWARE API DEFINITION FOR Two-wire Interface 1050 // ***************************************************************************** 1051 typedef struct _AT91S_TWI { 1052 AT91_REG TWI_CR; // Control Register 1053 AT91_REG TWI_MMR; // Master Mode Register 1054 AT91_REG TWI_SMR; // Slave Mode Register 1055 AT91_REG TWI_IADR; // Internal Address Register 1056 AT91_REG TWI_CWGR; // Clock Waveform Generator Register 1057 AT91_REG Reserved0[3]; // 1058 AT91_REG TWI_SR; // Status Register 1059 AT91_REG TWI_IER; // Interrupt Enable Register 1060 AT91_REG TWI_IDR; // Interrupt Disable Register 1061 AT91_REG TWI_IMR; // Interrupt Mask Register 1062 AT91_REG TWI_RHR; // Receive Holding Register 1063 AT91_REG TWI_THR; // Transmit Holding Register 1064 } AT91S_TWI, *AT91PS_TWI; 1065 1066 // -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 1067 #define AT91C_TWI_START (0x1u << 0) // (TWI) Send a START Condition 1068 #define AT91C_TWI_STOP (0x1u << 1) // (TWI) Send a STOP Condition 1069 #define AT91C_TWI_MSEN (0x1u << 2) // (TWI) TWI Master Transfer Enabled 1070 #define AT91C_TWI_MSDIS (0x1u << 3) // (TWI) TWI Master Transfer Disabled 1071 #define AT91C_TWI_SVEN (0x1u << 4) // (TWI) TWI Slave Transfer Enabled 1072 #define AT91C_TWI_SVDIS (0x1u << 5) // (TWI) TWI Slave Transfer Disabled 1073 #define AT91C_TWI_SWRST (0x1u << 7) // (TWI) Software Reset 1074 // -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 1075 #define AT91C_TWI_IADRSZ (0x3u << 8) // (TWI) Internal Device Address Size 1076 #define AT91C_TWI_IADRSZ_NO (0x0u << 8) // (TWI) No internal device address 1077 #define AT91C_TWI_IADRSZ_1_BYTE (0x1u << 8) // (TWI) One-byte internal device address 1078 #define AT91C_TWI_IADRSZ_2_BYTE (0x2u << 8) // (TWI) Two-byte internal device address 1079 #define AT91C_TWI_IADRSZ_3_BYTE (0x3u << 8) // (TWI) Three-byte internal device address 1080 #define AT91C_TWI_MREAD (0x1u << 12) // (TWI) Master Read Direction 1081 #define AT91C_TWI_DADR (0x7Fu << 16) // (TWI) Device Address 1082 // -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- 1083 #define AT91C_TWI_SADR (0x7Fu << 16) // (TWI) Slave Device Address 1084 // -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 1085 #define AT91C_TWI_CLDIV (0xFFu << 0) // (TWI) Clock Low Divider 1086 #define AT91C_TWI_CHDIV (0xFFu << 8) // (TWI) Clock High Divider 1087 #define AT91C_TWI_CKDIV (0x7u << 16) // (TWI) Clock Divider 1088 // -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 1089 #define AT91C_TWI_TXCOMP (0x1u << 0) // (TWI) Transmission Completed 1090 #define AT91C_TWI_RXRDY (0x1u << 1) // (TWI) Receive holding register ReaDY 1091 #define AT91C_TWI_TXRDY (0x1u << 2) // (TWI) Transmit holding register ReaDY 1092 #define AT91C_TWI_SVREAD (0x1u << 3) // (TWI) Slave Read 1093 #define AT91C_TWI_SVACC (0x1u << 4) // (TWI) Slave Access 1094 #define AT91C_TWI_GCACC (0x1u << 5) // (TWI) General Call Access 1095 #define AT91C_TWI_OVRE (0x1u << 6) // (TWI) Overrun Error 1096 #define AT91C_TWI_UNRE (0x1u << 7) // (TWI) Underrun Error 1097 #define AT91C_TWI_NACK (0x1u << 8) // (TWI) Not Acknowledged 1098 #define AT91C_TWI_ARBLST (0x1u << 9) // (TWI) Arbitration Lost 1099 // -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 1100 // -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 1101 // -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 1102 1103 // ***************************************************************************** 1104 // SOFTWARE API DEFINITION FOR Multimedia Card Interface 1105 // ***************************************************************************** 1106 typedef struct _AT91S_MCI { 1107 AT91_REG MCI_CR; // MCI Control Register 1108 AT91_REG MCI_MR; // MCI Mode Register 1109 AT91_REG MCI_DTOR; // MCI Data Timeout Register 1110 AT91_REG MCI_SDCR; // MCI SD Card Register 1111 AT91_REG MCI_ARGR; // MCI Argument Register 1112 AT91_REG MCI_CMDR; // MCI Command Register 1113 AT91_REG Reserved0[2]; // 1114 AT91_REG MCI_RSPR[4]; // MCI Response Register 1115 AT91_REG MCI_RDR; // MCI Receive Data Register 1116 AT91_REG MCI_TDR; // MCI Transmit Data Register 1117 AT91_REG Reserved1[2]; // 1118 AT91_REG MCI_SR; // MCI Status Register 1119 AT91_REG MCI_IER; // MCI Interrupt Enable Register 1120 AT91_REG MCI_IDR; // MCI Interrupt Disable Register 1121 AT91_REG MCI_IMR; // MCI Interrupt Mask Register 1122 AT91_REG Reserved2[44]; // 1123 AT91_REG MCI_RPR; // Receive Pointer Register 1124 AT91_REG MCI_RCR; // Receive Counter Register 1125 AT91_REG MCI_TPR; // Transmit Pointer Register 1126 AT91_REG MCI_TCR; // Transmit Counter Register 1127 AT91_REG MCI_RNPR; // Receive Next Pointer Register 1128 AT91_REG MCI_RNCR; // Receive Next Counter Register 1129 AT91_REG MCI_TNPR; // Transmit Next Pointer Register 1130 AT91_REG MCI_TNCR; // Transmit Next Counter Register 1131 AT91_REG MCI_PTCR; // PDC Transfer Control Register 1132 AT91_REG MCI_PTSR; // PDC Transfer Status Register 1133 } AT91S_MCI, *AT91PS_MCI; 1134 1135 // -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- 1136 #define AT91C_MCI_MCIEN (0x1u << 0) // (MCI) Multimedia Interface Enable 1137 #define AT91C_MCI_MCIDIS (0x1u << 1) // (MCI) Multimedia Interface Disable 1138 #define AT91C_MCI_PWSEN (0x1u << 2) // (MCI) Power Save Mode Enable 1139 #define AT91C_MCI_PWSDIS (0x1u << 3) // (MCI) Power Save Mode Disable 1140 // -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- 1141 #define AT91C_MCI_CLKDIV (0x1u << 0) // (MCI) Clock Divider 1142 #define AT91C_MCI_PWSDIV (0x1u << 8) // (MCI) Power Saving Divider 1143 #define AT91C_MCI_PDCPADV (0x1u << 14) // (MCI) PDC Padding Value 1144 #define AT91C_MCI_PDCMODE (0x1u << 15) // (MCI) PDC Oriented Mode 1145 #define AT91C_MCI_BLKLEN (0x1u << 18) // (MCI) Data Block Length 1146 // -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- 1147 #define AT91C_MCI_DTOCYC (0x1u << 0) // (MCI) Data Timeout Cycle Number 1148 #define AT91C_MCI_DTOMUL (0x7u << 4) // (MCI) Data Timeout Multiplier 1149 #define AT91C_MCI_DTOMUL_1 (0x0u << 4) // (MCI) DTOCYC x 1 1150 #define AT91C_MCI_DTOMUL_16 (0x1u << 4) // (MCI) DTOCYC x 16 1151 #define AT91C_MCI_DTOMUL_128 (0x2u << 4) // (MCI) DTOCYC x 128 1152 #define AT91C_MCI_DTOMUL_256 (0x3u << 4) // (MCI) DTOCYC x 256 1153 #define AT91C_MCI_DTOMUL_1024 (0x4u << 4) // (MCI) DTOCYC x 1024 1154 #define AT91C_MCI_DTOMUL_4096 (0x5u << 4) // (MCI) DTOCYC x 4096 1155 #define AT91C_MCI_DTOMUL_65536 (0x6u << 4) // (MCI) DTOCYC x 65536 1156 #define AT91C_MCI_DTOMUL_1048576 (0x7u << 4) // (MCI) DTOCYC x 1048576 1157 // -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- 1158 #define AT91C_MCI_SCDSEL (0x1u << 0) // (MCI) SD Card Selector 1159 #define AT91C_MCI_SCDBUS (0x1u << 7) // (MCI) SD Card Bus Width 1160 // -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- 1161 // -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- 1162 #define AT91C_MCI_CMDRDY (0x1u << 0) // (MCI) Command Ready flag 1163 #define AT91C_MCI_RXRDY (0x1u << 1) // (MCI) RX Ready flag 1164 #define AT91C_MCI_TXRDY (0x1u << 2) // (MCI) TX Ready flag 1165 #define AT91C_MCI_BLKE (0x1u << 3) // (MCI) Data Block Transfer Ended flag 1166 #define AT91C_MCI_DTIP (0x1u << 4) // (MCI) Data Transfer in Progress flag 1167 #define AT91C_MCI_NOTBUSY (0x1u << 5) // (MCI) Data Line Not Busy flag 1168 #define AT91C_MCI_ENDRX (0x1u << 6) // (MCI) End of RX Buffer flag 1169 #define AT91C_MCI_ENDTX (0x1u << 7) // (MCI) End of TX Buffer flag 1170 #define AT91C_MCI_RXBUFF (0x1u << 14) // (MCI) RX Buffer Full flag 1171 #define AT91C_MCI_TXBUFE (0x1u << 15) // (MCI) TX Buffer Empty flag 1172 #define AT91C_MCI_RINDE (0x1u << 16) // (MCI) Response Index Error flag 1173 #define AT91C_MCI_RDIRE (0x1u << 17) // (MCI) Response Direction Error flag 1174 #define AT91C_MCI_RCRCE (0x1u << 18) // (MCI) Response CRC Error flag 1175 #define AT91C_MCI_RENDE (0x1u << 19) // (MCI) Response End Bit Error flag 1176 #define AT91C_MCI_RTOE (0x1u << 20) // (MCI) Response Time-out Error flag 1177 #define AT91C_MCI_DCRCE (0x1u << 21) // (MCI) data CRC Error flag 1178 #define AT91C_MCI_DTOE (0x1u << 22) // (MCI) Data timeout Error flag 1179 #define AT91C_MCI_OVRE (0x1u << 30) // (MCI) Overrun flag 1180 #define AT91C_MCI_UNRE (0x1u << 31) // (MCI) Underrun flag 1181 // -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- 1182 // -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- 1183 // -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- 1184 1185 // ***************************************************************************** 1186 // SOFTWARE API DEFINITION FOR USB Device Interface 1187 // ***************************************************************************** 1188 typedef struct _AT91S_UDP { 1189 AT91_REG UDP_NUM; // Frame Number Register 1190 AT91_REG UDP_GLBSTATE; // Global State Register 1191 AT91_REG UDP_FADDR; // Function Address Register 1192 AT91_REG Reserved0[1]; // 1193 AT91_REG UDP_IER; // Interrupt Enable Register 1194 AT91_REG UDP_IDR; // Interrupt Disable Register 1195 AT91_REG UDP_IMR; // Interrupt Mask Register 1196 AT91_REG UDP_ISR; // Interrupt Status Register 1197 AT91_REG UDP_ICR; // Interrupt Clear Register 1198 AT91_REG Reserved1[1]; // 1199 AT91_REG UDP_RSTEP; // Reset Endpoint Register 1200 AT91_REG Reserved2[1]; // 1201 AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register 1202 AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register 1203 } AT91S_UDP, *AT91PS_UDP; 1204 1205 // -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 1206 #define AT91C_UDP_FRM_NUM (0x7FFu << 0) // (UDP) Frame Number as Defined in the Packet Field Formats 1207 #define AT91C_UDP_FRM_ERR (0x1u << 16) // (UDP) Frame Error 1208 #define AT91C_UDP_FRM_OK (0x1u << 17) // (UDP) Frame OK 1209 // -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 1210 #define AT91C_UDP_FADDEN (0x1u << 0) // (UDP) Function Address Enable 1211 #define AT91C_UDP_CONFG (0x1u << 1) // (UDP) Configured 1212 #define AT91C_UDP_RMWUPE (0x1u << 2) // (UDP) Remote Wake Up Enable 1213 #define AT91C_UDP_RSMINPR (0x1u << 3) // (UDP) A Resume Has Been Sent to the Host 1214 // -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 1215 #define AT91C_UDP_FADD (0xFFu << 0) // (UDP) Function Address Value 1216 #define AT91C_UDP_FEN (0x1u << 8) // (UDP) Function Enable 1217 // -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 1218 #define AT91C_UDP_EPINT0 (0x1u << 0) // (UDP) Endpoint 0 Interrupt 1219 #define AT91C_UDP_EPINT1 (0x1u << 1) // (UDP) Endpoint 0 Interrupt 1220 #define AT91C_UDP_EPINT2 (0x1u << 2) // (UDP) Endpoint 2 Interrupt 1221 #define AT91C_UDP_EPINT3 (0x1u << 3) // (UDP) Endpoint 3 Interrupt 1222 #define AT91C_UDP_EPINT4 (0x1u << 4) // (UDP) Endpoint 4 Interrupt 1223 #define AT91C_UDP_EPINT5 (0x1u << 5) // (UDP) Endpoint 5 Interrupt 1224 #define AT91C_UDP_EPINT6 (0x1u << 6) // (UDP) Endpoint 6 Interrupt 1225 #define AT91C_UDP_EPINT7 (0x1u << 7) // (UDP) Endpoint 7 Interrupt 1226 #define AT91C_UDP_RXSUSP (0x1u << 8) // (UDP) USB Suspend Interrupt 1227 #define AT91C_UDP_RXRSM (0x1u << 9) // (UDP) USB Resume Interrupt 1228 #define AT91C_UDP_EXTRSM (0x1u << 10) // (UDP) USB External Resume Interrupt 1229 #define AT91C_UDP_SOFINT (0x1u << 11) // (UDP) USB Start Of frame Interrupt 1230 #define AT91C_UDP_WAKEUP (0x1u << 13) // (UDP) USB Resume Interrupt 1231 // -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 1232 // -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 1233 // -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 1234 #define AT91C_UDP_ENDBUSRES (0x1u << 12) // (UDP) USB End Of Bus Reset Interrupt 1235 // -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 1236 // -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 1237 #define AT91C_UDP_EP0 (0x1u << 0) // (UDP) Reset Endpoint 0 1238 #define AT91C_UDP_EP1 (0x1u << 1) // (UDP) Reset Endpoint 1 1239 #define AT91C_UDP_EP2 (0x1u << 2) // (UDP) Reset Endpoint 2 1240 #define AT91C_UDP_EP3 (0x1u << 3) // (UDP) Reset Endpoint 3 1241 #define AT91C_UDP_EP4 (0x1u << 4) // (UDP) Reset Endpoint 4 1242 #define AT91C_UDP_EP5 (0x1u << 5) // (UDP) Reset Endpoint 5 1243 #define AT91C_UDP_EP6 (0x1u << 6) // (UDP) Reset Endpoint 6 1244 #define AT91C_UDP_EP7 (0x1u << 7) // (UDP) Reset Endpoint 7 1245 // -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 1246 #define AT91C_UDP_TXCOMP (0x1u << 0) // (UDP) Generates an IN packet with data previously written in the DPR 1247 #define AT91C_UDP_RX_DATA_BK0 (0x1u << 1) // (UDP) Receive Data Bank 0 1248 #define AT91C_UDP_RXSETUP (0x1u << 2) // (UDP) Sends STALL to the Host (Control endpoints) 1249 #define AT91C_UDP_ISOERROR (0x1u << 3) // (UDP) Isochronous error (Isochronous endpoints) 1250 #define AT91C_UDP_TXPKTRDY (0x1u << 4) // (UDP) Transmit Packet Ready 1251 #define AT91C_UDP_FORCESTALL (0x1u << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). 1252 #define AT91C_UDP_RX_DATA_BK1 (0x1u << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). 1253 #define AT91C_UDP_DIR (0x1u << 7) // (UDP) Transfer Direction 1254 #define AT91C_UDP_EPTYPE (0x7u << 8) // (UDP) Endpoint type 1255 #define AT91C_UDP_EPTYPE_CTRL (0x0u << 8) // (UDP) Control 1256 #define AT91C_UDP_EPTYPE_ISO_OUT (0x1u << 8) // (UDP) Isochronous OUT 1257 #define AT91C_UDP_EPTYPE_BULK_OUT (0x2u << 8) // (UDP) Bulk OUT 1258 #define AT91C_UDP_EPTYPE_INT_OUT (0x3u << 8) // (UDP) Interrupt OUT 1259 #define AT91C_UDP_EPTYPE_ISO_IN (0x5u << 8) // (UDP) Isochronous IN 1260 #define AT91C_UDP_EPTYPE_BULK_IN (0x6u << 8) // (UDP) Bulk IN 1261 #define AT91C_UDP_EPTYPE_INT_IN (0x7u << 8) // (UDP) Interrupt IN 1262 #define AT91C_UDP_DTGLE (0x1u << 11) // (UDP) Data Toggle 1263 #define AT91C_UDP_EPEDS (0x1u << 15) // (UDP) Endpoint Enable Disable 1264 #define AT91C_UDP_RXBYTECNT (0x7FFu << 16) // (UDP) Number Of Bytes Available in the FIFO 1265 1266 // ***************************************************************************** 1267 // SOFTWARE API DEFINITION FOR Timer Counter Channel Interface 1268 // ***************************************************************************** 1269 typedef struct _AT91S_TC { 1270 AT91_REG TC_CCR; // Channel Control Register 1271 AT91_REG TC_CMR; // Channel Mode Register 1272 AT91_REG Reserved0[2]; // 1273 AT91_REG TC_CV; // Counter Value 1274 AT91_REG TC_RA; // Register A 1275 AT91_REG TC_RB; // Register B 1276 AT91_REG TC_RC; // Register C 1277 AT91_REG TC_SR; // Status Register 1278 AT91_REG TC_IER; // Interrupt Enable Register 1279 AT91_REG TC_IDR; // Interrupt Disable Register 1280 AT91_REG TC_IMR; // Interrupt Mask Register 1281 } AT91S_TC, *AT91PS_TC; 1282 1283 // -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 1284 #define AT91C_TC_CLKEN (0x1u << 0) // (TC) Counter Clock Enable Command 1285 #define AT91C_TC_CLKDIS (0x1u << 1) // (TC) Counter Clock Disable Command 1286 #define AT91C_TC_SWTRG (0x1u << 2) // (TC) Software Trigger Command 1287 // -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 1288 #define AT91C_TC_CPCSTOP (0x1u << 6) // (TC) Counter Clock Stopped with RC Compare 1289 #define AT91C_TC_CPCDIS (0x1u << 7) // (TC) Counter Clock Disable with RC Compare 1290 #define AT91C_TC_EEVTEDG (0x3u << 8) // (TC) External Event Edge Selection 1291 #define AT91C_TC_EEVTEDG_NONE (0x0u << 8) // (TC) Edge: None 1292 #define AT91C_TC_EEVTEDG_RISING (0x1u << 8) // (TC) Edge: rising edge 1293 #define AT91C_TC_EEVTEDG_FALLING (0x2u << 8) // (TC) Edge: falling edge 1294 #define AT91C_TC_EEVTEDG_BOTH (0x3u << 8) // (TC) Edge: each edge 1295 #define AT91C_TC_EEVT (0x3u << 10) // (TC) External Event Selection 1296 #define AT91C_TC_EEVT_NONE (0x0u << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input 1297 #define AT91C_TC_EEVT_RISING (0x1u << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output 1298 #define AT91C_TC_EEVT_FALLING (0x2u << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output 1299 #define AT91C_TC_EEVT_BOTH (0x3u << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output 1300 #define AT91C_TC_ENETRG (0x1u << 12) // (TC) External Event Trigger enable 1301 #define AT91C_TC_WAVESEL (0x3u << 13) // (TC) Waveform Selection 1302 #define AT91C_TC_WAVESEL_UP (0x0u << 13) // (TC) UP mode without atomatic trigger on RC Compare 1303 #define AT91C_TC_WAVESEL_UP_AUTO (0x1u << 13) // (TC) UP mode with automatic trigger on RC Compare 1304 #define AT91C_TC_WAVESEL_UPDOWN (0x2u << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare 1305 #define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3u << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare 1306 #define AT91C_TC_CPCTRG (0x1u << 14) // (TC) RC Compare Trigger Enable 1307 #define AT91C_TC_WAVE (0x1u << 15) // (TC) 1308 #define AT91C_TC_ACPA (0x3u << 16) // (TC) RA Compare Effect on TIOA 1309 #define AT91C_TC_ACPA_NONE (0x0u << 16) // (TC) Effect: none 1310 #define AT91C_TC_ACPA_SET (0x1u << 16) // (TC) Effect: set 1311 #define AT91C_TC_ACPA_CLEAR (0x2u << 16) // (TC) Effect: clear 1312 #define AT91C_TC_ACPA_TOGGLE (0x3u << 16) // (TC) Effect: toggle 1313 #define AT91C_TC_ACPC (0x3u << 18) // (TC) RC Compare Effect on TIOA 1314 #define AT91C_TC_ACPC_NONE (0x0u << 18) // (TC) Effect: none 1315 #define AT91C_TC_ACPC_SET (0x1u << 18) // (TC) Effect: set 1316 #define AT91C_TC_ACPC_CLEAR (0x2u << 18) // (TC) Effect: clear 1317 #define AT91C_TC_ACPC_TOGGLE (0x3u << 18) // (TC) Effect: toggle 1318 #define AT91C_TC_AEEVT (0x3u << 20) // (TC) External Event Effect on TIOA 1319 #define AT91C_TC_AEEVT_NONE (0x0u << 20) // (TC) Effect: none 1320 #define AT91C_TC_AEEVT_SET (0x1u << 20) // (TC) Effect: set 1321 #define AT91C_TC_AEEVT_CLEAR (0x2u << 20) // (TC) Effect: clear 1322 #define AT91C_TC_AEEVT_TOGGLE (0x3u << 20) // (TC) Effect: toggle 1323 #define AT91C_TC_ASWTRG (0x3u << 22) // (TC) Software Trigger Effect on TIOA 1324 #define AT91C_TC_ASWTRG_NONE (0x0u << 22) // (TC) Effect: none 1325 #define AT91C_TC_ASWTRG_SET (0x1u << 22) // (TC) Effect: set 1326 #define AT91C_TC_ASWTRG_CLEAR (0x2u << 22) // (TC) Effect: clear 1327 #define AT91C_TC_ASWTRG_TOGGLE (0x3u << 22) // (TC) Effect: toggle 1328 #define AT91C_TC_BCPB (0x3u << 24) // (TC) RB Compare Effect on TIOB 1329 #define AT91C_TC_BCPB_NONE (0x0u << 24) // (TC) Effect: none 1330 #define AT91C_TC_BCPB_SET (0x1u << 24) // (TC) Effect: set 1331 #define AT91C_TC_BCPB_CLEAR (0x2u << 24) // (TC) Effect: clear 1332 #define AT91C_TC_BCPB_TOGGLE (0x3u << 24) // (TC) Effect: toggle 1333 #define AT91C_TC_BCPC (0x3u << 26) // (TC) RC Compare Effect on TIOB 1334 #define AT91C_TC_BCPC_NONE (0x0u << 26) // (TC) Effect: none 1335 #define AT91C_TC_BCPC_SET (0x1u << 26) // (TC) Effect: set 1336 #define AT91C_TC_BCPC_CLEAR (0x2u << 26) // (TC) Effect: clear 1337 #define AT91C_TC_BCPC_TOGGLE (0x3u << 26) // (TC) Effect: toggle 1338 #define AT91C_TC_BEEVT (0x3u << 28) // (TC) External Event Effect on TIOB 1339 #define AT91C_TC_BEEVT_NONE (0x0u << 28) // (TC) Effect: none 1340 #define AT91C_TC_BEEVT_SET (0x1u << 28) // (TC) Effect: set 1341 #define AT91C_TC_BEEVT_CLEAR (0x2u << 28) // (TC) Effect: clear 1342 #define AT91C_TC_BEEVT_TOGGLE (0x3u << 28) // (TC) Effect: toggle 1343 #define AT91C_TC_BSWTRG (0x3u << 30) // (TC) Software Trigger Effect on TIOB 1344 #define AT91C_TC_BSWTRG_NONE (0x0u << 30) // (TC) Effect: none 1345 #define AT91C_TC_BSWTRG_SET (0x1u << 30) // (TC) Effect: set 1346 #define AT91C_TC_BSWTRG_CLEAR (0x2u << 30) // (TC) Effect: clear 1347 #define AT91C_TC_BSWTRG_TOGGLE (0x3u << 30) // (TC) Effect: toggle 1348 // -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 1349 #define AT91C_TC_COVFS (0x1u << 0) // (TC) Counter Overflow 1350 #define AT91C_TC_LOVRS (0x1u << 1) // (TC) Load Overrun 1351 #define AT91C_TC_CPAS (0x1u << 2) // (TC) RA Compare 1352 #define AT91C_TC_CPBS (0x1u << 3) // (TC) RB Compare 1353 #define AT91C_TC_CPCS (0x1u << 4) // (TC) RC Compare 1354 #define AT91C_TC_LDRAS (0x1u << 5) // (TC) RA Loading 1355 #define AT91C_TC_LDRBS (0x1u << 6) // (TC) RB Loading 1356 #define AT91C_TC_ETRCS (0x1u << 7) // (TC) External Trigger 1357 #define AT91C_TC_ETRGS (0x1u << 16) // (TC) Clock Enabling 1358 #define AT91C_TC_MTIOA (0x1u << 17) // (TC) TIOA Mirror 1359 #define AT91C_TC_MTIOB (0x1u << 18) // (TC) TIOA Mirror 1360 // -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 1361 // -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 1362 // -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 1363 1364 // ***************************************************************************** 1365 // SOFTWARE API DEFINITION FOR Timer Counter Interface 1366 // ***************************************************************************** 1367 typedef struct _AT91S_TCB { 1368 AT91S_TC TCB_TC0; // TC Channel 0 1369 AT91_REG Reserved0[4]; // 1370 AT91S_TC TCB_TC1; // TC Channel 1 1371 AT91_REG Reserved1[4]; // 1372 AT91S_TC TCB_TC2; // TC Channel 2 1373 AT91_REG Reserved2[4]; // 1374 AT91_REG TCB_BCR; // TC Block Control Register 1375 AT91_REG TCB_BMR; // TC Block Mode Register 1376 } AT91S_TCB, *AT91PS_TCB; 1377 1378 // -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 1379 #define AT91C_TCB_SYNC (0x1u << 0) // (TCB) Synchro Command 1380 // -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 1381 #define AT91C_TCB_TC0XC0S (0x1u << 0) // (TCB) External Clock Signal 0 Selection 1382 #define AT91C_TCB_TC0XC0S_TCLK0 0x0u // (TCB) TCLK0 connected to XC0 1383 #define AT91C_TCB_TC0XC0S_NONE 0x1u // (TCB) None signal connected to XC0 1384 #define AT91C_TCB_TC0XC0S_TIOA1 0x2u // (TCB) TIOA1 connected to XC0 1385 #define AT91C_TCB_TC0XC0S_TIOA2 0x3u // (TCB) TIOA2 connected to XC0 1386 #define AT91C_TCB_TC1XC1S (0x1u << 2) // (TCB) External Clock Signal 1 Selection 1387 #define AT91C_TCB_TC1XC1S_TCLK1 (0x0u << 2) // (TCB) TCLK1 connected to XC1 1388 #define AT91C_TCB_TC1XC1S_NONE (0x1u << 2) // (TCB) None signal connected to XC1 1389 #define AT91C_TCB_TC1XC1S_TIOA0 (0x2u << 2) // (TCB) TIOA0 connected to XC1 1390 #define AT91C_TCB_TC1XC1S_TIOA2 (0x3u << 2) // (TCB) TIOA2 connected to XC1 1391 #define AT91C_TCB_TC2XC2S (0x1u << 4) // (TCB) External Clock Signal 2 Selection 1392 #define AT91C_TCB_TC2XC2S_TCLK2 (0x0u << 4) // (TCB) TCLK2 connected to XC2 1393 #define AT91C_TCB_TC2XC2S_NONE (0x1u << 4) // (TCB) None signal connected to XC2 1394 #define AT91C_TCB_TC2XC2S_TIOA0 (0x2u << 4) // (TCB) TIOA0 connected to XC2 1395 #define AT91C_TCB_TC2XC2S_TIOA2 (0x3u << 4) // (TCB) TIOA2 connected to XC2 1396 1397 // ***************************************************************************** 1398 // SOFTWARE API DEFINITION FOR USB Host Interface 1399 // ***************************************************************************** 1400 typedef struct _AT91S_UHP { 1401 AT91_REG UHP_HcRevision; // Revision 1402 AT91_REG UHP_HcControl; // Operating modes for the Host Controller 1403 AT91_REG UHP_HcCommandStatus; // Command & status Register 1404 AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register 1405 AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register 1406 AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register 1407 AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area 1408 AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor 1409 AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list 1410 AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register 1411 AT91_REG UHP_HcBulkHeadED; // First endpoint register of the Bulk list 1412 AT91_REG UHP_HcBulkCurrentED; // Current endpoint of the Bulk list 1413 AT91_REG UHP_HcBulkDoneHead; // Last completed transfer descriptor 1414 AT91_REG UHP_HcFmInterval; // Bit time between 2 consecutive SOFs 1415 AT91_REG UHP_HcFmRemaining; // Bit time remaining in the current Frame 1416 AT91_REG UHP_HcFmNumber; // Frame number 1417 AT91_REG UHP_HcPeriodicStart; // Periodic Start 1418 AT91_REG UHP_HcLSThreshold; // LS Threshold 1419 AT91_REG UHP_HcRhDescriptorA; // Root Hub characteristics A 1420 AT91_REG UHP_HcRhDescriptorB; // Root Hub characteristics B 1421 AT91_REG UHP_HcRhStatus; // Root Hub Status register 1422 AT91_REG UHP_HcRhPortStatus[2]; // Root Hub Port Status Register 1423 } AT91S_UHP, *AT91PS_UHP; 1424 1425 1426 // ***************************************************************************** 1427 // SOFTWARE API DEFINITION FOR Ethernet MAC 1428 // ***************************************************************************** 1429 typedef struct _AT91S_EMAC { 1430 AT91_REG EMAC_CTL; // Network Control Register 1431 AT91_REG EMAC_CFG; // Network Configuration Register 1432 AT91_REG EMAC_SR; // Network Status Register 1433 AT91_REG EMAC_TAR; // Transmit Address Register 1434 AT91_REG EMAC_TCR; // Transmit Control Register 1435 AT91_REG EMAC_TSR; // Transmit Status Register 1436 AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer 1437 AT91_REG Reserved0[1]; // 1438 AT91_REG EMAC_RSR; // Receive Status Register 1439 AT91_REG EMAC_ISR; // Interrupt Status Register 1440 AT91_REG EMAC_IER; // Interrupt Enable Register 1441 AT91_REG EMAC_IDR; // Interrupt Disable Register 1442 AT91_REG EMAC_IMR; // Interrupt Mask Register 1443 AT91_REG EMAC_MAN; // PHY Maintenance Register 1444 AT91_REG Reserved1[2]; // 1445 AT91_REG EMAC_FRA; // Frames Transmitted OK Register 1446 AT91_REG EMAC_SCOL; // Single Collision Frame Register 1447 AT91_REG EMAC_MCOL; // Multiple Collision Frame Register 1448 AT91_REG EMAC_OK; // Frames Received OK Register 1449 AT91_REG EMAC_SEQE; // Frame Check Sequence Error Register 1450 AT91_REG EMAC_ALE; // Alignment Error Register 1451 AT91_REG EMAC_DTE; // Deferred Transmission Frame Register 1452 AT91_REG EMAC_LCOL; // Late Collision Register 1453 AT91_REG EMAC_ECOL; // Excessive Collision Register 1454 AT91_REG EMAC_CSE; // Carrier Sense Error Register 1455 AT91_REG EMAC_TUE; // Transmit Underrun Error Register 1456 AT91_REG EMAC_CDE; // Code Error Register 1457 AT91_REG EMAC_ELR; // Excessive Length Error Register 1458 AT91_REG EMAC_RJB; // Receive Jabber Register 1459 AT91_REG EMAC_USF; // Undersize Frame Register 1460 AT91_REG EMAC_SQEE; // SQE Test Error Register 1461 AT91_REG EMAC_DRFC; // Discarded RX Frame Register 1462 AT91_REG Reserved2[3]; // 1463 AT91_REG EMAC_HSH; // Hash Address High[63:32] 1464 AT91_REG EMAC_HSL; // Hash Address Low[31:0] 1465 AT91_REG EMAC_SA1L; // Specific Address 1 Low, First 4 bytes 1466 AT91_REG EMAC_SA1H; // Specific Address 1 High, Last 2 bytes 1467 AT91_REG EMAC_SA2L; // Specific Address 2 Low, First 4 bytes 1468 AT91_REG EMAC_SA2H; // Specific Address 2 High, Last 2 bytes 1469 AT91_REG EMAC_SA3L; // Specific Address 3 Low, First 4 bytes 1470 AT91_REG EMAC_SA3H; // Specific Address 3 High, Last 2 bytes 1471 AT91_REG EMAC_SA4L; // Specific Address 4 Low, First 4 bytes 1472 AT91_REG EMAC_SA4H; // Specific Address 4 High, Last 2 bytesr 1473 } AT91S_EMAC, *AT91PS_EMAC; 1474 1475 // -------- EMAC_CTL : (EMAC Offset: 0x0) -------- 1476 #define AT91C_EMAC_LB (0x1u << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. 1477 #define AT91C_EMAC_LBL (0x1u << 1) // (EMAC) Loopback local. 1478 #define AT91C_EMAC_RE (0x1u << 2) // (EMAC) Receive enable. 1479 #define AT91C_EMAC_TE (0x1u << 3) // (EMAC) Transmit enable. 1480 #define AT91C_EMAC_MPE (0x1u << 4) // (EMAC) Management port enable. 1481 #define AT91C_EMAC_CSR (0x1u << 5) // (EMAC) Clear statistics registers. 1482 #define AT91C_EMAC_ISR (0x1u << 6) // (EMAC) Increment statistics registers. 1483 #define AT91C_EMAC_WES (0x1u << 7) // (EMAC) Write enable for statistics registers. 1484 #define AT91C_EMAC_BP (0x1u << 8) // (EMAC) Back pressure. 1485 // -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- 1486 #define AT91C_EMAC_SPD (0x1u << 0) // (EMAC) Speed. 1487 #define AT91C_EMAC_FD (0x1u << 1) // (EMAC) Full duplex. 1488 #define AT91C_EMAC_BR (0x1u << 2) // (EMAC) Bit rate. 1489 #define AT91C_EMAC_CAF (0x1u << 4) // (EMAC) Copy all frames. 1490 #define AT91C_EMAC_NBC (0x1u << 5) // (EMAC) No broadcast. 1491 #define AT91C_EMAC_MTI (0x1u << 6) // (EMAC) Multicast hash enable 1492 #define AT91C_EMAC_UNI (0x1u << 7) // (EMAC) Unicast hash enable. 1493 #define AT91C_EMAC_BIG (0x1u << 8) // (EMAC) Receive 1522 bytes. 1494 #define AT91C_EMAC_EAE (0x1u << 9) // (EMAC) External address match enable. 1495 #define AT91C_EMAC_CLK (0x3u << 10) // (EMAC) 1496 #define AT91C_EMAC_CLK_HCLK_8 (0x0u << 10) // (EMAC) HCLK divided by 8 1497 #define AT91C_EMAC_CLK_HCLK_16 (0x1u << 10) // (EMAC) HCLK divided by 16 1498 #define AT91C_EMAC_CLK_HCLK_32 (0x2u << 10) // (EMAC) HCLK divided by 32 1499 #define AT91C_EMAC_CLK_HCLK_64 (0x3u << 10) // (EMAC) HCLK divided by 64 1500 #define AT91C_EMAC_RTY (0x1u << 12) // (EMAC) 1501 #define AT91C_EMAC_RMII (0x1u << 13) // (EMAC) 1502 // -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- 1503 #define AT91C_EMAC_MDIO (0x1u << 1) // (EMAC) 1504 #define AT91C_EMAC_IDLE (0x1u << 2) // (EMAC) 1505 // -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- 1506 #define AT91C_EMAC_LEN (0x7FFu << 0) // (EMAC) 1507 #define AT91C_EMAC_NCRC (0x1u << 15) // (EMAC) 1508 // -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- 1509 #define AT91C_EMAC_OVR (0x1u << 0) // (EMAC) 1510 #define AT91C_EMAC_COL (0x1u << 1) // (EMAC) 1511 #define AT91C_EMAC_RLE (0x1u << 2) // (EMAC) 1512 #define AT91C_EMAC_TXIDLE (0x1u << 3) // (EMAC) 1513 #define AT91C_EMAC_BNQ (0x1u << 4) // (EMAC) 1514 #define AT91C_EMAC_COMP (0x1u << 5) // (EMAC) 1515 #define AT91C_EMAC_UND (0x1u << 6) // (EMAC) 1516 // -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 1517 #define AT91C_EMAC_BNA (0x1u << 0) // (EMAC) 1518 #define AT91C_EMAC_REC (0x1u << 1) // (EMAC) 1519 // -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 1520 #define AT91C_EMAC_DONE (0x1u << 0) // (EMAC) 1521 #define AT91C_EMAC_RCOM (0x1u << 1) // (EMAC) 1522 #define AT91C_EMAC_RBNA (0x1u << 2) // (EMAC) 1523 #define AT91C_EMAC_TOVR (0x1u << 3) // (EMAC) 1524 #define AT91C_EMAC_TUND (0x1u << 4) // (EMAC) 1525 #define AT91C_EMAC_RTRY (0x1u << 5) // (EMAC) 1526 #define AT91C_EMAC_TBRE (0x1u << 6) // (EMAC) 1527 #define AT91C_EMAC_TCOM (0x1u << 7) // (EMAC) 1528 #define AT91C_EMAC_TIDLE (0x1u << 8) // (EMAC) 1529 #define AT91C_EMAC_LINK (0x1u << 9) // (EMAC) 1530 #define AT91C_EMAC_ROVR (0x1u << 10) // (EMAC) 1531 #define AT91C_EMAC_HRESP (0x1u << 11) // (EMAC) 1532 // -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 1533 // -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 1534 // -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 1535 // -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 1536 #define AT91C_EMAC_DATA (0xFFFFu << 0) // (EMAC) 1537 #define AT91C_EMAC_CODE (0x3u << 16) // (EMAC) 1538 #define AT91C_EMAC_REGA (0x1Fu << 18) // (EMAC) 1539 #define AT91C_EMAC_PHYA (0x1Fu << 23) // (EMAC) 1540 #define AT91C_EMAC_RW (0x3u << 28) // (EMAC) 1541 #define AT91C_EMAC_HIGH (0x1u << 30) // (EMAC) 1542 #define AT91C_EMAC_LOW (0x1u << 31) // (EMAC) 1543 1544 // ***************************************************************************** 1545 // SOFTWARE API DEFINITION FOR External Bus Interface 1546 // ***************************************************************************** 1547 typedef struct _AT91S_EBI { 1548 AT91_REG EBI_CSA; // Chip Select Assignment Register 1549 AT91_REG EBI_CFGR; // Configuration Register 1550 } AT91S_EBI, *AT91PS_EBI; 1551 1552 // -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- 1553 #define AT91C_EBI_CS0A (0x1u << 0) // (EBI) Chip Select 0 Assignment 1554 #define AT91C_EBI_CS0A_SMC 0x0u // (EBI) Chip Select 0 is assigned to the Static Memory Controller. 1555 #define AT91C_EBI_CS0A_BFC 0x1u // (EBI) Chip Select 0 is assigned to the Burst Flash Controller. 1556 #define AT91C_EBI_CS1A (0x1u << 1) // (EBI) Chip Select 1 Assignment 1557 #define AT91C_EBI_CS1A_SMC (0x0u << 1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller. 1558 #define AT91C_EBI_CS1A_SDRAMC (0x1u << 1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller. 1559 #define AT91C_EBI_CS3A (0x1u << 3) // (EBI) Chip Select 3 Assignment 1560 #define AT91C_EBI_CS3A_SMC (0x0u << 3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2. 1561 #define AT91C_EBI_CS3A_SMC_SmartMedia (0x1u << 3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. 1562 #define AT91C_EBI_CS4A (0x1u << 4) // (EBI) Chip Select 4 Assignment 1563 #define AT91C_EBI_CS4A_SMC (0x0u << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2. 1564 #define AT91C_EBI_CS4A_SMC_CompactFlash (0x1u << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. 1565 // -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- 1566 #define AT91C_EBI_DBPUC (0x1u << 0) // (EBI) Data Bus Pull-Up Configuration 1567 #define AT91C_EBI_EBSEN (0x1u << 1) // (EBI) Bus Sharing Enable 1568 1569 // ***************************************************************************** 1570 // SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface 1571 // ***************************************************************************** 1572 typedef struct _AT91S_SMC2 { 1573 AT91_REG SMC2_CSR[8]; // SMC2 Chip Select Register 1574 } AT91S_SMC2, *AT91PS_SMC2; 1575 1576 // -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- 1577 #define AT91C_SMC2_NWS (0x7Fu << 0) // (SMC2) Number of Wait States 1578 #define AT91C_SMC2_WSEN (0x1u << 7) // (SMC2) Wait State Enable 1579 #define AT91C_SMC2_TDF (0xFu << 8) // (SMC2) Data Float Time 1580 #define AT91C_SMC2_BAT (0x1u << 12) // (SMC2) Byte Access Type 1581 #define AT91C_SMC2_DBW (0x1u << 13) // (SMC2) Data Bus Width 1582 #define AT91C_SMC2_DBW_16 (0x1u << 13) // (SMC2) 16-bit. 1583 #define AT91C_SMC2_DBW_8 (0x2u << 13) // (SMC2) 8-bit. 1584 #define AT91C_SMC2_DRP (0x1u << 15) // (SMC2) Data Read Protocol 1585 #define AT91C_SMC2_ACSS (0x3u << 16) // (SMC2) Address to Chip Select Setup 1586 #define AT91C_SMC2_ACSS_STANDARD (0x0u << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. 1587 #define AT91C_SMC2_ACSS_1_CYCLE (0x1u << 16) // (SMC2) One cycle less at the beginning and the end of the access. 1588 #define AT91C_SMC2_ACSS_2_CYCLES (0x2u << 16) // (SMC2) Two cycles less at the beginning and the end of the access. 1589 #define AT91C_SMC2_ACSS_3_CYCLES (0x3u << 16) // (SMC2) Three cycles less at the beginning and the end of the access. 1590 #define AT91C_SMC2_RWSETUP (0x7u << 24) // (SMC2) Read and Write Signal Setup Time 1591 #define AT91C_SMC2_RWHOLD (0x7u << 29) // (SMC2) Read and Write Signal Hold Time 1592 1593 // ***************************************************************************** 1594 // SOFTWARE API DEFINITION FOR SDRAM Controller Interface 1595 // ***************************************************************************** 1596 typedef struct _AT91S_SDRC { 1597 AT91_REG SDRC_MR; // SDRAM Controller Mode Register 1598 AT91_REG SDRC_TR; // SDRAM Controller Refresh Timer Register 1599 AT91_REG SDRC_CR; // SDRAM Controller Configuration Register 1600 AT91_REG SDRC_SRR; // SDRAM Controller Self Refresh Register 1601 AT91_REG SDRC_LPR; // SDRAM Controller Low Power Register 1602 AT91_REG SDRC_IER; // SDRAM Controller Interrupt Enable Register 1603 AT91_REG SDRC_IDR; // SDRAM Controller Interrupt Disable Register 1604 AT91_REG SDRC_IMR; // SDRAM Controller Interrupt Mask Register 1605 AT91_REG SDRC_ISR; // SDRAM Controller Interrupt Mask Register 1606 } AT91S_SDRC, *AT91PS_SDRC; 1607 1608 // -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- 1609 #define AT91C_SDRC_MODE (0xFu << 0) // (SDRC) Mode 1610 #define AT91C_SDRC_MODE_NORMAL_CMD 0x0u // (SDRC) Normal Mode 1611 #define AT91C_SDRC_MODE_NOP_CMD 0x1u // (SDRC) NOP Command 1612 #define AT91C_SDRC_MODE_PRCGALL_CMD 0x2u // (SDRC) All Banks Precharge Command 1613 #define AT91C_SDRC_MODE_LMR_CMD 0x3u // (SDRC) Load Mode Register Command 1614 #define AT91C_SDRC_MODE_RFSH_CMD 0x4u // (SDRC) Refresh Command 1615 #define AT91C_SDRC_DBW (0x1u << 4) // (SDRC) Data Bus Width 1616 #define AT91C_SDRC_DBW_32_BITS (0x0u << 4) // (SDRC) 32 Bits datas bus 1617 #define AT91C_SDRC_DBW_16_BITS (0x1u << 4) // (SDRC) 16 Bits datas bus 1618 // -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- 1619 #define AT91C_SDRC_COUNT (0xFFFu << 0) // (SDRC) Refresh Counter 1620 // -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- 1621 #define AT91C_SDRC_NC (0x3u << 0) // (SDRC) Number of Column Bits 1622 #define AT91C_SDRC_NC_8 0x0u // (SDRC) 8 Bits 1623 #define AT91C_SDRC_NC_9 0x1u // (SDRC) 9 Bits 1624 #define AT91C_SDRC_NC_10 0x2u // (SDRC) 10 Bits 1625 #define AT91C_SDRC_NC_11 0x3u // (SDRC) 11 Bits 1626 #define AT91C_SDRC_NR (0x3u << 2) // (SDRC) Number of Row Bits 1627 #define AT91C_SDRC_NR_11 (0x0u << 2) // (SDRC) 11 Bits 1628 #define AT91C_SDRC_NR_12 (0x1u << 2) // (SDRC) 12 Bits 1629 #define AT91C_SDRC_NR_13 (0x2u << 2) // (SDRC) 13 Bits 1630 #define AT91C_SDRC_NB (0x1u << 4) // (SDRC) Number of Banks 1631 #define AT91C_SDRC_NB_2_BANKS (0x0u << 4) // (SDRC) 2 banks 1632 #define AT91C_SDRC_NB_4_BANKS (0x1u << 4) // (SDRC) 4 banks 1633 #define AT91C_SDRC_CAS (0x3u << 5) // (SDRC) CAS Latency 1634 #define AT91C_SDRC_CAS_2 (0x2u << 5) // (SDRC) 2 cycles 1635 #define AT91C_SDRC_TWR (0xFu << 7) // (SDRC) Number of Write Recovery Time Cycles 1636 #define AT91C_SDRC_TRC (0xFu << 11) // (SDRC) Number of RAS Cycle Time Cycles 1637 #define AT91C_SDRC_TRP (0xFu << 15) // (SDRC) Number of RAS Precharge Time Cycles 1638 #define AT91C_SDRC_TRCD (0xFu << 19) // (SDRC) Number of RAS to CAS Delay Cycles 1639 #define AT91C_SDRC_TRAS (0xFu << 23) // (SDRC) Number of RAS Active Time Cycles 1640 #define AT91C_SDRC_TXSR (0xFu << 27) // (SDRC) Number of Command Recovery Time Cycles 1641 // -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- 1642 #define AT91C_SDRC_SRCB (0x1u << 0) // (SDRC) Self-refresh Command Bit 1643 // -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- 1644 #define AT91C_SDRC_LPCB (0x1u << 0) // (SDRC) Low-power Command Bit 1645 // -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- 1646 #define AT91C_SDRC_RES (0x1u << 0) // (SDRC) Refresh Error Status 1647 // -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- 1648 // -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- 1649 // -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- 1650 1651 // ***************************************************************************** 1652 // SOFTWARE API DEFINITION FOR Burst Flash Controller Interface 1653 // ***************************************************************************** 1654 typedef struct _AT91S_BFC { 1655 AT91_REG BFC_MR; // BFC Mode Register 1656 } AT91S_BFC, *AT91PS_BFC; 1657 1658 // -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- 1659 #define AT91C_BFC_BFCOM (0x3u << 0) // (BFC) Burst Flash Controller Operating Mode 1660 #define AT91C_BFC_BFCOM_DISABLED 0x0u // (BFC) NPCS0 is driven by the SMC or remains high. 1661 #define AT91C_BFC_BFCOM_ASYNC 0x1u // (BFC) Asynchronous 1662 #define AT91C_BFC_BFCOM_BURST_READ 0x2u // (BFC) Burst Read 1663 #define AT91C_BFC_BFCC (0x3u << 2) // (BFC) Burst Flash Controller Operating Mode 1664 #define AT91C_BFC_BFCC_MCK (0x1u << 2) // (BFC) Master Clock. 1665 #define AT91C_BFC_BFCC_MCK_DIV_2 (0x2u << 2) // (BFC) Master Clock divided by 2. 1666 #define AT91C_BFC_BFCC_MCK_DIV_4 (0x3u << 2) // (BFC) Master Clock divided by 4. 1667 #define AT91C_BFC_AVL (0xFu << 4) // (BFC) Address Valid Latency 1668 #define AT91C_BFC_PAGES (0x7u << 8) // (BFC) Page Size 1669 #define AT91C_BFC_PAGES_NO_PAGE (0x0u << 8) // (BFC) No page handling. 1670 #define AT91C_BFC_PAGES_16 (0x1u << 8) // (BFC) 16 bytes page size. 1671 #define AT91C_BFC_PAGES_32 (0x2u << 8) // (BFC) 32 bytes page size. 1672 #define AT91C_BFC_PAGES_64 (0x3u << 8) // (BFC) 64 bytes page size. 1673 #define AT91C_BFC_PAGES_128 (0x4u << 8) // (BFC) 128 bytes page size. 1674 #define AT91C_BFC_PAGES_256 (0x5u << 8) // (BFC) 256 bytes page size. 1675 #define AT91C_BFC_PAGES_512 (0x6u << 8) // (BFC) 512 bytes page size. 1676 #define AT91C_BFC_PAGES_1024 (0x7u << 8) // (BFC) 1024 bytes page size. 1677 #define AT91C_BFC_OEL (0x3u << 12) // (BFC) Output Enable Latency 1678 #define AT91C_BFC_BAAEN (0x1u << 16) // (BFC) Burst Address Advance Enable 1679 #define AT91C_BFC_BFOEH (0x1u << 17) // (BFC) Burst Flash Output Enable Handling 1680 #define AT91C_BFC_MUXEN (0x1u << 18) // (BFC) Multiplexed Bus Enable 1681 #define AT91C_BFC_RDYEN (0x1u << 19) // (BFC) Ready Enable Mode 1682 1683 // ***************************************************************************** 1684 // REGISTER ADDRESS DEFINITION FOR AT91RM9200 1685 // ***************************************************************************** 1686 // ========== Register definition for SYS peripheral ========== 1687 // ========== Register definition for MC peripheral ========== 1688 #define AT91C_MC_PUER ((AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register 1689 #define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register 1690 #define AT91C_MC_PUP ((AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals 1691 #define AT91C_MC_PUIA ((AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area 1692 #define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register 1693 #define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register 1694 // ========== Register definition for RTC peripheral ========== 1695 #define AT91C_RTC_IMR ((AT91_REG *) 0xFFFFFE28) // (RTC) Interrupt Mask Register 1696 #define AT91C_RTC_IER ((AT91_REG *) 0xFFFFFE20) // (RTC) Interrupt Enable Register 1697 #define AT91C_RTC_SR ((AT91_REG *) 0xFFFFFE18) // (RTC) Status Register 1698 #define AT91C_RTC_TIMALR ((AT91_REG *) 0xFFFFFE10) // (RTC) Time Alarm Register 1699 #define AT91C_RTC_TIMR ((AT91_REG *) 0xFFFFFE08) // (RTC) Time Register 1700 #define AT91C_RTC_CR ((AT91_REG *) 0xFFFFFE00) // (RTC) Control Register 1701 #define AT91C_RTC_VER ((AT91_REG *) 0xFFFFFE2C) // (RTC) Valid Entry Register 1702 #define AT91C_RTC_IDR ((AT91_REG *) 0xFFFFFE24) // (RTC) Interrupt Disable Register 1703 #define AT91C_RTC_SCCR ((AT91_REG *) 0xFFFFFE1C) // (RTC) Status Clear Command Register 1704 #define AT91C_RTC_CALALR ((AT91_REG *) 0xFFFFFE14) // (RTC) Calendar Alarm Register 1705 #define AT91C_RTC_CALR ((AT91_REG *) 0xFFFFFE0C) // (RTC) Calendar Register 1706 #define AT91C_RTC_MR ((AT91_REG *) 0xFFFFFE04) // (RTC) Mode Register 1707 // ========== Register definition for ST peripheral ========== 1708 #define AT91C_ST_CRTR ((AT91_REG *) 0xFFFFFD24) // (ST) Current Real-time Register 1709 #define AT91C_ST_IMR ((AT91_REG *) 0xFFFFFD1C) // (ST) Interrupt Mask Register 1710 #define AT91C_ST_IER ((AT91_REG *) 0xFFFFFD14) // (ST) Interrupt Enable Register 1711 #define AT91C_ST_RTMR ((AT91_REG *) 0xFFFFFD0C) // (ST) Real-time Mode Register 1712 #define AT91C_ST_PIMR ((AT91_REG *) 0xFFFFFD04) // (ST) Period Interval Mode Register 1713 #define AT91C_ST_RTAR ((AT91_REG *) 0xFFFFFD20) // (ST) Real-time Alarm Register 1714 #define AT91C_ST_IDR ((AT91_REG *) 0xFFFFFD18) // (ST) Interrupt Disable Register 1715 #define AT91C_ST_SR ((AT91_REG *) 0xFFFFFD10) // (ST) Status Register 1716 #define AT91C_ST_WDMR ((AT91_REG *) 0xFFFFFD08) // (ST) Watchdog Mode Register 1717 #define AT91C_ST_CR ((AT91_REG *) 0xFFFFFD00) // (ST) Control Register 1718 // ========== Register definition for PMC peripheral ========== 1719 #define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register 1720 #define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register 1721 #define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register 1722 #define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register 1723 #define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register 1724 #define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register 1725 #define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register 1726 #define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register 1727 #define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register 1728 #define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register 1729 #define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register 1730 #define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register 1731 // ========== Register definition for CKGR peripheral ========== 1732 #define AT91C_CKGR_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register 1733 #define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register 1734 #define AT91C_CKGR_PLLAR ((AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register 1735 #define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register 1736 // ========== Register definition for PIOD peripheral ========== 1737 #define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) // (PIOD) Pin Data Status Register 1738 #define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) // (PIOD) Clear Output Data Register 1739 #define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) // (PIOD) Output Write Enable Register 1740 #define AT91C_PIOD_MDER ((AT91_REG *) 0xFFFFFA50) // (PIOD) Multi-driver Enable Register 1741 #define AT91C_PIOD_IMR ((AT91_REG *) 0xFFFFFA48) // (PIOD) Interrupt Mask Register 1742 #define AT91C_PIOD_IER ((AT91_REG *) 0xFFFFFA40) // (PIOD) Interrupt Enable Register 1743 #define AT91C_PIOD_ODSR ((AT91_REG *) 0xFFFFFA38) // (PIOD) Output Data Status Register 1744 #define AT91C_PIOD_SODR ((AT91_REG *) 0xFFFFFA30) // (PIOD) Set Output Data Register 1745 #define AT91C_PIOD_PER ((AT91_REG *) 0xFFFFFA00) // (PIOD) PIO Enable Register 1746 #define AT91C_PIOD_OWDR ((AT91_REG *) 0xFFFFFAA4) // (PIOD) Output Write Disable Register 1747 #define AT91C_PIOD_PPUER ((AT91_REG *) 0xFFFFFA64) // (PIOD) Pull-up Enable Register 1748 #define AT91C_PIOD_MDDR ((AT91_REG *) 0xFFFFFA54) // (PIOD) Multi-driver Disable Register 1749 #define AT91C_PIOD_ISR ((AT91_REG *) 0xFFFFFA4C) // (PIOD) Interrupt Status Register 1750 #define AT91C_PIOD_IDR ((AT91_REG *) 0xFFFFFA44) // (PIOD) Interrupt Disable Register 1751 #define AT91C_PIOD_PDR ((AT91_REG *) 0xFFFFFA04) // (PIOD) PIO Disable Register 1752 #define AT91C_PIOD_ODR ((AT91_REG *) 0xFFFFFA14) // (PIOD) Output Disable Registerr 1753 #define AT91C_PIOD_OWSR ((AT91_REG *) 0xFFFFFAA8) // (PIOD) Output Write Status Register 1754 #define AT91C_PIOD_ABSR ((AT91_REG *) 0xFFFFFA78) // (PIOD) AB Select Status Register 1755 #define AT91C_PIOD_ASR ((AT91_REG *) 0xFFFFFA70) // (PIOD) Select A Register 1756 #define AT91C_PIOD_PPUSR ((AT91_REG *) 0xFFFFFA68) // (PIOD) Pad Pull-up Status Register 1757 #define AT91C_PIOD_PPUDR ((AT91_REG *) 0xFFFFFA60) // (PIOD) Pull-up Disable Register 1758 #define AT91C_PIOD_MDSR ((AT91_REG *) 0xFFFFFA58) // (PIOD) Multi-driver Status Register 1759 #define AT91C_PIOD_PSR ((AT91_REG *) 0xFFFFFA08) // (PIOD) PIO Status Register 1760 #define AT91C_PIOD_OER ((AT91_REG *) 0xFFFFFA10) // (PIOD) Output Enable Register 1761 #define AT91C_PIOD_OSR ((AT91_REG *) 0xFFFFFA18) // (PIOD) Output Status Register 1762 #define AT91C_PIOD_IFER ((AT91_REG *) 0xFFFFFA20) // (PIOD) Input Filter Enable Register 1763 #define AT91C_PIOD_BSR ((AT91_REG *) 0xFFFFFA74) // (PIOD) Select B Register 1764 #define AT91C_PIOD_IFDR ((AT91_REG *) 0xFFFFFA24) // (PIOD) Input Filter Disable Register 1765 #define AT91C_PIOD_IFSR ((AT91_REG *) 0xFFFFFA28) // (PIOD) Input Filter Status Register 1766 // ========== Register definition for PIOC peripheral ========== 1767 #define AT91C_PIOC_IFDR ((AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register 1768 #define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr 1769 #define AT91C_PIOC_ABSR ((AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register 1770 #define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) // (PIOC) Set Output Data Register 1771 #define AT91C_PIOC_IFSR ((AT91_REG *) 0xFFFFF828) // (PIOC) Input Filter Status Register 1772 #define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) // (PIOC) Clear Output Data Register 1773 #define AT91C_PIOC_ODSR ((AT91_REG *) 0xFFFFF838) // (PIOC) Output Data Status Register 1774 #define AT91C_PIOC_IER ((AT91_REG *) 0xFFFFF840) // (PIOC) Interrupt Enable Register 1775 #define AT91C_PIOC_IMR ((AT91_REG *) 0xFFFFF848) // (PIOC) Interrupt Mask Register 1776 #define AT91C_PIOC_OWDR ((AT91_REG *) 0xFFFFF8A4) // (PIOC) Output Write Disable Register 1777 #define AT91C_PIOC_MDDR ((AT91_REG *) 0xFFFFF854) // (PIOC) Multi-driver Disable Register 1778 #define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) // (PIOC) Pin Data Status Register 1779 #define AT91C_PIOC_IDR ((AT91_REG *) 0xFFFFF844) // (PIOC) Interrupt Disable Register 1780 #define AT91C_PIOC_ISR ((AT91_REG *) 0xFFFFF84C) // (PIOC) Interrupt Status Register 1781 #define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) // (PIOC) PIO Disable Register 1782 #define AT91C_PIOC_OWSR ((AT91_REG *) 0xFFFFF8A8) // (PIOC) Output Write Status Register 1783 #define AT91C_PIOC_OWER ((AT91_REG *) 0xFFFFF8A0) // (PIOC) Output Write Enable Register 1784 #define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register 1785 #define AT91C_PIOC_PPUSR ((AT91_REG *) 0xFFFFF868) // (PIOC) Pad Pull-up Status Register 1786 #define AT91C_PIOC_PPUDR ((AT91_REG *) 0xFFFFF860) // (PIOC) Pull-up Disable Register 1787 #define AT91C_PIOC_MDSR ((AT91_REG *) 0xFFFFF858) // (PIOC) Multi-driver Status Register 1788 #define AT91C_PIOC_MDER ((AT91_REG *) 0xFFFFF850) // (PIOC) Multi-driver Enable Register 1789 #define AT91C_PIOC_IFER ((AT91_REG *) 0xFFFFF820) // (PIOC) Input Filter Enable Register 1790 #define AT91C_PIOC_OSR ((AT91_REG *) 0xFFFFF818) // (PIOC) Output Status Register 1791 #define AT91C_PIOC_OER ((AT91_REG *) 0xFFFFF810) // (PIOC) Output Enable Register 1792 #define AT91C_PIOC_PSR ((AT91_REG *) 0xFFFFF808) // (PIOC) PIO Status Register 1793 #define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register 1794 #define AT91C_PIOC_BSR ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register 1795 #define AT91C_PIOC_PPUER ((AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register 1796 // ========== Register definition for PIOB peripheral ========== 1797 #define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register 1798 #define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pad Pull-up Status Register 1799 #define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register 1800 #define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register 1801 #define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register 1802 #define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register 1803 #define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register 1804 #define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register 1805 #define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register 1806 #define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register 1807 #define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register 1808 #define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register 1809 #define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register 1810 #define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr 1811 #define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register 1812 #define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register 1813 #define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register 1814 #define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register 1815 #define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register 1816 #define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register 1817 #define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register 1818 #define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register 1819 #define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register 1820 #define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register 1821 #define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register 1822 #define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register 1823 #define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register 1824 #define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register 1825 #define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register 1826 // ========== Register definition for PIOA peripheral ========== 1827 #define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register 1828 #define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register 1829 #define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register 1830 #define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register 1831 #define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register 1832 #define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register 1833 #define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register 1834 #define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register 1835 #define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register 1836 #define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register 1837 #define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register 1838 #define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register 1839 #define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register 1840 #define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register 1841 #define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr 1842 #define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register 1843 #define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register 1844 #define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register 1845 #define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pad Pull-up Status Register 1846 #define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register 1847 #define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register 1848 #define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register 1849 #define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register 1850 #define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register 1851 #define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register 1852 #define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register 1853 #define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register 1854 #define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register 1855 #define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register 1856 // ========== Register definition for DBGU peripheral ========== 1857 #define AT91C_DBGU_C2R ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID2 Register 1858 #define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register 1859 #define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register 1860 #define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register 1861 #define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register 1862 #define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register 1863 #define AT91C_DBGU_C1R ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID1 Register 1864 #define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register 1865 #define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register 1866 #define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register 1867 #define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register 1868 #define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register 1869 // ========== Register definition for PDC_DBGU peripheral ========== 1870 #define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register 1871 #define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register 1872 #define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register 1873 #define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register 1874 #define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register 1875 #define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register 1876 #define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register 1877 #define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register 1878 #define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register 1879 #define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register 1880 // ========== Register definition for AIC peripheral ========== 1881 #define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register 1882 #define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register 1883 #define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register 1884 #define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register 1885 #define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register 1886 #define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) 1887 #define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register 1888 #define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register 1889 #define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register 1890 #define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register 1891 #define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register 1892 #define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register 1893 #define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register 1894 #define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register 1895 #define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register 1896 #define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register 1897 #define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register 1898 #define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register 1899 // ========== Register definition for PDC_SPI peripheral ========== 1900 #define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register 1901 #define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register 1902 #define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register 1903 #define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register 1904 #define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register 1905 #define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register 1906 #define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register 1907 #define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register 1908 #define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register 1909 #define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register 1910 // ========== Register definition for SPI peripheral ========== 1911 #define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register 1912 #define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register 1913 #define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register 1914 #define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register 1915 #define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register 1916 #define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register 1917 #define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register 1918 #define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register 1919 #define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register 1920 // ========== Register definition for PDC_SSC2 peripheral ========== 1921 #define AT91C_SSC2_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_SSC2) PDC Transfer Control Register 1922 #define AT91C_SSC2_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_SSC2) Transmit Next Pointer Register 1923 #define AT91C_SSC2_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_SSC2) Receive Next Pointer Register 1924 #define AT91C_SSC2_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_SSC2) Transmit Pointer Register 1925 #define AT91C_SSC2_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_SSC2) Receive Pointer Register 1926 #define AT91C_SSC2_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_SSC2) PDC Transfer Status Register 1927 #define AT91C_SSC2_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_SSC2) Transmit Next Counter Register 1928 #define AT91C_SSC2_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_SSC2) Receive Next Counter Register 1929 #define AT91C_SSC2_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_SSC2) Transmit Counter Register 1930 #define AT91C_SSC2_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_SSC2) Receive Counter Register 1931 // ========== Register definition for SSC2 peripheral ========== 1932 #define AT91C_SSC2_IMR ((AT91_REG *) 0xFFFD804C) // (SSC2) Interrupt Mask Register 1933 #define AT91C_SSC2_IER ((AT91_REG *) 0xFFFD8044) // (SSC2) Interrupt Enable Register 1934 #define AT91C_SSC2_RC1R ((AT91_REG *) 0xFFFD803C) // (SSC2) Receive Compare 1 Register 1935 #define AT91C_SSC2_TSHR ((AT91_REG *) 0xFFFD8034) // (SSC2) Transmit Sync Holding Register 1936 #define AT91C_SSC2_CMR ((AT91_REG *) 0xFFFD8004) // (SSC2) Clock Mode Register 1937 #define AT91C_SSC2_IDR ((AT91_REG *) 0xFFFD8048) // (SSC2) Interrupt Disable Register 1938 #define AT91C_SSC2_TCMR ((AT91_REG *) 0xFFFD8018) // (SSC2) Transmit Clock Mode Register 1939 #define AT91C_SSC2_RCMR ((AT91_REG *) 0xFFFD8010) // (SSC2) Receive Clock ModeRegister 1940 #define AT91C_SSC2_CR ((AT91_REG *) 0xFFFD8000) // (SSC2) Control Register 1941 #define AT91C_SSC2_RFMR ((AT91_REG *) 0xFFFD8014) // (SSC2) Receive Frame Mode Register 1942 #define AT91C_SSC2_TFMR ((AT91_REG *) 0xFFFD801C) // (SSC2) Transmit Frame Mode Register 1943 #define AT91C_SSC2_THR ((AT91_REG *) 0xFFFD8024) // (SSC2) Transmit Holding Register 1944 #define AT91C_SSC2_SR ((AT91_REG *) 0xFFFD8040) // (SSC2) Status Register 1945 #define AT91C_SSC2_RC0R ((AT91_REG *) 0xFFFD8038) // (SSC2) Receive Compare 0 Register 1946 #define AT91C_SSC2_RSHR ((AT91_REG *) 0xFFFD8030) // (SSC2) Receive Sync Holding Register 1947 #define AT91C_SSC2_RHR ((AT91_REG *) 0xFFFD8020) // (SSC2) Receive Holding Register 1948 // ========== Register definition for PDC_SSC1 peripheral ========== 1949 #define AT91C_SSC1_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register 1950 #define AT91C_SSC1_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register 1951 #define AT91C_SSC1_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register 1952 #define AT91C_SSC1_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC1) Transmit Pointer Register 1953 #define AT91C_SSC1_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC1) Receive Pointer Register 1954 #define AT91C_SSC1_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC1) PDC Transfer Status Register 1955 #define AT91C_SSC1_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC1) Transmit Next Counter Register 1956 #define AT91C_SSC1_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register 1957 #define AT91C_SSC1_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC1) Transmit Counter Register 1958 #define AT91C_SSC1_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC1) Receive Counter Register 1959 // ========== Register definition for SSC1 peripheral ========== 1960 #define AT91C_SSC1_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC1) Receive Frame Mode Register 1961 #define AT91C_SSC1_CMR ((AT91_REG *) 0xFFFD4004) // (SSC1) Clock Mode Register 1962 #define AT91C_SSC1_IDR ((AT91_REG *) 0xFFFD4048) // (SSC1) Interrupt Disable Register 1963 #define AT91C_SSC1_SR ((AT91_REG *) 0xFFFD4040) // (SSC1) Status Register 1964 #define AT91C_SSC1_RC0R ((AT91_REG *) 0xFFFD4038) // (SSC1) Receive Compare 0 Register 1965 #define AT91C_SSC1_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC1) Receive Sync Holding Register 1966 #define AT91C_SSC1_RHR ((AT91_REG *) 0xFFFD4020) // (SSC1) Receive Holding Register 1967 #define AT91C_SSC1_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC1) Transmit Clock Mode Register 1968 #define AT91C_SSC1_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC1) Receive Clock ModeRegister 1969 #define AT91C_SSC1_CR ((AT91_REG *) 0xFFFD4000) // (SSC1) Control Register 1970 #define AT91C_SSC1_IMR ((AT91_REG *) 0xFFFD404C) // (SSC1) Interrupt Mask Register 1971 #define AT91C_SSC1_IER ((AT91_REG *) 0xFFFD4044) // (SSC1) Interrupt Enable Register 1972 #define AT91C_SSC1_RC1R ((AT91_REG *) 0xFFFD403C) // (SSC1) Receive Compare 1 Register 1973 #define AT91C_SSC1_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC1) Transmit Sync Holding Register 1974 #define AT91C_SSC1_THR ((AT91_REG *) 0xFFFD4024) // (SSC1) Transmit Holding Register 1975 #define AT91C_SSC1_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC1) Transmit Frame Mode Register 1976 // ========== Register definition for PDC_SSC0 peripheral ========== 1977 #define AT91C_SSC0_PTCR ((AT91_REG *) 0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register 1978 #define AT91C_SSC0_TNPR ((AT91_REG *) 0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register 1979 #define AT91C_SSC0_RNPR ((AT91_REG *) 0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register 1980 #define AT91C_SSC0_TPR ((AT91_REG *) 0xFFFD0108) // (PDC_SSC0) Transmit Pointer Register 1981 #define AT91C_SSC0_RPR ((AT91_REG *) 0xFFFD0100) // (PDC_SSC0) Receive Pointer Register 1982 #define AT91C_SSC0_PTSR ((AT91_REG *) 0xFFFD0124) // (PDC_SSC0) PDC Transfer Status Register 1983 #define AT91C_SSC0_TNCR ((AT91_REG *) 0xFFFD011C) // (PDC_SSC0) Transmit Next Counter Register 1984 #define AT91C_SSC0_RNCR ((AT91_REG *) 0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register 1985 #define AT91C_SSC0_TCR ((AT91_REG *) 0xFFFD010C) // (PDC_SSC0) Transmit Counter Register 1986 #define AT91C_SSC0_RCR ((AT91_REG *) 0xFFFD0104) // (PDC_SSC0) Receive Counter Register 1987 // ========== Register definition for SSC0 peripheral ========== 1988 #define AT91C_SSC0_IMR ((AT91_REG *) 0xFFFD004C) // (SSC0) Interrupt Mask Register 1989 #define AT91C_SSC0_IER ((AT91_REG *) 0xFFFD0044) // (SSC0) Interrupt Enable Register 1990 #define AT91C_SSC0_RC1R ((AT91_REG *) 0xFFFD003C) // (SSC0) Receive Compare 1 Register 1991 #define AT91C_SSC0_TSHR ((AT91_REG *) 0xFFFD0034) // (SSC0) Transmit Sync Holding Register 1992 #define AT91C_SSC0_THR ((AT91_REG *) 0xFFFD0024) // (SSC0) Transmit Holding Register 1993 #define AT91C_SSC0_TFMR ((AT91_REG *) 0xFFFD001C) // (SSC0) Transmit Frame Mode Register 1994 #define AT91C_SSC0_RFMR ((AT91_REG *) 0xFFFD0014) // (SSC0) Receive Frame Mode Register 1995 #define AT91C_SSC0_CMR ((AT91_REG *) 0xFFFD0004) // (SSC0) Clock Mode Register 1996 #define AT91C_SSC0_IDR ((AT91_REG *) 0xFFFD0048) // (SSC0) Interrupt Disable Register 1997 #define AT91C_SSC0_SR ((AT91_REG *) 0xFFFD0040) // (SSC0) Status Register 1998 #define AT91C_SSC0_RC0R ((AT91_REG *) 0xFFFD0038) // (SSC0) Receive Compare 0 Register 1999 #define AT91C_SSC0_RSHR ((AT91_REG *) 0xFFFD0030) // (SSC0) Receive Sync Holding Register 2000 #define AT91C_SSC0_RHR ((AT91_REG *) 0xFFFD0020) // (SSC0) Receive Holding Register 2001 #define AT91C_SSC0_TCMR ((AT91_REG *) 0xFFFD0018) // (SSC0) Transmit Clock Mode Register 2002 #define AT91C_SSC0_RCMR ((AT91_REG *) 0xFFFD0010) // (SSC0) Receive Clock ModeRegister 2003 #define AT91C_SSC0_CR ((AT91_REG *) 0xFFFD0000) // (SSC0) Control Register 2004 // ========== Register definition for PDC_US3 peripheral ========== 2005 #define AT91C_US3_PTSR ((AT91_REG *) 0xFFFCC124) // (PDC_US3) PDC Transfer Status Register 2006 #define AT91C_US3_TNCR ((AT91_REG *) 0xFFFCC11C) // (PDC_US3) Transmit Next Counter Register 2007 #define AT91C_US3_RNCR ((AT91_REG *) 0xFFFCC114) // (PDC_US3) Receive Next Counter Register 2008 #define AT91C_US3_TCR ((AT91_REG *) 0xFFFCC10C) // (PDC_US3) Transmit Counter Register 2009 #define AT91C_US3_RCR ((AT91_REG *) 0xFFFCC104) // (PDC_US3) Receive Counter Register 2010 #define AT91C_US3_PTCR ((AT91_REG *) 0xFFFCC120) // (PDC_US3) PDC Transfer Control Register 2011 #define AT91C_US3_TNPR ((AT91_REG *) 0xFFFCC118) // (PDC_US3) Transmit Next Pointer Register 2012 #define AT91C_US3_RNPR ((AT91_REG *) 0xFFFCC110) // (PDC_US3) Receive Next Pointer Register 2013 #define AT91C_US3_TPR ((AT91_REG *) 0xFFFCC108) // (PDC_US3) Transmit Pointer Register 2014 #define AT91C_US3_RPR ((AT91_REG *) 0xFFFCC100) // (PDC_US3) Receive Pointer Register 2015 // ========== Register definition for US3 peripheral ========== 2016 #define AT91C_US3_IF ((AT91_REG *) 0xFFFCC04C) // (US3) IRDA_FILTER Register 2017 #define AT91C_US3_NER ((AT91_REG *) 0xFFFCC044) // (US3) Nb Errors Register 2018 #define AT91C_US3_RTOR ((AT91_REG *) 0xFFFCC024) // (US3) Receiver Time-out Register 2019 #define AT91C_US3_THR ((AT91_REG *) 0xFFFCC01C) // (US3) Transmitter Holding Register 2020 #define AT91C_US3_CSR ((AT91_REG *) 0xFFFCC014) // (US3) Channel Status Register 2021 #define AT91C_US3_IDR ((AT91_REG *) 0xFFFCC00C) // (US3) Interrupt Disable Register 2022 #define AT91C_US3_MR ((AT91_REG *) 0xFFFCC004) // (US3) Mode Register 2023 #define AT91C_US3_XXR ((AT91_REG *) 0xFFFCC048) // (US3) XON_XOFF Register 2024 #define AT91C_US3_FIDI ((AT91_REG *) 0xFFFCC040) // (US3) FI_DI_Ratio Register 2025 #define AT91C_US3_TTGR ((AT91_REG *) 0xFFFCC028) // (US3) Transmitter Time-guard Register 2026 #define AT91C_US3_BRGR ((AT91_REG *) 0xFFFCC020) // (US3) Baud Rate Generator Register 2027 #define AT91C_US3_RHR ((AT91_REG *) 0xFFFCC018) // (US3) Receiver Holding Register 2028 #define AT91C_US3_IMR ((AT91_REG *) 0xFFFCC010) // (US3) Interrupt Mask Register 2029 #define AT91C_US3_IER ((AT91_REG *) 0xFFFCC008) // (US3) Interrupt Enable Register 2030 #define AT91C_US3_CR ((AT91_REG *) 0xFFFCC000) // (US3) Control Register 2031 // ========== Register definition for PDC_US2 peripheral ========== 2032 #define AT91C_US2_PTSR ((AT91_REG *) 0xFFFC8124) // (PDC_US2) PDC Transfer Status Register 2033 #define AT91C_US2_TNCR ((AT91_REG *) 0xFFFC811C) // (PDC_US2) Transmit Next Counter Register 2034 #define AT91C_US2_RNCR ((AT91_REG *) 0xFFFC8114) // (PDC_US2) Receive Next Counter Register 2035 #define AT91C_US2_TCR ((AT91_REG *) 0xFFFC810C) // (PDC_US2) Transmit Counter Register 2036 #define AT91C_US2_PTCR ((AT91_REG *) 0xFFFC8120) // (PDC_US2) PDC Transfer Control Register 2037 #define AT91C_US2_RCR ((AT91_REG *) 0xFFFC8104) // (PDC_US2) Receive Counter Register 2038 #define AT91C_US2_TNPR ((AT91_REG *) 0xFFFC8118) // (PDC_US2) Transmit Next Pointer Register 2039 #define AT91C_US2_RPR ((AT91_REG *) 0xFFFC8100) // (PDC_US2) Receive Pointer Register 2040 #define AT91C_US2_TPR ((AT91_REG *) 0xFFFC8108) // (PDC_US2) Transmit Pointer Register 2041 #define AT91C_US2_RNPR ((AT91_REG *) 0xFFFC8110) // (PDC_US2) Receive Next Pointer Register 2042 // ========== Register definition for US2 peripheral ========== 2043 #define AT91C_US2_XXR ((AT91_REG *) 0xFFFC8048) // (US2) XON_XOFF Register 2044 #define AT91C_US2_FIDI ((AT91_REG *) 0xFFFC8040) // (US2) FI_DI_Ratio Register 2045 #define AT91C_US2_TTGR ((AT91_REG *) 0xFFFC8028) // (US2) Transmitter Time-guard Register 2046 #define AT91C_US2_BRGR ((AT91_REG *) 0xFFFC8020) // (US2) Baud Rate Generator Register 2047 #define AT91C_US2_RHR ((AT91_REG *) 0xFFFC8018) // (US2) Receiver Holding Register 2048 #define AT91C_US2_IMR ((AT91_REG *) 0xFFFC8010) // (US2) Interrupt Mask Register 2049 #define AT91C_US2_IER ((AT91_REG *) 0xFFFC8008) // (US2) Interrupt Enable Register 2050 #define AT91C_US2_CR ((AT91_REG *) 0xFFFC8000) // (US2) Control Register 2051 #define AT91C_US2_IF ((AT91_REG *) 0xFFFC804C) // (US2) IRDA_FILTER Register 2052 #define AT91C_US2_NER ((AT91_REG *) 0xFFFC8044) // (US2) Nb Errors Register 2053 #define AT91C_US2_RTOR ((AT91_REG *) 0xFFFC8024) // (US2) Receiver Time-out Register 2054 #define AT91C_US2_THR ((AT91_REG *) 0xFFFC801C) // (US2) Transmitter Holding Register 2055 #define AT91C_US2_CSR ((AT91_REG *) 0xFFFC8014) // (US2) Channel Status Register 2056 #define AT91C_US2_IDR ((AT91_REG *) 0xFFFC800C) // (US2) Interrupt Disable Register 2057 #define AT91C_US2_MR ((AT91_REG *) 0xFFFC8004) // (US2) Mode Register 2058 // ========== Register definition for PDC_US1 peripheral ========== 2059 #define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register 2060 #define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register 2061 #define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register 2062 #define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register 2063 #define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register 2064 #define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register 2065 #define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register 2066 #define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register 2067 #define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register 2068 #define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register 2069 // ========== Register definition for US1 peripheral ========== 2070 #define AT91C_US1_XXR ((AT91_REG *) 0xFFFC4048) // (US1) XON_XOFF Register 2071 #define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register 2072 #define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register 2073 #define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register 2074 #define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register 2075 #define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register 2076 #define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register 2077 #define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register 2078 #define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register 2079 #define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register 2080 #define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register 2081 #define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register 2082 #define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register 2083 #define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register 2084 #define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register 2085 // ========== Register definition for PDC_US0 peripheral ========== 2086 #define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register 2087 #define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register 2088 #define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register 2089 #define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register 2090 #define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register 2091 #define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register 2092 #define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register 2093 #define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register 2094 #define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register 2095 #define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register 2096 // ========== Register definition for US0 peripheral ========== 2097 #define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register 2098 #define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register 2099 #define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register 2100 #define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register 2101 #define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register 2102 #define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register 2103 #define AT91C_US0_XXR ((AT91_REG *) 0xFFFC0048) // (US0) XON_XOFF Register 2104 #define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register 2105 #define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register 2106 #define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register 2107 #define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register 2108 #define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register 2109 #define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register 2110 #define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register 2111 #define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register 2112 // ========== Register definition for TWI peripheral ========== 2113 #define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register 2114 #define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register 2115 #define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register 2116 #define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register 2117 #define AT91C_TWI_SMR ((AT91_REG *) 0xFFFB8008) // (TWI) Slave Mode Register 2118 #define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register 2119 #define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register 2120 #define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register 2121 #define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register 2122 #define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register 2123 #define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register 2124 // ========== Register definition for PDC_MCI peripheral ========== 2125 #define AT91C_MCI_PTCR ((AT91_REG *) 0xFFFB4120) // (PDC_MCI) PDC Transfer Control Register 2126 #define AT91C_MCI_TNPR ((AT91_REG *) 0xFFFB4118) // (PDC_MCI) Transmit Next Pointer Register 2127 #define AT91C_MCI_RNPR ((AT91_REG *) 0xFFFB4110) // (PDC_MCI) Receive Next Pointer Register 2128 #define AT91C_MCI_TPR ((AT91_REG *) 0xFFFB4108) // (PDC_MCI) Transmit Pointer Register 2129 #define AT91C_MCI_RPR ((AT91_REG *) 0xFFFB4100) // (PDC_MCI) Receive Pointer Register 2130 #define AT91C_MCI_PTSR ((AT91_REG *) 0xFFFB4124) // (PDC_MCI) PDC Transfer Status Register 2131 #define AT91C_MCI_TNCR ((AT91_REG *) 0xFFFB411C) // (PDC_MCI) Transmit Next Counter Register 2132 #define AT91C_MCI_RNCR ((AT91_REG *) 0xFFFB4114) // (PDC_MCI) Receive Next Counter Register 2133 #define AT91C_MCI_TCR ((AT91_REG *) 0xFFFB410C) // (PDC_MCI) Transmit Counter Register 2134 #define AT91C_MCI_RCR ((AT91_REG *) 0xFFFB4104) // (PDC_MCI) Receive Counter Register 2135 // ========== Register definition for MCI peripheral ========== 2136 #define AT91C_MCI_IDR ((AT91_REG *) 0xFFFB4048) // (MCI) MCI Interrupt Disable Register 2137 #define AT91C_MCI_SR ((AT91_REG *) 0xFFFB4040) // (MCI) MCI Status Register 2138 #define AT91C_MCI_RDR ((AT91_REG *) 0xFFFB4030) // (MCI) MCI Receive Data Register 2139 #define AT91C_MCI_RSPR ((AT91_REG *) 0xFFFB4020) // (MCI) MCI Response Register 2140 #define AT91C_MCI_ARGR ((AT91_REG *) 0xFFFB4010) // (MCI) MCI Argument Register 2141 #define AT91C_MCI_DTOR ((AT91_REG *) 0xFFFB4008) // (MCI) MCI Data Timeout Register 2142 #define AT91C_MCI_CR ((AT91_REG *) 0xFFFB4000) // (MCI) MCI Control Register 2143 #define AT91C_MCI_IMR ((AT91_REG *) 0xFFFB404C) // (MCI) MCI Interrupt Mask Register 2144 #define AT91C_MCI_IER ((AT91_REG *) 0xFFFB4044) // (MCI) MCI Interrupt Enable Register 2145 #define AT91C_MCI_TDR ((AT91_REG *) 0xFFFB4034) // (MCI) MCI Transmit Data Register 2146 #define AT91C_MCI_CMDR ((AT91_REG *) 0xFFFB4014) // (MCI) MCI Command Register 2147 #define AT91C_MCI_SDCR ((AT91_REG *) 0xFFFB400C) // (MCI) MCI SD Card Register 2148 #define AT91C_MCI_MR ((AT91_REG *) 0xFFFB4004) // (MCI) MCI Mode Register 2149 // ========== Register definition for UDP peripheral ========== 2150 #define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register 2151 #define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register 2152 #define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register 2153 #define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register 2154 #define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register 2155 #define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register 2156 #define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register 2157 #define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register 2158 #define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register 2159 #define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register 2160 #define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register 2161 // ========== Register definition for TC5 peripheral ========== 2162 #define AT91C_TC5_CMR ((AT91_REG *) 0xFFFA4084) // (TC5) Channel Mode Register 2163 #define AT91C_TC5_IDR ((AT91_REG *) 0xFFFA40A8) // (TC5) Interrupt Disable Register 2164 #define AT91C_TC5_SR ((AT91_REG *) 0xFFFA40A0) // (TC5) Status Register 2165 #define AT91C_TC5_RB ((AT91_REG *) 0xFFFA4098) // (TC5) Register B 2166 #define AT91C_TC5_CV ((AT91_REG *) 0xFFFA4090) // (TC5) Counter Value 2167 #define AT91C_TC5_CCR ((AT91_REG *) 0xFFFA4080) // (TC5) Channel Control Register 2168 #define AT91C_TC5_IMR ((AT91_REG *) 0xFFFA40AC) // (TC5) Interrupt Mask Register 2169 #define AT91C_TC5_IER ((AT91_REG *) 0xFFFA40A4) // (TC5) Interrupt Enable Register 2170 #define AT91C_TC5_RC ((AT91_REG *) 0xFFFA409C) // (TC5) Register C 2171 #define AT91C_TC5_RA ((AT91_REG *) 0xFFFA4094) // (TC5) Register A 2172 // ========== Register definition for TC4 peripheral ========== 2173 #define AT91C_TC4_IMR ((AT91_REG *) 0xFFFA406C) // (TC4) Interrupt Mask Register 2174 #define AT91C_TC4_IER ((AT91_REG *) 0xFFFA4064) // (TC4) Interrupt Enable Register 2175 #define AT91C_TC4_RC ((AT91_REG *) 0xFFFA405C) // (TC4) Register C 2176 #define AT91C_TC4_RA ((AT91_REG *) 0xFFFA4054) // (TC4) Register A 2177 #define AT91C_TC4_CMR ((AT91_REG *) 0xFFFA4044) // (TC4) Channel Mode Register 2178 #define AT91C_TC4_IDR ((AT91_REG *) 0xFFFA4068) // (TC4) Interrupt Disable Register 2179 #define AT91C_TC4_SR ((AT91_REG *) 0xFFFA4060) // (TC4) Status Register 2180 #define AT91C_TC4_RB ((AT91_REG *) 0xFFFA4058) // (TC4) Register B 2181 #define AT91C_TC4_CV ((AT91_REG *) 0xFFFA4050) // (TC4) Counter Value 2182 #define AT91C_TC4_CCR ((AT91_REG *) 0xFFFA4040) // (TC4) Channel Control Register 2183 // ========== Register definition for TC3 peripheral ========== 2184 #define AT91C_TC3_IMR ((AT91_REG *) 0xFFFA402C) // (TC3) Interrupt Mask Register 2185 #define AT91C_TC3_CV ((AT91_REG *) 0xFFFA4010) // (TC3) Counter Value 2186 #define AT91C_TC3_CCR ((AT91_REG *) 0xFFFA4000) // (TC3) Channel Control Register 2187 #define AT91C_TC3_IER ((AT91_REG *) 0xFFFA4024) // (TC3) Interrupt Enable Register 2188 #define AT91C_TC3_CMR ((AT91_REG *) 0xFFFA4004) // (TC3) Channel Mode Register 2189 #define AT91C_TC3_RA ((AT91_REG *) 0xFFFA4014) // (TC3) Register A 2190 #define AT91C_TC3_RC ((AT91_REG *) 0xFFFA401C) // (TC3) Register C 2191 #define AT91C_TC3_IDR ((AT91_REG *) 0xFFFA4028) // (TC3) Interrupt Disable Register 2192 #define AT91C_TC3_RB ((AT91_REG *) 0xFFFA4018) // (TC3) Register B 2193 #define AT91C_TC3_SR ((AT91_REG *) 0xFFFA4020) // (TC3) Status Register 2194 // ========== Register definition for TCB1 peripheral ========== 2195 #define AT91C_TCB1_BCR ((AT91_REG *) 0xFFFA4140) // (TCB1) TC Block Control Register 2196 #define AT91C_TCB1_BMR ((AT91_REG *) 0xFFFA4144) // (TCB1) TC Block Mode Register 2197 // ========== Register definition for TC2 peripheral ========== 2198 #define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register 2199 #define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register 2200 #define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C 2201 #define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A 2202 #define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register 2203 #define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register 2204 #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register 2205 #define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B 2206 #define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value 2207 #define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register 2208 // ========== Register definition for TC1 peripheral ========== 2209 #define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register 2210 #define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register 2211 #define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C 2212 #define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A 2213 #define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register 2214 #define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register 2215 #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register 2216 #define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B 2217 #define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value 2218 #define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register 2219 // ========== Register definition for TC0 peripheral ========== 2220 #define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register 2221 #define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register 2222 #define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C 2223 #define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A 2224 #define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register 2225 #define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register 2226 #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register 2227 #define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B 2228 #define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value 2229 #define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register 2230 // ========== Register definition for TCB0 peripheral ========== 2231 #define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register 2232 #define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register 2233 // ========== Register definition for UHP peripheral ========== 2234 #define AT91C_UHP_HcRhDescriptorA ((AT91_REG *) 0x00300048) // (UHP) Root Hub characteristics A 2235 #define AT91C_UHP_HcRhPortStatus ((AT91_REG *) 0x00300054) // (UHP) Root Hub Port Status Register 2236 #define AT91C_UHP_HcRhDescriptorB ((AT91_REG *) 0x0030004C) // (UHP) Root Hub characteristics B 2237 #define AT91C_UHP_HcControl ((AT91_REG *) 0x00300004) // (UHP) Operating modes for the Host Controller 2238 #define AT91C_UHP_HcInterruptStatus ((AT91_REG *) 0x0030000C) // (UHP) Interrupt Status Register 2239 #define AT91C_UHP_HcRhStatus ((AT91_REG *) 0x00300050) // (UHP) Root Hub Status register 2240 #define AT91C_UHP_HcRevision ((AT91_REG *) 0x00300000) // (UHP) Revision 2241 #define AT91C_UHP_HcCommandStatus ((AT91_REG *) 0x00300008) // (UHP) Command & status Register 2242 #define AT91C_UHP_HcInterruptEnable ((AT91_REG *) 0x00300010) // (UHP) Interrupt Enable Register 2243 #define AT91C_UHP_HcHCCA ((AT91_REG *) 0x00300018) // (UHP) Pointer to the Host Controller Communication Area 2244 #define AT91C_UHP_HcControlHeadED ((AT91_REG *) 0x00300020) // (UHP) First Endpoint Descriptor of the Control list 2245 #define AT91C_UHP_HcInterruptDisable ((AT91_REG *) 0x00300014) // (UHP) Interrupt Disable Register 2246 #define AT91C_UHP_HcPeriodCurrentED ((AT91_REG *) 0x0030001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor 2247 #define AT91C_UHP_HcControlCurrentED ((AT91_REG *) 0x00300024) // (UHP) Endpoint Control and Status Register 2248 #define AT91C_UHP_HcBulkCurrentED ((AT91_REG *) 0x0030002C) // (UHP) Current endpoint of the Bulk list 2249 #define AT91C_UHP_HcFmInterval ((AT91_REG *) 0x00300034) // (UHP) Bit time between 2 consecutive SOFs 2250 #define AT91C_UHP_HcBulkHeadED ((AT91_REG *) 0x00300028) // (UHP) First endpoint register of the Bulk list 2251 #define AT91C_UHP_HcBulkDoneHead ((AT91_REG *) 0x00300030) // (UHP) Last completed transfer descriptor 2252 #define AT91C_UHP_HcFmRemaining ((AT91_REG *) 0x00300038) // (UHP) Bit time remaining in the current Frame 2253 #define AT91C_UHP_HcPeriodicStart ((AT91_REG *) 0x00300040) // (UHP) Periodic Start 2254 #define AT91C_UHP_HcLSThreshold ((AT91_REG *) 0x00300044) // (UHP) LS Threshold 2255 #define AT91C_UHP_HcFmNumber ((AT91_REG *) 0x0030003C) // (UHP) Frame number 2256 // ========== Register definition for EMAC peripheral ========== 2257 #define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFBC020) // (EMAC) Receive Status Register 2258 #define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFBC034) // (EMAC) PHY Maintenance Register 2259 #define AT91C_EMAC_HSH ((AT91_REG *) 0xFFFBC090) // (EMAC) Hash Address High[63:32] 2260 #define AT91C_EMAC_MCOL ((AT91_REG *) 0xFFFBC048) // (EMAC) Multiple Collision Frame Register 2261 #define AT91C_EMAC_IER ((AT91_REG *) 0xFFFBC028) // (EMAC) Interrupt Enable Register 2262 #define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFBC0A4) // (EMAC) Specific Address 2 High, Last 2 bytes 2263 #define AT91C_EMAC_HSL ((AT91_REG *) 0xFFFBC094) // (EMAC) Hash Address Low[31:0] 2264 #define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFBC05C) // (EMAC) Late Collision Register 2265 #define AT91C_EMAC_OK ((AT91_REG *) 0xFFFBC04C) // (EMAC) Frames Received OK Register 2266 #define AT91C_EMAC_CFG ((AT91_REG *) 0xFFFBC004) // (EMAC) Network Configuration Register 2267 #define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFBC0A8) // (EMAC) Specific Address 3 Low, First 4 bytes 2268 #define AT91C_EMAC_SEQE ((AT91_REG *) 0xFFFBC050) // (EMAC) Frame Check Sequence Error Register 2269 #define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFBC060) // (EMAC) Excessive Collision Register 2270 #define AT91C_EMAC_ELR ((AT91_REG *) 0xFFFBC070) // (EMAC) Excessive Length Error Register 2271 #define AT91C_EMAC_SR ((AT91_REG *) 0xFFFBC008) // (EMAC) Network Status Register 2272 #define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFBC018) // (EMAC) Receive Buffer Queue Pointer 2273 #define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFBC064) // (EMAC) Carrier Sense Error Register 2274 #define AT91C_EMAC_RJB ((AT91_REG *) 0xFFFBC074) // (EMAC) Receive Jabber Register 2275 #define AT91C_EMAC_USF ((AT91_REG *) 0xFFFBC078) // (EMAC) Undersize Frame Register 2276 #define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFBC02C) // (EMAC) Interrupt Disable Register 2277 #define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFBC098) // (EMAC) Specific Address 1 Low, First 4 bytes 2278 #define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFBC030) // (EMAC) Interrupt Mask Register 2279 #define AT91C_EMAC_FRA ((AT91_REG *) 0xFFFBC040) // (EMAC) Frames Transmitted OK Register 2280 #define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFBC0AC) // (EMAC) Specific Address 3 High, Last 2 bytes 2281 #define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFBC09C) // (EMAC) Specific Address 1 High, Last 2 bytes 2282 #define AT91C_EMAC_SCOL ((AT91_REG *) 0xFFFBC044) // (EMAC) Single Collision Frame Register 2283 #define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFBC054) // (EMAC) Alignment Error Register 2284 #define AT91C_EMAC_TAR ((AT91_REG *) 0xFFFBC00C) // (EMAC) Transmit Address Register 2285 #define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFBC0B0) // (EMAC) Specific Address 4 Low, First 4 bytes 2286 #define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFBC0A0) // (EMAC) Specific Address 2 Low, First 4 bytes 2287 #define AT91C_EMAC_TUE ((AT91_REG *) 0xFFFBC068) // (EMAC) Transmit Underrun Error Register 2288 #define AT91C_EMAC_DTE ((AT91_REG *) 0xFFFBC058) // (EMAC) Deferred Transmission Frame Register 2289 #define AT91C_EMAC_TCR ((AT91_REG *) 0xFFFBC010) // (EMAC) Transmit Control Register 2290 #define AT91C_EMAC_CTL ((AT91_REG *) 0xFFFBC000) // (EMAC) Network Control Register 2291 #define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFBC0B4) // (EMAC) Specific Address 4 High, Last 2 bytesr 2292 #define AT91C_EMAC_CDE ((AT91_REG *) 0xFFFBC06C) // (EMAC) Code Error Register 2293 #define AT91C_EMAC_SQEE ((AT91_REG *) 0xFFFBC07C) // (EMAC) SQE Test Error Register 2294 #define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFBC014) // (EMAC) Transmit Status Register 2295 #define AT91C_EMAC_DRFC ((AT91_REG *) 0xFFFBC080) // (EMAC) Discarded RX Frame Register 2296 // ========== Register definition for EBI peripheral ========== 2297 #define AT91C_EBI_CFGR ((AT91_REG *) 0xFFFFFF64) // (EBI) Configuration Register 2298 #define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) // (EBI) Chip Select Assignment Register 2299 // ========== Register definition for SMC2 peripheral ========== 2300 #define AT91C_SMC2_CSR ((AT91_REG *) 0xFFFFFF70) // (SMC2) SMC2 Chip Select Register 2301 // ========== Register definition for SDRC peripheral ========== 2302 #define AT91C_SDRC_IMR ((AT91_REG *) 0xFFFFFFAC) // (SDRC) SDRAM Controller Interrupt Mask Register 2303 #define AT91C_SDRC_IER ((AT91_REG *) 0xFFFFFFA4) // (SDRC) SDRAM Controller Interrupt Enable Register 2304 #define AT91C_SDRC_SRR ((AT91_REG *) 0xFFFFFF9C) // (SDRC) SDRAM Controller Self Refresh Register 2305 #define AT91C_SDRC_TR ((AT91_REG *) 0xFFFFFF94) // (SDRC) SDRAM Controller Refresh Timer Register 2306 #define AT91C_SDRC_ISR ((AT91_REG *) 0xFFFFFFB0) // (SDRC) SDRAM Controller Interrupt Mask Register 2307 #define AT91C_SDRC_IDR ((AT91_REG *) 0xFFFFFFA8) // (SDRC) SDRAM Controller Interrupt Disable Register 2308 #define AT91C_SDRC_LPR ((AT91_REG *) 0xFFFFFFA0) // (SDRC) SDRAM Controller Low Power Register 2309 #define AT91C_SDRC_CR ((AT91_REG *) 0xFFFFFF98) // (SDRC) SDRAM Controller Configuration Register 2310 #define AT91C_SDRC_MR ((AT91_REG *) 0xFFFFFF90) // (SDRC) SDRAM Controller Mode Register 2311 // ========== Register definition for BFC peripheral ========== 2312 #define AT91C_BFC_MR ((AT91_REG *) 0xFFFFFFC0) // (BFC) BFC Mode Register 2313 2314 #include <at91/at91_pioreg.h> 2315 2316 // ***************************************************************************** 2317 // PERIPHERAL ID DEFINITIONS FOR AT91RM9200 2318 // ***************************************************************************** 2319 #define AT91C_ID_FIQ 0u // Advanced Interrupt Controller (FIQ) 2320 #define AT91C_ID_SYS 1u // System Peripheral 2321 #define AT91C_ID_PIOA 2u // Parallel IO Controller A 2322 #define AT91C_ID_PIOB 3u // Parallel IO Controller B 2323 #define AT91C_ID_PIOC 4u // Parallel IO Controller C 2324 #define AT91C_ID_PIOD 5u // Parallel IO Controller D 2325 #define AT91C_ID_US0 6u // USART 0 2326 #define AT91C_ID_US1 7u // USART 1 2327 #define AT91C_ID_US2 8u // USART 2 2328 #define AT91C_ID_US3 9u // USART 3 2329 #define AT91C_ID_MCI 10u // Multimedia Card Interface 2330 #define AT91C_ID_UDP 11u // USB Device Port 2331 #define AT91C_ID_TWI 12u // Two-Wire Interface 2332 #define AT91C_ID_SPI 13u // Serial Peripheral Interface 2333 #define AT91C_ID_SSC0 14u // Serial Synchronous Controller 0 2334 #define AT91C_ID_SSC1 15u // Serial Synchronous Controller 1 2335 #define AT91C_ID_SSC2 16u // Serial Synchronous Controller 2 2336 #define AT91C_ID_TC0 17u // Timer Counter 0 2337 #define AT91C_ID_TC1 18u // Timer Counter 1 2338 #define AT91C_ID_TC2 19u // Timer Counter 2 2339 #define AT91C_ID_TC3 20u // Timer Counter 3 2340 #define AT91C_ID_TC4 21u // Timer Counter 4 2341 #define AT91C_ID_TC5 22u // Timer Counter 5 2342 #define AT91C_ID_UHP 23u // USB Host port 2343 #define AT91C_ID_EMAC 24u // Ethernet MAC 2344 #define AT91C_ID_IRQ0 25u // Advanced Interrupt Controller (IRQ0) 2345 #define AT91C_ID_IRQ1 26u // Advanced Interrupt Controller (IRQ1) 2346 #define AT91C_ID_IRQ2 27u // Advanced Interrupt Controller (IRQ2) 2347 #define AT91C_ID_IRQ3 28u // Advanced Interrupt Controller (IRQ3) 2348 #define AT91C_ID_IRQ4 29u // Advanced Interrupt Controller (IRQ4) 2349 #define AT91C_ID_IRQ5 30u // Advanced Interrupt Controller (IRQ5) 2350 #define AT91C_ID_IRQ6 31u // Advanced Interrupt Controller (IRQ6) 2351 2352 // ***************************************************************************** 2353 // BASE ADDRESS DEFINITIONS FOR AT91RM9200 2354 // ***************************************************************************** 2355 #define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address 2356 #define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address 2357 #define AT91C_BASE_RTC ((AT91PS_RTC) 0xFFFFFE00) // (RTC) Base Address 2358 #define AT91C_BASE_ST ((AT91PS_ST) 0xFFFFFD00) // (ST) Base Address 2359 #define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address 2360 #define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address 2361 #define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFFA00) // (PIOD) Base Address 2362 #define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) // (PIOC) Base Address 2363 #define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address 2364 #define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address 2365 #define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address 2366 #define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address 2367 #define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address 2368 #define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address 2369 #define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address 2370 #define AT91C_BASE_PDC_SSC2 ((AT91PS_PDC) 0xFFFD8100) // (PDC_SSC2) Base Address 2371 #define AT91C_BASE_SSC2 ((AT91PS_SSC) 0xFFFD8000) // (SSC2) Base Address 2372 #define AT91C_BASE_PDC_SSC1 ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC1) Base Address 2373 #define AT91C_BASE_SSC1 ((AT91PS_SSC) 0xFFFD4000) // (SSC1) Base Address 2374 #define AT91C_BASE_PDC_SSC0 ((AT91PS_PDC) 0xFFFD0100) // (PDC_SSC0) Base Address 2375 #define AT91C_BASE_SSC0 ((AT91PS_SSC) 0xFFFD0000) // (SSC0) Base Address 2376 #define AT91C_BASE_PDC_US3 ((AT91PS_PDC) 0xFFFCC100) // (PDC_US3) Base Address 2377 #define AT91C_BASE_US3 ((AT91PS_USART) 0xFFFCC000) // (US3) Base Address 2378 #define AT91C_BASE_PDC_US2 ((AT91PS_PDC) 0xFFFC8100) // (PDC_US2) Base Address 2379 #define AT91C_BASE_US2 ((AT91PS_USART) 0xFFFC8000) // (US2) Base Address 2380 #define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address 2381 #define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address 2382 #define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address 2383 #define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address 2384 #define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address 2385 #define AT91C_BASE_PDC_MCI ((AT91PS_PDC) 0xFFFB4100) // (PDC_MCI) Base Address 2386 #define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFB4000) // (MCI) Base Address 2387 #define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address 2388 #define AT91C_BASE_TC5 ((AT91PS_TC) 0xFFFA4080) // (TC5) Base Address 2389 #define AT91C_BASE_TC4 ((AT91PS_TC) 0xFFFA4040) // (TC4) Base Address 2390 #define AT91C_BASE_TC3 ((AT91PS_TC) 0xFFFA4000) // (TC3) Base Address 2391 #define AT91C_BASE_TCB1 ((AT91PS_TCB) 0xFFFA4080) // (TCB1) Base Address 2392 #define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address 2393 #define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address 2394 #define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address 2395 #define AT91C_BASE_TCB0 ((AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address 2396 #define AT91C_BASE_UHP ((AT91PS_UHP) 0x00300000) // (UHP) Base Address 2397 #define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) // (EMAC) Base Address 2398 #define AT91C_BASE_EBI ((AT91PS_EBI) 0xFFFFFF60) // (EBI) Base Address 2399 #define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) // (SMC2) Base Address 2400 #define AT91C_BASE_SDRC ((AT91PS_SDRC) 0xFFFFFF90) // (SDRC) Base Address 2401 #define AT91C_BASE_BFC ((AT91PS_BFC) 0xFFFFFFC0) // (BFC) Base Address 2402 2403 // ***************************************************************************** 2404 // MEMORY MAPPING DEFINITIONS FOR AT91RM9200 2405 // ***************************************************************************** 2406 #define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address 2407 #define AT91C_ISRAM_SIZE 0x00004000u // Internal SRAM size in byte (16 Kbyte) 2408 #define AT91C_IROM ((char *) 0x00100000) // Internal ROM base address 2409 #define AT91C_IROM_SIZE 0x00020000u // Internal ROM size in byte (128 Kbyte) 2410 2411 #endif 2412