xref: /freebsd/sys/arm64/apple/exynos_uart.h (revision ba2336d3044c681462224c12879ecc8f659be54a)
1 /* $NetBSD: s3c2xx0reg.h,v 1.4 2004/02/12 03:47:29 bsh Exp $ */
2 
3 /*-
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  * Copyright (c) 2002, 2003 Fujitsu Component Limited
7  * Copyright (c) 2002, 2003 Genetec Corporation
8  * All rights reserved.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. Neither the name of The Fujitsu Component Limited nor the name of
19  *    Genetec corporation may not be used to endorse or promote products
20  *    derived from this software without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
23  * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
24  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26  * DISCLAIMED.  IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
27  * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
29  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
30  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
33  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34  * SUCH DAMAGE.
35  */
36 
37 /* s3c2410-specific registers */
38 #define	UMCON_AFC		(1 << 4)	/* auto flow control */
39 #define	UMSTAT_DCTS		(1 << 2)	/* CTS change */
40 #define	ULCON_IR		(1 << 6)
41 #define	ULCON_PARITY_SHIFT	3
42 
43 /*
44  * Exynos-specific
45  *
46  * UFSTAT_TXFULL register differs between Exynos and others.
47  * Others have UFSTAT_TXFULL  (1 << 9)
48  */
49 #define	UFSTAT_TXFULL		(1 << 24)
50 #define	UFSTAT_S5L_TXFULL	(1 << 9)
51 
52 #define	SSCOM_UINTM		0x038
53 #define	 UINTM_TXINTR		(1 << 2)
54 #define	SSCOM_UINTP		0x030
55 #define	 UINTP_RXREADY		(1 << 0)
56 #define	 UINTP_TXEMPTY		(1 << 2)
57 
58 /* common for s3c2800 and s3c24x0 */
59 #define	SSCOM_ULCON		0x00		/* UART line control */
60 #define	 ULCON_PARITY_NONE	(0 << ULCON_PARITY_SHIFT)
61 #define	 ULCON_PARITY_ODD	(4 << ULCON_PARITY_SHIFT)
62 #define	 ULCON_PARITY_EVEN	(5 << ULCON_PARITY_SHIFT)
63 #define	 ULCON_PARITY_ONE	(6 << ULCON_PARITY_SHIFT)
64 #define	 ULCON_PARITY_ZERO	(7 << ULCON_PARITY_SHIFT)
65 #define	 ULCON_STOP		(1 << 2)
66 #define	 ULCON_LENGTH_5		0
67 #define	 ULCON_LENGTH_6		1
68 #define	 ULCON_LENGTH_7		2
69 #define	 ULCON_LENGTH_8		3
70 #define	SSCOM_UCON		0x04		/* UART control */
71 #define	 UCON_TXINT_TYPE	(1 << 9)	/* Tx interrupt. 0=pulse,1=level */
72 #define	 UCON_TXINT_TYPE_LEVEL	UCON_TXINT_TYPE
73 #define	 UCON_TXINT_TYPE_PULSE	0
74 #define	 UCON_RXINT_TYPE	(1 << 8)	/* Rx interrupt */
75 #define	 UCON_RXINT_TYPE_LEVEL	UCON_RXINT_TYPE
76 #define	 UCON_RXINT_TYPE_PULSE	0
77 #define	 UCON_TOINT		(1 << 7)	/* Rx timeout interrupt */
78 #define	 UCON_ERRINT		(1 << 6)	/* receive error interrupt */
79 #define	 UCON_LOOP		(1 << 5)	/* loopback */
80 #define	 UCON_SBREAK		(1 << 4)	/* send break */
81 #define	 UCON_TXMODE_DISABLE	(0 << 2)
82 #define	 UCON_TXMODE_INT	(1 << 2)
83 #define	 UCON_TXMODE_DMA	(2 << 2)
84 #define	 UCON_TXMODE_MASK	(3 << 2)
85 #define	 UCON_RXMODE_DISABLE	(0 << 0)
86 #define	 UCON_RXMODE_INT	(1 << 0)
87 #define	 UCON_RXMODE_DMA	(2 << 0)
88 #define	 UCON_RXMODE_MASK	(3 << 0)
89 #define  UCON_S5L_RX_TIMEOUT	(0x1 << 9)
90 #define  UCON_S5L_RXTHRESH	(0x1 << 12)
91 #define  UCON_S5L_TXTHRESH	(0x1 << 13)
92 #define	SSCOM_UFCON		0x08		/* FIFO control */
93 #define	 UFCON_TXTRIGGER_0	(0 << 6)
94 #define	 UFCON_TXTRIGGER_4	(1 << 6)
95 #define	 UFCON_TXTRIGGER_8	(2 << 6)
96 #define	 UFCON_TXTRIGGER_16	(3 << 6)
97 #define	 UFCON_RXTRIGGER_4	(0 << 4)
98 #define	 UFCON_RXTRIGGER_8	(1 << 4)
99 #define	 UFCON_RXTRIGGER_12	(2 << 4)
100 #define	 UFCON_RXTRIGGER_16	(3 << 4)
101 #define	 UFCON_TXFIFO_RESET	(1 << 2)
102 #define	 UFCON_RXFIFO_RESET	(1 << 1)
103 #define	 UFCON_FIFO_ENABLE	(1 << 0)
104 #define	SSCOM_UMCON		0x0c		/* MODEM control */
105 #define	 UMCON_RTS		(1 << 0)	/* Request to send */
106 #define	SSCOM_UTRSTAT		0x10		/* Status register */
107 #define	 UTRSTAT_TXSHIFTER_EMPTY	( 1<< 2)
108 #define	 UTRSTAT_TXEMPTY	(1 << 1)	/* TX fifo or buffer empty */
109 #define	 UTRSTAT_RXREADY	(1 << 0)	/* RX fifo or buffer is not empty */
110 #define	 UTRSTAT_S5L_RXTHRESH		(0x1 << 4)
111 #define	 UTRSTAT_S5L_TXTHRESH		(0x1 << 5)
112 #define	 UTRSTAT_S5L_RX_TIMEOUT		(0x1 << 9)
113 #define	SSCOM_UERSTAT		0x14		/* Error status register */
114 #define	 UERSTAT_BREAK		(1 << 3)	/* Break signal, not 2410 */
115 #define	 UERSTAT_FRAME		(1 << 2)	/* Frame error */
116 #define	 UERSTAT_PARITY		(1 << 1)	/* Parity error, not 2410 */
117 #define	 UERSTAT_OVERRUN	(1 << 0)	/* Overrun */
118 #define	 UERSTAT_ALL_ERRORS \
119 	(UERSTAT_OVERRUN|UERSTAT_BREAK|UERSTAT_FRAME|UERSTAT_PARITY)
120 #define	SSCOM_UFSTAT		0x18		/* Fifo status register */
121 #define	 UFSTAT_RXFULL		(1 <<8)		/* Rx fifo full */
122 #define	 UFSTAT_TXCOUNT_SHIFT	4		/* TX FIFO count */
123 #define	 UFSTAT_TXCOUNT		(0x0f << UFSTAT_TXCOUNT_SHIFT)
124 #define	 UFSTAT_RXCOUNT_SHIFT	0		/* RX FIFO count */
125 #define	 UFSTAT_RXCOUNT		(0x0f << UFSTAT_RXCOUNT_SHIFT)
126 #define	SSCOM_UMSTAT		0x1c		/* Modem status register */
127 #define	 UMSTAT_CTS		(1 << 0)	/* Clear to send */
128 #if _BYTE_ORDER == _LITTLE_ENDIAN
129 #define	SSCOM_UTXH		0x20		/* Transmit data register */
130 #define	SSCOM_URXH		0x24		/* Receive data register */
131 #else
132 #define	SSCOM_UTXH		0x23		/* Transmit data register */
133 #define	SSCOM_URXH		0x27		/* Receive data register */
134 #endif
135 #define	SSCOM_UBRDIV		0x28		/* baud-reate divisor */
136 #define	SSCOM_SIZE		0x2c
137