1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DC_SPL_TYPES_H__ 6 #define __DC_SPL_TYPES_H__ 7 8 #include "spl_os_types.h" // swap 9 #ifndef SPL_ASSERT 10 #define SPL_ASSERT(_bool) ((void *)0) 11 #endif 12 #include "spl_fixpt31_32.h" // fixed31_32 and related functions 13 #include "spl_custom_float.h" // custom float and related functions 14 15 struct spl_size { 16 uint32_t width; 17 uint32_t height; 18 }; 19 struct spl_rect { 20 int x; 21 int y; 22 int width; 23 int height; 24 }; 25 26 struct spl_ratios { 27 struct spl_fixed31_32 horz; 28 struct spl_fixed31_32 vert; 29 struct spl_fixed31_32 horz_c; 30 struct spl_fixed31_32 vert_c; 31 }; 32 struct spl_inits { 33 struct spl_fixed31_32 h; 34 struct spl_fixed31_32 h_c; 35 struct spl_fixed31_32 v; 36 struct spl_fixed31_32 v_c; 37 }; 38 39 struct spl_taps { 40 uint32_t v_taps; 41 uint32_t h_taps; 42 uint32_t v_taps_c; 43 uint32_t h_taps_c; 44 bool integer_scaling; 45 }; 46 enum spl_view_3d { 47 SPL_VIEW_3D_NONE = 0, 48 SPL_VIEW_3D_FRAME_SEQUENTIAL, 49 SPL_VIEW_3D_SIDE_BY_SIDE, 50 SPL_VIEW_3D_TOP_AND_BOTTOM, 51 SPL_VIEW_3D_COUNT, 52 SPL_VIEW_3D_FIRST = SPL_VIEW_3D_FRAME_SEQUENTIAL 53 }; 54 /* Pixel format */ 55 enum spl_pixel_format { 56 /*graph*/ 57 SPL_PIXEL_FORMAT_UNINITIALIZED, 58 SPL_PIXEL_FORMAT_INDEX8, 59 SPL_PIXEL_FORMAT_RGB565, 60 SPL_PIXEL_FORMAT_ARGB8888, 61 SPL_PIXEL_FORMAT_ARGB2101010, 62 SPL_PIXEL_FORMAT_ARGB2101010_XRBIAS, 63 SPL_PIXEL_FORMAT_FP16, 64 /*video*/ 65 SPL_PIXEL_FORMAT_420BPP8, 66 SPL_PIXEL_FORMAT_420BPP10, 67 /*end of pixel format definition*/ 68 SPL_PIXEL_FORMAT_INVALID, 69 SPL_PIXEL_FORMAT_422BPP8, 70 SPL_PIXEL_FORMAT_422BPP10, 71 SPL_PIXEL_FORMAT_GRPH_BEGIN = SPL_PIXEL_FORMAT_INDEX8, 72 SPL_PIXEL_FORMAT_GRPH_END = SPL_PIXEL_FORMAT_FP16, 73 SPL_PIXEL_FORMAT_VIDEO_BEGIN = SPL_PIXEL_FORMAT_420BPP8, 74 SPL_PIXEL_FORMAT_VIDEO_END = SPL_PIXEL_FORMAT_420BPP10, 75 SPL_PIXEL_FORMAT_UNKNOWN 76 }; 77 78 enum lb_memory_config { 79 /* Enable all 3 pieces of memory */ 80 LB_MEMORY_CONFIG_0 = 0, 81 82 /* Enable only the first piece of memory */ 83 LB_MEMORY_CONFIG_1 = 1, 84 85 /* Enable only the second piece of memory */ 86 LB_MEMORY_CONFIG_2 = 2, 87 88 /* Only applicable in 4:2:0 mode, enable all 3 pieces of memory and the 89 * last piece of chroma memory used for the luma storage 90 */ 91 LB_MEMORY_CONFIG_3 = 3 92 }; 93 94 /* Rotation angle */ 95 enum spl_rotation_angle { 96 SPL_ROTATION_ANGLE_0 = 0, 97 SPL_ROTATION_ANGLE_90, 98 SPL_ROTATION_ANGLE_180, 99 SPL_ROTATION_ANGLE_270, 100 SPL_ROTATION_ANGLE_COUNT 101 }; 102 enum spl_color_space { 103 SPL_COLOR_SPACE_UNKNOWN, 104 SPL_COLOR_SPACE_SRGB, 105 SPL_COLOR_SPACE_XR_RGB, 106 SPL_COLOR_SPACE_SRGB_LIMITED, 107 SPL_COLOR_SPACE_MSREF_SCRGB, 108 SPL_COLOR_SPACE_YCBCR601, 109 SPL_COLOR_SPACE_YCBCR709, 110 SPL_COLOR_SPACE_XV_YCC_709, 111 SPL_COLOR_SPACE_XV_YCC_601, 112 SPL_COLOR_SPACE_YCBCR601_LIMITED, 113 SPL_COLOR_SPACE_YCBCR709_LIMITED, 114 SPL_COLOR_SPACE_2020_RGB_FULLRANGE, 115 SPL_COLOR_SPACE_2020_RGB_LIMITEDRANGE, 116 SPL_COLOR_SPACE_2020_YCBCR, 117 SPL_COLOR_SPACE_ADOBERGB, 118 SPL_COLOR_SPACE_DCIP3, 119 SPL_COLOR_SPACE_DISPLAYNATIVE, 120 SPL_COLOR_SPACE_DOLBYVISION, 121 SPL_COLOR_SPACE_APPCTRL, 122 SPL_COLOR_SPACE_CUSTOMPOINTS, 123 SPL_COLOR_SPACE_YCBCR709_BLACK, 124 }; 125 126 enum chroma_cositing { 127 CHROMA_COSITING_NONE, 128 CHROMA_COSITING_LEFT, 129 CHROMA_COSITING_TOPLEFT, 130 CHROMA_COSITING_COUNT 131 }; 132 133 // Scratch space for calculating scaler params 134 struct spl_scaler_data { 135 int h_active; 136 int v_active; 137 struct spl_taps taps; 138 struct spl_rect viewport; 139 struct spl_rect viewport_c; 140 struct spl_rect recout; 141 struct spl_ratios ratios; 142 struct spl_ratios recip_ratios; 143 struct spl_inits inits; 144 }; 145 146 enum spl_transfer_func_type { 147 SPL_TF_TYPE_PREDEFINED, 148 SPL_TF_TYPE_DISTRIBUTED_POINTS, 149 SPL_TF_TYPE_BYPASS, 150 SPL_TF_TYPE_HWPWL 151 }; 152 153 enum spl_transfer_func_predefined { 154 SPL_TRANSFER_FUNCTION_SRGB, 155 SPL_TRANSFER_FUNCTION_BT709, 156 SPL_TRANSFER_FUNCTION_PQ, 157 SPL_TRANSFER_FUNCTION_LINEAR, 158 SPL_TRANSFER_FUNCTION_UNITY, 159 SPL_TRANSFER_FUNCTION_HLG, 160 SPL_TRANSFER_FUNCTION_HLG12, 161 SPL_TRANSFER_FUNCTION_GAMMA22, 162 SPL_TRANSFER_FUNCTION_GAMMA24, 163 SPL_TRANSFER_FUNCTION_GAMMA26 164 }; 165 166 /*==============================================================*/ 167 /* Below structs are defined to hold hw register data */ 168 169 // SPL output is used to set below registers 170 171 // MPC_SIZE - set based on scl_data h_active and v_active 172 struct mpc_size { 173 uint32_t width; 174 uint32_t height; 175 }; 176 // SCL_MODE - set based on scl_data.ratios and always_scale 177 enum scl_mode { 178 SCL_MODE_SCALING_444_BYPASS = 0, 179 SCL_MODE_SCALING_444_RGB_ENABLE = 1, 180 SCL_MODE_SCALING_444_YCBCR_ENABLE = 2, 181 SCL_MODE_SCALING_420_YCBCR_ENABLE = 3, 182 SCL_MODE_SCALING_420_LUMA_BYPASS = 4, 183 SCL_MODE_SCALING_420_CHROMA_BYPASS = 5, 184 SCL_MODE_DSCL_BYPASS = 6 185 }; 186 // SCL_BLACK_COLOR - set based on scl_data.format 187 struct scl_black_color { 188 uint32_t offset_rgb_y; 189 uint32_t offset_rgb_cbcr; 190 }; 191 // RATIO - set based on scl_data.ratios 192 struct ratio { 193 uint32_t h_scale_ratio; 194 uint32_t v_scale_ratio; 195 uint32_t h_scale_ratio_c; 196 uint32_t v_scale_ratio_c; 197 }; 198 199 // INIT - set based on scl_data.init 200 struct init { 201 // SCL_HORZ_FILTER_INIT 202 uint32_t h_filter_init_frac; // SCL_H_INIT_FRAC 203 uint32_t h_filter_init_int; // SCL_H_INIT_INT 204 // SCL_HORZ_FILTER_INIT_C 205 uint32_t h_filter_init_frac_c; // SCL_H_INIT_FRAC_C 206 uint32_t h_filter_init_int_c; // SCL_H_INIT_INT_C 207 // SCL_VERT_FILTER_INIT 208 uint32_t v_filter_init_frac; // SCL_V_INIT_FRAC 209 uint32_t v_filter_init_int; // SCL_V_INIT_INT 210 // SCL_VERT_FILTER_INIT_C 211 uint32_t v_filter_init_frac_c; // SCL_V_INIT_FRAC_C 212 uint32_t v_filter_init_int_c; // SCL_V_INIT_INT_C 213 // SCL_VERT_FILTER_INIT_BOT 214 uint32_t v_filter_init_bot_frac; // SCL_V_INIT_FRAC_BOT 215 uint32_t v_filter_init_bot_int; // SCL_V_INIT_INT_BOT 216 // SCL_VERT_FILTER_INIT_BOT_C 217 uint32_t v_filter_init_bot_frac_c; // SCL_V_INIT_FRAC_BOT_C 218 uint32_t v_filter_init_bot_int_c; // SCL_V_INIT_INT_BOT_C 219 }; 220 221 // FILTER - calculated based on scl_data ratios and taps 222 223 // iSHARP 224 struct isharp_noise_det { 225 uint32_t enable; // ISHARP_NOISEDET_EN 226 uint32_t mode; // ISHARP_NOISEDET_MODE 227 uint32_t uthreshold; // ISHARP_NOISEDET_UTHRE 228 uint32_t dthreshold; // ISHARP_NOISEDET_DTHRE 229 uint32_t pwl_start_in; // ISHARP_NOISEDET_PWL_START_IN 230 uint32_t pwl_end_in; // ISHARP_NOISEDET_PWL_END_IN 231 uint32_t pwl_slope; // ISHARP_NOISEDET_PWL_SLOPE 232 }; 233 struct isharp_lba { 234 uint32_t mode; // ISHARP_LBA_MODE 235 uint32_t in_seg[6]; 236 uint32_t base_seg[6]; 237 uint32_t slope_seg[6]; 238 }; 239 struct isharp_fmt { 240 uint32_t mode; // ISHARP_FMT_MODE 241 uint32_t norm; // ISHARP_FMT_NORM 242 }; 243 struct isharp_nldelta_sclip { 244 uint32_t enable_p; // ISHARP_NLDELTA_SCLIP_EN_P 245 uint32_t pivot_p; // ISHARP_NLDELTA_SCLIP_PIVOT_P 246 uint32_t slope_p; // ISHARP_NLDELTA_SCLIP_SLOPE_P 247 uint32_t enable_n; // ISHARP_NLDELTA_SCLIP_EN_N 248 uint32_t pivot_n; // ISHARP_NLDELTA_SCLIP_PIVOT_N 249 uint32_t slope_n; // ISHARP_NLDELTA_SCLIP_SLOPE_N 250 }; 251 enum isharp_en { 252 ISHARP_DISABLE, 253 ISHARP_ENABLE 254 }; 255 // Below struct holds values that can be directly used to program 256 // hardware registers. No conversion/clamping is required 257 struct dscl_prog_data { 258 struct spl_rect recout; // RECOUT - set based on scl_data.recout 259 struct mpc_size mpc_size; 260 uint32_t dscl_mode; 261 struct scl_black_color scl_black_color; 262 struct ratio ratios; 263 struct init init; 264 struct spl_taps taps; // TAPS - set based on scl_data.taps 265 struct spl_rect viewport; 266 struct spl_rect viewport_c; 267 // raw filter 268 const uint16_t *filter_h; 269 const uint16_t *filter_v; 270 const uint16_t *filter_h_c; 271 const uint16_t *filter_v_c; 272 // EASF registers 273 uint32_t easf_matrix_mode; 274 uint32_t easf_ltonl_en; 275 uint32_t easf_v_en; 276 uint32_t easf_v_sharp_factor; 277 uint32_t easf_v_ring; 278 uint32_t easf_v_bf1_en; 279 uint32_t easf_v_bf2_mode; 280 uint32_t easf_v_bf3_mode; 281 uint32_t easf_v_bf2_flat1_gain; 282 uint32_t easf_v_bf2_flat2_gain; 283 uint32_t easf_v_bf2_roc_gain; 284 uint32_t easf_v_ringest_3tap_dntilt_uptilt; 285 uint32_t easf_v_ringest_3tap_uptilt_max; 286 uint32_t easf_v_ringest_3tap_dntilt_slope; 287 uint32_t easf_v_ringest_3tap_uptilt1_slope; 288 uint32_t easf_v_ringest_3tap_uptilt2_slope; 289 uint32_t easf_v_ringest_3tap_uptilt2_offset; 290 uint32_t easf_v_ringest_eventap_reduceg1; 291 uint32_t easf_v_ringest_eventap_reduceg2; 292 uint32_t easf_v_ringest_eventap_gain1; 293 uint32_t easf_v_ringest_eventap_gain2; 294 uint32_t easf_v_bf_maxa; 295 uint32_t easf_v_bf_maxb; 296 uint32_t easf_v_bf_mina; 297 uint32_t easf_v_bf_minb; 298 uint32_t easf_v_bf1_pwl_in_seg0; 299 uint32_t easf_v_bf1_pwl_base_seg0; 300 uint32_t easf_v_bf1_pwl_slope_seg0; 301 uint32_t easf_v_bf1_pwl_in_seg1; 302 uint32_t easf_v_bf1_pwl_base_seg1; 303 uint32_t easf_v_bf1_pwl_slope_seg1; 304 uint32_t easf_v_bf1_pwl_in_seg2; 305 uint32_t easf_v_bf1_pwl_base_seg2; 306 uint32_t easf_v_bf1_pwl_slope_seg2; 307 uint32_t easf_v_bf1_pwl_in_seg3; 308 uint32_t easf_v_bf1_pwl_base_seg3; 309 uint32_t easf_v_bf1_pwl_slope_seg3; 310 uint32_t easf_v_bf1_pwl_in_seg4; 311 uint32_t easf_v_bf1_pwl_base_seg4; 312 uint32_t easf_v_bf1_pwl_slope_seg4; 313 uint32_t easf_v_bf1_pwl_in_seg5; 314 uint32_t easf_v_bf1_pwl_base_seg5; 315 uint32_t easf_v_bf1_pwl_slope_seg5; 316 uint32_t easf_v_bf1_pwl_in_seg6; 317 uint32_t easf_v_bf1_pwl_base_seg6; 318 uint32_t easf_v_bf1_pwl_slope_seg6; 319 uint32_t easf_v_bf1_pwl_in_seg7; 320 uint32_t easf_v_bf1_pwl_base_seg7; 321 uint32_t easf_v_bf3_pwl_in_set0; 322 uint32_t easf_v_bf3_pwl_base_set0; 323 uint32_t easf_v_bf3_pwl_slope_set0; 324 uint32_t easf_v_bf3_pwl_in_set1; 325 uint32_t easf_v_bf3_pwl_base_set1; 326 uint32_t easf_v_bf3_pwl_slope_set1; 327 uint32_t easf_v_bf3_pwl_in_set2; 328 uint32_t easf_v_bf3_pwl_base_set2; 329 uint32_t easf_v_bf3_pwl_slope_set2; 330 uint32_t easf_v_bf3_pwl_in_set3; 331 uint32_t easf_v_bf3_pwl_base_set3; 332 uint32_t easf_v_bf3_pwl_slope_set3; 333 uint32_t easf_v_bf3_pwl_in_set4; 334 uint32_t easf_v_bf3_pwl_base_set4; 335 uint32_t easf_v_bf3_pwl_slope_set4; 336 uint32_t easf_v_bf3_pwl_in_set5; 337 uint32_t easf_v_bf3_pwl_base_set5; 338 uint32_t easf_h_en; 339 uint32_t easf_h_sharp_factor; 340 uint32_t easf_h_ring; 341 uint32_t easf_h_bf1_en; 342 uint32_t easf_h_bf2_mode; 343 uint32_t easf_h_bf3_mode; 344 uint32_t easf_h_bf2_flat1_gain; 345 uint32_t easf_h_bf2_flat2_gain; 346 uint32_t easf_h_bf2_roc_gain; 347 uint32_t easf_h_ringest_eventap_reduceg1; 348 uint32_t easf_h_ringest_eventap_reduceg2; 349 uint32_t easf_h_ringest_eventap_gain1; 350 uint32_t easf_h_ringest_eventap_gain2; 351 uint32_t easf_h_bf_maxa; 352 uint32_t easf_h_bf_maxb; 353 uint32_t easf_h_bf_mina; 354 uint32_t easf_h_bf_minb; 355 uint32_t easf_h_bf1_pwl_in_seg0; 356 uint32_t easf_h_bf1_pwl_base_seg0; 357 uint32_t easf_h_bf1_pwl_slope_seg0; 358 uint32_t easf_h_bf1_pwl_in_seg1; 359 uint32_t easf_h_bf1_pwl_base_seg1; 360 uint32_t easf_h_bf1_pwl_slope_seg1; 361 uint32_t easf_h_bf1_pwl_in_seg2; 362 uint32_t easf_h_bf1_pwl_base_seg2; 363 uint32_t easf_h_bf1_pwl_slope_seg2; 364 uint32_t easf_h_bf1_pwl_in_seg3; 365 uint32_t easf_h_bf1_pwl_base_seg3; 366 uint32_t easf_h_bf1_pwl_slope_seg3; 367 uint32_t easf_h_bf1_pwl_in_seg4; 368 uint32_t easf_h_bf1_pwl_base_seg4; 369 uint32_t easf_h_bf1_pwl_slope_seg4; 370 uint32_t easf_h_bf1_pwl_in_seg5; 371 uint32_t easf_h_bf1_pwl_base_seg5; 372 uint32_t easf_h_bf1_pwl_slope_seg5; 373 uint32_t easf_h_bf1_pwl_in_seg6; 374 uint32_t easf_h_bf1_pwl_base_seg6; 375 uint32_t easf_h_bf1_pwl_slope_seg6; 376 uint32_t easf_h_bf1_pwl_in_seg7; 377 uint32_t easf_h_bf1_pwl_base_seg7; 378 uint32_t easf_h_bf3_pwl_in_set0; 379 uint32_t easf_h_bf3_pwl_base_set0; 380 uint32_t easf_h_bf3_pwl_slope_set0; 381 uint32_t easf_h_bf3_pwl_in_set1; 382 uint32_t easf_h_bf3_pwl_base_set1; 383 uint32_t easf_h_bf3_pwl_slope_set1; 384 uint32_t easf_h_bf3_pwl_in_set2; 385 uint32_t easf_h_bf3_pwl_base_set2; 386 uint32_t easf_h_bf3_pwl_slope_set2; 387 uint32_t easf_h_bf3_pwl_in_set3; 388 uint32_t easf_h_bf3_pwl_base_set3; 389 uint32_t easf_h_bf3_pwl_slope_set3; 390 uint32_t easf_h_bf3_pwl_in_set4; 391 uint32_t easf_h_bf3_pwl_base_set4; 392 uint32_t easf_h_bf3_pwl_slope_set4; 393 uint32_t easf_h_bf3_pwl_in_set5; 394 uint32_t easf_h_bf3_pwl_base_set5; 395 uint32_t easf_matrix_c0; 396 uint32_t easf_matrix_c1; 397 uint32_t easf_matrix_c2; 398 uint32_t easf_matrix_c3; 399 // iSharp 400 uint32_t isharp_en; // ISHARP_EN 401 struct isharp_noise_det isharp_noise_det; // ISHARP_NOISEDET 402 uint32_t isharp_nl_en; // ISHARP_NL_EN ? TODO:check this 403 struct isharp_lba isharp_lba; // ISHARP_LBA 404 struct isharp_fmt isharp_fmt; // ISHARP_FMT 405 const uint32_t *isharp_delta; 406 struct isharp_nldelta_sclip isharp_nldelta_sclip; // ISHARP_NLDELTA_SCLIP 407 /* blur and scale filter */ 408 const uint16_t *filter_blur_scale_v; 409 const uint16_t *filter_blur_scale_h; 410 int sharpness_level; /* Track sharpness level */ 411 }; 412 413 /* SPL input and output definitions */ 414 // SPL scratch struct 415 struct spl_scratch { 416 // Pack all SPL outputs in scl_data 417 struct spl_scaler_data scl_data; 418 }; 419 420 /* SPL input and output definitions */ 421 // SPL outputs struct 422 struct spl_out { 423 // Pack all output need to program hw registers 424 struct dscl_prog_data *dscl_prog_data; 425 }; 426 427 // end of SPL outputs 428 429 // SPL inputs 430 431 // Basic input information 432 struct basic_in { 433 enum spl_pixel_format format; // Pixel Format 434 enum chroma_cositing cositing; /* Chroma Subsampling Offset */ 435 struct spl_rect src_rect; // Source rect 436 struct spl_rect dst_rect; // Destination Rect 437 struct spl_rect clip_rect; // Clip rect 438 enum spl_rotation_angle rotation; // Rotation 439 bool horizontal_mirror; // Horizontal mirror 440 int mpc_combine_h; // MPC Horizontal Combine Factor (split_count) 441 int mpc_combine_v; // MPC Vertical Combine Factor (split_idx) 442 // Inputs for adaptive scaler - TODO 443 enum spl_transfer_func_type tf_type; /* Transfer function type */ 444 enum spl_transfer_func_predefined tf_predefined_type; /* Transfer function predefined type */ 445 // enum dc_transfer_func_predefined tf; 446 enum spl_color_space color_space; // Color Space 447 unsigned int max_luminance; // Max Luminance TODO: Is determined in dc_hw_sequencer.c is_sdr 448 bool film_grain_applied; // Film Grain Applied // TODO: To check from where to get this? 449 }; 450 451 // Basic output information 452 struct basic_out { 453 struct spl_size output_size; // Output Size 454 struct spl_rect dst_rect; // Destination Rect 455 struct spl_rect src_rect; // Source rect 456 int odm_combine_factor; // deprecated 457 struct spl_rect odm_slice_rect; // OPP input rect in timing active 458 enum spl_view_3d view_format; // TODO: View format Check if it is chroma subsampling 459 bool always_scale; // Is always scale enabled? Required for getting SCL_MODE 460 int max_downscale_src_width; // Required to get optimal no of taps 461 bool alpha_en; 462 bool use_two_pixels_per_container; 463 }; 464 enum sharpness_setting { 465 SHARPNESS_HW_OFF = 0, 466 SHARPNESS_ZERO, 467 SHARPNESS_CUSTOM 468 }; 469 struct spl_sharpness_range { 470 int sdr_rgb_min; 471 int sdr_rgb_max; 472 int sdr_rgb_mid; 473 int sdr_yuv_min; 474 int sdr_yuv_max; 475 int sdr_yuv_mid; 476 int hdr_rgb_min; 477 int hdr_rgb_max; 478 int hdr_rgb_mid; 479 }; 480 struct adaptive_sharpness { 481 bool enable; 482 int sharpness_level; 483 struct spl_sharpness_range sharpness_range; 484 }; 485 enum linear_light_scaling { // convert it in translation logic 486 LLS_PREF_DONT_CARE = 0, 487 LLS_PREF_YES, 488 LLS_PREF_NO 489 }; 490 struct spl_funcs { 491 void (*spl_calc_lb_num_partitions) 492 (bool alpha_en, 493 const struct spl_scaler_data *scl_data, 494 enum lb_memory_config lb_config, 495 int *num_part_y, 496 int *num_part_c); 497 }; 498 499 struct spl_debug { 500 int visual_confirm_base_offset; 501 int visual_confirm_dpp_offset; 502 }; 503 504 struct spl_in { 505 struct basic_out basic_out; 506 struct basic_in basic_in; 507 // Basic slice information 508 int odm_slice_index; // ODM Slice Index using get_odm_split_index 509 struct spl_taps scaling_quality; // Explicit Scaling Quality 510 struct spl_funcs *funcs; 511 // Inputs for isharp and EASF 512 struct adaptive_sharpness adaptive_sharpness; // Adaptive Sharpness 513 enum linear_light_scaling lls_pref; // Linear Light Scaling 514 bool prefer_easf; 515 bool disable_easf; 516 struct spl_debug debug; 517 bool is_fullscreen; 518 bool is_hdr_on; 519 int h_active; 520 int v_active; 521 int hdr_multx100; 522 }; 523 // end of SPL inputs 524 525 #endif /* __DC_SPL_TYPES_H__ */ 526