xref: /linux/drivers/spi/spi-tegra114.c (revision 06d07429858317ded2db7986113a9e0129cd599b)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * SPI driver for NVIDIA's Tegra114 SPI Controller.
4  *
5  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/dmaengine.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmapool.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18 #include <linux/kthread.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/of.h>
23 #include <linux/reset.h>
24 #include <linux/spi/spi.h>
25 
26 #define SPI_COMMAND1				0x000
27 #define SPI_BIT_LENGTH(x)			(((x) & 0x1f) << 0)
28 #define SPI_PACKED				(1 << 5)
29 #define SPI_TX_EN				(1 << 11)
30 #define SPI_RX_EN				(1 << 12)
31 #define SPI_BOTH_EN_BYTE			(1 << 13)
32 #define SPI_BOTH_EN_BIT				(1 << 14)
33 #define SPI_LSBYTE_FE				(1 << 15)
34 #define SPI_LSBIT_FE				(1 << 16)
35 #define SPI_BIDIROE				(1 << 17)
36 #define SPI_IDLE_SDA_DRIVE_LOW			(0 << 18)
37 #define SPI_IDLE_SDA_DRIVE_HIGH			(1 << 18)
38 #define SPI_IDLE_SDA_PULL_LOW			(2 << 18)
39 #define SPI_IDLE_SDA_PULL_HIGH			(3 << 18)
40 #define SPI_IDLE_SDA_MASK			(3 << 18)
41 #define SPI_CS_SW_VAL				(1 << 20)
42 #define SPI_CS_SW_HW				(1 << 21)
43 /* SPI_CS_POL_INACTIVE bits are default high */
44 						/* n from 0 to 3 */
45 #define SPI_CS_POL_INACTIVE(n)			(1 << (22 + (n)))
46 #define SPI_CS_POL_INACTIVE_MASK		(0xF << 22)
47 
48 #define SPI_CS_SEL_0				(0 << 26)
49 #define SPI_CS_SEL_1				(1 << 26)
50 #define SPI_CS_SEL_2				(2 << 26)
51 #define SPI_CS_SEL_3				(3 << 26)
52 #define SPI_CS_SEL_MASK				(3 << 26)
53 #define SPI_CS_SEL(x)				(((x) & 0x3) << 26)
54 #define SPI_CONTROL_MODE_0			(0 << 28)
55 #define SPI_CONTROL_MODE_1			(1 << 28)
56 #define SPI_CONTROL_MODE_2			(2 << 28)
57 #define SPI_CONTROL_MODE_3			(3 << 28)
58 #define SPI_CONTROL_MODE_MASK			(3 << 28)
59 #define SPI_MODE_SEL(x)				(((x) & 0x3) << 28)
60 #define SPI_M_S					(1 << 30)
61 #define SPI_PIO					(1 << 31)
62 
63 #define SPI_COMMAND2				0x004
64 #define SPI_TX_TAP_DELAY(x)			(((x) & 0x3F) << 6)
65 #define SPI_RX_TAP_DELAY(x)			(((x) & 0x3F) << 0)
66 
67 #define SPI_CS_TIMING1				0x008
68 #define SPI_SETUP_HOLD(setup, hold)		(((setup) << 4) | (hold))
69 #define SPI_CS_SETUP_HOLD(reg, cs, val)			\
70 		((((val) & 0xFFu) << ((cs) * 8)) |	\
71 		((reg) & ~(0xFFu << ((cs) * 8))))
72 
73 #define SPI_CS_TIMING2				0x00C
74 #define CYCLES_BETWEEN_PACKETS_0(x)		(((x) & 0x1F) << 0)
75 #define CS_ACTIVE_BETWEEN_PACKETS_0		(1 << 5)
76 #define CYCLES_BETWEEN_PACKETS_1(x)		(((x) & 0x1F) << 8)
77 #define CS_ACTIVE_BETWEEN_PACKETS_1		(1 << 13)
78 #define CYCLES_BETWEEN_PACKETS_2(x)		(((x) & 0x1F) << 16)
79 #define CS_ACTIVE_BETWEEN_PACKETS_2		(1 << 21)
80 #define CYCLES_BETWEEN_PACKETS_3(x)		(((x) & 0x1F) << 24)
81 #define CS_ACTIVE_BETWEEN_PACKETS_3		(1 << 29)
82 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val)		\
83 		(reg = (((val) & 0x1) << ((cs) * 8 + 5)) |	\
84 			((reg) & ~(1 << ((cs) * 8 + 5))))
85 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val)		\
86 		(reg = (((val) & 0x1F) << ((cs) * 8)) |		\
87 			((reg) & ~(0x1F << ((cs) * 8))))
88 #define MAX_SETUP_HOLD_CYCLES			16
89 #define MAX_INACTIVE_CYCLES			32
90 
91 #define SPI_TRANS_STATUS			0x010
92 #define SPI_BLK_CNT(val)			(((val) >> 0) & 0xFFFF)
93 #define SPI_SLV_IDLE_COUNT(val)			(((val) >> 16) & 0xFF)
94 #define SPI_RDY					(1 << 30)
95 
96 #define SPI_FIFO_STATUS				0x014
97 #define SPI_RX_FIFO_EMPTY			(1 << 0)
98 #define SPI_RX_FIFO_FULL			(1 << 1)
99 #define SPI_TX_FIFO_EMPTY			(1 << 2)
100 #define SPI_TX_FIFO_FULL			(1 << 3)
101 #define SPI_RX_FIFO_UNF				(1 << 4)
102 #define SPI_RX_FIFO_OVF				(1 << 5)
103 #define SPI_TX_FIFO_UNF				(1 << 6)
104 #define SPI_TX_FIFO_OVF				(1 << 7)
105 #define SPI_ERR					(1 << 8)
106 #define SPI_TX_FIFO_FLUSH			(1 << 14)
107 #define SPI_RX_FIFO_FLUSH			(1 << 15)
108 #define SPI_TX_FIFO_EMPTY_COUNT(val)		(((val) >> 16) & 0x7F)
109 #define SPI_RX_FIFO_FULL_COUNT(val)		(((val) >> 23) & 0x7F)
110 #define SPI_FRAME_END				(1 << 30)
111 #define SPI_CS_INACTIVE				(1 << 31)
112 
113 #define SPI_FIFO_ERROR				(SPI_RX_FIFO_UNF | \
114 			SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF)
115 #define SPI_FIFO_EMPTY			(SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY)
116 
117 #define SPI_TX_DATA				0x018
118 #define SPI_RX_DATA				0x01C
119 
120 #define SPI_DMA_CTL				0x020
121 #define SPI_TX_TRIG_1				(0 << 15)
122 #define SPI_TX_TRIG_4				(1 << 15)
123 #define SPI_TX_TRIG_8				(2 << 15)
124 #define SPI_TX_TRIG_16				(3 << 15)
125 #define SPI_TX_TRIG_MASK			(3 << 15)
126 #define SPI_RX_TRIG_1				(0 << 19)
127 #define SPI_RX_TRIG_4				(1 << 19)
128 #define SPI_RX_TRIG_8				(2 << 19)
129 #define SPI_RX_TRIG_16				(3 << 19)
130 #define SPI_RX_TRIG_MASK			(3 << 19)
131 #define SPI_IE_TX				(1 << 28)
132 #define SPI_IE_RX				(1 << 29)
133 #define SPI_CONT				(1 << 30)
134 #define SPI_DMA					(1 << 31)
135 #define SPI_DMA_EN				SPI_DMA
136 
137 #define SPI_DMA_BLK				0x024
138 #define SPI_DMA_BLK_SET(x)			(((x) & 0xFFFF) << 0)
139 
140 #define SPI_TX_FIFO				0x108
141 #define SPI_RX_FIFO				0x188
142 #define SPI_INTR_MASK				0x18c
143 #define SPI_INTR_ALL_MASK			(0x1fUL << 25)
144 #define MAX_CHIP_SELECT				4
145 #define SPI_FIFO_DEPTH				64
146 #define DATA_DIR_TX				(1 << 0)
147 #define DATA_DIR_RX				(1 << 1)
148 
149 #define SPI_DMA_TIMEOUT				(msecs_to_jiffies(1000))
150 #define DEFAULT_SPI_DMA_BUF_LEN			(16*1024)
151 #define TX_FIFO_EMPTY_COUNT_MAX			SPI_TX_FIFO_EMPTY_COUNT(0x40)
152 #define RX_FIFO_FULL_COUNT_ZERO			SPI_RX_FIFO_FULL_COUNT(0)
153 #define MAX_HOLD_CYCLES				16
154 #define SPI_DEFAULT_SPEED			25000000
155 
156 struct tegra_spi_soc_data {
157 	bool has_intr_mask_reg;
158 };
159 
160 struct tegra_spi_client_data {
161 	int tx_clk_tap_delay;
162 	int rx_clk_tap_delay;
163 };
164 
165 struct tegra_spi_data {
166 	struct device				*dev;
167 	struct spi_controller			*host;
168 	spinlock_t				lock;
169 
170 	struct clk				*clk;
171 	struct reset_control			*rst;
172 	void __iomem				*base;
173 	phys_addr_t				phys;
174 	unsigned				irq;
175 	u32					cur_speed;
176 
177 	struct spi_device			*cur_spi;
178 	struct spi_device			*cs_control;
179 	unsigned				cur_pos;
180 	unsigned				words_per_32bit;
181 	unsigned				bytes_per_word;
182 	unsigned				curr_dma_words;
183 	unsigned				cur_direction;
184 
185 	unsigned				cur_rx_pos;
186 	unsigned				cur_tx_pos;
187 
188 	unsigned				dma_buf_size;
189 	unsigned				max_buf_size;
190 	bool					is_curr_dma_xfer;
191 	bool					use_hw_based_cs;
192 
193 	struct completion			rx_dma_complete;
194 	struct completion			tx_dma_complete;
195 
196 	u32					tx_status;
197 	u32					rx_status;
198 	u32					status_reg;
199 	bool					is_packed;
200 
201 	u32					command1_reg;
202 	u32					dma_control_reg;
203 	u32					def_command1_reg;
204 	u32					def_command2_reg;
205 	u32					spi_cs_timing1;
206 	u32					spi_cs_timing2;
207 	u8					last_used_cs;
208 
209 	struct completion			xfer_completion;
210 	struct spi_transfer			*curr_xfer;
211 	struct dma_chan				*rx_dma_chan;
212 	u32					*rx_dma_buf;
213 	dma_addr_t				rx_dma_phys;
214 	struct dma_async_tx_descriptor		*rx_dma_desc;
215 
216 	struct dma_chan				*tx_dma_chan;
217 	u32					*tx_dma_buf;
218 	dma_addr_t				tx_dma_phys;
219 	struct dma_async_tx_descriptor		*tx_dma_desc;
220 	const struct tegra_spi_soc_data		*soc_data;
221 };
222 
223 static int tegra_spi_runtime_suspend(struct device *dev);
224 static int tegra_spi_runtime_resume(struct device *dev);
225 
tegra_spi_readl(struct tegra_spi_data * tspi,unsigned long reg)226 static inline u32 tegra_spi_readl(struct tegra_spi_data *tspi,
227 		unsigned long reg)
228 {
229 	return readl(tspi->base + reg);
230 }
231 
tegra_spi_writel(struct tegra_spi_data * tspi,u32 val,unsigned long reg)232 static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
233 		u32 val, unsigned long reg)
234 {
235 	writel(val, tspi->base + reg);
236 
237 	/* Read back register to make sure that register writes completed */
238 	if (reg != SPI_TX_FIFO)
239 		readl(tspi->base + SPI_COMMAND1);
240 }
241 
tegra_spi_clear_status(struct tegra_spi_data * tspi)242 static void tegra_spi_clear_status(struct tegra_spi_data *tspi)
243 {
244 	u32 val;
245 
246 	/* Write 1 to clear status register */
247 	val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
248 	tegra_spi_writel(tspi, val, SPI_TRANS_STATUS);
249 
250 	/* Clear fifo status error if any */
251 	val = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
252 	if (val & SPI_ERR)
253 		tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR,
254 				SPI_FIFO_STATUS);
255 }
256 
tegra_spi_calculate_curr_xfer_param(struct spi_device * spi,struct tegra_spi_data * tspi,struct spi_transfer * t)257 static unsigned tegra_spi_calculate_curr_xfer_param(
258 	struct spi_device *spi, struct tegra_spi_data *tspi,
259 	struct spi_transfer *t)
260 {
261 	unsigned remain_len = t->len - tspi->cur_pos;
262 	unsigned max_word;
263 	unsigned bits_per_word = t->bits_per_word;
264 	unsigned max_len;
265 	unsigned total_fifo_words;
266 
267 	tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
268 
269 	if ((bits_per_word == 8 || bits_per_word == 16 ||
270 	     bits_per_word == 32) && t->len > 3) {
271 		tspi->is_packed = true;
272 		tspi->words_per_32bit = 32/bits_per_word;
273 	} else {
274 		tspi->is_packed = false;
275 		tspi->words_per_32bit = 1;
276 	}
277 
278 	if (tspi->is_packed) {
279 		max_len = min(remain_len, tspi->max_buf_size);
280 		tspi->curr_dma_words = max_len/tspi->bytes_per_word;
281 		total_fifo_words = (max_len + 3) / 4;
282 	} else {
283 		max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
284 		max_word = min(max_word, tspi->max_buf_size/4);
285 		tspi->curr_dma_words = max_word;
286 		total_fifo_words = max_word;
287 	}
288 	return total_fifo_words;
289 }
290 
tegra_spi_fill_tx_fifo_from_client_txbuf(struct tegra_spi_data * tspi,struct spi_transfer * t)291 static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
292 	struct tegra_spi_data *tspi, struct spi_transfer *t)
293 {
294 	unsigned nbytes;
295 	unsigned tx_empty_count;
296 	u32 fifo_status;
297 	unsigned max_n_32bit;
298 	unsigned i, count;
299 	unsigned int written_words;
300 	unsigned fifo_words_left;
301 	u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
302 
303 	fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
304 	tx_empty_count = SPI_TX_FIFO_EMPTY_COUNT(fifo_status);
305 
306 	if (tspi->is_packed) {
307 		fifo_words_left = tx_empty_count * tspi->words_per_32bit;
308 		written_words = min(fifo_words_left, tspi->curr_dma_words);
309 		nbytes = written_words * tspi->bytes_per_word;
310 		max_n_32bit = DIV_ROUND_UP(nbytes, 4);
311 		for (count = 0; count < max_n_32bit; count++) {
312 			u32 x = 0;
313 
314 			for (i = 0; (i < 4) && nbytes; i++, nbytes--)
315 				x |= (u32)(*tx_buf++) << (i * 8);
316 			tegra_spi_writel(tspi, x, SPI_TX_FIFO);
317 		}
318 
319 		tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
320 	} else {
321 		unsigned int write_bytes;
322 		max_n_32bit = min(tspi->curr_dma_words,  tx_empty_count);
323 		written_words = max_n_32bit;
324 		nbytes = written_words * tspi->bytes_per_word;
325 		if (nbytes > t->len - tspi->cur_pos)
326 			nbytes = t->len - tspi->cur_pos;
327 		write_bytes = nbytes;
328 		for (count = 0; count < max_n_32bit; count++) {
329 			u32 x = 0;
330 
331 			for (i = 0; nbytes && (i < tspi->bytes_per_word);
332 							i++, nbytes--)
333 				x |= (u32)(*tx_buf++) << (i * 8);
334 			tegra_spi_writel(tspi, x, SPI_TX_FIFO);
335 		}
336 
337 		tspi->cur_tx_pos += write_bytes;
338 	}
339 
340 	return written_words;
341 }
342 
tegra_spi_read_rx_fifo_to_client_rxbuf(struct tegra_spi_data * tspi,struct spi_transfer * t)343 static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
344 		struct tegra_spi_data *tspi, struct spi_transfer *t)
345 {
346 	unsigned rx_full_count;
347 	u32 fifo_status;
348 	unsigned i, count;
349 	unsigned int read_words = 0;
350 	unsigned len;
351 	u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
352 
353 	fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
354 	rx_full_count = SPI_RX_FIFO_FULL_COUNT(fifo_status);
355 	if (tspi->is_packed) {
356 		len = tspi->curr_dma_words * tspi->bytes_per_word;
357 		for (count = 0; count < rx_full_count; count++) {
358 			u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO);
359 
360 			for (i = 0; len && (i < 4); i++, len--)
361 				*rx_buf++ = (x >> i*8) & 0xFF;
362 		}
363 		read_words += tspi->curr_dma_words;
364 		tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
365 	} else {
366 		u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
367 		u8 bytes_per_word = tspi->bytes_per_word;
368 		unsigned int read_bytes;
369 
370 		len = rx_full_count * bytes_per_word;
371 		if (len > t->len - tspi->cur_pos)
372 			len = t->len - tspi->cur_pos;
373 		read_bytes = len;
374 		for (count = 0; count < rx_full_count; count++) {
375 			u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask;
376 
377 			for (i = 0; len && (i < bytes_per_word); i++, len--)
378 				*rx_buf++ = (x >> (i*8)) & 0xFF;
379 		}
380 		read_words += rx_full_count;
381 		tspi->cur_rx_pos += read_bytes;
382 	}
383 
384 	return read_words;
385 }
386 
tegra_spi_copy_client_txbuf_to_spi_txbuf(struct tegra_spi_data * tspi,struct spi_transfer * t)387 static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
388 		struct tegra_spi_data *tspi, struct spi_transfer *t)
389 {
390 	/* Make the dma buffer to read by cpu */
391 	dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
392 				tspi->dma_buf_size, DMA_TO_DEVICE);
393 
394 	if (tspi->is_packed) {
395 		unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
396 
397 		memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
398 		tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
399 	} else {
400 		unsigned int i;
401 		unsigned int count;
402 		u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
403 		unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
404 		unsigned int write_bytes;
405 
406 		if (consume > t->len - tspi->cur_pos)
407 			consume = t->len - tspi->cur_pos;
408 		write_bytes = consume;
409 		for (count = 0; count < tspi->curr_dma_words; count++) {
410 			u32 x = 0;
411 
412 			for (i = 0; consume && (i < tspi->bytes_per_word);
413 							i++, consume--)
414 				x |= (u32)(*tx_buf++) << (i * 8);
415 			tspi->tx_dma_buf[count] = x;
416 		}
417 
418 		tspi->cur_tx_pos += write_bytes;
419 	}
420 
421 	/* Make the dma buffer to read by dma */
422 	dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
423 				tspi->dma_buf_size, DMA_TO_DEVICE);
424 }
425 
tegra_spi_copy_spi_rxbuf_to_client_rxbuf(struct tegra_spi_data * tspi,struct spi_transfer * t)426 static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
427 		struct tegra_spi_data *tspi, struct spi_transfer *t)
428 {
429 	/* Make the dma buffer to read by cpu */
430 	dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
431 		tspi->dma_buf_size, DMA_FROM_DEVICE);
432 
433 	if (tspi->is_packed) {
434 		unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
435 
436 		memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
437 		tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
438 	} else {
439 		unsigned int i;
440 		unsigned int count;
441 		unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
442 		u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
443 		unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
444 		unsigned int read_bytes;
445 
446 		if (consume > t->len - tspi->cur_pos)
447 			consume = t->len - tspi->cur_pos;
448 		read_bytes = consume;
449 		for (count = 0; count < tspi->curr_dma_words; count++) {
450 			u32 x = tspi->rx_dma_buf[count] & rx_mask;
451 
452 			for (i = 0; consume && (i < tspi->bytes_per_word);
453 							i++, consume--)
454 				*rx_buf++ = (x >> (i*8)) & 0xFF;
455 		}
456 
457 		tspi->cur_rx_pos += read_bytes;
458 	}
459 
460 	/* Make the dma buffer to read by dma */
461 	dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
462 		tspi->dma_buf_size, DMA_FROM_DEVICE);
463 }
464 
tegra_spi_dma_complete(void * args)465 static void tegra_spi_dma_complete(void *args)
466 {
467 	struct completion *dma_complete = args;
468 
469 	complete(dma_complete);
470 }
471 
tegra_spi_start_tx_dma(struct tegra_spi_data * tspi,int len)472 static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len)
473 {
474 	reinit_completion(&tspi->tx_dma_complete);
475 	tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
476 				tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
477 				DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
478 	if (!tspi->tx_dma_desc) {
479 		dev_err(tspi->dev, "Not able to get desc for Tx\n");
480 		return -EIO;
481 	}
482 
483 	tspi->tx_dma_desc->callback = tegra_spi_dma_complete;
484 	tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
485 
486 	dmaengine_submit(tspi->tx_dma_desc);
487 	dma_async_issue_pending(tspi->tx_dma_chan);
488 	return 0;
489 }
490 
tegra_spi_start_rx_dma(struct tegra_spi_data * tspi,int len)491 static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len)
492 {
493 	reinit_completion(&tspi->rx_dma_complete);
494 	tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
495 				tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
496 				DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
497 	if (!tspi->rx_dma_desc) {
498 		dev_err(tspi->dev, "Not able to get desc for Rx\n");
499 		return -EIO;
500 	}
501 
502 	tspi->rx_dma_desc->callback = tegra_spi_dma_complete;
503 	tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
504 
505 	dmaengine_submit(tspi->rx_dma_desc);
506 	dma_async_issue_pending(tspi->rx_dma_chan);
507 	return 0;
508 }
509 
tegra_spi_flush_fifos(struct tegra_spi_data * tspi)510 static int tegra_spi_flush_fifos(struct tegra_spi_data *tspi)
511 {
512 	unsigned long timeout = jiffies + HZ;
513 	u32 status;
514 
515 	status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
516 	if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
517 		status |= SPI_RX_FIFO_FLUSH | SPI_TX_FIFO_FLUSH;
518 		tegra_spi_writel(tspi, status, SPI_FIFO_STATUS);
519 		while ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
520 			status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
521 			if (time_after(jiffies, timeout)) {
522 				dev_err(tspi->dev,
523 					"timeout waiting for fifo flush\n");
524 				return -EIO;
525 			}
526 
527 			udelay(1);
528 		}
529 	}
530 
531 	return 0;
532 }
533 
tegra_spi_start_dma_based_transfer(struct tegra_spi_data * tspi,struct spi_transfer * t)534 static int tegra_spi_start_dma_based_transfer(
535 		struct tegra_spi_data *tspi, struct spi_transfer *t)
536 {
537 	u32 val;
538 	unsigned int len;
539 	int ret = 0;
540 	u8 dma_burst;
541 	struct dma_slave_config dma_sconfig = {0};
542 
543 	val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1);
544 	tegra_spi_writel(tspi, val, SPI_DMA_BLK);
545 
546 	if (tspi->is_packed)
547 		len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
548 					4) * 4;
549 	else
550 		len = tspi->curr_dma_words * 4;
551 
552 	/* Set attention level based on length of transfer */
553 	if (len & 0xF) {
554 		val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1;
555 		dma_burst = 1;
556 	} else if (((len) >> 4) & 0x1) {
557 		val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4;
558 		dma_burst = 4;
559 	} else {
560 		val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8;
561 		dma_burst = 8;
562 	}
563 
564 	if (!tspi->soc_data->has_intr_mask_reg) {
565 		if (tspi->cur_direction & DATA_DIR_TX)
566 			val |= SPI_IE_TX;
567 
568 		if (tspi->cur_direction & DATA_DIR_RX)
569 			val |= SPI_IE_RX;
570 	}
571 
572 	tegra_spi_writel(tspi, val, SPI_DMA_CTL);
573 	tspi->dma_control_reg = val;
574 
575 	dma_sconfig.device_fc = true;
576 	if (tspi->cur_direction & DATA_DIR_TX) {
577 		dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO;
578 		dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
579 		dma_sconfig.dst_maxburst = dma_burst;
580 		ret = dmaengine_slave_config(tspi->tx_dma_chan, &dma_sconfig);
581 		if (ret < 0) {
582 			dev_err(tspi->dev,
583 				"DMA slave config failed: %d\n", ret);
584 			return ret;
585 		}
586 
587 		tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t);
588 		ret = tegra_spi_start_tx_dma(tspi, len);
589 		if (ret < 0) {
590 			dev_err(tspi->dev,
591 				"Starting tx dma failed, err %d\n", ret);
592 			return ret;
593 		}
594 	}
595 
596 	if (tspi->cur_direction & DATA_DIR_RX) {
597 		dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
598 		dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
599 		dma_sconfig.src_maxburst = dma_burst;
600 		ret = dmaengine_slave_config(tspi->rx_dma_chan, &dma_sconfig);
601 		if (ret < 0) {
602 			dev_err(tspi->dev,
603 				"DMA slave config failed: %d\n", ret);
604 			return ret;
605 		}
606 
607 		/* Make the dma buffer to read by dma */
608 		dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
609 				tspi->dma_buf_size, DMA_FROM_DEVICE);
610 
611 		ret = tegra_spi_start_rx_dma(tspi, len);
612 		if (ret < 0) {
613 			dev_err(tspi->dev,
614 				"Starting rx dma failed, err %d\n", ret);
615 			if (tspi->cur_direction & DATA_DIR_TX)
616 				dmaengine_terminate_all(tspi->tx_dma_chan);
617 			return ret;
618 		}
619 	}
620 	tspi->is_curr_dma_xfer = true;
621 	tspi->dma_control_reg = val;
622 
623 	val |= SPI_DMA_EN;
624 	tegra_spi_writel(tspi, val, SPI_DMA_CTL);
625 	return ret;
626 }
627 
tegra_spi_start_cpu_based_transfer(struct tegra_spi_data * tspi,struct spi_transfer * t)628 static int tegra_spi_start_cpu_based_transfer(
629 		struct tegra_spi_data *tspi, struct spi_transfer *t)
630 {
631 	u32 val;
632 	unsigned cur_words;
633 
634 	if (tspi->cur_direction & DATA_DIR_TX)
635 		cur_words = tegra_spi_fill_tx_fifo_from_client_txbuf(tspi, t);
636 	else
637 		cur_words = tspi->curr_dma_words;
638 
639 	val = SPI_DMA_BLK_SET(cur_words - 1);
640 	tegra_spi_writel(tspi, val, SPI_DMA_BLK);
641 
642 	val = 0;
643 	if (tspi->cur_direction & DATA_DIR_TX)
644 		val |= SPI_IE_TX;
645 
646 	if (tspi->cur_direction & DATA_DIR_RX)
647 		val |= SPI_IE_RX;
648 
649 	tegra_spi_writel(tspi, val, SPI_DMA_CTL);
650 	tspi->dma_control_reg = val;
651 
652 	tspi->is_curr_dma_xfer = false;
653 
654 	val = tspi->command1_reg;
655 	val |= SPI_PIO;
656 	tegra_spi_writel(tspi, val, SPI_COMMAND1);
657 	return 0;
658 }
659 
tegra_spi_init_dma_param(struct tegra_spi_data * tspi,bool dma_to_memory)660 static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
661 			bool dma_to_memory)
662 {
663 	struct dma_chan *dma_chan;
664 	u32 *dma_buf;
665 	dma_addr_t dma_phys;
666 
667 	dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx");
668 	if (IS_ERR(dma_chan))
669 		return dev_err_probe(tspi->dev, PTR_ERR(dma_chan),
670 				     "Dma channel is not available\n");
671 
672 	dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
673 				&dma_phys, GFP_KERNEL);
674 	if (!dma_buf) {
675 		dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
676 		dma_release_channel(dma_chan);
677 		return -ENOMEM;
678 	}
679 
680 	if (dma_to_memory) {
681 		tspi->rx_dma_chan = dma_chan;
682 		tspi->rx_dma_buf = dma_buf;
683 		tspi->rx_dma_phys = dma_phys;
684 	} else {
685 		tspi->tx_dma_chan = dma_chan;
686 		tspi->tx_dma_buf = dma_buf;
687 		tspi->tx_dma_phys = dma_phys;
688 	}
689 	return 0;
690 }
691 
tegra_spi_deinit_dma_param(struct tegra_spi_data * tspi,bool dma_to_memory)692 static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
693 	bool dma_to_memory)
694 {
695 	u32 *dma_buf;
696 	dma_addr_t dma_phys;
697 	struct dma_chan *dma_chan;
698 
699 	if (dma_to_memory) {
700 		dma_buf = tspi->rx_dma_buf;
701 		dma_chan = tspi->rx_dma_chan;
702 		dma_phys = tspi->rx_dma_phys;
703 		tspi->rx_dma_chan = NULL;
704 		tspi->rx_dma_buf = NULL;
705 	} else {
706 		dma_buf = tspi->tx_dma_buf;
707 		dma_chan = tspi->tx_dma_chan;
708 		dma_phys = tspi->tx_dma_phys;
709 		tspi->tx_dma_buf = NULL;
710 		tspi->tx_dma_chan = NULL;
711 	}
712 	if (!dma_chan)
713 		return;
714 
715 	dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
716 	dma_release_channel(dma_chan);
717 }
718 
tegra_spi_set_hw_cs_timing(struct spi_device * spi)719 static int tegra_spi_set_hw_cs_timing(struct spi_device *spi)
720 {
721 	struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
722 	struct spi_delay *setup = &spi->cs_setup;
723 	struct spi_delay *hold = &spi->cs_hold;
724 	struct spi_delay *inactive = &spi->cs_inactive;
725 	u8 setup_dly, hold_dly;
726 	u32 setup_hold;
727 	u32 spi_cs_timing;
728 	u32 inactive_cycles;
729 	u8 cs_state;
730 
731 	if (setup->unit != SPI_DELAY_UNIT_SCK ||
732 	    hold->unit != SPI_DELAY_UNIT_SCK ||
733 	    inactive->unit != SPI_DELAY_UNIT_SCK) {
734 		dev_err(&spi->dev,
735 			"Invalid delay unit %d, should be SPI_DELAY_UNIT_SCK\n",
736 			SPI_DELAY_UNIT_SCK);
737 		return -EINVAL;
738 	}
739 
740 	setup_dly = min_t(u8, setup->value, MAX_SETUP_HOLD_CYCLES);
741 	hold_dly = min_t(u8, hold->value, MAX_SETUP_HOLD_CYCLES);
742 	if (setup_dly && hold_dly) {
743 		setup_hold = SPI_SETUP_HOLD(setup_dly - 1, hold_dly - 1);
744 		spi_cs_timing = SPI_CS_SETUP_HOLD(tspi->spi_cs_timing1,
745 						  spi_get_chipselect(spi, 0),
746 						  setup_hold);
747 		if (tspi->spi_cs_timing1 != spi_cs_timing) {
748 			tspi->spi_cs_timing1 = spi_cs_timing;
749 			tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING1);
750 		}
751 	}
752 
753 	inactive_cycles = min_t(u8, inactive->value, MAX_INACTIVE_CYCLES);
754 	if (inactive_cycles)
755 		inactive_cycles--;
756 	cs_state = inactive_cycles ? 0 : 1;
757 	spi_cs_timing = tspi->spi_cs_timing2;
758 	SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(spi_cs_timing, spi_get_chipselect(spi, 0),
759 					  cs_state);
760 	SPI_SET_CYCLES_BETWEEN_PACKETS(spi_cs_timing, spi_get_chipselect(spi, 0),
761 				       inactive_cycles);
762 	if (tspi->spi_cs_timing2 != spi_cs_timing) {
763 		tspi->spi_cs_timing2 = spi_cs_timing;
764 		tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING2);
765 	}
766 
767 	return 0;
768 }
769 
tegra_spi_setup_transfer_one(struct spi_device * spi,struct spi_transfer * t,bool is_first_of_msg,bool is_single_xfer)770 static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
771 					struct spi_transfer *t,
772 					bool is_first_of_msg,
773 					bool is_single_xfer)
774 {
775 	struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
776 	struct tegra_spi_client_data *cdata = spi->controller_data;
777 	u32 speed = t->speed_hz;
778 	u8 bits_per_word = t->bits_per_word;
779 	u32 command1, command2;
780 	int req_mode;
781 	u32 tx_tap = 0, rx_tap = 0;
782 
783 	if (speed != tspi->cur_speed) {
784 		clk_set_rate(tspi->clk, speed);
785 		tspi->cur_speed = speed;
786 	}
787 
788 	tspi->cur_spi = spi;
789 	tspi->cur_pos = 0;
790 	tspi->cur_rx_pos = 0;
791 	tspi->cur_tx_pos = 0;
792 	tspi->curr_xfer = t;
793 
794 	if (is_first_of_msg) {
795 		tegra_spi_clear_status(tspi);
796 
797 		command1 = tspi->def_command1_reg;
798 		command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
799 
800 		command1 &= ~SPI_CONTROL_MODE_MASK;
801 		req_mode = spi->mode & 0x3;
802 		if (req_mode == SPI_MODE_0)
803 			command1 |= SPI_CONTROL_MODE_0;
804 		else if (req_mode == SPI_MODE_1)
805 			command1 |= SPI_CONTROL_MODE_1;
806 		else if (req_mode == SPI_MODE_2)
807 			command1 |= SPI_CONTROL_MODE_2;
808 		else if (req_mode == SPI_MODE_3)
809 			command1 |= SPI_CONTROL_MODE_3;
810 
811 		if (spi->mode & SPI_LSB_FIRST)
812 			command1 |= SPI_LSBIT_FE;
813 		else
814 			command1 &= ~SPI_LSBIT_FE;
815 
816 		if (spi->mode & SPI_3WIRE)
817 			command1 |= SPI_BIDIROE;
818 		else
819 			command1 &= ~SPI_BIDIROE;
820 
821 		if (tspi->cs_control) {
822 			if (tspi->cs_control != spi)
823 				tegra_spi_writel(tspi, command1, SPI_COMMAND1);
824 			tspi->cs_control = NULL;
825 		} else
826 			tegra_spi_writel(tspi, command1, SPI_COMMAND1);
827 
828 		/* GPIO based chip select control */
829 		if (spi_get_csgpiod(spi, 0))
830 			gpiod_set_value(spi_get_csgpiod(spi, 0), 1);
831 
832 		if (is_single_xfer && !(t->cs_change)) {
833 			tspi->use_hw_based_cs = true;
834 			command1 &= ~(SPI_CS_SW_HW | SPI_CS_SW_VAL);
835 		} else {
836 			tspi->use_hw_based_cs = false;
837 			command1 |= SPI_CS_SW_HW;
838 			if (spi->mode & SPI_CS_HIGH)
839 				command1 |= SPI_CS_SW_VAL;
840 			else
841 				command1 &= ~SPI_CS_SW_VAL;
842 		}
843 
844 		if (tspi->last_used_cs != spi_get_chipselect(spi, 0)) {
845 			if (cdata && cdata->tx_clk_tap_delay)
846 				tx_tap = cdata->tx_clk_tap_delay;
847 			if (cdata && cdata->rx_clk_tap_delay)
848 				rx_tap = cdata->rx_clk_tap_delay;
849 			command2 = SPI_TX_TAP_DELAY(tx_tap) |
850 				   SPI_RX_TAP_DELAY(rx_tap);
851 			if (command2 != tspi->def_command2_reg)
852 				tegra_spi_writel(tspi, command2, SPI_COMMAND2);
853 			tspi->last_used_cs = spi_get_chipselect(spi, 0);
854 		}
855 
856 	} else {
857 		command1 = tspi->command1_reg;
858 		command1 &= ~SPI_BIT_LENGTH(~0);
859 		command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
860 	}
861 
862 	return command1;
863 }
864 
tegra_spi_start_transfer_one(struct spi_device * spi,struct spi_transfer * t,u32 command1)865 static int tegra_spi_start_transfer_one(struct spi_device *spi,
866 		struct spi_transfer *t, u32 command1)
867 {
868 	struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
869 	unsigned total_fifo_words;
870 	int ret;
871 
872 	total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t);
873 
874 	if (t->rx_nbits == SPI_NBITS_DUAL || t->tx_nbits == SPI_NBITS_DUAL)
875 		command1 |= SPI_BOTH_EN_BIT;
876 	else
877 		command1 &= ~SPI_BOTH_EN_BIT;
878 
879 	if (tspi->is_packed)
880 		command1 |= SPI_PACKED;
881 	else
882 		command1 &= ~SPI_PACKED;
883 
884 	command1 &= ~(SPI_CS_SEL_MASK | SPI_TX_EN | SPI_RX_EN);
885 	tspi->cur_direction = 0;
886 	if (t->rx_buf) {
887 		command1 |= SPI_RX_EN;
888 		tspi->cur_direction |= DATA_DIR_RX;
889 	}
890 	if (t->tx_buf) {
891 		command1 |= SPI_TX_EN;
892 		tspi->cur_direction |= DATA_DIR_TX;
893 	}
894 	command1 |= SPI_CS_SEL(spi_get_chipselect(spi, 0));
895 	tegra_spi_writel(tspi, command1, SPI_COMMAND1);
896 	tspi->command1_reg = command1;
897 
898 	dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n",
899 		tspi->def_command1_reg, (unsigned)command1);
900 
901 	ret = tegra_spi_flush_fifos(tspi);
902 	if (ret < 0)
903 		return ret;
904 	if (total_fifo_words > SPI_FIFO_DEPTH)
905 		ret = tegra_spi_start_dma_based_transfer(tspi, t);
906 	else
907 		ret = tegra_spi_start_cpu_based_transfer(tspi, t);
908 	return ret;
909 }
910 
911 static struct tegra_spi_client_data
tegra_spi_parse_cdata_dt(struct spi_device * spi)912 	*tegra_spi_parse_cdata_dt(struct spi_device *spi)
913 {
914 	struct tegra_spi_client_data *cdata;
915 	struct device_node *target_np;
916 
917 	target_np = spi->dev.of_node;
918 	if (!target_np) {
919 		dev_dbg(&spi->dev, "device node not found\n");
920 		return NULL;
921 	}
922 
923 	cdata = kzalloc(sizeof(*cdata), GFP_KERNEL);
924 	if (!cdata)
925 		return NULL;
926 
927 	of_property_read_u32(target_np, "nvidia,tx-clk-tap-delay",
928 			     &cdata->tx_clk_tap_delay);
929 	of_property_read_u32(target_np, "nvidia,rx-clk-tap-delay",
930 			     &cdata->rx_clk_tap_delay);
931 	return cdata;
932 }
933 
tegra_spi_cleanup(struct spi_device * spi)934 static void tegra_spi_cleanup(struct spi_device *spi)
935 {
936 	struct tegra_spi_client_data *cdata = spi->controller_data;
937 
938 	spi->controller_data = NULL;
939 	if (spi->dev.of_node)
940 		kfree(cdata);
941 }
942 
tegra_spi_setup(struct spi_device * spi)943 static int tegra_spi_setup(struct spi_device *spi)
944 {
945 	struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
946 	struct tegra_spi_client_data *cdata = spi->controller_data;
947 	u32 val;
948 	unsigned long flags;
949 	int ret;
950 
951 	dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
952 		spi->bits_per_word,
953 		spi->mode & SPI_CPOL ? "" : "~",
954 		spi->mode & SPI_CPHA ? "" : "~",
955 		spi->max_speed_hz);
956 
957 	if (!cdata) {
958 		cdata = tegra_spi_parse_cdata_dt(spi);
959 		spi->controller_data = cdata;
960 	}
961 
962 	ret = pm_runtime_resume_and_get(tspi->dev);
963 	if (ret < 0) {
964 		dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
965 		if (cdata)
966 			tegra_spi_cleanup(spi);
967 		return ret;
968 	}
969 
970 	if (tspi->soc_data->has_intr_mask_reg) {
971 		val = tegra_spi_readl(tspi, SPI_INTR_MASK);
972 		val &= ~SPI_INTR_ALL_MASK;
973 		tegra_spi_writel(tspi, val, SPI_INTR_MASK);
974 	}
975 
976 	spin_lock_irqsave(&tspi->lock, flags);
977 	/* GPIO based chip select control */
978 	if (spi_get_csgpiod(spi, 0))
979 		gpiod_set_value(spi_get_csgpiod(spi, 0), 0);
980 
981 	val = tspi->def_command1_reg;
982 	if (spi->mode & SPI_CS_HIGH)
983 		val &= ~SPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0));
984 	else
985 		val |= SPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0));
986 	tspi->def_command1_reg = val;
987 	tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
988 	spin_unlock_irqrestore(&tspi->lock, flags);
989 
990 	pm_runtime_put(tspi->dev);
991 	return 0;
992 }
993 
tegra_spi_transfer_end(struct spi_device * spi)994 static void tegra_spi_transfer_end(struct spi_device *spi)
995 {
996 	struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
997 	int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;
998 
999 	/* GPIO based chip select control */
1000 	if (spi_get_csgpiod(spi, 0))
1001 		gpiod_set_value(spi_get_csgpiod(spi, 0), 0);
1002 
1003 	if (!tspi->use_hw_based_cs) {
1004 		if (cs_val)
1005 			tspi->command1_reg |= SPI_CS_SW_VAL;
1006 		else
1007 			tspi->command1_reg &= ~SPI_CS_SW_VAL;
1008 		tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
1009 	}
1010 
1011 	tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1012 }
1013 
tegra_spi_dump_regs(struct tegra_spi_data * tspi)1014 static void tegra_spi_dump_regs(struct tegra_spi_data *tspi)
1015 {
1016 	dev_dbg(tspi->dev, "============ SPI REGISTER DUMP ============\n");
1017 	dev_dbg(tspi->dev, "Command1:    0x%08x | Command2:    0x%08x\n",
1018 		tegra_spi_readl(tspi, SPI_COMMAND1),
1019 		tegra_spi_readl(tspi, SPI_COMMAND2));
1020 	dev_dbg(tspi->dev, "DMA_CTL:     0x%08x | DMA_BLK:     0x%08x\n",
1021 		tegra_spi_readl(tspi, SPI_DMA_CTL),
1022 		tegra_spi_readl(tspi, SPI_DMA_BLK));
1023 	dev_dbg(tspi->dev, "TRANS_STAT:  0x%08x | FIFO_STATUS: 0x%08x\n",
1024 		tegra_spi_readl(tspi, SPI_TRANS_STATUS),
1025 		tegra_spi_readl(tspi, SPI_FIFO_STATUS));
1026 }
1027 
tegra_spi_transfer_one_message(struct spi_controller * host,struct spi_message * msg)1028 static int tegra_spi_transfer_one_message(struct spi_controller *host,
1029 			struct spi_message *msg)
1030 {
1031 	bool is_first_msg = true;
1032 	struct tegra_spi_data *tspi = spi_controller_get_devdata(host);
1033 	struct spi_transfer *xfer;
1034 	struct spi_device *spi = msg->spi;
1035 	int ret;
1036 	bool skip = false;
1037 	int single_xfer;
1038 
1039 	msg->status = 0;
1040 	msg->actual_length = 0;
1041 
1042 	single_xfer = list_is_singular(&msg->transfers);
1043 	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1044 		u32 cmd1;
1045 
1046 		reinit_completion(&tspi->xfer_completion);
1047 
1048 		cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg,
1049 						    single_xfer);
1050 
1051 		if (!xfer->len) {
1052 			ret = 0;
1053 			skip = true;
1054 			goto complete_xfer;
1055 		}
1056 
1057 		ret = tegra_spi_start_transfer_one(spi, xfer, cmd1);
1058 		if (ret < 0) {
1059 			dev_err(tspi->dev,
1060 				"spi can not start transfer, err %d\n", ret);
1061 			goto complete_xfer;
1062 		}
1063 
1064 		is_first_msg = false;
1065 		ret = wait_for_completion_timeout(&tspi->xfer_completion,
1066 						SPI_DMA_TIMEOUT);
1067 		if (WARN_ON(ret == 0)) {
1068 			dev_err(tspi->dev, "spi transfer timeout\n");
1069 			if (tspi->is_curr_dma_xfer &&
1070 			    (tspi->cur_direction & DATA_DIR_TX))
1071 				dmaengine_terminate_all(tspi->tx_dma_chan);
1072 			if (tspi->is_curr_dma_xfer &&
1073 			    (tspi->cur_direction & DATA_DIR_RX))
1074 				dmaengine_terminate_all(tspi->rx_dma_chan);
1075 			ret = -EIO;
1076 			tegra_spi_dump_regs(tspi);
1077 			tegra_spi_flush_fifos(tspi);
1078 			reset_control_assert(tspi->rst);
1079 			udelay(2);
1080 			reset_control_deassert(tspi->rst);
1081 			tspi->last_used_cs = host->num_chipselect + 1;
1082 			goto complete_xfer;
1083 		}
1084 
1085 		if (tspi->tx_status ||  tspi->rx_status) {
1086 			dev_err(tspi->dev, "Error in Transfer\n");
1087 			ret = -EIO;
1088 			tegra_spi_dump_regs(tspi);
1089 			goto complete_xfer;
1090 		}
1091 		msg->actual_length += xfer->len;
1092 
1093 complete_xfer:
1094 		if (ret < 0 || skip) {
1095 			tegra_spi_transfer_end(spi);
1096 			spi_transfer_delay_exec(xfer);
1097 			goto exit;
1098 		} else if (list_is_last(&xfer->transfer_list,
1099 					&msg->transfers)) {
1100 			if (xfer->cs_change)
1101 				tspi->cs_control = spi;
1102 			else {
1103 				tegra_spi_transfer_end(spi);
1104 				spi_transfer_delay_exec(xfer);
1105 			}
1106 		} else if (xfer->cs_change) {
1107 			tegra_spi_transfer_end(spi);
1108 			spi_transfer_delay_exec(xfer);
1109 		}
1110 
1111 	}
1112 	ret = 0;
1113 exit:
1114 	msg->status = ret;
1115 	spi_finalize_current_message(host);
1116 	return ret;
1117 }
1118 
handle_cpu_based_xfer(struct tegra_spi_data * tspi)1119 static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
1120 {
1121 	struct spi_transfer *t = tspi->curr_xfer;
1122 	unsigned long flags;
1123 
1124 	spin_lock_irqsave(&tspi->lock, flags);
1125 	if (tspi->tx_status ||  tspi->rx_status) {
1126 		dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n",
1127 			tspi->status_reg);
1128 		dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
1129 			tspi->command1_reg, tspi->dma_control_reg);
1130 		tegra_spi_dump_regs(tspi);
1131 		tegra_spi_flush_fifos(tspi);
1132 		complete(&tspi->xfer_completion);
1133 		spin_unlock_irqrestore(&tspi->lock, flags);
1134 		reset_control_assert(tspi->rst);
1135 		udelay(2);
1136 		reset_control_deassert(tspi->rst);
1137 		return IRQ_HANDLED;
1138 	}
1139 
1140 	if (tspi->cur_direction & DATA_DIR_RX)
1141 		tegra_spi_read_rx_fifo_to_client_rxbuf(tspi, t);
1142 
1143 	if (tspi->cur_direction & DATA_DIR_TX)
1144 		tspi->cur_pos = tspi->cur_tx_pos;
1145 	else
1146 		tspi->cur_pos = tspi->cur_rx_pos;
1147 
1148 	if (tspi->cur_pos == t->len) {
1149 		complete(&tspi->xfer_completion);
1150 		goto exit;
1151 	}
1152 
1153 	tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
1154 	tegra_spi_start_cpu_based_transfer(tspi, t);
1155 exit:
1156 	spin_unlock_irqrestore(&tspi->lock, flags);
1157 	return IRQ_HANDLED;
1158 }
1159 
handle_dma_based_xfer(struct tegra_spi_data * tspi)1160 static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
1161 {
1162 	struct spi_transfer *t = tspi->curr_xfer;
1163 	long wait_status;
1164 	int err = 0;
1165 	unsigned total_fifo_words;
1166 	unsigned long flags;
1167 
1168 	/* Abort dmas if any error */
1169 	if (tspi->cur_direction & DATA_DIR_TX) {
1170 		if (tspi->tx_status) {
1171 			dmaengine_terminate_all(tspi->tx_dma_chan);
1172 			err += 1;
1173 		} else {
1174 			wait_status = wait_for_completion_interruptible_timeout(
1175 				&tspi->tx_dma_complete, SPI_DMA_TIMEOUT);
1176 			if (wait_status <= 0) {
1177 				dmaengine_terminate_all(tspi->tx_dma_chan);
1178 				dev_err(tspi->dev, "TxDma Xfer failed\n");
1179 				err += 1;
1180 			}
1181 		}
1182 	}
1183 
1184 	if (tspi->cur_direction & DATA_DIR_RX) {
1185 		if (tspi->rx_status) {
1186 			dmaengine_terminate_all(tspi->rx_dma_chan);
1187 			err += 2;
1188 		} else {
1189 			wait_status = wait_for_completion_interruptible_timeout(
1190 				&tspi->rx_dma_complete, SPI_DMA_TIMEOUT);
1191 			if (wait_status <= 0) {
1192 				dmaengine_terminate_all(tspi->rx_dma_chan);
1193 				dev_err(tspi->dev, "RxDma Xfer failed\n");
1194 				err += 2;
1195 			}
1196 		}
1197 	}
1198 
1199 	spin_lock_irqsave(&tspi->lock, flags);
1200 	if (err) {
1201 		dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n",
1202 			tspi->status_reg);
1203 		dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
1204 			tspi->command1_reg, tspi->dma_control_reg);
1205 		tegra_spi_dump_regs(tspi);
1206 		tegra_spi_flush_fifos(tspi);
1207 		complete(&tspi->xfer_completion);
1208 		spin_unlock_irqrestore(&tspi->lock, flags);
1209 		reset_control_assert(tspi->rst);
1210 		udelay(2);
1211 		reset_control_deassert(tspi->rst);
1212 		return IRQ_HANDLED;
1213 	}
1214 
1215 	if (tspi->cur_direction & DATA_DIR_RX)
1216 		tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
1217 
1218 	if (tspi->cur_direction & DATA_DIR_TX)
1219 		tspi->cur_pos = tspi->cur_tx_pos;
1220 	else
1221 		tspi->cur_pos = tspi->cur_rx_pos;
1222 
1223 	if (tspi->cur_pos == t->len) {
1224 		complete(&tspi->xfer_completion);
1225 		goto exit;
1226 	}
1227 
1228 	/* Continue transfer in current message */
1229 	total_fifo_words = tegra_spi_calculate_curr_xfer_param(tspi->cur_spi,
1230 							tspi, t);
1231 	if (total_fifo_words > SPI_FIFO_DEPTH)
1232 		err = tegra_spi_start_dma_based_transfer(tspi, t);
1233 	else
1234 		err = tegra_spi_start_cpu_based_transfer(tspi, t);
1235 
1236 exit:
1237 	spin_unlock_irqrestore(&tspi->lock, flags);
1238 	return IRQ_HANDLED;
1239 }
1240 
tegra_spi_isr_thread(int irq,void * context_data)1241 static irqreturn_t tegra_spi_isr_thread(int irq, void *context_data)
1242 {
1243 	struct tegra_spi_data *tspi = context_data;
1244 
1245 	if (!tspi->is_curr_dma_xfer)
1246 		return handle_cpu_based_xfer(tspi);
1247 	return handle_dma_based_xfer(tspi);
1248 }
1249 
tegra_spi_isr(int irq,void * context_data)1250 static irqreturn_t tegra_spi_isr(int irq, void *context_data)
1251 {
1252 	struct tegra_spi_data *tspi = context_data;
1253 
1254 	tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
1255 	if (tspi->cur_direction & DATA_DIR_TX)
1256 		tspi->tx_status = tspi->status_reg &
1257 					(SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF);
1258 
1259 	if (tspi->cur_direction & DATA_DIR_RX)
1260 		tspi->rx_status = tspi->status_reg &
1261 					(SPI_RX_FIFO_OVF | SPI_RX_FIFO_UNF);
1262 	tegra_spi_clear_status(tspi);
1263 
1264 	return IRQ_WAKE_THREAD;
1265 }
1266 
1267 static struct tegra_spi_soc_data tegra114_spi_soc_data = {
1268 	.has_intr_mask_reg = false,
1269 };
1270 
1271 static struct tegra_spi_soc_data tegra124_spi_soc_data = {
1272 	.has_intr_mask_reg = false,
1273 };
1274 
1275 static struct tegra_spi_soc_data tegra210_spi_soc_data = {
1276 	.has_intr_mask_reg = true,
1277 };
1278 
1279 static const struct of_device_id tegra_spi_of_match[] = {
1280 	{
1281 		.compatible = "nvidia,tegra114-spi",
1282 		.data	    = &tegra114_spi_soc_data,
1283 	}, {
1284 		.compatible = "nvidia,tegra124-spi",
1285 		.data	    = &tegra124_spi_soc_data,
1286 	}, {
1287 		.compatible = "nvidia,tegra210-spi",
1288 		.data	    = &tegra210_spi_soc_data,
1289 	},
1290 	{}
1291 };
1292 MODULE_DEVICE_TABLE(of, tegra_spi_of_match);
1293 
tegra_spi_probe(struct platform_device * pdev)1294 static int tegra_spi_probe(struct platform_device *pdev)
1295 {
1296 	struct spi_controller	*host;
1297 	struct tegra_spi_data	*tspi;
1298 	struct resource		*r;
1299 	int ret, spi_irq;
1300 	int bus_num;
1301 
1302 	host = spi_alloc_host(&pdev->dev, sizeof(*tspi));
1303 	if (!host) {
1304 		dev_err(&pdev->dev, "host allocation failed\n");
1305 		return -ENOMEM;
1306 	}
1307 	platform_set_drvdata(pdev, host);
1308 	tspi = spi_controller_get_devdata(host);
1309 
1310 	if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
1311 				 &host->max_speed_hz))
1312 		host->max_speed_hz = 25000000; /* 25MHz */
1313 
1314 	/* the spi->mode bits understood by this driver: */
1315 	host->use_gpio_descriptors = true;
1316 	host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
1317 			  SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE;
1318 	host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1319 	host->setup = tegra_spi_setup;
1320 	host->cleanup = tegra_spi_cleanup;
1321 	host->transfer_one_message = tegra_spi_transfer_one_message;
1322 	host->set_cs_timing = tegra_spi_set_hw_cs_timing;
1323 	host->num_chipselect = MAX_CHIP_SELECT;
1324 	host->auto_runtime_pm = true;
1325 	bus_num = of_alias_get_id(pdev->dev.of_node, "spi");
1326 	if (bus_num >= 0)
1327 		host->bus_num = bus_num;
1328 
1329 	tspi->host = host;
1330 	tspi->dev = &pdev->dev;
1331 	spin_lock_init(&tspi->lock);
1332 
1333 	tspi->soc_data = of_device_get_match_data(&pdev->dev);
1334 	if (!tspi->soc_data) {
1335 		dev_err(&pdev->dev, "unsupported tegra\n");
1336 		ret = -ENODEV;
1337 		goto exit_free_host;
1338 	}
1339 
1340 	tspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
1341 	if (IS_ERR(tspi->base)) {
1342 		ret = PTR_ERR(tspi->base);
1343 		goto exit_free_host;
1344 	}
1345 	tspi->phys = r->start;
1346 
1347 	spi_irq = platform_get_irq(pdev, 0);
1348 	if (spi_irq < 0) {
1349 		ret = spi_irq;
1350 		goto exit_free_host;
1351 	}
1352 	tspi->irq = spi_irq;
1353 
1354 	tspi->clk = devm_clk_get(&pdev->dev, "spi");
1355 	if (IS_ERR(tspi->clk)) {
1356 		dev_err(&pdev->dev, "can not get clock\n");
1357 		ret = PTR_ERR(tspi->clk);
1358 		goto exit_free_host;
1359 	}
1360 
1361 	tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
1362 	if (IS_ERR(tspi->rst)) {
1363 		dev_err(&pdev->dev, "can not get reset\n");
1364 		ret = PTR_ERR(tspi->rst);
1365 		goto exit_free_host;
1366 	}
1367 
1368 	tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
1369 	tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1370 
1371 	ret = tegra_spi_init_dma_param(tspi, true);
1372 	if (ret < 0)
1373 		goto exit_free_host;
1374 	ret = tegra_spi_init_dma_param(tspi, false);
1375 	if (ret < 0)
1376 		goto exit_rx_dma_free;
1377 	tspi->max_buf_size = tspi->dma_buf_size;
1378 	init_completion(&tspi->tx_dma_complete);
1379 	init_completion(&tspi->rx_dma_complete);
1380 
1381 	init_completion(&tspi->xfer_completion);
1382 
1383 	pm_runtime_enable(&pdev->dev);
1384 	if (!pm_runtime_enabled(&pdev->dev)) {
1385 		ret = tegra_spi_runtime_resume(&pdev->dev);
1386 		if (ret)
1387 			goto exit_pm_disable;
1388 	}
1389 
1390 	ret = pm_runtime_resume_and_get(&pdev->dev);
1391 	if (ret < 0) {
1392 		dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1393 		goto exit_pm_disable;
1394 	}
1395 
1396 	reset_control_assert(tspi->rst);
1397 	udelay(2);
1398 	reset_control_deassert(tspi->rst);
1399 	tspi->def_command1_reg  = SPI_M_S;
1400 	tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1401 	tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1);
1402 	tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2);
1403 	tspi->def_command2_reg = tegra_spi_readl(tspi, SPI_COMMAND2);
1404 	tspi->last_used_cs = host->num_chipselect + 1;
1405 	pm_runtime_put(&pdev->dev);
1406 	ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
1407 				   tegra_spi_isr_thread, IRQF_ONESHOT,
1408 				   dev_name(&pdev->dev), tspi);
1409 	if (ret < 0) {
1410 		dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1411 			tspi->irq);
1412 		goto exit_pm_disable;
1413 	}
1414 
1415 	host->dev.of_node = pdev->dev.of_node;
1416 	ret = devm_spi_register_controller(&pdev->dev, host);
1417 	if (ret < 0) {
1418 		dev_err(&pdev->dev, "can not register to host err %d\n", ret);
1419 		goto exit_free_irq;
1420 	}
1421 	return ret;
1422 
1423 exit_free_irq:
1424 	free_irq(spi_irq, tspi);
1425 exit_pm_disable:
1426 	pm_runtime_disable(&pdev->dev);
1427 	if (!pm_runtime_status_suspended(&pdev->dev))
1428 		tegra_spi_runtime_suspend(&pdev->dev);
1429 	tegra_spi_deinit_dma_param(tspi, false);
1430 exit_rx_dma_free:
1431 	tegra_spi_deinit_dma_param(tspi, true);
1432 exit_free_host:
1433 	spi_controller_put(host);
1434 	return ret;
1435 }
1436 
tegra_spi_remove(struct platform_device * pdev)1437 static void tegra_spi_remove(struct platform_device *pdev)
1438 {
1439 	struct spi_controller *host = platform_get_drvdata(pdev);
1440 	struct tegra_spi_data	*tspi = spi_controller_get_devdata(host);
1441 
1442 	free_irq(tspi->irq, tspi);
1443 
1444 	if (tspi->tx_dma_chan)
1445 		tegra_spi_deinit_dma_param(tspi, false);
1446 
1447 	if (tspi->rx_dma_chan)
1448 		tegra_spi_deinit_dma_param(tspi, true);
1449 
1450 	pm_runtime_disable(&pdev->dev);
1451 	if (!pm_runtime_status_suspended(&pdev->dev))
1452 		tegra_spi_runtime_suspend(&pdev->dev);
1453 }
1454 
1455 #ifdef CONFIG_PM_SLEEP
tegra_spi_suspend(struct device * dev)1456 static int tegra_spi_suspend(struct device *dev)
1457 {
1458 	struct spi_controller *host = dev_get_drvdata(dev);
1459 
1460 	return spi_controller_suspend(host);
1461 }
1462 
tegra_spi_resume(struct device * dev)1463 static int tegra_spi_resume(struct device *dev)
1464 {
1465 	struct spi_controller *host = dev_get_drvdata(dev);
1466 	struct tegra_spi_data *tspi = spi_controller_get_devdata(host);
1467 	int ret;
1468 
1469 	ret = pm_runtime_resume_and_get(dev);
1470 	if (ret < 0) {
1471 		dev_err(dev, "pm runtime failed, e = %d\n", ret);
1472 		return ret;
1473 	}
1474 	tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
1475 	tegra_spi_writel(tspi, tspi->def_command2_reg, SPI_COMMAND2);
1476 	tspi->last_used_cs = host->num_chipselect + 1;
1477 	pm_runtime_put(dev);
1478 
1479 	return spi_controller_resume(host);
1480 }
1481 #endif
1482 
tegra_spi_runtime_suspend(struct device * dev)1483 static int tegra_spi_runtime_suspend(struct device *dev)
1484 {
1485 	struct spi_controller *host = dev_get_drvdata(dev);
1486 	struct tegra_spi_data *tspi = spi_controller_get_devdata(host);
1487 
1488 	/* Flush all write which are in PPSB queue by reading back */
1489 	tegra_spi_readl(tspi, SPI_COMMAND1);
1490 
1491 	clk_disable_unprepare(tspi->clk);
1492 	return 0;
1493 }
1494 
tegra_spi_runtime_resume(struct device * dev)1495 static int tegra_spi_runtime_resume(struct device *dev)
1496 {
1497 	struct spi_controller *host = dev_get_drvdata(dev);
1498 	struct tegra_spi_data *tspi = spi_controller_get_devdata(host);
1499 	int ret;
1500 
1501 	ret = clk_prepare_enable(tspi->clk);
1502 	if (ret < 0) {
1503 		dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1504 		return ret;
1505 	}
1506 	return 0;
1507 }
1508 
1509 static const struct dev_pm_ops tegra_spi_pm_ops = {
1510 	SET_RUNTIME_PM_OPS(tegra_spi_runtime_suspend,
1511 		tegra_spi_runtime_resume, NULL)
1512 	SET_SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend, tegra_spi_resume)
1513 };
1514 static struct platform_driver tegra_spi_driver = {
1515 	.driver = {
1516 		.name		= "spi-tegra114",
1517 		.pm		= &tegra_spi_pm_ops,
1518 		.of_match_table	= tegra_spi_of_match,
1519 	},
1520 	.probe =	tegra_spi_probe,
1521 	.remove_new =	tegra_spi_remove,
1522 };
1523 module_platform_driver(tegra_spi_driver);
1524 
1525 MODULE_ALIAS("platform:spi-tegra114");
1526 MODULE_DESCRIPTION("NVIDIA Tegra114 SPI Controller Driver");
1527 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1528 MODULE_LICENSE("GPL v2");
1529