1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2016-2017 Micron Technology, Inc. 4 * 5 * Authors: 6 * Peter Pan <peterpandong@micron.com> 7 */ 8 #ifndef __LINUX_MTD_SPINAND_H 9 #define __LINUX_MTD_SPINAND_H 10 11 #include <linux/mutex.h> 12 #include <linux/bitops.h> 13 #include <linux/device.h> 14 #include <linux/mtd/mtd.h> 15 #include <linux/mtd/nand.h> 16 #include <linux/spi/spi.h> 17 #include <linux/spi/spi-mem.h> 18 19 /** 20 * Standard SPI NAND flash operations 21 */ 22 23 #define SPINAND_RESET_1S_0_0_OP \ 24 SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \ 25 SPI_MEM_OP_NO_ADDR, \ 26 SPI_MEM_OP_NO_DUMMY, \ 27 SPI_MEM_OP_NO_DATA) 28 29 #define SPINAND_WR_EN_1S_0_0_OP \ 30 SPI_MEM_OP(SPI_MEM_OP_CMD(0x06, 1), \ 31 SPI_MEM_OP_NO_ADDR, \ 32 SPI_MEM_OP_NO_DUMMY, \ 33 SPI_MEM_OP_NO_DATA) 34 35 #define SPINAND_WR_DIS_1S_0_0_OP \ 36 SPI_MEM_OP(SPI_MEM_OP_CMD(0x04, 1), \ 37 SPI_MEM_OP_NO_ADDR, \ 38 SPI_MEM_OP_NO_DUMMY, \ 39 SPI_MEM_OP_NO_DATA) 40 41 #define SPINAND_READID_1S_1S_1S_OP(naddr, ndummy, buf, len) \ 42 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \ 43 SPI_MEM_OP_ADDR(naddr, 0, 1), \ 44 SPI_MEM_OP_DUMMY(ndummy, 1), \ 45 SPI_MEM_OP_DATA_IN(len, buf, 1)) 46 47 #define SPINAND_SET_FEATURE_1S_1S_1S_OP(reg, valptr) \ 48 SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \ 49 SPI_MEM_OP_ADDR(1, reg, 1), \ 50 SPI_MEM_OP_NO_DUMMY, \ 51 SPI_MEM_OP_DATA_OUT(1, valptr, 1)) 52 53 #define SPINAND_GET_FEATURE_1S_1S_1S_OP(reg, valptr) \ 54 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), \ 55 SPI_MEM_OP_ADDR(1, reg, 1), \ 56 SPI_MEM_OP_NO_DUMMY, \ 57 SPI_MEM_OP_DATA_IN(1, valptr, 1)) 58 59 #define SPINAND_BLK_ERASE_1S_1S_0_OP(addr) \ 60 SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), \ 61 SPI_MEM_OP_ADDR(3, addr, 1), \ 62 SPI_MEM_OP_NO_DUMMY, \ 63 SPI_MEM_OP_NO_DATA) 64 65 #define SPINAND_PAGE_READ_1S_1S_0_OP(addr) \ 66 SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), \ 67 SPI_MEM_OP_ADDR(3, addr, 1), \ 68 SPI_MEM_OP_NO_DUMMY, \ 69 SPI_MEM_OP_NO_DATA) 70 71 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \ 72 SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \ 73 SPI_MEM_OP_ADDR(2, addr, 1), \ 74 SPI_MEM_OP_DUMMY(ndummy, 1), \ 75 SPI_MEM_OP_DATA_IN(len, buf, 1), \ 76 SPI_MEM_OP_MAX_FREQ(freq)) 77 78 #define SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \ 79 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \ 80 SPI_MEM_OP_ADDR(2, addr, 1), \ 81 SPI_MEM_OP_DUMMY(ndummy, 1), \ 82 SPI_MEM_OP_DATA_IN(len, buf, 1), \ 83 SPI_MEM_OP_MAX_FREQ(freq)) 84 85 #define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \ 86 SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \ 87 SPI_MEM_OP_ADDR(3, addr, 1), \ 88 SPI_MEM_OP_DUMMY(ndummy, 1), \ 89 SPI_MEM_OP_DATA_IN(len, buf, 1), \ 90 SPI_MEM_OP_MAX_FREQ(freq)) 91 92 #define SPINAND_PAGE_READ_FROM_CACHE_FAST_3A_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \ 93 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \ 94 SPI_MEM_OP_ADDR(3, addr, 1), \ 95 SPI_MEM_OP_DUMMY(ndummy, 1), \ 96 SPI_MEM_OP_DATA_IN(len, buf, 1), \ 97 SPI_MEM_OP_MAX_FREQ(freq)) 98 99 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_1D_OP(addr, ndummy, buf, len, freq) \ 100 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0d, 1), \ 101 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \ 102 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \ 103 SPI_MEM_DTR_OP_DATA_IN(len, buf, 1), \ 104 SPI_MEM_OP_MAX_FREQ(freq)) 105 106 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_2S_OP(addr, ndummy, buf, len, freq) \ 107 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ 108 SPI_MEM_OP_ADDR(2, addr, 1), \ 109 SPI_MEM_OP_DUMMY(ndummy, 1), \ 110 SPI_MEM_OP_DATA_IN(len, buf, 2), \ 111 SPI_MEM_OP_MAX_FREQ(freq)) 112 113 #define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_2S_OP(addr, ndummy, buf, len, freq) \ 114 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ 115 SPI_MEM_OP_ADDR(3, addr, 1), \ 116 SPI_MEM_OP_DUMMY(ndummy, 1), \ 117 SPI_MEM_OP_DATA_IN(len, buf, 2), \ 118 SPI_MEM_OP_MAX_FREQ(freq)) 119 120 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_2D_OP(addr, ndummy, buf, len, freq) \ 121 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3d, 1), \ 122 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \ 123 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \ 124 SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \ 125 SPI_MEM_OP_MAX_FREQ(freq)) 126 127 #define SPINAND_PAGE_READ_FROM_CACHE_1S_2S_2S_OP(addr, ndummy, buf, len, freq) \ 128 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ 129 SPI_MEM_OP_ADDR(2, addr, 2), \ 130 SPI_MEM_OP_DUMMY(ndummy, 2), \ 131 SPI_MEM_OP_DATA_IN(len, buf, 2), \ 132 SPI_MEM_OP_MAX_FREQ(freq)) 133 134 #define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_2S_2S_OP(addr, ndummy, buf, len, freq) \ 135 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ 136 SPI_MEM_OP_ADDR(3, addr, 2), \ 137 SPI_MEM_OP_DUMMY(ndummy, 2), \ 138 SPI_MEM_OP_DATA_IN(len, buf, 2), \ 139 SPI_MEM_OP_MAX_FREQ(freq)) 140 141 #define SPINAND_PAGE_READ_FROM_CACHE_1S_2D_2D_OP(addr, ndummy, buf, len, freq) \ 142 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbd, 1), \ 143 SPI_MEM_DTR_OP_ADDR(2, addr, 2), \ 144 SPI_MEM_DTR_OP_DUMMY(ndummy, 2), \ 145 SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \ 146 SPI_MEM_OP_MAX_FREQ(freq)) 147 148 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(addr, ndummy, buf, len, freq) \ 149 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ 150 SPI_MEM_OP_ADDR(2, addr, 1), \ 151 SPI_MEM_OP_DUMMY(ndummy, 1), \ 152 SPI_MEM_OP_DATA_IN(len, buf, 4), \ 153 SPI_MEM_OP_MAX_FREQ(freq)) 154 155 #define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_4S_OP(addr, ndummy, buf, len, freq) \ 156 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ 157 SPI_MEM_OP_ADDR(3, addr, 1), \ 158 SPI_MEM_OP_DUMMY(ndummy, 1), \ 159 SPI_MEM_OP_DATA_IN(len, buf, 4), \ 160 SPI_MEM_OP_MAX_FREQ(freq)) 161 162 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_4D_OP(addr, ndummy, buf, len, freq) \ 163 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6d, 1), \ 164 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \ 165 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \ 166 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \ 167 SPI_MEM_OP_MAX_FREQ(freq)) 168 169 #define SPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(addr, ndummy, buf, len, freq) \ 170 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ 171 SPI_MEM_OP_ADDR(2, addr, 4), \ 172 SPI_MEM_OP_DUMMY(ndummy, 4), \ 173 SPI_MEM_OP_DATA_IN(len, buf, 4), \ 174 SPI_MEM_OP_MAX_FREQ(freq)) 175 176 #define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_4S_4S_OP(addr, ndummy, buf, len, freq) \ 177 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ 178 SPI_MEM_OP_ADDR(3, addr, 4), \ 179 SPI_MEM_OP_DUMMY(ndummy, 4), \ 180 SPI_MEM_OP_DATA_IN(len, buf, 4), \ 181 SPI_MEM_OP_MAX_FREQ(freq)) 182 183 #define SPINAND_PAGE_READ_FROM_CACHE_1S_4D_4D_OP(addr, ndummy, buf, len, freq) \ 184 SPI_MEM_OP(SPI_MEM_OP_CMD(0xed, 1), \ 185 SPI_MEM_DTR_OP_ADDR(2, addr, 4), \ 186 SPI_MEM_DTR_OP_DUMMY(ndummy, 4), \ 187 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \ 188 SPI_MEM_OP_MAX_FREQ(freq)) 189 190 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_8S_OP(addr, ndummy, buf, len, freq) \ 191 SPI_MEM_OP(SPI_MEM_OP_CMD(0x8b, 1), \ 192 SPI_MEM_OP_ADDR(2, addr, 1), \ 193 SPI_MEM_OP_DUMMY(ndummy, 1), \ 194 SPI_MEM_OP_DATA_IN(len, buf, 8), \ 195 SPI_MEM_OP_MAX_FREQ(freq)) 196 197 #define SPINAND_PAGE_READ_FROM_CACHE_1S_8S_8S_OP(addr, ndummy, buf, len, freq) \ 198 SPI_MEM_OP(SPI_MEM_OP_CMD(0xcb, 1), \ 199 SPI_MEM_OP_ADDR(2, addr, 8), \ 200 SPI_MEM_OP_DUMMY(ndummy, 8), \ 201 SPI_MEM_OP_DATA_IN(len, buf, 8), \ 202 SPI_MEM_OP_MAX_FREQ(freq)) 203 204 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_8D_OP(addr, ndummy, buf, len, freq) \ 205 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9d, 1), \ 206 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \ 207 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \ 208 SPI_MEM_DTR_OP_DATA_IN(len, buf, 8), \ 209 SPI_MEM_OP_MAX_FREQ(freq)) 210 211 #define SPINAND_PROG_EXEC_1S_1S_0_OP(addr) \ 212 SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \ 213 SPI_MEM_OP_ADDR(3, addr, 1), \ 214 SPI_MEM_OP_NO_DUMMY, \ 215 SPI_MEM_OP_NO_DATA) 216 217 #define SPINAND_PROG_LOAD_1S_1S_1S_OP(reset, addr, buf, len) \ 218 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1), \ 219 SPI_MEM_OP_ADDR(2, addr, 1), \ 220 SPI_MEM_OP_NO_DUMMY, \ 221 SPI_MEM_OP_DATA_OUT(len, buf, 1)) 222 223 #define SPINAND_PROG_LOAD_1S_1S_4S_OP(reset, addr, buf, len) \ 224 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \ 225 SPI_MEM_OP_ADDR(2, addr, 1), \ 226 SPI_MEM_OP_NO_DUMMY, \ 227 SPI_MEM_OP_DATA_OUT(len, buf, 4)) 228 229 #define SPINAND_PROG_LOAD_1S_1S_8S_OP(addr, buf, len) \ 230 SPI_MEM_OP(SPI_MEM_OP_CMD(0x82, 1), \ 231 SPI_MEM_OP_ADDR(2, addr, 1), \ 232 SPI_MEM_OP_NO_DUMMY, \ 233 SPI_MEM_OP_DATA_OUT(len, buf, 8)) 234 235 #define SPINAND_PROG_LOAD_1S_8S_8S_OP(reset, addr, buf, len) \ 236 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0xc2 : 0xc4, 1), \ 237 SPI_MEM_OP_ADDR(2, addr, 8), \ 238 SPI_MEM_OP_NO_DUMMY, \ 239 SPI_MEM_OP_DATA_OUT(len, buf, 8)) 240 241 /** 242 * Octal DDR SPI NAND flash operations 243 */ 244 245 #define SPINAND_RESET_8D_0_0_OP \ 246 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0xff, 8), \ 247 SPI_MEM_OP_NO_ADDR, \ 248 SPI_MEM_OP_NO_DUMMY, \ 249 SPI_MEM_OP_NO_DATA) 250 251 #define SPINAND_READID_8D_8D_8D_OP(naddr, ndummy, buf, len) \ 252 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x9f, 8), \ 253 SPI_MEM_DTR_OP_ADDR(naddr, 0, 8), \ 254 SPI_MEM_DTR_OP_DUMMY(ndummy, 8), \ 255 SPI_MEM_DTR_OP_DATA_IN(len, buf, 8)) 256 257 #define SPINAND_WR_EN_8D_0_0_OP \ 258 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x06, 8), \ 259 SPI_MEM_OP_NO_ADDR, \ 260 SPI_MEM_OP_NO_DUMMY, \ 261 SPI_MEM_OP_NO_DATA) 262 263 #define SPINAND_WR_DIS_8D_0_0_OP \ 264 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x04, 8), \ 265 SPI_MEM_OP_NO_ADDR, \ 266 SPI_MEM_OP_NO_DUMMY, \ 267 SPI_MEM_OP_NO_DATA) 268 269 #define SPINAND_SET_FEATURE_8D_8D_8D_OP(reg, valptr) \ 270 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x1f, 8), \ 271 SPI_MEM_DTR_OP_RPT_ADDR(reg, 8), \ 272 SPI_MEM_OP_NO_DUMMY, \ 273 SPI_MEM_DTR_OP_DATA_OUT(2, valptr, 8)) 274 275 #define SPINAND_GET_FEATURE_8D_8D_8D_OP(reg, valptr) \ 276 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x0f, 8), \ 277 SPI_MEM_DTR_OP_RPT_ADDR(reg, 8), \ 278 SPI_MEM_DTR_OP_DUMMY(14, 8), \ 279 SPI_MEM_DTR_OP_DATA_IN(2, valptr, 8)) 280 281 #define SPINAND_BLK_ERASE_8D_8D_0_OP(addr) \ 282 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0xd8, 8), \ 283 SPI_MEM_DTR_OP_ADDR(2, addr, 8), \ 284 SPI_MEM_OP_NO_DUMMY, \ 285 SPI_MEM_OP_NO_DATA) 286 287 #define SPINAND_PAGE_READ_8D_8D_0_OP(addr) \ 288 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x13, 8), \ 289 SPI_MEM_DTR_OP_ADDR(2, addr, 8), \ 290 SPI_MEM_OP_NO_DUMMY, \ 291 SPI_MEM_OP_NO_DATA) 292 293 #define SPINAND_PAGE_READ_PACKED_8D_8D_0_OP(addr) \ 294 SPI_MEM_OP(SPI_MEM_DTR_OP_PACKED_CMD(0x13, addr >> 16, 8), \ 295 SPI_MEM_DTR_OP_ADDR(2, addr & 0xffff, 8), \ 296 SPI_MEM_OP_NO_DUMMY, \ 297 SPI_MEM_OP_NO_DATA) 298 299 #define SPINAND_PAGE_READ_FROM_CACHE_8D_8D_8D_OP(addr, ndummy, buf, len, freq) \ 300 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x9d, 8), \ 301 SPI_MEM_DTR_OP_ADDR(2, addr, 8), \ 302 SPI_MEM_DTR_OP_DUMMY(ndummy, 8), \ 303 SPI_MEM_DTR_OP_DATA_IN(len, buf, 8), \ 304 SPI_MEM_OP_MAX_FREQ(freq)) 305 306 #define SPINAND_PROG_EXEC_8D_8D_0_OP(addr) \ 307 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x10, 8), \ 308 SPI_MEM_DTR_OP_ADDR(2, addr, 8), \ 309 SPI_MEM_OP_NO_DUMMY, \ 310 SPI_MEM_OP_NO_DATA) 311 312 #define SPINAND_PROG_LOAD_8D_8D_8D_OP(reset, addr, buf, len) \ 313 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD((reset ? 0xc2 : 0xc4), 8), \ 314 SPI_MEM_DTR_OP_ADDR(2, addr, 8), \ 315 SPI_MEM_OP_NO_DUMMY, \ 316 SPI_MEM_DTR_OP_DATA_OUT(len, buf, 8)) 317 318 /* feature register */ 319 #define REG_BLOCK_LOCK 0xa0 320 #define BL_ALL_UNLOCKED 0x00 321 322 /* configuration register */ 323 #define REG_CFG 0xb0 324 #define CFG_OTP_ENABLE BIT(6) 325 #define CFG_ECC_ENABLE BIT(4) 326 #define CFG_QUAD_ENABLE BIT(0) 327 328 /* status register */ 329 #define REG_STATUS 0xc0 330 #define STATUS_BUSY BIT(0) 331 #define STATUS_ERASE_FAILED BIT(2) 332 #define STATUS_PROG_FAILED BIT(3) 333 #define STATUS_ECC_MASK GENMASK(5, 4) 334 #define STATUS_ECC_NO_BITFLIPS (0 << 4) 335 #define STATUS_ECC_HAS_BITFLIPS (1 << 4) 336 #define STATUS_ECC_UNCOR_ERROR (2 << 4) 337 338 struct spinand_op; 339 struct spinand_device; 340 341 #define SPINAND_MAX_ID_LEN 6 342 /* 343 * For erase, write and read operation, we got the following timings : 344 * tBERS (erase) 1ms to 4ms 345 * tPROG 300us to 400us 346 * tREAD 25us to 100us 347 * In order to minimize latency, the min value is divided by 4 for the 348 * initial delay, and dividing by 20 for the poll delay. 349 * For reset, 5us/10us/500us if the device is respectively 350 * reading/programming/erasing when the RESET occurs. Since we always 351 * issue a RESET when the device is IDLE, 5us is selected for both initial 352 * and poll delay. 353 */ 354 #define SPINAND_READ_INITIAL_DELAY_US 6 355 #define SPINAND_READ_POLL_DELAY_US 5 356 #define SPINAND_RESET_INITIAL_DELAY_US 5 357 #define SPINAND_RESET_POLL_DELAY_US 5 358 #define SPINAND_WRITE_INITIAL_DELAY_US 75 359 #define SPINAND_WRITE_POLL_DELAY_US 15 360 #define SPINAND_ERASE_INITIAL_DELAY_US 250 361 #define SPINAND_ERASE_POLL_DELAY_US 50 362 363 #define SPINAND_WAITRDY_TIMEOUT_MS 400 364 365 /** 366 * struct spinand_id - SPI NAND id structure 367 * @data: buffer containing the id bytes. Currently 6 bytes large, but can 368 * be extended if required 369 * @len: ID length 370 */ 371 struct spinand_id { 372 u8 data[SPINAND_MAX_ID_LEN]; 373 int len; 374 }; 375 376 enum spinand_readid_method { 377 SPINAND_READID_METHOD_OPCODE, 378 SPINAND_READID_METHOD_OPCODE_ADDR, 379 SPINAND_READID_METHOD_OPCODE_DUMMY, 380 }; 381 382 /** 383 * struct spinand_devid - SPI NAND device id structure 384 * @id: device id of current chip 385 * @len: number of bytes in device id 386 * @method: method to read chip id 387 * There are 3 possible variants: 388 * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately 389 * after read_id opcode. 390 * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after 391 * read_id opcode + 1-byte address. 392 * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after 393 * read_id opcode + 1 dummy byte. 394 */ 395 struct spinand_devid { 396 const u8 *id; 397 const u8 len; 398 const enum spinand_readid_method method; 399 }; 400 401 /** 402 * struct manufacurer_ops - SPI NAND manufacturer specific operations 403 * @init: initialize a SPI NAND device 404 * @cleanup: cleanup a SPI NAND device 405 * 406 * Each SPI NAND manufacturer driver should implement this interface so that 407 * NAND chips coming from this vendor can be initialized properly. 408 */ 409 struct spinand_manufacturer_ops { 410 int (*init)(struct spinand_device *spinand); 411 void (*cleanup)(struct spinand_device *spinand); 412 }; 413 414 /** 415 * struct spinand_manufacturer - SPI NAND manufacturer instance 416 * @id: manufacturer ID 417 * @name: manufacturer name 418 * @devid_len: number of bytes in device ID 419 * @chips: supported SPI NANDs under current manufacturer 420 * @nchips: number of SPI NANDs available in chips array 421 * @ops: manufacturer operations 422 */ 423 struct spinand_manufacturer { 424 u8 id; 425 char *name; 426 const struct spinand_info *chips; 427 const size_t nchips; 428 const struct spinand_manufacturer_ops *ops; 429 }; 430 431 /* SPI NAND manufacturers */ 432 extern const struct spinand_manufacturer alliancememory_spinand_manufacturer; 433 extern const struct spinand_manufacturer ato_spinand_manufacturer; 434 extern const struct spinand_manufacturer dosilicon_spinand_manufacturer; 435 extern const struct spinand_manufacturer esmt_8c_spinand_manufacturer; 436 extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; 437 extern const struct spinand_manufacturer fmsh_spinand_manufacturer; 438 extern const struct spinand_manufacturer foresee_spinand_manufacturer; 439 extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; 440 extern const struct spinand_manufacturer macronix_spinand_manufacturer; 441 extern const struct spinand_manufacturer micron_spinand_manufacturer; 442 extern const struct spinand_manufacturer paragon_spinand_manufacturer; 443 extern const struct spinand_manufacturer skyhigh_spinand_manufacturer; 444 extern const struct spinand_manufacturer toshiba_spinand_manufacturer; 445 extern const struct spinand_manufacturer winbond_spinand_manufacturer; 446 extern const struct spinand_manufacturer xtx_spinand_manufacturer; 447 448 /** 449 * struct spinand_op_variants - SPI NAND operation variants 450 * @ops: the list of variants for a given operation 451 * @nops: the number of variants 452 * 453 * Some operations like read-from-cache/write-to-cache have several variants 454 * depending on the number of IO lines you use to transfer data or address 455 * cycles. This structure is a way to describe the different variants supported 456 * by a chip and let the core pick the best one based on the SPI mem controller 457 * capabilities. 458 */ 459 struct spinand_op_variants { 460 const struct spi_mem_op *ops; 461 unsigned int nops; 462 }; 463 464 #define SPINAND_OP_VARIANTS(name, ...) \ 465 const struct spinand_op_variants name = { \ 466 .ops = (struct spi_mem_op[]) { __VA_ARGS__ }, \ 467 .nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) / \ 468 sizeof(struct spi_mem_op), \ 469 } 470 471 /** 472 * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND 473 * chip 474 * @get_status: get the ECC status. Should return a positive number encoding 475 * the number of corrected bitflips if correction was possible or 476 * -EBADMSG if there are uncorrectable errors. I can also return 477 * other negative error codes if the error is not caused by 478 * uncorrectable bitflips 479 * @ooblayout: the OOB layout used by the on-die ECC implementation 480 */ 481 struct spinand_ecc_info { 482 int (*get_status)(struct spinand_device *spinand, u8 status); 483 const struct mtd_ooblayout_ops *ooblayout; 484 }; 485 486 /* SPI NAND flags */ 487 #define SPINAND_HAS_QE_BIT BIT(0) 488 #define SPINAND_HAS_CR_FEAT_BIT BIT(1) 489 #define SPINAND_HAS_PROG_PLANE_SELECT_BIT BIT(2) 490 #define SPINAND_HAS_READ_PLANE_SELECT_BIT BIT(3) 491 #define SPINAND_NO_RAW_ACCESS BIT(4) 492 #define SPINAND_ODTR_PACKED_PAGE_READ BIT(5) 493 494 /** 495 * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure 496 * @status: status of the last wait operation that will be used in case 497 * ->get_status() is not populated by the spinand device. 498 */ 499 struct spinand_ondie_ecc_conf { 500 u8 status; 501 }; 502 503 /** 504 * struct spinand_otp_layout - structure to describe the SPI NAND OTP area 505 * @npages: number of pages in the OTP 506 * @start_page: start page of the user/factory OTP area. 507 */ 508 struct spinand_otp_layout { 509 unsigned int npages; 510 unsigned int start_page; 511 }; 512 513 /** 514 * struct spinand_fact_otp_ops - SPI NAND OTP methods for factory area 515 * @info: get the OTP area information 516 * @read: read from the SPI NAND OTP area 517 */ 518 struct spinand_fact_otp_ops { 519 int (*info)(struct spinand_device *spinand, size_t len, 520 struct otp_info *buf, size_t *retlen); 521 int (*read)(struct spinand_device *spinand, loff_t from, size_t len, 522 size_t *retlen, u8 *buf); 523 }; 524 525 /** 526 * struct spinand_user_otp_ops - SPI NAND OTP methods for user area 527 * @info: get the OTP area information 528 * @lock: lock an OTP region 529 * @erase: erase an OTP region 530 * @read: read from the SPI NAND OTP area 531 * @write: write to the SPI NAND OTP area 532 */ 533 struct spinand_user_otp_ops { 534 int (*info)(struct spinand_device *spinand, size_t len, 535 struct otp_info *buf, size_t *retlen); 536 int (*lock)(struct spinand_device *spinand, loff_t from, size_t len); 537 int (*erase)(struct spinand_device *spinand, loff_t from, size_t len); 538 int (*read)(struct spinand_device *spinand, loff_t from, size_t len, 539 size_t *retlen, u8 *buf); 540 int (*write)(struct spinand_device *spinand, loff_t from, size_t len, 541 size_t *retlen, const u8 *buf); 542 }; 543 544 /** 545 * struct spinand_fact_otp - SPI NAND OTP grouping structure for factory area 546 * @layout: OTP region layout 547 * @ops: OTP access ops 548 */ 549 struct spinand_fact_otp { 550 const struct spinand_otp_layout layout; 551 const struct spinand_fact_otp_ops *ops; 552 }; 553 554 /** 555 * struct spinand_user_otp - SPI NAND OTP grouping structure for user area 556 * @layout: OTP region layout 557 * @ops: OTP access ops 558 */ 559 struct spinand_user_otp { 560 const struct spinand_otp_layout layout; 561 const struct spinand_user_otp_ops *ops; 562 }; 563 564 /** 565 * enum spinand_bus_interface - SPI NAND bus interface types 566 * @SSDR: Bus configuration supporting all 1S-XX-XX operations, including dual and quad 567 * @ODTR: Bus configuration supporting only 8D-8D-8D operations 568 */ 569 enum spinand_bus_interface { 570 SSDR, 571 ODTR, 572 }; 573 574 /** 575 * struct spinand_info - Structure used to describe SPI NAND chips 576 * @model: model name 577 * @devid: device ID 578 * @flags: OR-ing of the SPINAND_XXX flags 579 * @memorg: memory organization 580 * @eccreq: ECC requirements 581 * @eccinfo: on-die ECC info 582 * @op_variants: operations variants 583 * @op_variants.read_cache: variants of the read-cache operation 584 * @op_variants.write_cache: variants of the write-cache operation 585 * @op_variants.update_cache: variants of the update-cache operation 586 * @vendor_ops: vendor specific operations 587 * @select_target: function used to select a target/die. Required only for 588 * multi-die chips 589 * @configure_chip: Align the chip configuration with the core settings 590 * @set_cont_read: enable/disable continuous cached reads 591 * @fact_otp: SPI NAND factory OTP info. 592 * @user_otp: SPI NAND user OTP info. 593 * @read_retries: the number of read retry modes supported 594 * @set_read_retry: enable/disable read retry for data recovery 595 * 596 * Each SPI NAND manufacturer driver should have a spinand_info table 597 * describing all the chips supported by the driver. 598 */ 599 struct spinand_info { 600 const char *model; 601 struct spinand_devid devid; 602 u32 flags; 603 struct nand_memory_organization memorg; 604 struct nand_ecc_props eccreq; 605 struct spinand_ecc_info eccinfo; 606 struct { 607 const struct spinand_op_variants *read_cache; 608 const struct spinand_op_variants *write_cache; 609 const struct spinand_op_variants *update_cache; 610 } op_variants; 611 const struct spinand_op_variants *vendor_ops; 612 int (*select_target)(struct spinand_device *spinand, 613 unsigned int target); 614 int (*configure_chip)(struct spinand_device *spinand, 615 enum spinand_bus_interface iface); 616 int (*set_cont_read)(struct spinand_device *spinand, 617 bool enable); 618 struct spinand_fact_otp fact_otp; 619 struct spinand_user_otp user_otp; 620 unsigned int read_retries; 621 int (*set_read_retry)(struct spinand_device *spinand, 622 unsigned int read_retry); 623 }; 624 625 #define SPINAND_ID(__method, ...) \ 626 { \ 627 .id = (const u8[]){ __VA_ARGS__ }, \ 628 .len = sizeof((u8[]){ __VA_ARGS__ }), \ 629 .method = __method, \ 630 } 631 632 #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \ 633 { \ 634 .read_cache = __read, \ 635 .write_cache = __write, \ 636 .update_cache = __update, \ 637 } 638 639 #define SPINAND_INFO_VENDOR_OPS(__ops) \ 640 .vendor_ops = __ops 641 642 #define SPINAND_ECCINFO(__ooblayout, __get_status) \ 643 .eccinfo = { \ 644 .ooblayout = __ooblayout, \ 645 .get_status = __get_status, \ 646 } 647 648 #define SPINAND_SELECT_TARGET(__func) \ 649 .select_target = __func 650 651 #define SPINAND_CONFIGURE_CHIP(__configure_chip) \ 652 .configure_chip = __configure_chip 653 654 #define SPINAND_CONT_READ(__set_cont_read) \ 655 .set_cont_read = __set_cont_read 656 657 #define SPINAND_FACT_OTP_INFO(__npages, __start_page, __ops) \ 658 .fact_otp = { \ 659 .layout = { \ 660 .npages = __npages, \ 661 .start_page = __start_page, \ 662 }, \ 663 .ops = __ops, \ 664 } 665 666 #define SPINAND_USER_OTP_INFO(__npages, __start_page, __ops) \ 667 .user_otp = { \ 668 .layout = { \ 669 .npages = __npages, \ 670 .start_page = __start_page, \ 671 }, \ 672 .ops = __ops, \ 673 } 674 675 #define SPINAND_READ_RETRY(__read_retries, __set_read_retry) \ 676 .read_retries = __read_retries, \ 677 .set_read_retry = __set_read_retry 678 679 #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \ 680 __flags, ...) \ 681 { \ 682 .model = __model, \ 683 .devid = __id, \ 684 .memorg = __memorg, \ 685 .eccreq = __eccreq, \ 686 .op_variants = __op_variants, \ 687 .flags = __flags, \ 688 __VA_ARGS__ \ 689 } 690 691 struct spinand_dirmap { 692 struct spi_mem_dirmap_desc *wdesc; 693 struct spi_mem_dirmap_desc *rdesc; 694 }; 695 696 /** 697 * struct spinand_mem_ops - SPI NAND memory operations 698 * @reset: reset op template 699 * @readid: read ID op template 700 * @wr_en: write enable op template 701 * @wr_dis: write disable op template 702 * @set_feature: set feature op template 703 * @get_feature: get feature op template 704 * @blk_erase: blk erase op template 705 * @page_read: page read op template 706 * @prog_exec: prog exec op template 707 * @read_cache: read cache op template 708 * @write_cache: write cache op template 709 * @update_cache: update cache op template 710 */ 711 struct spinand_mem_ops { 712 struct spi_mem_op reset; 713 struct spi_mem_op readid; 714 struct spi_mem_op wr_en; 715 struct spi_mem_op wr_dis; 716 struct spi_mem_op set_feature; 717 struct spi_mem_op get_feature; 718 struct spi_mem_op blk_erase; 719 struct spi_mem_op page_read; 720 struct spi_mem_op prog_exec; 721 const struct spi_mem_op *read_cache; 722 const struct spi_mem_op *write_cache; 723 const struct spi_mem_op *update_cache; 724 }; 725 726 /** 727 * struct spinand_device - SPI NAND device instance 728 * @base: NAND device instance 729 * @spimem: pointer to the SPI mem object 730 * @lock: lock used to serialize accesses to the NAND 731 * @id: NAND ID as returned by READ_ID 732 * @flags: NAND flags 733 * @ssdr_op_templates: Templates for all single SDR SPI mem operations 734 * @odtr_op_templates: Templates for all octal DTR SPI mem operations 735 * @op_templates: Templates for all SPI mem operations 736 * @bus_iface: Current bus interface 737 * @select_target: select a specific target/die. Usually called before sending 738 * a command addressing a page or an eraseblock embedded in 739 * this die. Only required if your chip exposes several dies 740 * @cur_target: currently selected target/die 741 * @eccinfo: on-die ECC information 742 * @cfg_cache: config register cache. One entry per die 743 * @databuf: bounce buffer for data 744 * @oobbuf: bounce buffer for OOB data 745 * @scratchbuf: buffer used for everything but page accesses. This is needed 746 * because the spi-mem interface explicitly requests that buffers 747 * passed in spi_mem_op be DMA-able, so we can't based the bufs on 748 * the stack 749 * @manufacturer: SPI NAND manufacturer information 750 * @configure_chip: Align the chip configuration with the core settings 751 * @cont_read_possible: Field filled by the core once the whole system 752 * configuration is known to tell whether continuous reads are 753 * suitable to use or not in general with this chip/configuration. 754 * A per-transfer check must of course be done to ensure it is 755 * actually relevant to enable this feature. 756 * @set_cont_read: Enable/disable the continuous read feature 757 * @priv: manufacturer private data 758 * @fact_otp: SPI NAND factory OTP info. 759 * @user_otp: SPI NAND user OTP info. 760 * @read_retries: the number of read retry modes supported 761 * @set_read_retry: Enable/disable the read retry feature 762 */ 763 struct spinand_device { 764 struct nand_device base; 765 struct spi_mem *spimem; 766 struct mutex lock; 767 struct spinand_id id; 768 u32 flags; 769 770 struct spinand_mem_ops ssdr_op_templates; 771 struct spinand_mem_ops odtr_op_templates; 772 struct spinand_mem_ops *op_templates; 773 enum spinand_bus_interface bus_iface; 774 775 struct spinand_dirmap *dirmaps; 776 777 int (*select_target)(struct spinand_device *spinand, 778 unsigned int target); 779 unsigned int cur_target; 780 781 struct spinand_ecc_info eccinfo; 782 783 u8 *cfg_cache; 784 u8 *databuf; 785 u8 *oobbuf; 786 u8 *scratchbuf; 787 const struct spinand_manufacturer *manufacturer; 788 void *priv; 789 790 int (*configure_chip)(struct spinand_device *spinand, 791 enum spinand_bus_interface iface); 792 bool cont_read_possible; 793 int (*set_cont_read)(struct spinand_device *spinand, 794 bool enable); 795 796 const struct spinand_fact_otp *fact_otp; 797 const struct spinand_user_otp *user_otp; 798 799 unsigned int read_retries; 800 int (*set_read_retry)(struct spinand_device *spinand, 801 unsigned int retry_mode); 802 }; 803 804 struct spi_mem_op spinand_fill_wr_en_op(struct spinand_device *spinand); 805 struct spi_mem_op spinand_fill_set_feature_op(struct spinand_device *spinand, u64 reg, const void *valptr); 806 struct spi_mem_op spinand_fill_get_feature_op(struct spinand_device *spinand, u64 reg, void *valptr); 807 struct spi_mem_op spinand_fill_prog_exec_op(struct spinand_device *spinand, u64 addr); 808 809 #define SPINAND_OP(spinand, op_name, ...) \ 810 spinand_fill_ ## op_name ## _op(spinand, ##__VA_ARGS__) 811 812 /** 813 * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance 814 * @mtd: MTD instance 815 * 816 * Return: the SPI NAND device attached to @mtd. 817 */ 818 static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd) 819 { 820 return container_of(mtd_to_nanddev(mtd), struct spinand_device, base); 821 } 822 823 /** 824 * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device 825 * @spinand: SPI NAND device 826 * 827 * Return: the MTD device embedded in @spinand. 828 */ 829 static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand) 830 { 831 return nanddev_to_mtd(&spinand->base); 832 } 833 834 /** 835 * nand_to_spinand() - Get the SPI NAND device embedding an NAND object 836 * @nand: NAND object 837 * 838 * Return: the SPI NAND device embedding @nand. 839 */ 840 static inline struct spinand_device *nand_to_spinand(struct nand_device *nand) 841 { 842 return container_of(nand, struct spinand_device, base); 843 } 844 845 /** 846 * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object 847 * @spinand: SPI NAND device 848 * 849 * Return: the NAND device embedded in @spinand. 850 */ 851 static inline struct nand_device * 852 spinand_to_nand(struct spinand_device *spinand) 853 { 854 return &spinand->base; 855 } 856 857 /** 858 * spinand_set_of_node - Attach a DT node to a SPI NAND device 859 * @spinand: SPI NAND device 860 * @np: DT node 861 * 862 * Attach a DT node to a SPI NAND device. 863 */ 864 static inline void spinand_set_of_node(struct spinand_device *spinand, 865 struct device_node *np) 866 { 867 nanddev_set_of_node(&spinand->base, np); 868 } 869 870 bool spinand_op_is_odtr(const struct spi_mem_op *op); 871 872 int spinand_match_and_init(struct spinand_device *spinand, 873 const struct spinand_info *table, 874 unsigned int table_size, 875 enum spinand_readid_method rdid_method); 876 877 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val); 878 int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val); 879 int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val); 880 int spinand_write_enable_op(struct spinand_device *spinand); 881 int spinand_select_target(struct spinand_device *spinand, unsigned int target); 882 883 int spinand_wait(struct spinand_device *spinand, unsigned long initial_delay_us, 884 unsigned long poll_delay_us, u8 *s); 885 886 int spinand_read_page(struct spinand_device *spinand, 887 const struct nand_page_io_req *req); 888 889 int spinand_write_page(struct spinand_device *spinand, 890 const struct nand_page_io_req *req); 891 892 size_t spinand_otp_page_size(struct spinand_device *spinand); 893 size_t spinand_fact_otp_size(struct spinand_device *spinand); 894 size_t spinand_user_otp_size(struct spinand_device *spinand); 895 896 int spinand_fact_otp_read(struct spinand_device *spinand, loff_t ofs, 897 size_t len, size_t *retlen, u8 *buf); 898 int spinand_user_otp_read(struct spinand_device *spinand, loff_t ofs, 899 size_t len, size_t *retlen, u8 *buf); 900 int spinand_user_otp_write(struct spinand_device *spinand, loff_t ofs, 901 size_t len, size_t *retlen, const u8 *buf); 902 903 int spinand_set_mtd_otp_ops(struct spinand_device *spinand); 904 905 #endif /* __LINUX_MTD_SPINAND_H */ 906