xref: /illumos-gate/usr/src/lib/libjedec/common/spd_ddr3.h (revision 8119dad84d6416f13557b0ba8e2aaf9064cbcfd3)
1 /*
2  * This file and its contents are supplied under the terms of the
3  * Common Development and Distribution License ("CDDL"), version 1.0.
4  * You may only use this file in accordance with the terms of version
5  * 1.0 of the CDDL.
6  *
7  * A full copy of the text of the CDDL should have accompanied this
8  * source.  A copy of the CDDL is also available via the Internet at
9  * http://www.illumos.org/license/CDDL.
10  */
11 
12 /*
13  * Copyright 2024 Oxide Computer Company
14  */
15 
16 #ifndef _SPD_DDR3_H
17 #define	_SPD_DDR3_H
18 
19 /*
20  * Definitions for use in DDR3 Serial Presence Decoding
21  * based on JEDEC Standard 21-C Section Annex K: Serial Presence Detect
22  * (SPD) for DDR3 SDRAM Modules Release 6.
23  *
24  * DDR3 modules are organized in a 256 byte memory map:
25  *
26  *   o Base Configuration and DRAM parameters (bytes 0x00-0x3b)
27  *   o Standard Module Parameters (bytes 0x40-0x74) these vary on whether
28  *     something is considered an RDIMM, UDIMM, etc.
29  *   o Manufacturing Information (bytes 0x75-0xaf)
30  *   o End User Programmable data (0xb0-0xff).
31  */
32 
33 #include <sys/bitext.h>
34 #include "spd_common.h"
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
40 /*
41  * Number of Bytes Used / Number of Bytes in SPD Device / CRC Coverage
42  */
43 #define	SPD_DDR3_NBYTES		0x00
44 #define	SPD_DDR3_NBYTES_CRC(r)		bitx8(r, 7, 7)
45 #define	SPD_DDR3_NBYTES_CRC_125		0
46 #define	SPD_DDR3_NBYTES_CRC_116		1
47 #define	SPD_DDR3_NBYTES_TOTAL(r)	bitx8(r, 6, 4)
48 #define	SPD_DDR3_NBYTES_TOTAL_UNDEF	0
49 #define	SPD_DDR3_NBYTES_TOTAL_256	1
50 #define	SPD_DDR3_NBYTES_USED(r)		bitx8(r, 3, 0)
51 #define	SPD_DDR3_NBYTES_USED_UNDEF	0
52 #define	SPD_DDR3_NBYTES_USED_128	1
53 #define	SPD_DDR3_NBYTES_USED_176	2
54 #define	SPD_DDR3_NBYTES_USED_256	3
55 
56 /*
57  * SPD Revision. This is the same as described in SPD_DDR4_SPD_REV as
58  * defined in spd_ddr4.h.
59  */
60 #define	SPD_DDR3_SPD_REV	0x01
61 #define	SPD_DDR3_SPD_REV_ENC(r)	bitx8(r, 7, 4)
62 #define	SPD_DDR3_SPD_REV_ADD(r)	bitx8(r, 3, 0)
63 #define	SPD_DDR3_SPD_REV_V1	1
64 
65 /*
66  * Key Byte / DRAM Device Type. This field identifies the type of DDR device and
67  * is actually consistent across all SPD versions. Known values are in the
68  * spd_dram_type_t enumeration.
69  */
70 #define	SPD_DDR3_DRAM_TYPE	0x02
71 
72 /*
73  * Key Byte / Module Type. This is used to describe what kind of DDR module it
74  * is, which tells us what the module-specific section contents are. These bits,
75  * unlike the one above are device specific.
76  */
77 #define	SPD_DDR3_MOD_TYPE	0x03
78 #define	SPD_DDR3_MOD_TYPE_TYPE(r)	bitx8(r, 3, 0)
79 #define	SPD_DDR3_MOD_TYPE_TYPE_UNDEF		0
80 #define	SPD_DDR3_MOD_TYPE_TYPE_RDIMM		1
81 #define	SPD_DDR3_MOD_TYPE_TYPE_UDIMM		2
82 #define	SPD_DDR3_MOD_TYPE_TYPE_SODIMM		3
83 #define	SPD_DDR3_MOD_TYPE_TYPE_MICRO_DIMM	4
84 #define	SPD_DDR3_MOD_TYPE_TYPE_MINI_RDIMM	5
85 #define	SPD_DDR3_MOD_TYPE_TYPE_MINI_UDIMM	6
86 #define	SPD_DDR3_MOD_TYPE_TYPE_MINI_CDIMM	7
87 #define	SPD_DDR3_MOD_TYPE_TYPE_72b_SORDIMM	8
88 #define	SPD_DDR3_MOD_TYPE_TYPE_72b_SOUDIMM	9
89 #define	SPD_DDR3_MOD_TYPE_TYPE_72b_SOCDIMM	10
90 #define	SPD_DDR3_MOD_TYPE_TYPE_LRDIMM		11
91 #define	SPD_DDR3_MOD_TYPE_TYPE_16b_SODIMM	12
92 #define	SPD_DDR3_MOD_TYPE_TYPE_32b_SODIMM	13
93 
94 /*
95  * SDRAM Density and Banks
96  */
97 #define	SPD_DDR3_DENSITY	0x04
98 #define	SPD_DDR3_DENSITY_NBA_BITS(r)	bitx8(r, 6, 4)
99 #define	SPD_DDR3_DENSITY_NBA_BITS_BASE	3
100 #define	SPD_DDR3_DENSITY_NBA_BITS_MAX	6
101 #define	SPD_DDR3_DENSITY_DENSITY(r)	bitx8(r, 3, 0)
102 #define	SPD_DDR3_DENSITY_DENSITY_256Mb	0
103 #define	SPD_DDR3_DENSITY_DENSITY_512Mb	1
104 #define	SPD_DDR3_DENSITY_DENSITY_1Gb	2
105 #define	SPD_DDR3_DENSITY_DENSITY_2Gb	3
106 #define	SPD_DDR3_DENSITY_DENSITY_4Gb	4
107 #define	SPD_DDR3_DENSITY_DENSITY_8Gb	5
108 #define	SPD_DDR3_DENSITY_DENSITY_16Gb	6
109 #define	SPD_DDR3_DENSITY_DENSITY_32Gb	7
110 #define	SPD_DDR3_DENSITY_DENSITY_12Gb	8
111 #define	SPD_DDR3_DENSITY_DENSITY_24Gb	9
112 
113 /*
114  * SDRAM Addressing.
115  */
116 #define	SPD_DDR3_ADDR		0x05
117 #define	SPD_DDR3_ADDR_NROWS(r)		bitx8(r, 5, 3)
118 #define	SPD_DDR3_ADDR_NROWS_BASE	12
119 #define	SPD_DDR3_ADDR_NROWS_MAX		16
120 #define	SPD_DDR3_ADDR_NCOLS(r)		bitx8(r, 2, 0)
121 #define	SPD_DDR3_ADDR_NCOLS_BASE	9
122 #define	SPD_DDR3_ADDR_NCOLS_MAX		12
123 
124 /*
125  * Module Nominal Voltage, VDD
126  */
127 #define	SPD_DDR3_VOLT		0x06
128 #define	SPD_DDR3_VOLT_V1P25_OPER(r)	bitx8(r, 2, 2)
129 #define	SPD_DDR3_VOLT_V1P35_OPER(r)	bitx8(r, 1, 1)
130 #define	SPD_DDR3_VOLT_V1P5_OPER(r)	bitx8(r, 0, 0)
131 
132 /*
133  * Module Organization
134  */
135 #define	SPD_DDR3_MOD_ORG	0x07
136 #define	SPD_DDR3_MOD_ORG_NRANKS(r)	bitx(r, 5, 3)
137 #define	SPD_DDR3_MOD_ORG_NRANKS_1	0
138 #define	SPD_DDR3_MOD_ORG_NRANKS_2	1
139 #define	SPD_DDR3_MOD_ORG_NRANKS_3	2
140 #define	SPD_DDR3_MOD_ORG_NRANKS_4	3
141 #define	SPD_DDR3_MOD_ORG_NRANKS_8	4
142 #define	SPD_DDR4_MOD_ORG_WIDTH(r)	bitx8(r, 2, 0)
143 #define	SPD_DDR3_MOD_ORG_WIDTH_BASE	2
144 #define	SPD_DDR3_MOD_ORG_WIDTH_MAX	32
145 
146 /*
147  * Module Memory Bus Width
148  */
149 #define	SPD_DDR3_BUS_WIDTH	0x08
150 #define	SPD_DDR3_BUS_WIDTH_EXT(r)	bitx8(r, 4, 3)
151 #define	SPD_DDR3_BUS_WIDTH_EXT_NONE	0
152 #define	SPD_DDR3_BUS_WIDTH_EXT_8b	1
153 #define	SPD_DDR3_BUS_WIDTH_PRI(r)	bitx8(r, 2, 0)
154 #define	SPD_DDR3_BUS_WIDTH_PRI_BASE	3
155 #define	SPD_DDR3_BUS_WIDTH_PRI_MAX	64
156 
157 /*
158  * Fine Timebase (FTB) Dividend / Divisor. While LPDDR3+ and DDR4+ use fixed
159  * timebases, DDR3 does not and the fine time base is defined as a divisor and
160  * dividend.
161  */
162 #define	SPD_DDR3_FTB		0x09
163 #define	SPD_DDR3_FTB_DIVIDEND(r)	bitx8(r, 7, 4)
164 #define	SPD_DDR3_FTB_DIVISOR(r)		bitx8(r, 3, 0)
165 #define	SPD_DDR3_FTB_PS		1
166 
167 /*
168  * Medium Timebase (MTB) Dividend and Divisor. Like the FTB, this is split into
169  * two different values. DDR3 only defines a single valid MTB value, a dividend
170  * of 1 and a divisor of 8 meaning that the MTB is 125 ps.
171  */
172 #define	SPD_DDR3_MTB_DIVIDEND	0x0a
173 #define	SPD_DDR3_MTB_DIVISOR	0x0b
174 #define	SPD_DDR3_MTB_PS		125
175 #define	SPD_DDR3_MTB_125PS_DIVIDEND	1
176 #define	SPD_DDR3_MTB_125PS_DIVISOR	8
177 
178 /*
179  * SDRAM Minimum Cycle Time t~CK~min. This is only in units of MTB.
180  * Fine offset for ^
181  */
182 #define	SPD_DDR3_TCK_MIN	0x0c
183 #define	SPD_DDR3_TCK_MIN_FINE	0x22
184 
185 /*
186  * Supported CAS Latencies. There are two bytes that are used to get at what
187  * speeds are supported. This starts at CL4 and goes up by 1 each time.
188  */
189 #define	SPD_DDR3_CAS_SUP0	0x0e
190 #define	SPD_DDR3_CAS_SUP1	0x0f
191 #define	SPD_DDR3_CAS_BASE	0x04
192 
193 /*
194  * Minimum CAS Latency Time t~AA~min.
195  * Fine Offset for ^
196  */
197 #define	SPD_DDR3_TAA_MIN	0x10
198 #define	SPD_DDR3_TAA_MIN_FINE	0x23
199 
200 /*
201  * Minimum Write Recovery Time t~WR~min.
202  */
203 #define	SPD_DDR3_TWR_MIN	0x11
204 
205 /*
206  * Minimum RAS to CAS Delay Time t~RCD~min.
207  * Fine Offset for ^
208  */
209 #define	SPD_DDR3_TRCD_MIN	0x12
210 #define	SPD_DDR3_TRCD_MIN_FINE	0x24
211 
212 /*
213  * Minimum Row Active to Row Active Delay Time t~RRD~min
214  */
215 #define	SPD_DDR3_TRRD_MIN	0x13
216 
217 /*
218  * Minimum Row Precharge Delay Time t~RP~min.
219  * Fine Offset for ^
220  */
221 #define	SPD_DDR3_TRP_MIN	0x14
222 #define	SPD_DDR3_TRP_MIN_FINE	0x25
223 
224 /*
225  * Upper Nibbles for t~RAS~min and t~RC~min. These are bits 11:9 of
226  * these values. The lower byte is in subsequent values.
227  * Minimum Active to Precharge Delay Time t~RAS~min.
228  * Minimum Active to Active/Refresh Delay Time t~RC~min.
229  * Fine Offset for ^
230  */
231 #define	SPD_DDR3_RAS_RC_UPPER	0x15
232 #define	SPD_DDR3_RAS_RC_UPPER_RC(r)	bitx8(r, 7, 4)
233 #define	SPD_DDR3_RAS_RC_UPPER_RAS(r)	bitx8(r, 3, 0)
234 #define	SPD_DDR3_TRAS_MIN	0x16
235 #define	SPD_DDR3_TRC_MIN	0x17
236 #define	SPD_DDR3_TRC_MIN_FINE	0x26
237 
238 /*
239  * Minimum Refresh Recovery Delay Time t~RFC~min. This value is split into two
240  * bytes of MTB.
241  */
242 #define	SPD_DDR3_TRFC_MIN_LSB	0x18
243 #define	SPD_DDR3_TRFC_MIN_MSB	0x19
244 
245 /*
246  * Minimum Internal Write to Read Command Delay t~WTR~min.
247  */
248 #define	SPD_DDR3_TWTR_MIN	0x1a
249 
250 /*
251  * Minimum Internal Read to Precharge Command Delay Time t~RTP~min.
252  */
253 #define	SPD_DDR3_TRTP_MIN	0x1b
254 
255 /*
256  * Upper Nibble for t~FAW~
257  * Minimum Four Activate Window Delay Time t~FAW~min
258  */
259 #define	SPD_DDR3_TFAW_NIB	0x1c
260 #define	SPD_DDR3_TFAB_NIB_UPPER_TFAW(r)	bitx8(r, 3, 0)
261 #define	SPD_DDR3_TFAW_LSB	0x1d
262 
263 /*
264  * SDRAM Optional Features
265  */
266 #define	SPD_DDR3_OPT_FEAT	0x1e
267 #define	SPD_DDR3_OPT_FEAT_DLLO(r)	bitx8(r, 7, 7)
268 #define	SPD_DDR3_OPT_FEAT_RZQ7(r)	bitx8(r, 1, 1)
269 #define	SPD_DDR3_OPT_FEAT_RZQ6(r)	bitx8(r, 0, 0)
270 
271 /*
272  * SDRAM Thermal and Refresh Options
273  */
274 #define	SPD_DDR3_REFRESH		0x1f
275 #define	SPD_DDR3_REFRESH_PASR_SUP(r)	bitx8(r, 7, 7)
276 #define	SPD_DDR3_REFRESH_ODTS_SUP(r)	bitx8(r, 3, 3)
277 #define	SPD_DDR3_REFRESH_ASR_SUP(r)	bitx8(r, 2, 2)
278 #define	SPD_DDR3_REFRESH_ETR_REF(r)	bitx8(r, 1, 1)
279 #define	SPD_DDR3_REFRESH_ETR_REF_2X	0
280 #define	SPD_DDR3_REFRESH_ETR_REF_1X	1
281 #define	SPD_DDR3_REFRESH_ETR_TEMP(r)	bitx8(r, 0, 0)
282 #define	SPD_DDR3_REFRESH_ETR_TEMP_85C	0
283 #define	SPD_DDR3_REFRESH_ETR_TEMP_95C	1
284 
285 /*
286  * Module Thermal Sensor. If present, this complies with TSE2002. The remaining
287  * bits here are used for thermal sensor accuracy and all values are undefined.
288  */
289 #define	SPD_DDR3_MOD_THERM	0x20
290 #define	SPD_DDR3_MOD_THERM_PRES(r)	bitx8(r, 7, 7)
291 
292 /*
293  * SDRAM Device Type
294  */
295 #define	SPD_DDR3_TYPE		0x21
296 #define	SPD_DDR3_PKG_TYPE(r)		bitx8(r, 7, 7)
297 #define	SPD_DDR3_PKG_TYPE_MONO		0
298 #define	SPD_DDR3_PKG_TYPE_NOT		1
299 #define	SPD_DDR3_PKG_DIE_CNT(r)		bitx8(r, 6, 4)
300 #define	SPD_DDR3_PKG_DIE_CNT_MIN	1
301 #define	SPD_DDR3_PKG_DIE_CNT_MAX	8
302 #define	SPD_DDR3_PKG_SIG_LOAD(r)	bitx8(r, 1, 0)
303 #define	SPD_DDR3_PKG_SIG_LOAD_UNSPEC	0
304 #define	SPD_DDR3_PKG_SIG_LOAD_MULTI	1
305 #define	SPD_DDR3_PKG_SIG_LOAD_SINGLE	2
306 
307 /*
308  * SDRAM Maximum Active Count
309  */
310 #define	SPD_DDR3_MAC		0x29
311 #define	SPD_DDR3_MAC_MAW(r)		bitx8(r, 5, 4)
312 #define	SPD_DDR3_MAC_MAW_8192X		0
313 #define	SPD_DDR3_MAC_MAW_4096X		1
314 #define	SPD_DDR3_MAC_MAW_2048X		2
315 #define	SPD_DDR3_MAC_MAC(r)		bitx8(r, 3, 0)
316 #define	SPD_DDR3_MAC_MAC_UNTESTED	0
317 #define	SPD_DDR3_MAC_MAC_700K		1
318 #define	SPD_DDR3_MAC_MAC_600K		2
319 #define	SPD_DDR3_MAC_MAC_500K		3
320 #define	SPD_DDR3_MAC_MAC_400K		4
321 #define	SPD_DDR3_MAC_MAC_300K		5
322 #define	SPD_DDR3_MAC_MAC_200K		6
323 #define	SPD_DDR3_MAC_MAC_UNLIMITED	8
324 
325 /*
326  * Module Specific Bytes. There are four annexes defined: UDIMMs, RDIMMs,
327  * CDIMMs, and LRDIMMS.
328  */
329 
330 /*
331  * Annex K.1 Module Specific Bytes for Unbuffered Memory Module Types.
332  */
333 
334 /*
335  * UDIMM: Raw Card Extension, Module Nominal Height. Bits 7-5 here have a raw
336  * card revision. The revision extension, bits 7:5, are only valid when the
337  * value of the normal reference card used in byte 0x3e is set to 0b11 (3).
338  */
339 #define	SPD_DDR3_UDIMM_HEIGHT	0x3c
340 #define	SPD_DDR3_UDIMM_HEIGHT_REV(r)	bitx8(r, 7, 5)
341 #define	SPD_DDR3_UDIMM_HEIGHT_MM(r)	bitx8(r, 4, 0)
342 #define	SPD_DDR3_UDIMM_HEIGHT_LT15MM	0
343 #define	SPD_DDR3_UDIMM_HEIGHT_BASE	15
344 
345 /*
346  * UDIMM: Module Maximum Thickness. These measure thicknesses in mm,
347  * with zero value meaning less than or equal to 1mm.
348  */
349 #define	SPD_DDR3_UDIMM_THICK	0x3d
350 #define	SPD_DDR3_UDIMM_THICK_BACK(r)	bitx8(r, 7, 4)
351 #define	SPD_DDR3_UDIMM_THICK_FRONT(r)	bitx8(r, 3, 0)
352 #define	SPD_DDR3_UDIMM_THICK_BASE	1
353 
354 /*
355  * UDIMM: Reference Raw Card Used. Bit 7 is used as basically another
356  * bit for bits 4-0. We do not define each meaning of these bit combinations in
357  * this header, that is left for tables in the library. When bits 6:5 are 0b11
358  * (3) then we must add in the reference card value in byte 0x80 to bits 6:5.
359  */
360 #define	SPD_DDR3_UDIMM_REF	0x3e
361 #define	SPD_DDR3_UDIMM_REF_EXT(r)	bitx8(r, 7, 7)
362 #define	SPD_DDR3_UDIMM_REF_REV(r)	bitx8(r, 6, 5)
363 #define	SPD_DDR3_UDIMM_REV_USE_HEIGHT	3
364 #define	SPD_DDR3_UDIMM_REF_CARD(r)	bitx8(r, 4, 0)
365 
366 /*
367  * UDIMM: Address Mapping from Edge Connector to DRAM.
368  */
369 #define	SPD_DDR3_UDIMM_MAP	0x3f
370 #define	SPD_DDR3_UDIMM_MAP_R1(r)	bitx8(r, 0, 0)
371 #define	SPD_DDR3_UDIMM_MAP_R1_STD	0
372 #define	SPD_DDR3_UDIMM_MAP_R1_MIRROR	1
373 
374 /*
375  * Annex K.2 Module Specific bytes for Registered Memory Module Types.
376  */
377 
378 /*
379  * RDIMM: Raw Card Extension, Module Nominal Height
380  * RDIMM: Module Maximum Thickness
381  * RDIMM: Reference Raw Card Used
382  *
383  * These have the same definitions as the DDR3 UDIMM.
384  */
385 #define	SPD_DDR3_RDIMM_HEIGHT	0x3c
386 #define	SPD_DDR3_RDIMM_THICK	0x3d
387 #define	SPD_DDR3_RDIMM_REF	0x3e
388 
389 /*
390  * RDIMM: DIMM Module Attributes
391  */
392 #define	SPD_DDR3_RDIMM_ATTR	0x3f
393 #define	SPD_DDR3_RDIMM_ATTR_NROWS(r)	bitx8(r, 3, 2)
394 #define	SPD_DDR3_RDIMM_ATTR_NREGS(r)	bitx8(r, 1, 0)
395 
396 /*
397  * RDIMM: Thermal Heat Spreader Solution.
398  */
399 #define	SPD_DDR3_RDIMM_THERM	0x40
400 #define	SPD_DDR3_RDIMM_THERM_IMPL(r)	bitx8(r, 7, 7)
401 
402 /*
403  * RDIMM: Register Manufacturer JEDEC ID. This contains the JEDEC ID for the
404  * manufacturer encoded as the number of continuation bytes and then the actual
405  * code. This works with libjedec_vendor_string.
406  */
407 #define	SPD_DDR3_RDIMM_REG_MFG_ID0	0x41
408 #define	SPD_DDR3_RDIMM_REG_MFG_ID1	0x42
409 
410 /*
411  * RDIMM: Register Revision Number. This value is just a straight up hex encoded
412  * value. It's a bit arbitrary. For example, they say 0x31 can be rev 3.1, while
413  * 0x01 is just revision 1, and 0xB1 is revision B1.
414  */
415 #define	SPD_DDR3_RDIMM_REV	0x43
416 #define	SPD_DDR3_RDIMM_REV_UNDEF	0xff
417 
418 /*
419  * RDIMM: Register Type
420  */
421 #define	SPD_DDR3_RDIMM_RTYPE	0x44
422 #define	SPD_DDR3_RDIMM_RTYPE_TYPE(r)	bitx8(r, 2, 0)
423 #define	SPD_DDR3_RDIMM_RTYPE_TYPE_SSTE32882	0
424 
425 /*
426  * Byte 69 (0x45) is reserved for future use.
427  */
428 
429 /*
430  * RDIMM: SSTE32882: RC3 / RC2 - Drive Strength, Command/Address. The lower
431  * nibble is reserved.
432  */
433 #define	SPD_DDR3_RDIMM_CADS	0x46
434 #define	SPD_DDR3_RDIMM_CADS_CAA(r)	bitx8(r, 5, 4)
435 #define	SPD_DDR3_RDIMM_DS_LIGHT		0
436 #define	SPD_DDR3_RDIMM_DS_MODERATE	1
437 #define	SPD_DDR3_RDIMM_DS_STRONG	2
438 #define	SPD_DDR3_RDIMM_DS_VERY_STRONG	3	/* LRDIMMs only */
439 #define	SPD_DDR3_RDIMM_CADS_CAB(r)	bitx8(r, 7, 6)
440 
441 /*
442  * RDIMM: SSTE32882: RC5 / RC4 - Drive Strength, Control and Clock
443  */
444 #define	SPD_DDR3_RDIMM_CCDS	0x47
445 #define	SPD_DDR3_RDIMM_CCDS_CLK0(r)	bitx8(r, 7, 6)
446 #define	SPD_DDR3_RDIMM_CCDS_CLK1(r)	bitx8(r, 5, 4)
447 #define	SPD_DDR3_RDIMM_CCDS_CTLB(r)	bitx8(r, 3, 2)
448 #define	SPD_DDR3_RDIMM_CCDS_CTLA(r)	bitx8(r, 1, 0)
449 
450 /*
451  * Bytes 72-76 have definitions but must be written as zero and are all
452  * reserved. As such we don't define any of them. The rest of the section is
453  * fully reserved.
454  */
455 
456 /*
457  * Annex K.3: Module Specific Bytes for Clocked Memory Module Types
458  *
459  * CDIMM: Raw Card Extension, Module Nominal Height
460  * CDIMM: Module Maximum Thickness
461  * CDIMM: Reference Raw Card Used
462  *
463  * These have the same definitions as the DDR3 UDIMM.
464  */
465 #define	SPD_DDR3_CDIMM_HEIGHT	0x3c
466 #define	SPD_DDR3_CDIMM_THICK	0x3d
467 #define	SPD_DDR3_CDIMM_REF	0x3e
468 
469 /*
470  * Annex K.4: Module Specific Bytes for Load Reduced Memory Module Types
471  */
472 
473 /*
474  * LRDIMM: Raw Card Extension, Module Nominal Height
475  * LRDIMM: Module Maximum Thickness
476  * LRDIMM: Reference Raw Card Used
477  *
478  * These have the same definitions as the DDR3 UDIMM.
479  */
480 #define	SPD_DDR3_LRDIMM_HEIGHT	0x3c
481 #define	SPD_DDR3_LRDIMM_THICK	0x3d
482 #define	SPD_DDR3_LRDIMM_REF	0x3e
483 
484 /*
485  * LRDIMM: Module Attributes
486  */
487 #define	SPD_DDR3_LRDIMM_ATTR	0x3f
488 #define	SPD_DDR3_LRDIMM_ATTR_HS(r)	bitx8(r, 7, 7)
489 #define	SPD_DDR3_LRDIMM_ATTR_RN(r)	bitx8(r, 5, 5)
490 #define	SPD_DDR3_LRDIMM_ATTR_RN_CONTIG	0
491 #define	SPD_DDR3_LRDIMM_ATTR_RN_EVEN	1
492 #define	SPD_DDR3_LRDIMM_ATTR_ORIENT(r)	bitx8(r, 4, 4)
493 #define	SPD_DDR3_LRDIMM_ATTR_ORIENT_VERT	0
494 #define	SPD_DDR3_LRDIMM_ATTR_ORIENT_HORIZ	1
495 #define	SPD_DDR3_LRDIMM_ATTR_NROWS(r)	bitx8(r, 3, 2)
496 #define	SPD_DDR3_LRDIMM_ATTR_MIR(r)	bitx8(r, 1, 0)
497 #define	SPD_DDR3_LRDIMM_ATTR_MIR_ALL_NONE	0
498 #define	SPD_DDR3_LRDIMM_ATTR_MIR_ODD_ARE	1
499 
500 /*
501  * LRDIMM: Memory Buffer Revision Number
502  * LRDIMM: Memory Buffer Manufacturer ID Code
503  */
504 #define	SPD_DDR3_LRDIMM_MB_REV	0x40
505 #define	SPD_DDR3_LRDIMM_MB_MFG_ID0	0x41
506 #define	SPD_DDR3_LRDIMM_MB_MFG_ID1	0x42
507 
508 /*
509  * LRDIMM: F0RC3 / F0RC2 - Timing Control & Drive Strength, Address/Command &
510  * QxCS_n
511  *
512  * Drive strength values and encodings are shared with RDIMMs.
513  */
514 #define	SPD_DDR3_LRDIMM_TCDS	0x43
515 #define	SPD_DDR3_LRDIMM_TCDS_QxCS(r)	bitx8(r, 7, 6)
516 #define	SPD_DDR3_LRDIMM_TCDS_AC(r)	bitx8(r, 5, 4)
517 #define	SPD_DDR3_LRDIMM_TCDS_SWAP(r)	bitx8(r, 1, 1)
518 #define	SPD_DDR3_LRDIMM_TCDS_SWAP_NONE	0
519 #define	SPD_DDR3_LRDIMM_TCDS_SWAP_R15	1
520 #define	SPD_DDR3_LRDIMM_TCDS_ACPL(r)	bitx8(r, 0, 0)
521 #define	SPD_DDR3_LRDIMM_TCDS_ACPL_STD		0
522 #define	SPD_DDR3_LRDIMM_TCDS_ACPL_F1RC12	1
523 
524 /*
525  * LRDIMM: F0RC5 / F0RC4 - Drive Strength, QxODT & QxCKE and Clock
526  */
527 #define	SPD_DDR3_LRDIMM_CKDS	0x44
528 #define	SPD_DDR3_LRDIMM_CKDS_Y0Y2(r)	bitx8(r, 7, 6)
529 #define	SPD_DDR3_LRDIMM_CKDS_Y1Y3(r)	bitx8(r, 5, 4)
530 #define	SPD_DDR3_LRDIMM_CKDS_CKE(r)	bitx8(r, 3, 2)
531 #define	SPD_DDR3_LRDIMM_CKDS_ODT(r)	bitx8(r, 1, 0)
532 
533 /*
534  * LRDIMM: F1RC11 / F1RC8 - Extended Delay for Clocks, QxCS_n and QxODT & QxCKE
535  *
536  * Delay measures are defined in terms of 1/128 clock cycles.
537  */
538 #define	SPD_DDR3_LRDIMM_EXTD	0x45
539 #define	SPD_DDR3_LRDIMM_EXTD_CKE(r)	bitx8(r, 7, 6)
540 #define	SPD_DDR3_LRDIMM_EXTD_ODT(r)	bitx8(r, 5, 4)
541 #define	SPD_DDR3_LRDIMM_EXTD_CS(r)	bitx8(r, 3, 2)
542 #define	SPD_DDR3_LRDIMM_EXTD_Y(r)	bitx8(r, 1, 0)
543 
544 /*
545  * LRDIMM: F1RC13 / F1RC12 - Additive Delay for QxCS and QxCA
546  *
547  * Values are shared between this and the next registers. The Y value delay
548  * controls are bit 0 in SPD_DDR3_LRDIMM_TCDS_ACPL.
549  */
550 #define	SPD_DDR3_LRDIMM_ADDD_CSY	0x46
551 #define	SPD_DDR3_LRDIMM_ADDD_CSY_CS_EN(r)	bitx8(r, 7, 7)
552 #define	SPD_DDR3_LRDIMM_ADDD_CSY_CS(r)		bitx8(r, 6, 4)
553 #define	SPD_DDR3_LRDIMM_ADDD_CSY_Y(r)		bitx8(r, 2, 0)
554 #define	SPD_DDR3_LRDIMM_ADD_BASE		8
555 
556 /*
557  * LRDIMM: F1RC15 / F1RC14 - Additive Delay for QxODT and QxCKE
558  */
559 #define	SPD_DDR3_LRDIMM_ADDD_ODT	0x47
560 #define	SPD_DDR3_LRDIMM_ADDD_ODT_CKE_EN(r)	bitx8(r, 7, 7)
561 #define	SPD_DDR3_LRDIMM_ADDD_ODT_CKE(r)		bitx8(r, 6, 4)
562 #define	SPD_DDR3_LRDIMM_ADDD_ODT_ODT_EN(r)	bitx8(r, 3, 3)
563 #define	SPD_DDR3_LRDIMM_ADDD_ODT_ODT(r)		bitx8(r, 2, 0)
564 
565 /*
566  * This constant represents the gap between a register and its corresponding
567  * speed variants. This section of LRDIMM data has a version for 800, 133, and
568  * 1866 which are all 6 registers apart.
569  */
570 #define	SPD_DDR3_LRDIMM_STRIDE	6
571 
572 /*
573  * LRDIMM: F3RC9 / F3RC8 - DRAM Interface MDQ Termination and Drive Strength
574  * <= 1066
575  * LRDIMM: F3RC9 / F3RC8 - DRAM Interface MDQ Termination and Drive Strength
576  * >= 1333 <= 1600
577  * LRDIMM: F3RC9 / F3RC8 - DRAM Interface MDQ Termination and Drive Strength
578  * >= 1866 <= 2133
579  */
580 #define	SPD_DDR3_LRDIMM_MDQ_800		0x48
581 #define	SPD_DDR3_LRDIMM_MDQ_1333	0x4e
582 #define	SPD_DDR3_LRDIMM_MDQ_1866	0x54
583 #define	SPD_DDR3_LRDIMM_MDQ_DS(r)	bitx8(r, 6, 4)
584 #define	SPD_DDR3_LRDIMM_MDQ_DS_40R	0
585 #define	SPD_DDR3_LRDIMM_MDQ_DS_34R	1
586 #define	SPD_DDR3_LRDIMM_MDQ_DS_48R	2
587 #define	SPD_DDR3_LRDIMM_MDQ_DS_27R	3
588 #define	SPD_DDR3_LRDIMM_MDQ_DS_20R	4
589 #define	SPD_DDR3_LRDIMM_MDQ_ODT(r)	bitx8(r, 2, 0)
590 #define	SPD_DDR3_LRDIMM_MDQ_ODT_DIS	0
591 #define	SPD_DDR3_LRDIMM_MDQ_ODT_60R	1
592 #define	SPD_DDR3_LRDIMM_MDQ_ODT_120R	2
593 #define	SPD_DDR3_LRDIMM_MDQ_ODT_40R	3
594 #define	SPD_DDR3_LRDIMM_MDQ_ODT_30R	5
595 #define	SPD_DDR3_LRDIMM_MDQ_ODT_240R	6
596 #define	SPD_DDR3_LRDIMM_MDQ_ODT_80R	7
597 
598 /*
599  * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 0/1 R/W QxODT Control <= 1066
600  * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 2/3 R/W QxODT Control <= 1066
601  * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 4/5 R/W QxODT Control <= 1066
602  * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 6/7 R/W QxODT Control <= 1066
603  * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 0/1 R/W QxODT Control >= 1333 <= 1600
604  * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 2/3 R/W QxODT Control >= 1333 <= 1600
605  * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 4/5 R/W QxODT Control >= 1333 <= 1600
606  * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 6/7 R/W QxODT Control >= 1333 <= 1600
607  * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 0/1 R/W QxODT Control >= 1866 <= 2133
608  * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 2/3 R/W QxODT Control >= 1866 <= 2133
609  * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 4/5 R/W QxODT Control >= 1866 <= 2133
610  * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 6/7 R/W QxODT Control >= 1866 <= 2133
611  *
612  * These registers all have the same layout, just different targeted ranks.
613  */
614 #define	SPD_DDR3_LRDIMM_ODT_R0_800	0x49
615 #define	SPD_DDR3_LRDIMM_ODT_R2_800	0x4a
616 #define	SPD_DDR3_LRDIMM_ODT_R4_800	0x4b
617 #define	SPD_DDR3_LRDIMM_ODT_R6_800	0x4c
618 #define	SPD_DDR3_LRDIMM_ODT_R0_1333	0x4f
619 #define	SPD_DDR3_LRDIMM_ODT_R2_1333	0x50
620 #define	SPD_DDR3_LRDIMM_ODT_R4_1333	0x51
621 #define	SPD_DDR3_LRDIMM_ODT_R6_1333	0x52
622 #define	SPD_DDR3_LRDIMM_ODT_R0_1866	0x55
623 #define	SPD_DDR3_LRDIMM_ODT_R2_1866	0x56
624 #define	SPD_DDR3_LRDIMM_ODT_R4_1866	0x57
625 #define	SPD_DDR3_LRDIMM_ODT_R6_1866	0x58
626 #define	SPD_DDR3_LRDIMM_ODT_R1_ODT1_WR(r)	bitx8(r, 7, 7)
627 #define	SPD_DDR3_LRDIMM_ODT_R1_ODT0_WR(r)	bitx8(r, 6, 6)
628 #define	SPD_DDR3_LRDIMM_ODT_R0_ODT1_WR(r)	bitx8(r, 5, 5)
629 #define	SPD_DDR3_LRDIMM_ODT_R0_ODT0_WR(r)	bitx8(r, 4, 4)
630 #define	SPD_DDR3_LRDIMM_ODT_R1_ODT1_RD(r)	bitx8(r, 3, 3)
631 #define	SPD_DDR3_LRDIMM_ODT_R1_ODT0_RD(r)	bitx8(r, 2, 2)
632 #define	SPD_DDR3_LRDIMM_ODT_R0_ODT1_RD(r)	bitx8(r, 1, 1)
633 #define	SPD_DDR3_LRDIMM_ODT_R0_ODT0_RD(r)	bitx8(r, 0, 0)
634 
635 /*
636  * LRDIMM: MR1,2 <= 1066
637  * LRDIMM: MR1,2 >= 1333 <= 1600
638  * LRDIMM: MR1,2 >= 1866 <= 2133
639  */
640 #define	SPD_DDR3_LRDIMM_RTT_800		0x4d
641 #define	SPD_DDR3_LRDIMM_RTT_1333	0x53
642 #define	SPD_DDR3_LRDIMM_RTT_1866	0x59
643 #define	SPD_DDR3_LRDIMM_RTT_WR(r)	bitx8(r, 7, 6)
644 #define	SPD_DDR3_LRDIMM_RTT_WR_DIS	0
645 #define	SPD_DDR3_LRDIMM_RTT_WR_60R	1
646 #define	SPD_DDR3_LRDIMM_RTT_WR_120R	2
647 #define	SPD_DDR3_LRDIMM_RTT_NOM(r)	bitx8(r, 4, 2)
648 #define	SPD_DDR3_LRDIMM_RTT_NOM_DIS	0
649 #define	SPD_DDR3_LRDIMM_RTT_NOM_60R	1
650 #define	SPD_DDR3_LRDIMM_RTT_NOM_120R	2
651 #define	SPD_DDR3_LRDIMM_RTT_NOM_40R	3
652 #define	SPD_DDR3_LRDIMM_RTT_NOM_20R	4
653 #define	SPD_DDR3_LRDIMM_RTT_NOM_30R	5
654 #define	SPD_DDR3_LRDIMM_RTT_IMP(r)	bitx8(r, 1, 0)
655 #define	SPD_DDR3_LRDIMM_RTT_IMP_40R	0
656 #define	SPD_DDR3_LRDIMM_RTT_IMP_34R	1
657 
658 /*
659  * LRDIMM: Minimum Module Delay Time for 1.5V
660  * LRDIMM: Maximum Module Delay Time for 1.5V
661  * LRDIMM: Minimum Module Delay Time for 1.35V
662  * LRDIMM: Maximum Module Delay Time for 1.35V
663  * LRDIMM: Minimum Module Delay Time for 1.25V
664  * LRDIMM: Maximum Module Delay Time for 1.25V
665  */
666 #define	SPD_DDR3_LRDIMM_MIN_DELAY_1V5	0x5a
667 #define	SPD_DDR3_LRDIMM_MAX_DELAY_1V5	0x5b
668 #define	SPD_DDR3_LRDIMM_MIN_DELAY_1V35	0x5c
669 #define	SPD_DDR3_LRDIMM_MAX_DELAY_1V35	0x5d
670 #define	SPD_DDR3_LRDIMM_MIN_DELAY_1V25	0x5e
671 #define	SPD_DDR3_LRDIMM_MAX_DELAY_1V25	0x5f
672 
673 /*
674  * LRDIMM: Memory Buffer Personality Bytes
675  */
676 #define	SPD_DDR3_LRDIMM_PERS	0x66
677 #define	SPD_DDR3_LRDIMM_PERS_NBYTES	15
678 
679 
680 /*
681  * S2.3 Unique Module ID Bytes. This is a two byte JEP-108 style ID.
682  */
683 #define	SPD_DDR3_MFG_MOD_ID0	0x75
684 #define	SPD_DDR3_MFG_MOD_ID1	0x76
685 
686 /*
687  * Module Manufacturing Location
688  */
689 #define	SPD_DDR3_MFG_LOC	0x77
690 
691 /*
692  * Module Manufacturing Date. Encoded as two BCD bytes for the year and week.
693  */
694 #define	SPD_DDR3_MFG_YEAR	0x78
695 #define	SPD_DDR3_MFG_WEEK	0x79
696 
697 /*
698  * Module Serial Number
699  */
700 #define	SPD_DDR3_MOD_SN		0x7a
701 #define	SPD_DDR3_MOD_SN_LEN	4
702 
703 /*
704  * SPD Cyclical Redundancy Code (CRC)
705  */
706 #define	SPD_DDR3_CRC_LSB	0x7e
707 #define	SPD_DDR3_CRC_MSB	0x7f
708 
709 /*
710  * Module Part Number
711  */
712 #define	SPD_DDR3_MOD_PN		0x80
713 #define	SPD_DDR3_MOD_PN_LEN	18
714 
715 /*
716  * Module Revision Code
717  */
718 #define	SPD_DDR3_MOD_REV	0x92
719 #define	SPD_DDR3_MOD_REV_LEN	2
720 
721 /*
722  * DRAM Manufacturer ID Code. This is a two byte JEP-108 style ID.
723  */
724 #define	SPD_DDR3_MFG_DRAM_ID0	0x94
725 #define	SPD_DDR3_MFG_DRAM_ID1	0x95
726 
727 /*
728  * The remaining portions of this are defined for the manufacturer's and end
729  * user's use.
730  */
731 
732 #ifdef __cplusplus
733 }
734 #endif
735 
736 #endif /* _SPD_DDR3_H */
737