1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SIL3XXX_H 28 #define _SIL3XXX_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * PCI IDs 38 */ 39 #define SILICON_IMAGE_VENDOR_ID 0x1095 40 #define SIL3112_DEVICE_ID 0x3112 41 #define SIL3114_DEVICE_ID 0x3114 42 #define SIL3512_DEVICE_ID 0x3512 43 44 /* Base Register 5 Indirect Address Offset */ 45 46 #define PCI_CONF_BA5_IND_ADDRESS 0xc0 47 #define PCI_CONF_BA5_IND_ACCESS 0xc4 48 49 /* 50 * FIS Configuration channel offsets 51 * Sil3114 has 4 channels 52 * Sil3112 has 2 channels 53 * Sil3512 has 2 channels 54 */ 55 #define SFISCFG_0 0x14c /* SFISCfg Channel 0 */ 56 #define SFISCFG_1 0x1cc /* SFISCfg Channel 1 */ 57 #define SFISCFG_2 0x34c /* SFISCfg Channel 2 */ 58 #define SFISCFG_3 0x3cc /* SFISCfg Channel 3 */ 59 60 /* 61 * FIFO count and contrl offsets for channel 0-4 62 */ 63 #define FIFO_CNTCTL_0 0x40 64 #define FIFO_CNTCTL_1 0x44 65 #define FIFO_CNTCTL_2 0x240 66 #define FIFO_CNTCTL_3 0x244 67 68 /* 69 * Errata Sil-AN-0028-C (Sil3512 Rev 0.3) 70 * Errata Sil-AN-0109-B2 (Sil3114 Rev 0.3) 71 * To prevent erroneous ERR set for queued DMA transfers 72 * greater then 8k, FIS reception for FIS0cfg needs to be set 73 * to Accept FIS without Interlock 74 * Default SFISCfg value of 0x10401555 in channel SFISCfg 75 * register need to be changed to 0x10401554. 76 */ 77 #define SFISCFG_ERRATA 0x10401554 78 79 80 #define PUT_BAR5_INDIRECT(handle, address, value) \ 81 {\ 82 pci_config_put32(handle, PCI_CONF_BA5_IND_ADDRESS, address); \ 83 pci_config_put32(handle, PCI_CONF_BA5_IND_ACCESS, value); \ 84 } 85 86 #define GET_BAR5_INDIRECT(handle, address, rval) \ 87 {\ 88 pci_config_put32(handle, PCI_CONF_BA5_IND_ADDRESS, address); \ 89 rval = pci_config_get32(handle, PCI_CONF_BA5_IND_ACCESS); \ 90 } 91 92 uint_t sil3xxx_init_controller(dev_info_t *, ushort_t, ushort_t); 93 94 #ifdef __cplusplus 95 } 96 #endif 97 98 #endif /* _SIL3XXX_H */ 99