xref: /illumos-gate/usr/src/uts/common/sys/scsi/generic/sff_frames.h (revision ac88567a7a5bb7f01cf22cf366bc9d6203e24d7a)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
24  */
25 
26 #ifndef _SYS_SCSI_GENERIC_SFF_FRAMES_H
27 #define	_SYS_SCSI_GENERIC_SFF_FRAMES_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 #include <sys/sysmacros.h>
34 
35 /*
36  * The definitions of SMP frame formats defined by SFF-8485.
37  * These are NOT compatible with the generic SAS-1 and/or SAS-2 SMP frame
38  * formats, but the function numbers and result codes are defined by SAS-2.
39  */
40 
41 #pragma	pack(1)
42 
43 typedef struct sff_request_frame {
44 	uint8_t srf_frame_type;
45 	uint8_t srf_function;
46 	uint8_t srf_data[1];
47 } sff_request_frame_t;
48 
49 typedef struct sff_response_frame {
50 	uint8_t srf_frame_type;
51 	uint8_t srf_function;
52 	uint8_t srf_result;
53 	uint8_t _reserved1;
54 	uint8_t srf_data[1];
55 } sff_response_frame_t;
56 
57 /*
58  * SFF-8485 8.4.1 GPIO register overview
59  */
60 typedef enum sff_gpio_reg_type {
61 	SFF_GPIO_CFG = 0x00,
62 	SFF_GPIO_RX = 0x01,
63 	SFF_GPIO_RX_GP = 0x02,
64 	SFF_GPIO_TX = 0x03,
65 	SFF_GPIO_TX_GP = 0x04
66 } sff_gpio_reg_type_t;
67 
68 /*
69  * SFF-8485 8.4.2.1 GPIO configuration registers overview
70  */
71 typedef enum sff_gpio_cfg_reg_index {
72 	SFF_GPIO_CFG_0 = 0x00,
73 	SFF_GPIO_CFG_1 = 0x01
74 } sff_gpio_cfg_reg_index_t;
75 
76 /*
77  * SFF-8485 8.4.2.2 GPIO_CFG[0] register
78  */
79 typedef struct sff_gpio_cfg_reg_0 {
80 	uint8_t _reserved1;
81 	DECL_BITFIELD2(
82 	    sgcr0_version	:4,
83 	    _reserved2		:4);
84 	DECL_BITFIELD3(
85 	    sgcr0_gp_register_count	:4,
86 	    sgcr0_cfg_register_count	:3,
87 	    sgcr0_gpio_enable		:1);
88 	uint8_t sgcr0_supported_drive_count;
89 } sff_gpio_cfg_reg_0_t;
90 
91 /*
92  * SFF-8485 8.4.2.3 GPIO_CFG[1] register
93  */
94 typedef struct sff_gpio_cfg_reg_1 {
95 	uint8_t _reserved1;
96 	DECL_BITFIELD2(
97 	    sgcr1_blink_gen_rate_a	:4,
98 	    sgcr1_blink_gen_rate_b	:4);
99 	DECL_BITFIELD2(
100 	    sgcr1_max_activity_on	:4,
101 	    sgcr1_force_activity_off	:4);
102 	DECL_BITFIELD2(
103 	    sgcr1_stretch_activity_on	:4,
104 	    sgcr1_stretch_activity_off	:4);
105 } sff_gpio_cfg_reg_1_t;
106 
107 /*
108  * SFF-8485 8.4.3 GPIO receive registers
109  */
110 typedef struct sff_gpio_rx_reg {
111 	DECL_BITFIELD2(
112 	    sgrr_drive_3_gpio_input	:3,
113 	    _reserved1			:5);
114 	DECL_BITFIELD2(
115 	    sgrr_drive_2_gpio_input	:3,
116 	    _reserved1			:5);
117 	DECL_BITFIELD2(
118 	    sgrr_drive_1_gpio_input	:3,
119 	    _reserved1			:5);
120 	DECL_BITFIELD2(
121 	    sgrr_drive_0_gpio_input	:3,
122 	    _reserved1			:5);
123 } sff_gpio_rx_reg_t;
124 
125 /*
126  * SFF-8485 8.4.4 GPIO transmit registers
127  */
128 typedef enum sff_drive_error {
129 	SFF_DRIVE_ERR_DISABLE = 0x0,
130 	SFF_DRIVE_ERR_ENABLE = 0x1,
131 	SFF_DRIVE_ERR_BLINK_A_1_0 = 0x2,
132 	SFF_DRIVE_ERR_BLINK_A_0_1 = 0x3,
133 	SFF_DRIVE_ERR_ENABLE_4 = 0x4,
134 	SFF_DRIVE_ERR_ENABLE_5 = 0x5,
135 	SFF_DRIVE_ERR_BLINK_B_1_0 = 0x6,
136 	SFF_DRIVE_ERR_BLINK_B_0_1 = 0x7
137 } sff_drive_error_t;
138 
139 typedef enum sff_drive_locate {
140 	SFF_DRIVE_LOC_DISABLE = 0x0,
141 	SFF_DRIVE_LOC_ENABLE = 0x1,
142 	SFF_DRIVE_BLINK_A_1_0 = 0x2,
143 	SFF_DRIVE_BLINK_A_0_1 = 0x3
144 } sff_drive_locate_t;
145 
146 typedef enum sff_drive_activity {
147 	SFF_DRIVE_ACT_DISABLE = 0x0,
148 	SFF_DRIVE_ACT_ENABLE = 0x1,
149 	SFF_DRIVE_ACT_BLINK_A_1_0 = 0x2,
150 	SFF_DRIVE_ACT_BLINK_A_0_1 = 0x3,
151 	SFF_DRIVE_ACT_ENABLE_END = 0x4,
152 	SFF_DRIVE_ACT_ENABLE_START = 0x5,
153 	SFF_DRIVE_ACT_BLINK_B_1_0 = 0x6,
154 	SFF_DRIVE_ACT_BLINK_B_0_1 = 0x7
155 } sff_drive_activity_t;
156 
157 typedef struct sff_gpio_tx_reg {
158 	DECL_BITFIELD3(
159 	    sgtr_drive_3_error		:3,	/* sff_drive_error_t */
160 	    sgtr_drive_3_locate		:2,	/* sff_drive_locate_t */
161 	    sgtr_drive_3_activity	:3);	/* sff_drive_activity_t */
162 	DECL_BITFIELD3(
163 	    sgtr_drive_2_error		:3,	/* sff_drive_error_t */
164 	    sgtr_drive_2_locate		:2,	/* sff_drive_locate_t */
165 	    sgtr_drive_2_activity	:3);	/* sff_drive_activity_t */
166 	DECL_BITFIELD3(
167 	    sgtr_drive_1_error		:3,	/* sff_drive_error_t */
168 	    sgtr_drive_1_locate		:2,	/* sff_drive_locate_t */
169 	    sgtr_drive_1_activity	:3);	/* sff_drive_activity_t */
170 	DECL_BITFIELD3(
171 	    sgtr_drive_0_error		:3,	/* sff_drive_error_t */
172 	    sgtr_drive_0_locate		:2,	/* sff_drive_locate_t */
173 	    sgtr_drive_0_activity	:3);	/* sff_drive_activity_t */
174 } sff_gpio_tx_reg_t;
175 
176 /*
177  * SFF-8485 8.4.5.1 GPIO general purpose receive registers overview
178  */
179 typedef enum sff_gpio_rx_gp_reg_index {
180 	SFF_GPIO_REG_RX_GP_CFG = 0x00,
181 	SFF_GPIO_REG_RX_GP_1 = 0x01	/* ... */
182 } sff_gpio_rx_gp_reg_index_t;
183 
184 /*
185  * SFF-8485 8.4.5.2 GPIO_RX_GP_CFG register
186  */
187 typedef struct sff_gpio_rx_gp_cfg_reg {
188 	uint8_t _reserved1[2];
189 	uint8_t sgrgcr_count;
190 	uint8_t _reserved2;
191 } sff_gpio_rx_gp_cfg_reg_t;
192 
193 /*
194  * SFF-8485 8.4.5.3 GPIO_RX_GP[1..n] register
195  */
196 typedef uint8_t sff_gpio_rx_gp_reg_t[4];	/* little-endian */
197 
198 /*
199  * SFF-8485 8.4.6.1 GPIO general purpose transmit registers overview
200  */
201 typedef enum sff_gpio_tx_gp_reg_index {
202 	SFF_GPIO_REG_TX_GP_CFG = 0x00,
203 	SFF_GPIO_REG_TX_GP_1 = 0x01	/* ... */
204 } sff_gpio_tx_gp_reg_index_t;
205 
206 /*
207  * SFF-8485 8.4.6.2 GPIO_TX_GP_CFG register
208  */
209 typedef struct sff_gpio_tx_cfg_reg {
210 	uint8_t _reserved1[2];
211 	uint8_t sgtcr_count;
212 	DECL_BITFIELD5(
213 	    sgtcr_sload_0	:1,
214 	    sgtcr_sload_1	:1,
215 	    sgtcr_sload_2	:1,
216 	    sgtcr_sload_3	:1,
217 	    _reserved2		:4);
218 } sff_gpio_tx_cfg_reg_t;
219 
220 /*
221  * SFF-8485 8.4.6.3 GPIO_TX_GP[1..n] registers
222  */
223 typedef uint8_t sff_gpio_tx_gp_reg_t[4];	/* little-endian */
224 
225 /*
226  * SFF-8485 8.2.2 READ GPIO REGISTER request
227  */
228 typedef struct sff_read_gpio_req {
229 	uint8_t srgr_register_type;
230 	uint8_t srgr_register_index;
231 	uint8_t srgr_register_count;
232 	uint8_t _reserved1[3];
233 } sff_read_gpio_req_t;
234 
235 typedef uint8_t sff_gpio_reg_t[4];
236 
237 /*
238  * SFF-8485 8.2.2 READ GPIO REGISTER response
239  */
240 typedef struct sff_read_gpio_resp {
241 	sff_gpio_reg_t srgr_regs[1];
242 } smp_response_frame_t;
243 
244 /*
245  * SFF-8485 8.2.3 WRITE GPIO REGISTER request (no additional response)
246  */
247 typedef struct sff_write_gpio_req {
248 	uint8_t swgr_register_type;
249 	uint8_t swgr_register_index;
250 	uint8_t swgr_register_count;
251 	uint8_t _reserved1[3];
252 	sff_gpio_reg_t swgr_regs[1];
253 } sff_write_gpio_req_t;
254 
255 #pragma	pack()
256 
257 #ifdef	__cplusplus
258 }
259 #endif
260 
261 #endif	/* _SYS_SCSI_GENERIC_SFF_FRAMES_H */
262