1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #ifndef _LINUX_QCOM_GENI_SE 8 #define _LINUX_QCOM_GENI_SE 9 10 #include <linux/interconnect.h> 11 12 /** 13 * enum geni_se_xfer_mode: Transfer modes supported by Serial Engines 14 * 15 * @GENI_SE_INVALID: Invalid mode 16 * @GENI_SE_FIFO: FIFO mode. Data is transferred with SE FIFO 17 * by programmed IO method 18 * @GENI_SE_DMA: Serial Engine DMA mode. Data is transferred 19 * with SE by DMAengine internal to SE 20 * @GENI_GPI_DMA: GPI DMA mode. Data is transferred using a DMAengine 21 * configured by a firmware residing on a GSI engine. This DMA name is 22 * interchangeably used as GSI or GPI which seem to imply the same DMAengine 23 */ 24 25 enum geni_se_xfer_mode { 26 GENI_SE_INVALID, 27 GENI_SE_FIFO, 28 GENI_SE_DMA, 29 GENI_GPI_DMA, 30 }; 31 32 /* Protocols supported by GENI Serial Engines */ 33 enum geni_se_protocol_type { 34 GENI_SE_NONE, 35 GENI_SE_SPI, 36 GENI_SE_UART, 37 GENI_SE_I2C, 38 GENI_SE_I3C, 39 GENI_SE_SPI_SLAVE, 40 GENI_SE_INVALID_PROTO = 255, 41 }; 42 43 struct geni_wrapper; 44 struct clk; 45 46 enum geni_icc_path_index { 47 GENI_TO_CORE, 48 CPU_TO_GENI, 49 GENI_TO_DDR 50 }; 51 52 struct geni_icc_path { 53 struct icc_path *path; 54 unsigned int avg_bw; 55 }; 56 57 /** 58 * struct geni_se - GENI Serial Engine 59 * @base: Base Address of the Serial Engine's register block 60 * @dev: Pointer to the Serial Engine device 61 * @wrapper: Pointer to the parent QUP Wrapper core 62 * @clk: Handle to the core serial engine clock 63 * @num_clk_levels: Number of valid clock levels in clk_perf_tbl 64 * @clk_perf_tbl: Table of clock frequency input to serial engine clock 65 * @icc_paths: Array of ICC paths for SE 66 */ 67 struct geni_se { 68 void __iomem *base; 69 struct device *dev; 70 struct geni_wrapper *wrapper; 71 struct clk *clk; 72 unsigned int num_clk_levels; 73 unsigned long *clk_perf_tbl; 74 struct geni_icc_path icc_paths[3]; 75 }; 76 77 /* Common SE registers */ 78 #define GENI_FORCE_DEFAULT_REG 0x20 79 #define GENI_OUTPUT_CTRL 0x24 80 #define SE_GENI_STATUS 0x40 81 #define GENI_SER_M_CLK_CFG 0x48 82 #define GENI_SER_S_CLK_CFG 0x4c 83 #define GENI_IF_DISABLE_RO 0x64 84 #define GENI_FW_REVISION_RO 0x68 85 #define SE_GENI_CLK_SEL 0x7c 86 #define SE_GENI_CFG_SEQ_START 0x84 87 #define SE_GENI_DMA_MODE_EN 0x258 88 #define SE_GENI_M_CMD0 0x600 89 #define SE_GENI_M_CMD_CTRL_REG 0x604 90 #define SE_GENI_M_IRQ_STATUS 0x610 91 #define SE_GENI_M_IRQ_EN 0x614 92 #define SE_GENI_M_IRQ_CLEAR 0x618 93 #define SE_GENI_M_IRQ_EN_SET 0x61c 94 #define SE_GENI_M_IRQ_EN_CLEAR 0x620 95 #define SE_GENI_S_CMD0 0x630 96 #define SE_GENI_S_CMD_CTRL_REG 0x634 97 #define SE_GENI_S_IRQ_STATUS 0x640 98 #define SE_GENI_S_IRQ_EN 0x644 99 #define SE_GENI_S_IRQ_CLEAR 0x648 100 #define SE_GENI_S_IRQ_EN_SET 0x64c 101 #define SE_GENI_S_IRQ_EN_CLEAR 0x650 102 #define SE_GENI_TX_FIFOn 0x700 103 #define SE_GENI_RX_FIFOn 0x780 104 #define SE_GENI_TX_FIFO_STATUS 0x800 105 #define SE_GENI_RX_FIFO_STATUS 0x804 106 #define SE_GENI_TX_WATERMARK_REG 0x80c 107 #define SE_GENI_RX_WATERMARK_REG 0x810 108 #define SE_GENI_RX_RFR_WATERMARK_REG 0x814 109 #define SE_GENI_IOS 0x908 110 #define SE_GENI_M_GP_LENGTH 0x910 111 #define SE_GENI_S_GP_LENGTH 0x914 112 #define SE_DMA_TX_IRQ_STAT 0xc40 113 #define SE_DMA_TX_IRQ_CLR 0xc44 114 #define SE_DMA_TX_FSM_RST 0xc58 115 #define SE_DMA_RX_IRQ_STAT 0xd40 116 #define SE_DMA_RX_IRQ_CLR 0xd44 117 #define SE_DMA_RX_LEN_IN 0xd54 118 #define SE_DMA_RX_FSM_RST 0xd58 119 #define SE_HW_PARAM_0 0xe24 120 #define SE_HW_PARAM_1 0xe28 121 122 /* GENI_FORCE_DEFAULT_REG fields */ 123 #define FORCE_DEFAULT BIT(0) 124 125 /* GENI_OUTPUT_CTRL fields */ 126 #define GENI_IO_MUX_0_EN BIT(0) 127 128 /* GENI_STATUS fields */ 129 #define M_GENI_CMD_ACTIVE BIT(0) 130 #define S_GENI_CMD_ACTIVE BIT(12) 131 132 /* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */ 133 #define SER_CLK_EN BIT(0) 134 #define CLK_DIV_MSK GENMASK(15, 4) 135 #define CLK_DIV_SHFT 4 136 137 /* GENI_IF_DISABLE_RO fields */ 138 #define FIFO_IF_DISABLE (BIT(0)) 139 140 /* GENI_FW_REVISION_RO fields */ 141 #define FW_REV_PROTOCOL_MSK GENMASK(15, 8) 142 #define FW_REV_PROTOCOL_SHFT 8 143 144 /* GENI_CLK_SEL fields */ 145 #define CLK_SEL_MSK GENMASK(2, 0) 146 147 /* SE_GENI_CFG_SEQ_START fields */ 148 #define START_TRIGGER BIT(0) 149 150 /* SE_GENI_DMA_MODE_EN */ 151 #define GENI_DMA_MODE_EN BIT(0) 152 153 /* GENI_M_CMD0 fields */ 154 #define M_OPCODE_MSK GENMASK(31, 27) 155 #define M_OPCODE_SHFT 27 156 #define M_PARAMS_MSK GENMASK(26, 0) 157 158 /* GENI_M_CMD_CTRL_REG */ 159 #define M_GENI_CMD_CANCEL BIT(2) 160 #define M_GENI_CMD_ABORT BIT(1) 161 #define M_GENI_DISABLE BIT(0) 162 163 /* GENI_S_CMD0 fields */ 164 #define S_OPCODE_MSK GENMASK(31, 27) 165 #define S_OPCODE_SHFT 27 166 #define S_PARAMS_MSK GENMASK(26, 0) 167 168 /* GENI_S_CMD_CTRL_REG */ 169 #define S_GENI_CMD_CANCEL BIT(2) 170 #define S_GENI_CMD_ABORT BIT(1) 171 #define S_GENI_DISABLE BIT(0) 172 173 /* GENI_M_IRQ_EN fields */ 174 #define M_CMD_DONE_EN BIT(0) 175 #define M_CMD_OVERRUN_EN BIT(1) 176 #define M_ILLEGAL_CMD_EN BIT(2) 177 #define M_CMD_FAILURE_EN BIT(3) 178 #define M_CMD_CANCEL_EN BIT(4) 179 #define M_CMD_ABORT_EN BIT(5) 180 #define M_TIMESTAMP_EN BIT(6) 181 #define M_RX_IRQ_EN BIT(7) 182 #define M_GP_SYNC_IRQ_0_EN BIT(8) 183 #define M_GP_IRQ_0_EN BIT(9) 184 #define M_GP_IRQ_1_EN BIT(10) 185 #define M_GP_IRQ_2_EN BIT(11) 186 #define M_GP_IRQ_3_EN BIT(12) 187 #define M_GP_IRQ_4_EN BIT(13) 188 #define M_GP_IRQ_5_EN BIT(14) 189 #define M_TX_FIFO_NOT_EMPTY_EN BIT(21) 190 #define M_IO_DATA_DEASSERT_EN BIT(22) 191 #define M_IO_DATA_ASSERT_EN BIT(23) 192 #define M_RX_FIFO_RD_ERR_EN BIT(24) 193 #define M_RX_FIFO_WR_ERR_EN BIT(25) 194 #define M_RX_FIFO_WATERMARK_EN BIT(26) 195 #define M_RX_FIFO_LAST_EN BIT(27) 196 #define M_TX_FIFO_RD_ERR_EN BIT(28) 197 #define M_TX_FIFO_WR_ERR_EN BIT(29) 198 #define M_TX_FIFO_WATERMARK_EN BIT(30) 199 #define M_SEC_IRQ_EN BIT(31) 200 #define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \ 201 M_IO_DATA_DEASSERT_EN | \ 202 M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \ 203 M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \ 204 M_TX_FIFO_WR_ERR_EN) 205 206 /* GENI_S_IRQ_EN fields */ 207 #define S_CMD_DONE_EN BIT(0) 208 #define S_CMD_OVERRUN_EN BIT(1) 209 #define S_ILLEGAL_CMD_EN BIT(2) 210 #define S_CMD_FAILURE_EN BIT(3) 211 #define S_CMD_CANCEL_EN BIT(4) 212 #define S_CMD_ABORT_EN BIT(5) 213 #define S_GP_SYNC_IRQ_0_EN BIT(8) 214 #define S_GP_IRQ_0_EN BIT(9) 215 #define S_GP_IRQ_1_EN BIT(10) 216 #define S_GP_IRQ_2_EN BIT(11) 217 #define S_GP_IRQ_3_EN BIT(12) 218 #define S_GP_IRQ_4_EN BIT(13) 219 #define S_GP_IRQ_5_EN BIT(14) 220 #define S_IO_DATA_DEASSERT_EN BIT(22) 221 #define S_IO_DATA_ASSERT_EN BIT(23) 222 #define S_RX_FIFO_RD_ERR_EN BIT(24) 223 #define S_RX_FIFO_WR_ERR_EN BIT(25) 224 #define S_RX_FIFO_WATERMARK_EN BIT(26) 225 #define S_RX_FIFO_LAST_EN BIT(27) 226 #define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \ 227 S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN) 228 229 /* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */ 230 #define WATERMARK_MSK GENMASK(5, 0) 231 232 /* GENI_TX_FIFO_STATUS fields */ 233 #define TX_FIFO_WC GENMASK(27, 0) 234 235 /* GENI_RX_FIFO_STATUS fields */ 236 #define RX_LAST BIT(31) 237 #define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28) 238 #define RX_LAST_BYTE_VALID_SHFT 28 239 #define RX_FIFO_WC_MSK GENMASK(24, 0) 240 241 /* SE_GENI_IOS fields */ 242 #define IO2_DATA_IN BIT(1) 243 #define RX_DATA_IN BIT(0) 244 245 /* SE_GENI_M_GP_LENGTH and SE_GENI_S_GP_LENGTH fields */ 246 #define GP_LENGTH GENMASK(31, 0) 247 248 /* SE_DMA_TX_IRQ_STAT Register fields */ 249 #define TX_DMA_DONE BIT(0) 250 #define TX_EOT BIT(1) 251 #define TX_SBE BIT(2) 252 #define TX_RESET_DONE BIT(3) 253 254 /* SE_DMA_RX_IRQ_STAT Register fields */ 255 #define RX_DMA_DONE BIT(0) 256 #define RX_EOT BIT(1) 257 #define RX_SBE BIT(2) 258 #define RX_RESET_DONE BIT(3) 259 #define RX_FLUSH_DONE BIT(4) 260 #define RX_DMA_PARITY_ERR BIT(5) 261 #define RX_DMA_BREAK GENMASK(8, 7) 262 #define RX_GENI_GP_IRQ GENMASK(10, 5) 263 #define RX_GENI_GP_IRQ_EXT GENMASK(13, 12) 264 #define RX_GENI_CANCEL_IRQ BIT(14) 265 266 /* SE_HW_PARAM_0 fields */ 267 #define TX_FIFO_WIDTH_MSK GENMASK(29, 24) 268 #define TX_FIFO_WIDTH_SHFT 24 269 /* 270 * For QUP HW Version >= 3.10 Tx fifo depth support is increased 271 * to 256bytes and corresponding bits are 16 to 23 272 */ 273 #define TX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16) 274 #define TX_FIFO_DEPTH_MSK GENMASK(21, 16) 275 #define TX_FIFO_DEPTH_SHFT 16 276 277 /* SE_HW_PARAM_1 fields */ 278 #define RX_FIFO_WIDTH_MSK GENMASK(29, 24) 279 #define RX_FIFO_WIDTH_SHFT 24 280 /* 281 * For QUP HW Version >= 3.10 Rx fifo depth support is increased 282 * to 256bytes and corresponding bits are 16 to 23 283 */ 284 #define RX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16) 285 #define RX_FIFO_DEPTH_MSK GENMASK(21, 16) 286 #define RX_FIFO_DEPTH_SHFT 16 287 288 #define HW_VER_MAJOR_MASK GENMASK(31, 28) 289 #define HW_VER_MAJOR_SHFT 28 290 #define HW_VER_MINOR_MASK GENMASK(27, 16) 291 #define HW_VER_MINOR_SHFT 16 292 #define HW_VER_STEP_MASK GENMASK(15, 0) 293 294 #define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT) 295 #define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT) 296 #define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK) 297 298 /* QUP SE VERSION value for major number 2 and minor number 5 */ 299 #define QUP_SE_VERSION_2_5 0x20050000 300 301 /* 302 * Define bandwidth thresholds that cause the underlying Core 2X interconnect 303 * clock to run at the named frequency. These baseline values are recommended 304 * by the hardware team, and are not dynamically scaled with GENI bandwidth 305 * beyond basic on/off. 306 */ 307 #define CORE_2X_19_2_MHZ 960 308 #define CORE_2X_50_MHZ 2500 309 #define CORE_2X_100_MHZ 5000 310 #define CORE_2X_150_MHZ 7500 311 #define CORE_2X_200_MHZ 10000 312 #define CORE_2X_236_MHZ 16383 313 314 #define GENI_DEFAULT_BW Bps_to_icc(1000) 315 316 #if IS_ENABLED(CONFIG_QCOM_GENI_SE) 317 318 u32 geni_se_get_qup_hw_version(struct geni_se *se); 319 320 /** 321 * geni_se_read_proto() - Read the protocol configured for a serial engine 322 * @se: Pointer to the concerned serial engine. 323 * 324 * Return: Protocol value as configured in the serial engine. 325 */ 326 static inline u32 geni_se_read_proto(struct geni_se *se) 327 { 328 u32 val; 329 330 val = readl_relaxed(se->base + GENI_FW_REVISION_RO); 331 332 return (val & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT; 333 } 334 335 /** 336 * geni_se_setup_m_cmd() - Setup the primary sequencer 337 * @se: Pointer to the concerned serial engine. 338 * @cmd: Command/Operation to setup in the primary sequencer. 339 * @params: Parameter for the sequencer command. 340 * 341 * This function is used to configure the primary sequencer with the 342 * command and its associated parameters. 343 */ 344 static inline void geni_se_setup_m_cmd(struct geni_se *se, u32 cmd, u32 params) 345 { 346 u32 m_cmd; 347 348 m_cmd = (cmd << M_OPCODE_SHFT) | (params & M_PARAMS_MSK); 349 writel(m_cmd, se->base + SE_GENI_M_CMD0); 350 } 351 352 /** 353 * geni_se_setup_s_cmd() - Setup the secondary sequencer 354 * @se: Pointer to the concerned serial engine. 355 * @cmd: Command/Operation to setup in the secondary sequencer. 356 * @params: Parameter for the sequencer command. 357 * 358 * This function is used to configure the secondary sequencer with the 359 * command and its associated parameters. 360 */ 361 static inline void geni_se_setup_s_cmd(struct geni_se *se, u32 cmd, u32 params) 362 { 363 u32 s_cmd; 364 365 s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0); 366 s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK); 367 s_cmd |= (cmd << S_OPCODE_SHFT); 368 s_cmd |= (params & S_PARAMS_MSK); 369 writel(s_cmd, se->base + SE_GENI_S_CMD0); 370 } 371 372 /** 373 * geni_se_cancel_m_cmd() - Cancel the command configured in the primary 374 * sequencer 375 * @se: Pointer to the concerned serial engine. 376 * 377 * This function is used to cancel the currently configured command in the 378 * primary sequencer. 379 */ 380 static inline void geni_se_cancel_m_cmd(struct geni_se *se) 381 { 382 writel_relaxed(M_GENI_CMD_CANCEL, se->base + SE_GENI_M_CMD_CTRL_REG); 383 } 384 385 /** 386 * geni_se_cancel_s_cmd() - Cancel the command configured in the secondary 387 * sequencer 388 * @se: Pointer to the concerned serial engine. 389 * 390 * This function is used to cancel the currently configured command in the 391 * secondary sequencer. 392 */ 393 static inline void geni_se_cancel_s_cmd(struct geni_se *se) 394 { 395 writel_relaxed(S_GENI_CMD_CANCEL, se->base + SE_GENI_S_CMD_CTRL_REG); 396 } 397 398 /** 399 * geni_se_abort_m_cmd() - Abort the command configured in the primary sequencer 400 * @se: Pointer to the concerned serial engine. 401 * 402 * This function is used to force abort the currently configured command in the 403 * primary sequencer. 404 */ 405 static inline void geni_se_abort_m_cmd(struct geni_se *se) 406 { 407 writel_relaxed(M_GENI_CMD_ABORT, se->base + SE_GENI_M_CMD_CTRL_REG); 408 } 409 410 /** 411 * geni_se_abort_s_cmd() - Abort the command configured in the secondary 412 * sequencer 413 * @se: Pointer to the concerned serial engine. 414 * 415 * This function is used to force abort the currently configured command in the 416 * secondary sequencer. 417 */ 418 static inline void geni_se_abort_s_cmd(struct geni_se *se) 419 { 420 writel_relaxed(S_GENI_CMD_ABORT, se->base + SE_GENI_S_CMD_CTRL_REG); 421 } 422 423 /** 424 * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine 425 * based on QUP HW version 426 * @se: Pointer to the concerned serial engine. 427 * 428 * This function is used to get the depth i.e. number of elements in the 429 * TX fifo of the serial engine. 430 * 431 * Return: TX fifo depth in units of FIFO words. 432 */ 433 static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se) 434 { 435 u32 val, hw_version, hw_major, hw_minor, tx_fifo_depth_mask; 436 437 hw_version = geni_se_get_qup_hw_version(se); 438 hw_major = GENI_SE_VERSION_MAJOR(hw_version); 439 hw_minor = GENI_SE_VERSION_MINOR(hw_version); 440 441 if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3) 442 tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK_256_BYTES; 443 else 444 tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK; 445 446 val = readl_relaxed(se->base + SE_HW_PARAM_0); 447 448 return (val & tx_fifo_depth_mask) >> TX_FIFO_DEPTH_SHFT; 449 } 450 451 /** 452 * geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine 453 * @se: Pointer to the concerned serial engine. 454 * 455 * This function is used to get the width i.e. word size per element in the 456 * TX fifo of the serial engine. 457 * 458 * Return: TX fifo width in bits 459 */ 460 static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se) 461 { 462 u32 val; 463 464 val = readl_relaxed(se->base + SE_HW_PARAM_0); 465 466 return (val & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT; 467 } 468 469 /** 470 * geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine 471 * based on QUP HW version 472 * @se: Pointer to the concerned serial engine. 473 * 474 * This function is used to get the depth i.e. number of elements in the 475 * RX fifo of the serial engine. 476 * 477 * Return: RX fifo depth in units of FIFO words 478 */ 479 static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se) 480 { 481 u32 val, hw_version, hw_major, hw_minor, rx_fifo_depth_mask; 482 483 hw_version = geni_se_get_qup_hw_version(se); 484 hw_major = GENI_SE_VERSION_MAJOR(hw_version); 485 hw_minor = GENI_SE_VERSION_MINOR(hw_version); 486 487 if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3) 488 rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK_256_BYTES; 489 else 490 rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK; 491 492 val = readl_relaxed(se->base + SE_HW_PARAM_1); 493 494 return (val & rx_fifo_depth_mask) >> RX_FIFO_DEPTH_SHFT; 495 } 496 497 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr); 498 499 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode); 500 501 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words, 502 bool msb_to_lsb, bool tx_cfg, bool rx_cfg); 503 504 int geni_se_resources_off(struct geni_se *se); 505 506 int geni_se_resources_on(struct geni_se *se); 507 508 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl); 509 510 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq, 511 unsigned int *index, unsigned long *res_freq, 512 bool exact); 513 514 void geni_se_tx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len); 515 516 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, 517 dma_addr_t *iova); 518 519 void geni_se_rx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len); 520 521 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, 522 dma_addr_t *iova); 523 524 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len); 525 526 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len); 527 528 int geni_icc_get(struct geni_se *se, const char *icc_ddr); 529 530 int geni_icc_set_bw(struct geni_se *se); 531 void geni_icc_set_tag(struct geni_se *se, u32 tag); 532 533 int geni_icc_enable(struct geni_se *se); 534 535 int geni_icc_disable(struct geni_se *se); 536 537 int geni_load_se_firmware(struct geni_se *se, enum geni_se_protocol_type protocol); 538 #endif 539 #endif 540